Self-calibrating barrier modulation pixel

Abstract

A pixel array is provided, the pixel array comprising: a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage, a sample and hold stage comprising at least a first capacitor and a second capacitor, and an input of the sample and hold stage electrically coupled to the diffusion node through an amplifier, the transfer transistor configured to be pulsed to different voltage levels to transfer portions of the accumulated charge carriers to the diffusion node, the at least second capacitor configured to store a low conversion gain signal representative of the first portion of the accumulated charge carriers, and the first capacitor configured to store a high conversion gain signal representative of the remaining portion of the accumulated charge carriers. Further provided are methods of operating the pixel array and image sensors comprising the pixel array.

Description

[Technical Field]

[0001] Priority Claims and Cross-References This patent application claims priority to U.S. Provisional Application No. 63 / 263,861, filed November 10, 2021, and German Application No. 102021120779.7, filed August 10, 2021, which are incorporated herein by reference in their entireties.

[0002] The present invention relates to a pixel array, an image sensor, and a method for operating a pixel array. [Background technology]

[0003] CMOS image sensors are used in a wide range of applications, such as camera modules, smartphones, tablet computers, and laptops. Some applications require a high dynamic range (HDR), e.g., greater than 85 dB. The dynamic range (DR) is limited on the one hand by the noise floor in low-light conditions and on the other hand by saturation effects in strong-light conditions. Furthermore, the size of the pixels in such image sensors must be kept small. Summary of the Invention [Problem to be solved by the invention]

[0004] An object to be achieved is to provide a pixel array with a high dynamic range and a method for operating such a pixel array.A further object to be achieved is to provide an image sensor with a pixel array with a high dynamic range. [Means for solving the problem]

[0005] These objects are achieved by means of the subject matter of the independent claims. Further developments and embodiments are described in the dependent claims.

[0006] Here and hereinafter, the terms "pixel" and "pixel array" refer to a light-receiving element that may be arranged, together with other pixels, in a two-dimensional array, also called a matrix. The pixels in the array are arranged in rows and columns. The terms "row" and "column" can be used interchangeably because they depend only on the orientation of the pixel array. A pixel may also include circuitry for controlling signals to and from the pixel. Thus, a pixel may form a so-called active pixel. A pixel may receive light in any wavelength range. The term "light" may refer generally to electromagnetic radiation, including, for example, infrared (IR) radiation, ultraviolet (UV) radiation, and visible (VIS) light.

[0007] In one embodiment, the pixel array comprises a photodetector configured to accumulate charge carriers by converting electromagnetic radiation. The pixel array may form global shutter pixels, in particular voltage-domain global shutter pixels, abbreviated as VGS pixels. It is also possible for the pixels to form rolling shutter pixels. The photodetector may in particular be a photodiode or a pinned photodiode. The photodiode may be arranged on a substrate, in particular a semiconductor substrate.

[0008] In some embodiments, the pixel array includes a transfer transistor electrically coupled to the photodetector. In some embodiments, the pixel array includes a diffusion node electrically coupled to the transfer transistor. The transfer transistor forms a switch. A first terminal of the transfer transistor is connected to the photodetector, and a second terminal of the transfer transistor is connected to the diffusion node. Applying a transfer signal to the gate of the transfer transistor allows charge carriers to diffuse from the photodetector toward the diffusion node. The diffusion node may be a floating diffusion node, abbreviated as FD node. The FD node may include a capacitance for temporarily storing charge carriers. Hereinafter, the terms FD node and diffusion node are used synonymously.

[0009] In one embodiment, the pixel array includes a reset transistor electrically coupled to the diffusion node and a pixel power supply voltage. The reset transistor is provided to reset the FD node. The reset transistor forms a switch. A first terminal of the reset transistor is connected to the pixel power supply voltage and a second terminal is coupled to the FD node. By applying a reset signal to the gate of the reset transistor, any excess charge carriers are drained to the pixel power supply.

[0010] In one embodiment, the pixel array includes a sample-and-hold stage including at least a first capacitor and a second capacitor. The input of the sample-and-hold stage is electrically coupled to the diffusion node via an amplifier. The sample-and-hold stage may be abbreviated as an S / H stage. The first capacitor and the second capacitor may be referred to as S / H capacitors. The S / H stage may include an amplifier. The amplifier may be formed as a common-drain amplifier, also known as a source follower. The gate terminal of the source follower is connected to the FD node and serves as the input terminal of the amplifier. The common terminal may be connected to a power supply voltage. An amplified signal is generated at the output terminal of the amplifier based on the charge signal at the FD node. The amplifier may be used as a voltage buffer. The amplifier may be configured to buffer the signal, thereby isolating the FD node from further pixel components. The capacitor is electrically coupled to the output terminal of the amplifier via a switching transistor. The capacitors may have the same or similar capacitance.

[0011] In some embodiments, the transfer transistor is configured to be pulsed to different voltage levels to transfer portions of the stored charge carriers to the diffusion node. The different voltage levels may be partial voltage levels. Thus, the potential barrier between the photodetector and the diffusion node may be altered or modulated. Thus, the pixel array may be used for barrier modulation. Depending on the barrier, some of the stored charge carriers may overcome the barrier and be transferred to the diffusion node.

[0012] In some embodiments, at least the second capacitor is configured to store a low conversion gain signal representing a first portion of the accumulated charge carriers. The low conversion gain signal may be referred to as an LCG signal. The LCG signal may be stored in the second capacitor or may be redistributed to both the first and second capacitors. The LCG signal refers to a signal generated with a low gain. This may mean that the signal is based on only a portion of the accumulated charge carriers, particularly only the first portion. This may also mean that the LCG signal is additionally attenuated.

[0013] In some embodiments, the first capacitor is configured to store a high conversion gain signal representing the remaining portion of the accumulated charge carriers. The high conversion gain signal may be referred to as an HCG signal. The HCG signal is stored in the first capacitor. The HCG signal refers to a signal generated with a high gain. This may mean that the signal is based on the remaining portion of the accumulated charge carriers, which may be the main portion. This may also mean that the HCG signal is additionally amplified.

[0014] The pixel array barrier utilizes barrier modulation of the transfer gate. The barrier modulation can increase the dynamic range of the pixel array. Furthermore, only two capacitors are required to realize this function of the pixel array. This allows the area of ​​the pixel array to be reduced.

[0015] In one embodiment, a pixel array comprises: a photodetector configured to accumulate charge carriers by converting electromagnetic radiation; a transfer transistor electrically coupled to the photodetector; a diffusion node electrically coupled to the transfer transistor; a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage; a sample and hold stage comprising at least a first capacitor and a second capacitor; and an input of the sample and hold stage electrically coupled to the diffusion node through an amplifier; the transfer transistor configured to be pulsed to different voltage levels to transfer multiple portions of the accumulated charge carriers to the diffusion node; the at least second capacitor configured to store a low conversion gain signal representative of a first portion of the accumulated charge carriers; and the first capacitor configured to store a high conversion gain signal representative of a remaining portion of the accumulated charge carriers.

[0016] In one embodiment, the low conversion gain signal and the high conversion gain signal have a common noise level. The common noise level may consist of, among other things, thermal noise and reset noise. Therefore, the LCG signal may be used as a reference level for the HCG signal. This means that the HCG signal can be obtained using correlated double sampling (CDS). Because the HCG signal is used in low-light conditions, thermal noise is an important parameter. In this case, the LCG signal may comprise only noise without any video information. The HCG signal may be equal to the LCG signal plus an additional video signal, which may represent a pure video signal without noise. Therefore, the noise of the HCG signal is correlated with the noise of the LCG signal. Thermal noise and reset noise can be effectively suppressed by CDS. Performing CDS may mean that the LCG signal is subtracted from the HCG signal. In high-light conditions, the LCG is further processed. Here, thermal noise is less important because photon shot noise dominates at high illuminance. Double delta sampling (DDS) is sufficient here. Based on the respective amplitude levels, a decision can be made to use the LCG signal or the HCG signal for further processing.

[0017] In one embodiment, the high conversion gain signal indicates a calibration level for adjusting the pixel output signal according to a pixel-specific knee point value. Therefore, it is possible to adjust the pixel output signal based on the LCG signal and the HCG signal according to the pixel-specific knee point value determined based on the calibration level. Knowing the voltage level for barrier modulation and the HCG signal allows inferring information about the barrier. Therefore, the HCG signal can be used as a calibration level for the LCG signal. This may mean that the calibration level is equal to the HCG signal.

[0018] In one embodiment, the pixel array further includes a dual conversion gain transistor and a dual conversion gain capacitor. The dual conversion gain transistor connects the diffusion node to a terminal node of the dual conversion gain capacitor, and the reset transistor is electrically coupled to the diffusion node via the terminal node and the dual conversion gain transistor. The dual conversion gain may be abbreviated as DCG. The DCG capacitor may also be referred to as a third capacitor hereinafter. The DCG transistor may also be referred to as a coupling transistor hereinafter. The DCG transistor and the DCG capacitor may adjust the conversion gain of the LCG signal and the HCG signal.

[0019] In one embodiment, the pixel array further comprises at least two switching transistors, each of which is assigned to a respective capacitor of the sample-and-hold stage and couples a terminal node of the respective capacitor to an input of the sample-and-hold stage, and by applying a respective switch signal, the LCG signal and the HCG signal can be transferred to the respective capacitor and stored therein.

[0020] In one embodiment, the first capacitor and the second capacitor of the sample and hold stage are arranged in parallel, and in this embodiment, the capacitors can be independently controlled by assigned switching transistors.

[0021] In one embodiment, at least two capacitors of the sample-and-hold stage are arranged in cascade. In this embodiment, a first switching transistor couples the output terminal of the amplifier to a terminal node of the first capacitor. A second switching transistor couples the terminal node of the first capacitor to a terminal node of the second capacitor. Fewer circuit components are required than in a parallel arrangement.

[0022] In one embodiment, the sample and hold stage comprises only two capacitors.

[0023] In some embodiments, the sample and hold stage further comprises a predetermined number of additional capacitors, each configured to store an additional signal representative of an additional portion of the stored charge carriers, and each additional signal may indicate an additional calibration level for adjusting the pixel output signal.

[0024] In some embodiments, the pixel array comprises a further amplifier coupled to the output of the sample and hold stage, and a select transistor electrically connecting the further amplifier to the column bus.

[0025] Furthermore, there is provided an image sensor comprising a pixel array as described in one of the above embodiments. In particular, the image sensor may comprise an array of pixel arrays. This means that all features disclosed for the pixel array are also disclosed and applicable to the image sensor, and vice versa.

[0026] Image sensors can be conveniently utilized in optoelectronic devices such as smartphones, tablet computers, laptops, or camera modules. For example, camera modules are configured to operate in the visible range for photography and / or videography. Furthermore, pixel arrays are particularly suited to operating in global shutter mode because signals are stored in pixel-level memories, i.e., first and second capacitors. The global shutter mode is particularly suited to infrared applications, where the image sensor device further includes a light source synchronized with the pixels. Therefore, optoelectronic devices including such image sensors can also function in the infrared (IR) range, for example, for 3D imaging and / or identification purposes. Infrared-sensitive image sensors can be used in dark environments where a video feed is required. Such applications range from face unlocking of mobile phones to driver monitoring systems. In both of these applications, illuminators in the near-infrared (SWIR) spectrum can be deployed to prevent phone users / drivers from being dazzled by the light shining on them.

[0027] Furthermore, a method for operating a pixel array is provided. The pixel array described above can be preferably utilized for the method for operating a pixel array described herein. This can mean that the pixel array can be configured to operate according to the following method. All features disclosed for the pixel array and image sensor are also disclosed for the method for operating the pixel array, and vice versa.

[0028] In one embodiment of the method, the method includes accumulating charge carriers using a photodetector included in the pixel array during an exposure period during a first integration period. The method further includes pulsing a transfer transistor to a first voltage level during the exposure period at the end of the first integration period to transfer a portion of the accumulated charge carriers to the diffusion node, the portion being configured to be discharged to a power supply voltage. The first integration period is a portion of the exposure period. This may mean that the exposure period is subdivided into several integration periods, for example, a first integration period and a second integration period. The first voltage level may be a voltage level below a threshold voltage of the transfer transistor. This may mean that the first voltage level is a partial voltage level. Applying the first voltage level to the transfer transistor lowers a potential barrier between the photodetector and the diffusion node. Thus, excess charge carriers can overcome the lowered potential barrier and be transferred from the photodetector to the diffusion node. These excess charge carriers are referred to as the portion of accumulated charge carriers. The portion is configured to be discharged to the power supply voltage. This may mean that after the portion has been transferred to the diffusion node, the diffusion node is reset. The resetting of the diffusion node may be achieved by applying a reset signal to a reset transistor connected between the diffusion node and the pixel power supply terminal, as mentioned above. The draining of the portion may take place at the end of the exposure period or after the exposure period, for example at the beginning of a storage period or a dedicated draining period.

[0029] In some embodiments, the method further includes continuing to accumulate charge carriers using the photodetector during a second integration period during the exposure period. The second integration period is part of the exposure period. The second integration period follows the first integration period. The second integration period can immediately follow the first integration period. The exposure period can comprise or consist of the first integration period and the second integration period. The exposure period can comprise more integration periods. The charge carriers accumulated in the photodiode after the second integration period can comprise the charge carriers accumulated during the first integration period and the second integration period minus the amount of charge carriers that will be drained.

[0030] In one embodiment, the method further includes pulsing the transfer transistor to a first voltage level during a storage period to transfer a first portion of the accumulated charge carriers to the diffusion node and storing a low conversion gain signal representing the first portion of the accumulated charge carriers in at least a second capacitor coupled to the diffusion node. The storage period can be immediately after the exposure period. Transferring the first portion of the accumulated charge carriers can occur after resetting the diffusion node to drain a portion of the accumulated charge carriers. The first portion of the accumulated charge carriers is different from the amount of the accumulated charge carriers. However, because the first voltage level is again applied to the transfer gate, the potential barrier is lowered by the same amount. Therefore, the first portion of the accumulated charge carriers corresponds to the excess charge carriers accumulated during the second integration period. The first portion of the accumulated charge carriers is not drained but is stored. As mentioned above, when two capacitors are arranged in cascade, the LCG signal representing the first portion of the accumulated charge carriers can be distributed to both capacitors. When the capacitors are arranged in parallel, the LCG signal can be stored in the second capacitor. Storing the LCG signal can be achieved by applying a switch signal to each switch (switching transistor) assigned to a capacitor.

[0031] In one embodiment, the method further includes pulsing the transfer transistor to a full voltage level during the storage period to transfer a remaining portion of the stored charge carriers to the diffusion node, and storing a high conversion gain signal representing the remaining portion of the stored charge carriers in a first capacitor coupled to the diffusion node. Pulsing the transfer transistor to the full voltage level occurs after pulsing the transfer transistor to a first voltage level. The full voltage level may be a voltage level that exceeds a threshold voltage level of the transfer transistor. Thus, applying the full voltage level causes the transfer transistor to become conductive. Thus, applying the full voltage level causes a potential barrier between the photodetector and the diffusion node to be lower than the potential barrier when the first voltage level is applied. Specifically, the potential barrier may be completely dissipated. Thus, the remaining charge carriers stored in the photodetector are transferred to the diffusion node.

[0032] In some embodiments, the method further comprises reading out the low conversion gain signal and the high conversion gain signal stored in the capacitors during a readout period. The readout period may be immediately after the storage period. As mentioned above, reading out each signal may be performed by applying a select signal to a select transistor. The select signal connects the capacitor on which the signal is stored to a column bus of the pixel. As explained above, the capacitor may be electrically coupled to the column bus via an additional amplifier. The additional amplifier may be implemented as an additional source follower.

[0033] The described method involves modulating the barrier of a transfer transistor. This modulation can increase the dynamic range of a pixel array by draining a portion of the accumulated charge carriers under high-light conditions. The HCG signal contains a knee-point calibration value required during linearization of the pixel output signal. Knowing the respective lengths of the first and second integration periods and the first voltage level allows for the reconstruction of the linearized signal. The transfer transistor of each pixel is subject to variations and fluctuations in the manufacturing process. Therefore, the threshold voltage of the transfer transistor is different for each pixel. This can mean that the barrier between the photodetector and the diffusion node is different for each pixel when the first voltage level is applied. However, knowing the exact barrier level is important to overcome fixed pattern noise (FPN). From the first voltage level and the pixel's HCG signal (corresponding to the remaining portion of the accumulated charge carriers after applying the first voltage level), information about the dependence of the output signal on the barrier can be derived. Furthermore, because the first voltage level applied during the exposure period is also applied during the storage period, the ratio of the first integration period to the second integration period and the HCG signal can be used to determine how much charge carriers were drained to the supply voltage at the end of the first integration period. Given this amount and the LCG signal, the pixel output signal for use in high light conditions can be reconstructed.

[0034] Furthermore, the LCG signal may serve as a reference level for the HCG signal because the diffusion nodes are not reset between the storage of the LCG signal and the storage of the HCG signal, and therefore both signals are based on a common noise level. Thus, CDS can be performed for the HCG signal used in low light conditions (where the LCG signal contains only noise and no video information).

[0035] In one embodiment, the method includes accumulating charge carriers using a photodetector included in the pixel array during an exposure period, pulsing a transfer transistor to a first voltage level at the end of the first integration period to transfer a portion of the accumulated charge carriers to a diffusion node, the portion being configured to drain to a power supply voltage, and continuing to accumulate charge carriers using the photodetector during a second integration period. The method further includes pulsing the transfer transistor to a first voltage level during a storage period to transfer a first portion of the accumulated charge carriers to the diffusion node, storing a low conversion gain signal representative of the first portion of the accumulated charge carriers on at least a second capacitor coupled to the diffusion node, pulsing the transfer transistor to a full voltage level to transfer a remaining portion of the accumulated charge carriers to the diffusion node, and storing a high conversion gain signal representative of the remaining portion of the accumulated charge carriers on a first capacitor coupled to the diffusion node. The method further comprises reading out the low conversion gain signal and the high conversion gain signal stored on the capacitor during a readout period.

[0036] In some embodiments, the method further includes pulsing the transfer transistor at least one additional time to a respective additional voltage level during the exposure period and after the second integration period, with each additional pulsing configured to drain an additional portion of the stored charge carriers to the pixel power supply voltage. Following each additional pulsing, the photodetector continues to accumulate additional charge carriers during each additional integration period. In some examples, the additional voltage levels are the second voltage level or the third voltage level, respectively. In some examples, the additional integration periods are the third integration period or the fourth integration period, respectively. The third integration period may follow the pulse to the second voltage level. The fourth integration period may follow the pulse to the third voltage level, and so on. In other words, during the exposure period, the transfer transistor may be pulsed n times to several partial voltage levels, and charge is drained to the power supply. Draining multiple portions of the stored charge carriers to the power supply may occur after the exposure period. Therefore, the dynamic range may be further expanded because n additional barrier levels are available.

[0037] In some embodiments, successive pulses are applied during an exposure period at equal or decreasing voltage levels. In some examples, the first voltage level is greater than or equal to the second voltage level. In some examples, the second voltage level is greater than or equal to the third voltage level, and so on.

[0038] In some embodiments, the integration periods following the pulsed activation during the exposure period decrease with each integration period. This means that the time interval between the integration periods decreases. In some examples, the first integration period is longer than the second integration period. In some examples, the second integration period may be longer than the third integration period, which may be longer than the fourth integration period, and so on. In this way, the amount of accumulated charge carriers decreases with each integration period. Therefore, information about the amount of accumulated charge carriers drained is not lost and can be reconstructed based on knowledge of the voltage levels and integration periods. Therefore, it is possible to reconstruct the linearized pixel output signal.

[0039] In one embodiment, the high conversion gain signal indicates a calibration level based on the remaining portion of the stored charge carriers. The HCG signal includes a calibration level because the first voltage level applied during the exposure period is also applied during the storage period.

[0040] In some embodiments, the method further includes adjusting the pixel output signal based on the low conversion gain signal and / or the high conversion gain signal in response to a pixel-specific knee-point value determined based on the calibration level. Given the first voltage level and the HCG signal, information about the barrier can be derived. Therefore, the HCG signal can be used as a calibration level for the LCG signal. This may mean that the calibration level is equal to the HCG signal. In other words, information about the drained portion of the accumulated charge carriers is not lost and can be reconstructed based on the first voltage level, the HCG signal, and the integration period. Furthermore, the calibration level is required in post-processing to remove FPN caused by transfer transistor variations. The calibration level can also be used as a reference for removing FPN variations caused by the additional n-1 pulses generated during integration.

[0041] In one embodiment, reading out the low conversion gain signal comprises double delta sampling (DDS). DDS can be performed by using a reset level as a reference level for the LCG signal. The reset level can be read out at a step during the readout period, for example, after the HCG signal and the LCG signal are read out. Resetting the FD node is performed by applying a reset signal to a reset transistor. The reset level refers to a non-video signal of the pixel array, i.e., it does not involve a video signal from the photodetector. Resetting the FD node introduces additional noise that is uncorrelated with the noise of the HCG signal and the LCG signal. However, the reset level of the pixel array comprises information about fixed pattern noise (FPN).

[0042] In one embodiment, reading the high conversion gain signal comprises correlated double sampling. As mentioned above, the LCG signal can be used as a reference level for the HCG signal to perform CDS because both signals are based on a common noise level. Therefore, the LCG signal can be subtracted from the HCG signal.

[0043] In one embodiment, the diffusion node is not reset between transferring the first portion of the stored charge carriers and transferring the remaining portion of the stored charge carriers, so that the high conversion gain signal and the low conversion gain signal are based on a common noise level.

[0044] In some embodiments, the method further includes pulsing the transfer transistor to respective additional voltage levels during the storage period to transfer additional portions of the accumulated charge carriers to the diffusion node, and storing additional signals representing the additional portions of the accumulated charge carriers in additional capacitors coupled to the diffusion node. This may mean that the S / H stage may include additional capacitors arranged in cascade with or in parallel with the first and second capacitors. The additional voltage levels may be the respective voltage levels applied during the exposure period. That is, the additional voltage levels may be the second voltage level, the third voltage level, etc. Pulsing the transfer transistor to the respective additional voltage levels may precede pulsing the transfer transistor to the first voltage level during the storage period. The order in which the corresponding voltage levels are applied during the storage period may be the reverse of the order in which the corresponding pulses are applied during the exposure period. Thus, the corresponding additional portions of the accumulated charge carriers may serve as additional calibration levels, providing information about the amount of charge carriers ejected to the respective voltage levels during the exposure period in the corresponding pulses.

[0045] In one embodiment, the further signal indicates a further calibration level based on a further portion of the stored charge carriers, and the step of adjusting the pixel output signal is performed in response to a further pixel-specific knee-point value determined based on the further calibration level.

[0046] In an embodiment, the method further comprises reading out the further signal stored on the further capacitor during the readout period, wherein reading the further signal comprises correlated double sampling, which may mean that the further signal, the LCG signal, and the HCG signal are based on a common noise level.

[0047] Further, another method for operating a pixel array is provided. The pixel array described above can also be used for this operating method. This means that all features disclosed for the pixel array and image sensor are also disclosed for the following method of operating a pixel array, and vice versa. Furthermore, aspects of the method discussed above are also important for the following method. Thus, embodiments of the above method are also disclosed and applicable to the following method.

[0048] In one embodiment, a method for operating a pixel array includes accumulating charge carriers using a photodetector included in the pixel array during an exposure period. The method further includes performing the following steps during the accumulation: a first step of pulsing a transfer transistor to a first voltage level to transfer a portion of the accumulated charge carriers to a diffusion node, the portion being configured to be drained to a power supply voltage; a second step of pulsing the transfer transistor to the first voltage level to transfer a further portion of the accumulated charge carriers to the diffusion node, the further portion being configured to be drained to the power supply voltage; a second step of pulsing the transfer transistor to the first voltage level to transfer a first portion of the accumulated charge carriers to the diffusion node; and storing a low conversion gain signal representative of the first portion of the accumulated charge carriers in at least a second capacitor coupled to the diffusion node. At the end of the exposure period, the method further includes pulsing the transfer transistor to a full voltage level to transfer a remaining portion of the accumulated charge carriers to the diffusion node. After the pulsing to the full voltage level, the method further comprises storing a high conversion gain signal representative of a remaining portion of the stored charge carriers in a first capacitor coupled to the diffusion node.

[0049] In an embodiment, the method further comprises reading out the low conversion gain signal and the high conversion gain signal stored on the capacitor during a readout period.

[0050] The second voltage level may be lower than the first voltage level. The first voltage level may be lower than the full voltage level. The full voltage level may be, for example, 2.8 V. The first voltage level may be, for example, 0.8 V. The second voltage level may be, for example, 0.4 V. Storing the high conversion gain signal and the low conversion gain signal in the capacitor may occur during a storage period. Thus, the storage period may overlap with the exposure period. The period from the first pulse to the first voltage level to the second pulse to the first voltage level may be referred to as the first integration period. The period from the pulse to the second voltage level to the second pulse to the first voltage level may be referred to as the second integration period. Thus, the second integration period is shorter than the first integration period and overlaps with the first integration period. As described above, draining that portion and further portions of the stored charge carriers is accomplished by applying a reset signal to the reset transistor.

[0051] Advantageously, the method for operating a pixel array uses barrier modulation of transfer transistors to increase the dynamic range of the pixel array. Advantageously, only storage capacitors, i.e., a first capacitor and a second capacitor, are required, one of which stores an LCG signal representing a first portion of the accumulated charge carriers, and the other of which stores an HCG signal representing the remaining portion of the accumulated charge carriers. Advantageously, the pixel output signal can be reconstructed based on the LCG signal and the HCG signal. The HCG signal can indicate a calibration level for barrier modulation, particularly in strong light conditions. The LCG signal can indicate a reference level for correlated double sampling, particularly in weak light conditions.

[0052] In some embodiments, a first portion of the accumulated charge carriers is stored by applying a low conversion gain. This may mean that the LCG signal is sampled / stored at a low conversion gain. This may be achieved by enabling a coupling signal to the coupling transistor. The coupling transistor may be referred to as a dual conversion gain transistor. In some embodiments, the remaining portion of the accumulated charge carriers is stored by applying a high conversion gain. This may mean that the HCG signal is sampled / stored at a high conversion gain. This may be achieved by disabling the coupling signal. By applying the coupling signal to the dual conversion gain transistor, the diffusion node is electrically connected to the dual conversion gain capacitor, which may be referred to as the third capacitor. Thus, the diffusion node and the dual conversion gain capacitor may be shorted. By shorting the diffusion node and the dual conversion gain capacitor, the overall capacitance increases. If the charge is kept constant, this leads to a decrease in the voltage signal. Therefore, the voltage on the diffusion node may be reduced. Therefore, by increasing the capacitance, the gain decreases. This means that if the diffusion node and the third capacitor are shorted, the gain of the pixel array decreases. In other words, if the third capacitor is electrically disconnected from the diffusion node, the gain of the pixel array increases. Thus, two different conversion gains can be provided. The use of dual gains allows for a larger dynamic range of the pixel array. Advantageously, dual gains can be combined with barrier modulation, allowing for an even larger dynamic range. Advantageously, only two storage capacitors are required: a first capacitor and a second capacitor. Thus, in dual conversion gain mode, both gains are stored in pixel-level capacitors and are available for reconstruction at the column level.

[0053] The first capacitor and the second capacitor may be arranged in parallel or in cascade. Before the exposure period, there may be a reset period to remove any excess charge carriers from the photodiode and the diffusion node.

[0054] After the pulse to the second voltage level, there may be further pulses to further voltage levels, as described above, which may mean that in some embodiments the method further comprises, after the pulsing to the second voltage level, pulsing the transfer transistor at least one additional time to each further voltage level, with each additional pulsing configured to drain an additional quantity of stored charge carriers into the pixel supply voltage.

[0055] In some embodiments, the voltage levels at which successive pulses are applied are equal or decrease with each pulse. In some embodiments, the high conversion gain signal indicates a calibration level based on a remaining portion of the accumulated charge carriers. In some embodiments, the method further comprises adjusting the pixel output signal based on the low conversion gain signal and / or the high conversion gain signal in response to a pixel-specific knee-point value determined based on the calibration level. In some embodiments, reading the low conversion gain signal is a double delta sampling read. In some embodiments, reading the high conversion gain signal is a correlated double sampling read.

[0056] Further embodiments of the method will be apparent to those skilled in the art from the pixel array embodiments and methods of operating the pixel array described above, and vice versa. The pixel array may form a voltage-domain global shutter pixel. Alternatively, the pixel array may form a rolling shutter pixel. The disclosed method achieves HDR without affecting the pixel's pipeline mode (pipelining of each signal to the S / H capacitor). The dynamic range can be further extended by using multiple barriers. The pixel array can have a smaller area by utilizing only two S / H capacitors. Furthermore, low-light performance can be improved by utilizing dual conversion gain components. Because the method utilizes self-calibrating barrier modulation, no additional readings are required. This is possible because the HCG signal includes a calibration level as a reference level for calibrating additional barriers. The present disclosure applies to any system in which one of the readings is used as knee-point calibration and additional knee points are used to calibrate using the first knee-point as the reference level.

[0057] Furthermore, there is provided a method for operating an imaging device, the imaging device comprising a pixel array as described above, which means that all features disclosed for the pixel array and the image sensor are also disclosed for the method of operating the imaging device and vice versa.

[0058] In one embodiment, a method of operating an imaging device includes: During the exposure period, accumulating charge carriers using a photodetector of a pixel of the imaging device during a first integration period; a first step of pulsing a transfer transistor to a first voltage level at the end of a first integration period, the transfer transistor being electrically coupled to the photodetector; continuing to accumulate charge carriers with the photodetector during a second integration period; a second step of pulsing the transfer transistor to a second voltage level at the end of the second integration period; continuing to accumulate charge carriers with the photodetector during a third integration period; During the storage period, resetting a diffusion node electrically coupled to the transfer transistor and a gain conversion node electrically coupled to the diffusion node; a third step of pulsing the transfer transistor to a first voltage level to transfer a first portion of the stored charge carriers to the diffusion node and the gain conversion node; storing a low conversion gain signal representative of a first portion of the accumulated charge carriers in a pair of capacitors electrically coupled to the diffusion node; a fourth step of pulsing the transfer transistor to a threshold voltage level to transfer the remaining portion of the stored charge carriers to the diffusion node; storing a high conversion gain signal representative of the remaining portion of the stored charge carriers in a first capacitor of the pair of capacitors; During the readout period, and reading out the low conversion gain signal and the high conversion gain signal stored in the pair of capacitors.

[0059] In some embodiments, the method further comprises: During the exposure period, after the third integration period, further pulsing the transfer transistor at least once to each further voltage level; After each additional pulsing, the photodetector continues to accumulate additional charge carriers during each additional integration period.

[0060] In one embodiment, each pulse during the exposure period drains a portion of the stored charge carriers into the pixel supply voltage.

[0061] In one embodiment, the first voltage level is higher than the second voltage level.

[0062] In one embodiment, reading out the low conversion gain signal comprises double delta sampling, and reading out the high conversion gain signal comprises correlated double sampling.

[0063] In one embodiment, the diffusion node is not reset between transferring the first portion of the stored charge carriers and transferring the remaining portion of the stored charge carriers, so that the high conversion gain signal and the low conversion gain signal are based on a common noise level.

[0064] In some embodiments, the high conversion gain signal indicates a calibration level based on the remaining fraction of stored charge carriers.

[0065] In an embodiment, the method further comprises adjusting the pixel output signal based on the read low and high conversion gain signals in response to a pixel-specific knee-point value determined based on the calibration level.

[0066] Furthermore, there is provided an imaging device comprising a pixel array as described above, which means that all features disclosed for the pixel array and image sensor are also disclosed for the imaging device and vice versa.

[0067] In one embodiment, the imaging device comprises a plurality of pixels, each pixel comprising: a photodetector configured to accumulate charge carriers by converting electromagnetic radiation; a transfer transistor electrically coupled to the photodetector; a diffusion node electrically coupled to the transfer transistor; a gain conversion node electrically coupled to the diffusion node via a gain switch; a reset switch electrically coupled to the diffusion node through the gain switch; a sample-and-hold stage comprising a pair of capacitors, the input of the sample-and-hold stage being electrically coupled to the diffusion node through an amplifier; the transfer transistor is configured to be pulsed to different voltage levels; a pair of capacitors configured to store a low conversion gain signal representative of a first portion of the accumulated charge carriers; A first capacitor of the pair of capacitors is further configured to store a high conversion gain signal representative of the remaining portion of the stored charge carriers.

[0068] In some embodiments, the imaging device further comprises a dual gain capacitor electrically coupled to the gain conversion node.

[0069] In one embodiment, the pair of capacitors comprises a first capacitor and a second capacitor, a first terminal of the first capacitor electrically coupled to the amplifier via a first switch, a first terminal of the second capacitor electrically coupled to the first terminal of the first capacitor via a second switch, forming an output of the sample and hold stage, and second terminals of both capacitors electrically connected to a constant voltage node.

[0070] In some embodiments, the imaging device further comprises a selector switch that electrically connects the output of the sample and hold stage to the column bus through a further amplifier.

[0071] The following description of the drawings may further illustrate and explain aspects of the pixel array and methods of operating the pixel array. Components and portions of the pixel array that are functionally identical or have the same effect are designated by the same reference symbols. Identical or substantially identical components and portions are described only with respect to the drawing in which they first appear. Their descriptions are not necessarily repeated in successive drawings. [Brief explanation of the drawings]

[0072] [Figure 1] FIG. 1 illustrates an exemplary embodiment of a pixel array. [Figure 2] FIG. 1 illustrates an exemplary embodiment of an image sensor. [Figure 3] FIG. 2 illustrates exemplary operations performed by a pixel array. [Figure 4] FIG. 2 illustrates exemplary signal timing for a pixel array. [Figure 5] FIG. 10 shows the charge in the photodiode during barrier modulation. [Figure 6] FIG. 1 illustrates exemplary characteristics of a pixel array. [Figure 7] FIG. 1 shows a linear reconstructed signal. [Figure 8] FIG. 2 illustrates another exemplary embodiment of a pixel array. [Figure 9] FIG. 2 illustrates another exemplary embodiment of a pixel array. [Figure 10] FIG. 10 illustrates another exemplary signal timing diagram for a pixel array. DETAILED DESCRIPTION OF THE INVENTION

[0073] 1, an exemplary embodiment of a pixel array 10 included in an image sensor 200 is shown. The illustrated pixel array 10 can be operated to achieve a high dynamic range (HDR). The pixel array 10 is configured to convert electromagnetic radiation into a high conversion gain (HCG) signal and a low conversion gain (LCG) signal.

[0074] The pixel array 10 includes a photodiode 20 configured to convert electromagnetic radiation into charge carriers. The photodiode 20 may also be referred to as a photodetector 20. The photodiode 20 includes an anode terminal and a cathode terminal. The anode terminal of the photodiode 20 is connected to a negative pixel power supply voltage VSS, which may be ground (GND). The photodiode 20 may convert light of any wavelength, for example, visible light, infrared light, and / or ultraviolet light.

[0075] The pixel further includes a transfer transistor 30 between the photodiode 20 and a diffusion node 42. The transfer transistor 30 acts as a switch. The transfer transistor 30 is configured to be pulsed to different voltage levels to transfer portions of the stored charge carriers to the diffusion node 42. A first terminal of the transfer transistor 30 is electrically connected to the cathode terminal of the photodiode 20. A second terminal of the transfer transistor 30 is electrically connected to the diffusion node 42. The diffusion node 42 may hereinafter be referred to as a floating diffusion (FD) node. The FD node 42 may have or be connected to a capacitance 40 (shown in FIG. 8). The capacitance may be implemented as a capacitor (not shown) and may be referred to as an FD capacitance. Alternatively, the capacitance may be formed by parasitic capacitance. The transfer transistor 30 is configured to receive a transfer signal TX to transfer charge carriers from the photodiode 20 to the FD node 42. The FD node 42, and in particular the FD capacitance, is configured to buffer or temporarily store charge carriers from the photodiode 20. The FD capacitance can be configured to convert charge carriers into a voltage signal.

[0076] The pixel array 10 further includes a reset transistor 50 electrically coupled to the FD node 42 for resetting the FD node 42. The reset transistor 50 acts as a switch. A first terminal of the reset transistor 50 is electrically connected to a pixel power supply voltage VDD. A second terminal of the reset transistor 50 is electrically connected to the FD node 42 via a coupling transistor 140. The coupling transistor 140 may be named a dual conversion gain (DCG) transistor 140. The reset transistor 30 is configured to receive a reset signal RST for resetting the FD node 42 by applying the pixel power supply voltage VDD, thereby draining any excess charge carriers.

[0077] The pixel array 10 further includes an amplifier 60, which is electrically connected to the FD node 42. The amplifier 60 is configured to generate a low conversion gain (LCG) signal and a high conversion gain (HCG) signal, respectively, in response to the capacitance voltage at the FD node 42. As shown in FIG. 1, the amplifier 60 may form a common-drain amplifier, also known as a source follower. A gate terminal 62 of the source follower is connected to the FD node 42 and serves as an input terminal 62 of the amplifier 60. The common terminal is connected to a power supply voltage VDD. Respective amplified signals are generated at output terminals 64 of the amplifier 60.

[0078] The pixel array 10 further includes a first capacitor 70 and a second capacitor 80. The first capacitor 70 includes a terminal node 72 and a further terminal node 74. As shown in FIG. 1, the further terminal node 74 may be connected to a reference potential VSS1. The second capacitor 80 further includes a terminal node 82 and a further terminal node 84. As shown in FIG. 1, the further terminal node 84 may be connected to a reference potential VSS1. At least the second capacitor 80 is configured to store an LCG signal representing a first portion of the accumulated charge carriers. The first capacitor 70 is configured to store an HCG signal representing the remaining portion of the accumulated charge carriers.

[0079] The pixel array 10 further includes a first switch 90 between the output terminal 64 of the amplifier 60 and the first capacitor 70. The first switch 90 is provided to transfer the LCG signal and the HCG signal to one or both of the capacitors 70, 80. The first switch 90 may be formed by a first switching transistor 90. The first switching transistor has a gate terminal configured to receive a first switch signal S1. A first terminal of the first switching transistor 90 is connected to the output terminal 64 of the amplifier 60. A second terminal of the first switching transistor 90 is connected to the terminal node 72 of the first capacitor 70.

[0080] The pixel array 10 further includes a second switch 100 disposed between the output terminal 64 of the amplifier 60 and the second capacitor 80. The second switch 100 is provided to transfer the LCG signal or the HCG signal to the second capacitor 80. The second switch 100 may be formed by a second switching transistor 100. The second switching transistor 100 may have a gate terminal configured to receive a second switch signal S2. A first terminal of the second switching transistor 100 is connected to a second terminal of the first switching transistor 90 and a terminal node 72 of the first capacitor 70. A second terminal of the second switching transistor 100 is connected to a terminal node 82 of the second capacitor 80.

[0081] 1 further comprises a precharge transistor 160 electrically coupled to the output terminal 64 of the amplifier 60. The precharge transistor 160 may be provided for precharging the first capacitor 70 and the second capacitor 80, which may in particular mean that the capacitors 70, 80 are discharged before a new signal is stored therein. The precharge transistor 160 has a first terminal connected to the output terminal 64 of the amplifier 60 and a second terminal connected to a reference potential VSS1. By applying a precharge signal PC to the precharge transistor 160, the first capacitor 70 and the second capacitor 80 are discharged and a bias current flows through the amplifier 60.

[0082] In an alternative embodiment not shown, the second terminal of the precharge transistor 160 is connected to a further reference potential VSS_PC, which may be different from the reference voltage VSS1.

[0083] 1 further comprises a further amplifier 100, which has an input terminal 112 electrically connected to the second capacitor 80 and is configured to generate a pixel output signal at an output terminal 114 of the further amplifier 110. Like the amplifier 60, the further amplifier 110 may be implemented as a source follower, with the gate 112 serving as the input terminal 112 and the common terminal being connected to a pixel supply voltage VDD.

[0084] The pixel array 10 further comprises a select transistor 120 between the output terminal 114 of the further amplifier 110 and the column bus 130 for transferring the pixel output signal to the column bus 130. The select transistor 120 has a first terminal connected to the output terminal 114 of the further amplifier 110 and a second terminal connected to the column bus 130. By applying a select signal SEL to the select transistor 120, the pixel output signal is transferred to the column bus 130.

[0085] The pixel array 10 further includes a coupling transistor 140 between the FD node 42 and the reset transistor 50. The pixel array 10 further includes a third capacitor 150. The third capacitor 150 includes a terminal node 152 and a further terminal node 154. The further terminal node 154 of the third capacitor 150 is connected to a second further reference potential Vref, which may be VSS. The coupling transistor 140 has a first terminal connected to the FD node 42 and a second terminal connected to the terminal node 152 of the third capacitor 150. By applying a coupling signal DCG to the coupling transistor 140, the FD node 42 is shorted to the terminal node 152 of the third capacitor 150. Therefore, the overall capacitance increases, and the conversion gain decreases. The coupling transistor 140 may be named a dual conversion gain transistor 140, and the third capacitor 150 may be named a dual conversion gain capacitor 150. The coupling signal DCG may be referred to as a dual conversion gain signal DCG.

[0086] The capacitance of the FD node 42 comprises, for example, the input terminal 62 of the amplifier 60, the capacitance of the pn junction of the terminal of the transfer transistor 30, and the capacitance of the pn junction of the first terminal of the coupling transistor 140. Thus, the parasitic capacitance of the transistors connected to the FD node 42 may result in the capacitance of the FD node 42. The value of the capacitance of the FD node 42 may be the sum of the values ​​of the parasitic capacitance of the transistors connected to the FD node 42. Optionally, the pixel array 10 includes, for example, a capacitor (not shown) connected to the FD node 42. This capacitor may contribute to the capacitance.

[0087] For example, the capacitance of the first capacitor 70 and the capacitance of the second capacitor 80 are equal. The capacitance of the first capacitor 70 is higher than, for example, the capacitance value of the FD node 42. The capacitance of the second capacitor 80 is higher than, for example, the capacitance value of the FD node 42. The capacitance of the third capacitor 150 is higher than, for example, the capacitance value of the FD node 42. The first capacitor 70 and the second capacitor 80 are realized, for example, as metal-insulator-metal capacitors or metal-insulator-semiconductor capacitors. The third capacitor 150 is realized, for example, as a metal-insulator-metal capacitor or metal-insulator-semiconductor capacitor.

[0088] First and second capacitors 70 and 80 and first and second switching transistors 90 and 100 form a sample-and-hold stage that is electrically coupled to diffusion node 42 through amplifier 60. Amplifier 60 and / or a further amplifier 110 and / or pre-charge transistor 160 may be part of the sample-and-hold stage.

[0089] 2 shows an exemplary embodiment of an image sensor 200 with pixel arrays 10. The image sensor 200 comprises an array of pixel arrays 10. In addition, the image sensor 200 further comprises a row driver 204 that provides a transfer signal TX, a coupling signal DCG, a reset signal RST, a precharge signal PC, a first switch signal S1, a second switch signal S2, and a select signal SEL to the array of pixel arrays 10. The row driver 204 provides these signals for each of the rows. The image sensor 200 includes an evaluation circuit 205 for digitizing the signals on the column bus 130.

[0090] In the following, the operation of the pixel array 10 will be described. Figure 3 shows exemplary operations performed by the pixel array 10 shown in Figure 1. In Figure 3, the operations are shown in blocks. A method for operating the pixel array 10 comprises the following blocks, which may be named, for example, as procedures or steps:

[0091] Block 350: Start of exposure: Electromagnetic radiation is converted into charge carriers by the photodiode 20. This means that the charge carriers are accumulated in the photodiode 20. This stage may be called the exposure period EP. The exposure period EP may be subdivided into several subsequent integration periods T1, T2, T3, etc. The number of integration periods may be at least two.

[0092] Block 351: The transfer barrier is modified based on system inputs. A transfer signal TX provided to the transfer transistor 30 controls the barrier between the photodiode 20 and the FD node 42. The transfer transistor is pulsed to a first voltage level V1 of the transfer signal TX. The first voltage level V1 of the transfer signal TX is selected to lower the barrier for charge carrier flow between the photodiode 20 and the FD node 42, which means that a certain amount of the accumulated charge carriers are transferred to the FD node 42. The charge carriers then continue to accumulate. The transfer transistor can be pulsed to a second voltage level V2 of the transfer signal TX. The second voltage level V2 of the transfer signal TX can be selected so that the first voltage level V1 is greater than the second voltage level V2. A second pulse transfers an additional amount of the accumulated charge carriers to the FD node 42. Any number of pulses can be applied during the entire exposure. For example, a third pulse to a third voltage level V3 is applied. In one example, the first voltage level V1 is greater than or equal to the second voltage level V2. In general, the voltage level of each subsequent pulse can be less than or equal to the voltage level of the preceding pulse. This can mean that V1 ≥ V2 ≥ V3, etc.

[0093] The quantity of stored charge carriers is to be discharged to the pixel supply voltage VDD. Discharging the quantity to the pixel supply voltage VDD can be done by simultaneously applying the reset signal RST and the coupling signal DCG, so that the FD node 42 is electrically connected to the pixel supply voltage VDD. Discharging the quantity can be done during the exposure period EP, at the end of the exposure period EP, or after the exposure period EP, for example at the beginning of the storage period FS or in a dedicated discharge period D (see Figure 4).

[0094] In other words, during the entire exposure time, the transfer transistor 30 may be pulsed n times to some partial level and the charge is drained to the power supply VDD through the DCG transistor 140 and the reset transistor 150. Thus, multiple barriers may be used during exposure and calibrated to use the first barrier level as a reference point to further extend the dynamic range.

[0095] In one example, after a first integration period T1, the transfer transistor 30 is pulsed to a first (partial) voltage level V1, which drains a portion of the photodiode charge to the power supply VDD. After some time, the transfer transistor 30 can be pulsed again to a second voltage level V2. The time between the first pulse to the first voltage level V1 and the second pulse to the second voltage level V2 can be termed the second integration period T2. The time after the second pulse to the second voltage level V2 can be termed the third integration period T3. The first voltage level V1 can be greater than the second voltage level V2, i.e., V1>V2.

[0096] Block 352: A first portion of the charge carriers accumulated by the photodiode 20 is transferred to the FD node 42 and the third capacitor 150. A pulse of the transfer signal TX is applied to the transfer transistor 30 corresponding to the first voltage level V1, which means that the first voltage level V1 is applied to the transfer transistor 30. A pulse of the coupling signal DCG is applied to the coupling transistor 140. A first portion of the charge carriers corresponding to the charge carriers accumulated in the last integration period is transferred from the photodiode 20 to the FD node 42 and the capacitance 40 of the third capacitor 150 via the transfer transistor 30 and the coupling transistor 140. Thus, the charge carriers generate a capacitance voltage VC at the input 62 of the amplifier 60. Because the overall capacitance of the FD node and the third capacitor is large, the gain of the signal applied at the input terminal 62 of the amplifier 60 is reduced (low gain).

[0097] Block 353: In a first stage FS1 of the storage period FS, a first portion of charge carriers is stored in the first capacitor 70 and the second capacitor 80. The first switching transistor 90 and the second switching transistor 100 are set to a conductive state to transfer the first portion of charge carriers from the FD node 42 to the second capacitor 80. This may mean that an amplified capacitance voltage is applied to the first capacitor 70 and the second capacitor 80. The second switch signal S2 may have a short pulse to equalize the voltages at the first capacitor 70 and the second capacitor 80. This may mean that the signal is redistributed to the first capacitor 70 and the second capacitor 80. The amplified capacitance voltage corresponds to a low conversion gain (LCG) signal.

[0098] Block 354: Reading of the second capacitor 80 in the first stage RO1 of the read period RO. The output voltage VO drawn from the second capacitor 80 is amplified by a further amplifier 110. When the selection transistor 120 is set to the conducting state in the first read stage RO1 of the read period RO, the amplified output voltage is applied to the column line 130 for digitization. The first digitized value is generated as a function of the first value of the output voltage VO, for example, by an evaluation circuit (shown in FIG. 2). The first value of the output voltage VO corresponds to the LCG signal.

[0099] Block 355: Transfer of the remaining charge carriers to the FD node 42. The second pulse of the transfer signal TX is applied to the transfer transistor 30 for transferring the remaining charge carriers from the photodiode 20 to the FD node 42. Since the second pulse can correspond to the full voltage level Vf of the transfer transistor 30, the barrier between the photodiode 20 and the FD node 42 is minimized or eliminated.

[0100] The first voltage level V1 of the transfer signal results in a higher barrier than the full voltage level Vf. In one example, V1 < Vf. Since the coupling transistor 140 remains in the non-conducting state, the single capacitance of the FD node 42 increases the gain of the signal applied at the input terminal 62 of the amplifier 60.

[0101] Block 356: Store the remaining charge carriers accumulated by the photodiode 20 in the first capacitor 70 in the second stage FS2 of the storage period FS. This can mean that the capacitance voltage VC drawn at the FD node 42 is amplified by the amplifier 60. The amplified capacitance voltage is applied to the first capacitor 70 by applying a pulse of the first switch signal S1 to the first switching transistor 90. The amplified capacitance voltage corresponds to the high conversion gain (HCG) signal.

[0102] Block 357: Reading of the first capacitor 70 during the second phase RO2 of the readout period RO. After the output voltage VO at the second capacitor 80 is read in block 354 during the first readout phase RO1, the second switching transistor 100 is set to a conductive state. Thus, the voltages at the first capacitor 70 and the second capacitor 80 are equal. Since the capacitance voltage VC is still amplified by the amplifier 60, the output voltage VO at the second capacitor 80 is equal to the amplified capacitance voltage. The output voltage VO is amplified by the further amplifier 110. When the selection transistor 120 is set to a conductive state during the second readout phase RO2 of the readout phase RO, the amplified output voltage is provided to the column line 130 for digitization. A second digitized value is generated by the evaluation circuit as a function of the second value of the output voltage VO. The second value of the output voltage VO corresponds to the HCG signal.

[0103] Typically, the steps of blocks 352, 353, 355, and 356 are performed during the frame storage period FS, and the steps of blocks 354 and 357 are performed during the readout period RO.

[0104] Block 358: Subtract the voltage of the second capacitor 80 or the digitized value of the voltage of the second capacitor 80 from the voltage of the first capacitor 70 or the digitized value of the voltage of the first capacitor 70. The output signal representing the illuminance IL of the photodiode 20 is a function of the first digitized value (obtained from block 353) and the second digitized value (obtained from block 357). In one example, the first digitized value (obtained from block 353) is subtracted from the second digitized value (obtained from block 357) by the evaluation circuit. This operation allows the HCG signal to be obtained using correlated double sampling (CDS) because the first (digitized) value and the second (digitized) value are based on a common noise level.

[0105] Block 359: Increase the gain of the LCG signal. This may mean that the LCG signal is adjusted. Specifically, the LCG signal may be amplified. Adjusting or amplifying the LCG signal may be performed by the evaluation circuit 205. The LCG signal is sampled at a lower gain by the third capacitor 150 (dual conversion gain capacitor 150) to increase the dynamic range. To correct this gain adjustment, the gain of the LCG signal is increased in block 359. Additionally, the LCG signal may be obtained using double delta sampling (DDS). The LCG signal is used in cases of high illumination, where photon shot noise is dominant and thermal noise is not significant. Therefore, correlated double sampling is not necessary to remove noise from the video signal. However, it may be desirable to remove fixed pattern noise (FPN) from the video signal. By performing double delta sampling (DDS), FPN can be removed from the LCG signal. The DDS may be performed by subtracting a reset level from the LCG signal, which may be read out in a third phase RO3 of the readout period RO after the second readout phase RO2.

[0106] Block 360: For each pixel knee-point calibration, the HCG signal includes the first calibration level required for post-processing to remove FPN caused by variations in the transfer transistor 30, which affect its threshold voltage. Because the same first voltage level V1 applied for barrier modulation during the exposure period is also applied during frame storage, the HCG signal includes the knee-point calibration value needed during linearization and for FPN correction. Knee-point corrections for additional pulses of the transfer transistor 30 (e.g., to a second voltage level V2) during integration can be mapped, utilizing the exact calibration value of the first voltage level V1 as a reference point. The calibration value is also used as a reference for removing FPN variations caused by additional pulses generated during integration. Because any number of pulses can be applied during the entire exposure, the exact calibration value of the first voltage level V1 can also be used as a reference for correcting for such additional pulses. For example, for a third pulse to a third voltage level V3, the V3 pulse can be corrected by using the exact level of V1 as a reference. Knee-point calibration is performed separately for each pixel. Furthermore, the pixel array 10 is self-calibrating because the barrier information is contained in the HCG signal. Therefore, no additional readout is required. Block 360 is optional.

[0107] Block 361: Linearization. It is possible to reconstruct a linearized pixel output signal, i.e. a pixel output signal that is linearly dependent on the illumination level. Such reconstruction is described below. The length of the integration period can be used to reconstruct the pixel output signal. The voltage levels V1, V2, etc. of the pulses for barrier modulation of the transfer transistor 30 can optionally be used to reconstruct the pixel output signal.

[0108] 4 shows an exemplary timing diagram implemented by the pixel array 10 shown in FIG. 1. The following signals are shown as a function of time: transfer signal TX, coupling signal DCG, reset signal RST, first switch signal S1, and second switch signal S2. Note that the signal timings shown are rather exemplary and may vary. Furthermore, the scale of the time intervals should not be construed as a strict indication.

[0109] FIG. 4 shows a reset period R, an exposure period EP, a discharge period D, and a (frame) storage period FS. The readout period RO is not shown. The readout period RO follows the storage period FS. The storage period FS follows the exposure period EP. The exposure period EP follows the reset period R. The exposure period EP includes a first integration period T1, a second integration period T2, and a third integration period T3. The third integration period follows the second integration period T2, and the second integration period T2 follows the first integration period T1. The storage period FS includes a first storage step FS1 and a second storage step FS2. The second storage step FS2 follows the first storage step FS1. The storage period FS may be a global storage period for each pixel in the pixel array. The readout period RO may be performed separately for each row. Therefore, there may be a time gap between the second storage step FS2 and the readout period RO.

[0110] During the reset period R, the reset signal RST, the coupling signal DCG, and the transfer signal TX are applied. This may mean that the reset transistor 50, the coupling transistor 140 (dual conversion gain transistor 140), and the transfer transistor 30 are pulsed to drain any excess charge carriers by connecting the photodiode 20 and the FD node 42 to the pixel supply voltage VDD. The transfer transistor 30 may be pulsed to the full voltage level Vf.

[0111] During the first integration period T1, charge carriers are accumulated by the photodiode 20. The amount of accumulated charge carriers depends on the length of the first integration period T1. At the end of the first integration period T1, the transfer gate 30 is pulsed to a first voltage level V1. This leads to the transfer of a portion of the accumulated charge carriers to the diffusion node 42. Said portion is configured to be discharged to the pixel supply voltage VDD in a final stage.

[0112] After the pulse of transfer gate 30, charge carriers continue to be accumulated by photodiode 20 during a second integration period T2, which may be shorter than the first integration period T1. The amount of accumulated charge carriers during the second integration period T2 depends on the length of the second integration period T2.

[0113] At the end of the second integration period T2, the transfer gate 30 is pulsed to a second voltage level V2, which may be lower than the first voltage level, which leads to the transfer of a further portion of the stored charge carriers to the diffusion node 42. The further portion is also configured to be drained to the pixel supply voltage VDD at a later stage.

[0114] After the pulse of transfer gate 30, charge carriers continue to be accumulated by photodiode 20 during a third integration period T3. The third integration period T3 may be shorter than the second integration period T2. The amount of accumulated charge carriers during the third integration period T3 depends on the length of the third integration period T3.

[0115] In the subsequent drain period, a reset pulse RST and a coupling pulse DCG are applied at the end of the third integration period T3, which removes any excess charge carriers from the diffusion node 42, specifically the amount of accumulated charge carriers transferred during the exposure period by the TX pulses (V1, V2, etc.), thus draining said amount to the pixel supply voltage VDD.

[0116] During a first storage phase FS1 following the storage period FS, the transfer gate 30 is again pulsed to the first voltage level V1. This results in the transfer of a first portion of the accumulated charge carriers to the FD node 42. The first portion may correspond to the charge carriers accumulated during the last integration period, e.g., the third integration period T3. Simultaneously, the coupling signal DCG goes high, reducing the gain by shorting the third capacitor 150 to the FD node 42. Then, the first switch signal S1 and the second switch signal S2 are applied to store an LCG signal representing the first portion of the accumulated charge carriers in the pair of capacitors 70, 80 electrically coupled to the FD node 42 via the source follower 60. The LCG signal may be redistributed to the first capacitor 70 and the second capacitor 80.

[0117] The second storage stage FS2 follows pulsing the transfer transistor 30 to the full voltage level Vf to transfer the remaining portion of the stored charge carriers to the FD node 42. All remaining charge carriers are transferred. Because the coupling signal DCG remains low, a high conversion gain is achieved. A first switch signal S1 is then applied to the first switch 90 to store the HCG signal, representing the remaining portion of the stored charge carriers, in the first capacitor 70.

[0118] FIG. 5 further illustrates the barrier modulation and complements the timing diagram of FIG. 4 with respect to the exposure period EP. In FIG. 5, the charge Qout accumulated in the photodiode 20 during the exposure period EP is shown over time. During the first integration period T1, charge accumulates in the photodiode 20, causing the charge signal Qout to increase. As shown in FIG. 5, the accumulated charge may reach a saturation level Qsat. At the end of the first integration period T1, a pulse modulates the barrier to a first voltage level V1. This results in a decrease in the charge signal Qout in the photodiode 20. The charge signal Qout decreases to a first barrier level Qbarr1, which corresponds to the first voltage level V1. During the second integration period T2, the charge signal Qout continues to increase from the first barrier level Qbarr1 due to photoconversion in the photodiode 20. At the end of the second integration period T2, a pulse to a second voltage level V2 is applied, which leads to a further decrease in the charge signal Qout. When the second voltage level V2 is lower than the first voltage level V1, the charge signal Qout drops to a second barrier level Qbarr2, which is higher than the first barrier level Qbarr1. During the third integration period T3, the charge signal Qout continues to increase from the second barrier level Qbarr2 due to photoconversion in the photodiode 20. As explained above, the charge corresponding to the signal drop shown in FIG. 5 is drained to the power supply. Therefore, the charge signal Qout in the photodiode 20 is affected by both the skimming operation / barrier modulation.

[0119] FIG. 6 shows exemplary characteristics of pixel array 10 operated according to the methods of FIGS. 3 and 4. The response signal SIG in pseudo units is shown as a function of illumination IL in pseudo units. The response signal SIG may be the charge-equivalent signal on the sample-and-hold capacitors (first capacitor 70 and second capacitor 80). Signal SIG1 (thin solid line) is the signal resulting from the first integration period T1. Signal SIG1 saturates at higher exposure levels because pulsing transfer gate 30 to first voltage level V1 results in draining excess charge carriers to pixel supply voltage VDD.

[0120] Signal SIG2 (dotted line) is a signal resulting from the second integration period T2. The slope of signal SIG2 is gentler than that of signal SIG1 because integration period T2 may be shorter than integration period T1. Alternatively or additionally, the slope of signal SIG2 is gentler than that of signal SIG1 because both signals are obtained at different conversion gains. For example, signal SIG1 (up to the knee point) is obtained at a high conversion gain. For example, signal SIG2 is obtained at a low conversion gain. Therefore, the slope depends, for example, on the capacitance value of FD node 42 and on the capacitance value of third capacitor 150. The difference in slope depends on the gain ratio. Signal SIG2 may saturate at higher illumination levels because pulsing transfer gate 30 to first voltage level V2 leads to the draining of excess charge carriers to pixel supply voltage VDD.

[0121] Signal SIG3 (dashed line) is a signal resulting from the third integration period T3. The slope of signal SIG3 is gentler than the slope of signal SIG2 because integration period T3 may be shorter than integration period T2. Alternatively or additionally, the slope of signal SIG3 is gentler than the slope of signal SIG2 because both signals are obtained at different conversion gains. For example, signal SIG2 (up to its knee point) is obtained at a high conversion gain. For example, signal SIG3 is obtained at a low conversion gain. Therefore, the slope depends, for example, on the capacitance value of FD node 42 and on the capacitance value of third capacitor 150. The difference in slope depends on the ratio of the gains.

[0122] The output signal SIG4 (thick solid line) is a signal obtained by combining the signals SIG1, SIG2, and SIG3. Furthermore, the output signal SIG3 may be a function of the signals SIG1, SIG2, SIG3, and a reset signal (not shown). Combining the signals SIG1, SIG2, and SIG3 can increase the dynamic range of the pixel array 10. The exact saturation level of the signal SIG1 can be determined from the HCG signal because, after a pulse to the first voltage level V1, the HCG signal corresponds to the remaining charge carriers. This may mean that the signal SIG1 corresponds to the HCG signal. The signal SIG3 may correspond to the LCG signal. Furthermore, the exact saturation level of the signal SIG2 can also be determined from the HCG signal based on knowledge of the length of the integration periods T1-T3 and the voltage levels V1-V2. In other words, the knee point correction for V2 is mapped using the exact calibration value of V1 as a reference point.

[0123] FIG. 7 shows the reconstructed linear signal Qlin depending on the light intensity IL. The linearized signal Qlin and the light intensity / illuminance are shown in pseudo units. Note that the intensity range shown in FIG. 7 corresponds to the intensity range shown in FIG. 6. The linearized signal Qlin is the effective signal after reconstruction. The linearized signal Qlin may be based on the signals SIG1, SIG2, and SIG3 shown in FIG. 6. This may mean that the linearized signal Qlin is reconstructed using the signals SIG1 to SIG3 obtained during the exposure period EP. As shown, the linearized signal Qlin may saturate at very high illumination levels. However, the dynamic range increases with barrier modulation.

[0124] FIG. 8 shows another embodiment of the pixel array 10. The embodiment according to FIG. 8 differs from the embodiment according to FIG. 1 in that the capacitors 70, 80 are arranged in parallel, not in cascade. This means that the second switch 100 coupled to the second capacitor 80 is connected directly to the output terminal 64 of the amplifier 60, rather than via the first switch 90 as in FIG. 1. It should be noted that the pre-charge gate 160 can also be implemented as a constant current source configured to provide a fixed current. Furthermore, the embodiment according to FIG. 8 further comprises a second further amplifier 110′ and a further select gate 120′ coupled to the second capacitor 80, while the further amplifier 110 and the select gate 120 are coupled to the first capacitor 70. However, it should be noted that the embodiment shown shows a parallel arrangement of the capacitors 70, 80 by way of example only. Other arrangements are possible. For example, the parallel-arranged capacitors 70, 80 could share a common further amplifier 110 by means of an additional switch. Those skilled in the art will understand how to implement similar signal timing as shown in FIG. 4. However, the signal timing may change slightly during frame storage and readout because the first switch and second switch may be operated independently.

[0125] The pixel array 10 may include additional capacitors arranged in a similar manner, as indicated by the ovals in FIG. 8 . In this manner, at least one additional signal may be stored in the additional capacitor. The additional signal may correspond to the signal shown in FIG. 6 . For example, the additional signal may correspond to signal SIG2. Signal SIG2 indicates an additional calibration level, which may correspond to the saturation level. Thus, the pixel output signal may be determined based on the additional calibration level. In this case, the method for operating the pixel array 10 may include an additional storage step, e.g., a third storage step FS3, in which the additional signal is stored in the additional capacitor. The additional storage step may precede the first storage step FS1. The additional storage step may be brought about by pulsing the transfer transistor 30 to a respective voltage level, e.g., a second voltage level V2. In general, the pixel array 10 may include n sample-and-hold (S / H) capacitors that enable n additional self-calibration points, such that all readings except the first are CDS readings (the first reading is DDS). Therefore, the dynamic range can be extended and calibration levels corresponding to multiple barriers required for knee-point calibration and linearization can be directly obtained.

[0126] 9 shows another embodiment of the pixel array 10. The embodiment according to FIG. 9 differs from the embodiment according to FIG. 1 in that it comprises a further capacitor 75 arranged in cascade with the first capacitor 70 and the second capacitor 80. A further switching transistor 95 is assigned to the further capacitor 75. That is, the further switching transistor 95 connects a terminal node of the first capacitor 70 to a terminal node of the further capacitor 75. A second switching transistor 100 connects a terminal node of the further capacitor 75 to a terminal node of the second capacitor 80. The pixel array 10 may comprise a second further capacitor arranged in a manner similar to that indicated by the oval. As in the embodiment of FIG. 8, at least one further signal may be stored in the (further) capacitors 70, 75, 80, so that further self-calibration points can be stored for determining the pixel output signal. To that end, the method for operating the pixel array 10 may comprise a further storage step, for example a third storage step FS3, in which a further signal is stored in a further capacitor 75 or redistributed to at least some of the S / H capacitors 70, 75, 80, respectively. In that way, calibration levels corresponding to multiple barriers can be directly obtained.

[0127] FIG. 10 shows a timing diagram according to another embodiment of the operational method performed by the pixel array 10 shown in FIG. 1. As in FIG. 4, the following signals are shown as a function of time: transfer signal TX, coupling signal DCG, reset signal RST, first switch signal S1, and second switch signal S2. Note that the signal timings shown are rather exemplary and may vary. Furthermore, the time intervals should not be construed as being to scale.

[0128] The timing includes an exposure period EP, during which charge carriers are accumulated using the photodetector 20 comprising the pixel array 10. Prior to the exposure period EP, a TX pulse to the full voltage level Vf is applied to the transfer transistor 30. Because the reset signal RST and the coupling signal DCG are simultaneously high, this leads to a reset of the photodiode 20 and the diffusion node 42, at which point any excess charge carriers are removed, thereby preparing the pixel array 10 to capture a new frame. As shown in FIG. 10, the coupling signal DCG and the reset signal RST may remain high for a predetermined period within the exposure period EP.

[0129] During the accumulation of charge carriers, ie the exposure period EP, the following steps are carried out:

[0130] The transfer transistor is pulsed to a first voltage level V1 to transfer a portion of the stored charge carriers to the diffusion node 42. The portion is configured to be drained to the power supply voltage, which is achieved by the fact that both the coupling signal DCG and the reset signal RST are high. Thus, the floating diffusion node 42 is electrically connected to the pixel power supply voltage VDD.

[0131] The transfer transistor 30 is then pulsed to a second voltage level V2 to transfer a further portion of the stored charge carriers to the diffusion node 42. The second voltage level V2 is lower than the first voltage level V1, resulting in a higher barrier between the photodiode 20 and the diffusion node 42. The further portion is configured to be drained to the power supply voltage VDD, which is achieved by the fact that both the coupling signal DCG and the reset signal RST are still high. The reset signal RST then falls, so that the diffusion node 42 is no longer connected to the pixel power supply voltage VDD.

[0132] Transfer transistor 30 is then pulsed to a first voltage level V1 to transfer a first portion of the stored charge carriers to diffusion node 42. A representation of the first portion is configured to be stored as a low conversion gain signal (LCG signal). The LCG signal is stored at low conversion gain, which is achieved by the fact that the DCG signal is still high, so that diffusion node 42 is electrically connected to coupling capacitor 150, resulting in an increased capacitance.

[0133] A low conversion gain signal representing a first portion of the accumulated charge carriers is stored on a second capacitor 80, which is coupled to the diffusion node 42 via the amplifier 60 and switching capacitors 90, 100. This is accomplished by both switch signals S1 and S2 going high. The low conversion gain signal may be redistributed to the first capacitor 70 and the second capacitor 80. Thereafter, because the diffusion node 42 is no longer connected to the coupling capacitor 150, the coupling signal DCG goes low to increase the conversion gain.

[0134] At the end of the exposure period, the transfer transistor 30 is pulsed to the full voltage level Vf to transfer the remaining portion of the stored charge carriers to the diffusion node 42. A representation of the remaining portion is configured to be stored as a high conversion gain signal (HCG signal). The HCG signal is stored at high conversion gain, which is achieved by the fact that the DCG signal is low.

[0135] After the pulsing to the full voltage level Vf, a high conversion gain signal representing the remaining portion of the accumulated charge carriers is stored on a first capacitor 70, which is coupled to the diffusion node 42 via the amplifier 60 and the first switching transistor 90. This is accomplished by the first switch signal S1 going high. Alternatively, the first switch signal S1 can remain high after storing the LCG signal, as indicated by the dashed line. During a readout period (not shown), the low conversion gain signal and the high conversion gain signal stored on the capacitors are read out and transferred to an evaluation circuit via the column bus 130.

[0136] In the example shown, the period from the first pulse to the first voltage level V1 to the second pulse to the first voltage level is denoted by T1. The period from the pulse to the second voltage level V2 to the second pulse to the first voltage level is denoted by T2. The LCG signal provides information about the exposure during periods T1 and T2.

[0137] The HCG signal provides information about the total exposure during the exposure period (low light) or the first barrier (high light). Reconstructing the linearized signal depends on the light conditions.

[0138] In the following, the signal corresponding to the reset level minus the LCG signal will be referred to as the DDS signal, and the signal corresponding to the LCG signal minus the HCG signal will be referred to as the CDS signal.

[0139] In low light conditions, where none of the barrier pulses TX affect the charge on the photodiode, reconstruction is achieved by reading the CDS signal.

[0140] In low to medium light conditions, where only the second barrier pulse TX (pulse to the second voltage level V2) affects the charge on the photodiode, reconstruction is achieved by summing the CDS and DDS signals in the digital domain.

[0141] In medium to strong light conditions, where both barrier pulses (to the first and second voltage levels) affect the charge on the photodiode, reconstruction is achieved by using only the DDS signal, which is multiplied by the period ratio EP / T1 for linearization.

[0142] In medium to strong light conditions, where the barrier pulse TX affects the photodiode charge, reconstruction is achieved by using only the DDS signal. An offset can be subtracted (second barrier level Qbarr2 - first barrier level Qbarr1). The first barrier level Qbarr1 is equal to the CDS reading, and the second barrier level Qbarr2 can be estimated.

[0143] For linearization, the DDS signal after offset removal is multiplied by the period ratio EP / T2.

[0144] The example shown illustrates a method for operating pixel array 10 using barrier modulation with two barriers, however, as the experienced reader will readily recognize, the method can be extended with additional barriers.

[0145] Embodiments of pixel array 10 and methods of operating such pixel array 10 disclosed herein have been discussed for the purpose of familiarizing the reader with aspects of the novel concepts. While preferred embodiments have been shown and described, many variations, modifications, equivalents, and substitutions of the disclosed concepts may be made by those skilled in the art without unnecessarily departing from the scope of the claims.

[0146] It will be understood that the present disclosure is not limited to the disclosed embodiments, nor to those particularly shown and described above. Rather, features recited in separate dependent claims or in the description may be advantageously combined. Moreover, the scope of the present disclosure includes those variations and modifications that are apparent to those skilled in the art and that fall within the scope of the appended claims.

[0147] The term "comprises", when used in the claims or the description, does not exclude other elements or steps of the corresponding feature or procedure. Where the words "a" or "an" are used in conjunction with a feature, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope. [Explanation of symbols]

[0148] 10 pixel array 20 Photodiode 30 Transfer Transistor 40 capacitance 42 Diffusion Nodes 44 Further terminal nodes of capacitance 50 Reset transistor 60 Amplifier 62 Amplifier input terminal 64 Amplifier output terminal 70 First capacitor 72 Terminal node of the first capacitor 74 further terminal node of the first capacitor 75 additional capacitors 80 Second Capacitor 82 Second capacitor terminal node 84 Further terminal node of second capacitor 90 First switch, switching transistor 95 More Switches, Switching Transistors 100 Second switch, switching transistor 110 More Amplifiers 112 Further amplifier input terminal 114 Further amplifier output terminal 120 Select transistor 130 bus 140 Dual Conversion Gain Transistor 150 Dual Conversion Gain (3rd) Capacitor 152 Third capacitor terminal node 154 Further terminal node of the third capacitor 160 Precharge transistor 200 image sensors 204 line driver 205 Evaluation circuit 350 blocks 351 blocks 352 blocks 353 Block 354 blocks 355 blocks 356 blocks 357 blocks 358 blocks 359 blocks 360 blocks 361 blocks D Emission period DCG combined signal, dual conversion gain signal FS1 Storage Stage FS2 Storage Stage IL illuminance / light intensity Qbarr1 First barrier level Qbarr2 Second Barrier Level Qlin Linearized signal Qout Charge signal Qsat saturation level RST Reset signal S1 Switch signal S2 Switch signal SIG1 signal SIG2 signal SIG3 signal SIG4 signal T1 Integration Period T2 Integration Period T3 Integration Period EP pixel exposure, exposure period FS storage period RO Pixel readout, readout period R Reset Period TX Transfer Signal V1 Voltage Level V2 Voltage Level Vf Full voltage level Vref Second additional reference potential VSS Negative pixel power supply voltage, GND VSS1 reference potential VSS_PC Additional reference potential VDD Pixel power supply voltage

Claims

1. A method of operating a pixel array (10), comprising: During the exposure period (EP), accumulating charge carriers using a photodetector (20) included in the pixel array (10) during a first integration period (T1); at the end of the first integration period (T1), pulsing a transfer transistor (30) to a first voltage level (V1) to transfer a portion of the stored charge carriers to a diffusion node (42), the portion being configured to be drained to a pixel power supply voltage (VDD); continuing to accumulate charge carriers using the photodetector (20) during a second integration period (T2); after the second integration period (T2), pulsing the transfer transistor (30) at least one additional time to a respective further voltage level (V2, V3), each additional pulse causes an additional quantity of the stored charge carriers to be drained into the pixel supply voltage (VDD); continuing to accumulate additional charge carriers using the photodetector (20) for a respective additional integration period (T3, T4) after each additional pulsing; During the storage period (FS), pulsing the transfer transistor (30) to the first voltage level (V1) to transfer a first portion of the stored charge carriers to the diffusion node (42); storing a low conversion gain signal representative of the first portion of the accumulated charge carriers in at least a second capacitor (80) coupled to the diffusion node (42); pulsing the transfer transistor (30) to a full voltage level (Vf) to transfer the remaining portion of the stored charge carriers to the diffusion node (42); storing a high conversion gain signal representative of the remaining portion of the accumulated charge carriers in a first capacitor (70) coupled to the diffusion node (42); During the readout period (RO), reading out the low conversion gain signal and the high conversion gain signal stored in the capacitors (70, 80); performing correlated double sampling by using the low conversion gain signal as a reference level for the high conversion gain signal; A method comprising:

2. 2. The method of claim 1, wherein the voltage levels (V1, V2, V3) at which successive pulses are applied during the exposure period are equal or decrease with each pulse.

3. 2. The method of claim 1, wherein the integration periods (T1, T2, T3, T4) after said pulsing during said exposure period (EP) decrease by integration period.

4. The method of claim 1 , wherein the high conversion gain signal indicates a calibration level based on the remaining portion of the stored charge carriers.

5. 5. The method of claim 4, further comprising adjusting a pixel output signal based on the low conversion gain signal and / or the high conversion gain signal in response to a pixel-specific knee-point value determined based on the calibration level.

6. The method of claim 1 , wherein reading the low conversion gain signal comprises double delta sampling.

7. 2. The method of claim 1, wherein the high conversion gain signal and the low conversion gain signal are based on a common noise level because the diffusion node (42) is not reset between transferring the first portion of the stored charge carriers and transferring the remaining portion of the stored charge carriers.

8. During the storage period (FS), pulsing the transfer transistor (30) to the respective additional voltage level to transfer an additional portion of the stored charge carriers to the diffusion node (42); storing a further signal representative of the further portion of the stored charge carriers in a further capacitor (75) coupled to the diffusion node (42); The method of claim 1 further comprising:

9. The method of claim 8, wherein the high conversion gain signal indicates a calibration level based on the remaining portion of the stored charge carriers; the method further comprising adjusting a pixel output signal based on the low conversion gain signal and / or the high conversion gain signal in response to a pixel-specific knee-point value determined based on the calibration level; the further signal indicates a further calibration level based on the further portion of the stored charge carriers; The method of claim 8 , wherein adjusting the pixel output signal is performed in response to a further pixel-specific knee-point value determined based on the further calibration level.

10. During the readout period (RO), 9. The method of claim 8, further comprising the step of reading out the further signal stored on the further capacitor (75), wherein reading out the further signal comprises correlated double sampling.

11. The method of claim 1, wherein the first capacitor (70) and the second capacitor (80) are arranged in a cascade connection, a first switching transistor (90) couples the output terminal of the amplifier (60) to a terminal node of the first capacitor (70), and a second switching transistor (100) couples the terminal node of the first capacitor (70) to a terminal node of the second capacitor (80).

12. The pixel array (10) further comprises a dual conversion gain transistor (140) and a dual conversion gain capacitor (150); the dual conversion gain transistor (140) connects the diffusion node (42) to a terminal node of the dual conversion gain capacitor (150); 2. The method of claim 1, wherein a reset transistor is electrically coupled to the diffusion node through a terminal node of the dual conversion gain capacitor and the dual conversion gain transistor.

13. A method of operating a pixel array (10), comprising: During an exposure period (EP), charge carriers are accumulated using a photodetector (20) included in the pixel array (10), and during the accumulation, a first step of pulsing a transfer transistor (30) to a first voltage level (V1) to transfer a portion of the stored charge carriers to a diffusion node (42), the portion being configured to be drained to a power supply voltage (VDD); pulsing the transfer transistor (30) to a second voltage level (V2) to transfer a further portion of the stored charge carriers to the diffusion node (42), the further portion being configured to be drained to the power supply voltage (VDD); a second step of pulsing the transfer transistor (30) to the first voltage level (V1) to transfer a first portion of the stored charge carriers to the diffusion node (42); and storing a low conversion gain signal representative of the first portion of the accumulated charge carriers in at least a second capacitor (80) coupled to the diffusion node (42); and At the end of the exposure period (EP), pulsing the transfer transistor (30) to a full voltage level (Vf) to transfer the remaining portion of the stored charge carriers to the diffusion node (42); storing a high conversion gain signal representative of the remaining portion of the stored charge carriers in a first capacitor (70) coupled to the diffusion node (42) after the pulsing to the full voltage level (Vf); reading out the low conversion gain signal and the high conversion gain signal stored in the capacitors (70, 80) during a readout period (RO); performing correlated double sampling by using the low conversion gain signal as a reference level for the high conversion gain signal; A method comprising:

14. The method of claim 13 , wherein the low conversion gain signal and the high conversion gain signal have a common noise level.

15. 14. The method of claim 13, wherein the high conversion gain signal indicates a calibration level for adjusting a pixel output signal according to a pixel-specific knee-point value.

16. The method described in claim 13, wherein the first capacitor (70) and the second capacitor (80) are arranged in a cascade connection, a first switching transistor (90) couples the output terminal of the amplifier (60) to a terminal node of the first capacitor (70), and a second switching transistor (100) couples the terminal node of the first capacitor (70) to a terminal node of the second capacitor (80).

17. The pixel array (10) further comprising a dual conversion gain transistor (140) and a dual conversion gain capacitor (150); the dual conversion gain transistor (140) connects the diffusion node (42) to a terminal node of the dual conversion gain capacitor (150); 14. The method of claim 13, wherein a reset transistor (50) is electrically coupled to the diffusion node (42) through a terminal node of the dual conversion gain capacitor (150) and the dual conversion gain transistor (140).

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