Power device structure and manufacturing method thereof

Abstract

An exemplary semiconductor processing method may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The method may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom portion of the one or more features. The method may include providing a silicon-containing material. The method may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may isolate regions of remaining p-type silicon-containing material.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Non-Provisional Patent Application No. 17 / 572,963, entitled "POWER DEVICE STRUCTURES AND METHODS OF MAKING," filed January 11, 2022, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002]

[0002] The present technology relates to semiconductor systems, processes, and apparatus. More particularly, the present technology relates to processes and systems that improve scaling of high aspect ratio power devices. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on substrate surfaces. Producing patterned materials on substrates requires controlled methods for forming and removing material. As devices become increasingly miniaturized, features within integrated circuits become smaller and the aspect ratios of structures can become larger, making it difficult to maintain the dimensions of these structures during processing steps. Increased exposure during processing can result in recessed features within the material that may have uneven or tapered sidewalls, depending on the process. Developing materials with straight sidewalls can become more challenging. Additionally, backfilling recessed features with material without seams and / or voids can also become more challenging.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005] An exemplary semiconductor processing method may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The method may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from underneath the one or more features. The method may include providing a silicon-containing material. The method may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may isolate regions of the remaining p-type silicon-containing material.

[0006] In some embodiments, one or more features may be characterized by a width of about 1.5 μm or greater. The p-type silicon-containing material may be characterized by a thickness between about 5 nm and about 250 nm. While forming the p-type silicon-containing material on the substrate, a temperature within the semiconductor processing chamber may be maintained at about 600° C. or greater. The method may include providing an oxygen-containing precursor to form an oxygen-containing material over at least a portion of the p-type silicon-containing material. The oxygen-containing precursor may passivate at least a portion of the p-type silicon-containing material. The method may include removing the oxygen-containing material from the p-type silicon-containing material before depositing the second n-type silicon-containing material. The first n-type silicon-containing material and the second n-type silicon-containing material may be doped with phosphorus, arsenic, or a combination of both. The p-type silicon-containing material may be doped with boron. A ratio of the width of the second n-type silicon-containing material to the width of the p-type silicon-containing material may be about 15 or greater. The p-type silicon-containing material may be characterized by an aspect ratio of about 50 or greater. The method may include removing a portion of a second n-type silicon-containing material extending above the first n-type silicon-containing material, the p-type silicon-containing material, or both. In some embodiments, the p-type silicon-containing material may be the first p-type silicon-containing material. The method may further include forming a second p-type silicon-containing material on the substrate. The second p-type silicon-containing material may connect to individual portions of the first p-type silicon-containing material.

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a p-type silicon-containing material on a substrate. The p-type silicon-containing material may extend along at least a portion of one or more features defined in a first n-type silicon-containing material on the substrate. The method may include removing a portion of the p-type silicon-containing material. The removed portion of the p-type silicon-containing material may be located underneath the one or more features. The method may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features.

[0008] In some embodiments, the one or more features may be characterized by an aspect ratio of about 40 or greater. The p-type silicon-containing material may be characterized by a thickness of about 150 nm or less. A ratio of the width of the first n-type silicon-containing material or the second n-type silicon-containing material to the width of the p-type silicon-containing material may be about 15 or greater. The p-type silicon-containing material may be conformally formed along sidewalls of one or more features defined in the first n-type silicon-containing material. The method may include forming an oxygen-containing material over at least a portion of the p-type silicon-containing material. The oxygen-containing precursor may passivate at least a portion of the p-type silicon-containing material. The method may include contacting the oxygen-containing material with an etching reactant. The etching reactant may remove the oxygen-containing material. The second n-type silicon-containing material may fill the one or more features without any voids and without intermittent etching.

[0009] Some embodiments of the present technology may include a power device. The device may include a first silicon-containing material and a second silicon-containing material. The first silicon-containing material may define one or more features characterized by an aspect ratio of about 50 or greater. The first silicon-containing material may be or include n-type silicon. A second silicon-containing material may be disposed within the one or more features defined by the first silicon-containing material. The second silicon-containing material may be or include p-type silicon. The second silicon-containing material may conformally fill the one or more features. The second silicon-containing material may be void-free within the one or more features.

[0010]

[0010] Such techniques may offer numerous advantages over conventional methods and techniques. For example, the process may allow wider features to be formed in the substrate material while producing higher aspect ratio structures. Furthermore, by increasing the initial feature width, an improved etch profile may be produced through the substrate material, which may improve device uniformity and filling. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0011]

[0011] The nature and advantages of the techniques of the present disclosure may be further understood by referring to the remainder of this specification and the following drawings. [Brief explanation of the drawings]

[0012] [Figure 1]

[0012] A schematic top view of an exemplary processing system according to some embodiments of the present technique is shown. [Figure 2]

[0013] 1 illustrates exemplary steps in a semiconductor processing method according to some embodiments of the present technique. [Figure 3A]

[0014] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3B] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3C] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3D] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3E] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3F]3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3G] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3H] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. [Figure 3I] 3A-3I illustrate exemplary schematic cross-sectional structures that may include and be produced using layers of material, according to some embodiments of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0015] Some of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.

[0014]

[0016] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0015]

[0017] As device sizes continue to decrease, many material layers may be reduced in thickness and size to scale the devices. Features within semiconductor structures may become smaller, and the aspect ratio of the features may increase. As the aspect ratio of a feature increases, it may become more difficult to uniformly etch the feature without tapering the sides of the feature and compromising the feature dimensions or integrity, due to increased exposure closer to the surface of the structure being processed. Furthermore, refilling features with higher aspect ratios may become increasingly difficult due to pinch-off at the top of the feature, which prevents the feature from filling without seams and / or voids.

[0016]

[0018] In forming power device structures, conventional techniques have limited device scaling for features with increased aspect ratios due to the inherent effects of long etching and deposition processes. For example, in superjunction structures, p-type silicon pillars are formed by filling trenches etched in n-type silicon with p-type silicon. In these structures, on-resistance is controlled by the pitch or width of the different materials. This resistance can be improved by reducing the width of the p-type silicon pillars. Scaling of p-type silicon pillars is limited by etching and the ability to fill trenches without seams or voids. For example, increasing the aspect ratio with conventional etching can result in pitch degradation and feature tapering due to the extended exposure of the upper regions of the formed features. Furthermore, the filling process for high-aspect ratio features can lead to pinch-off before the deeper regions of the feature are filled. As a result, conventional techniques have been limited to lower aspect ratio or shorter structures to limit performance impact or device failure. Thus, many conventional techniques have limited ability to prevent structural defects in the final device or improve upon past designs.

[0017]

[0019] The present technology overcomes these challenges by redefining how pillars are formed within the base material. By forming a thin epitaxial liner within the generally wider features before backfilling, the pillars of material can be maintained at significantly smaller widths than in conventional techniques. More specifically, the width of the pillars of material can be defined by the width of the epitaxial liner rather than the width of the recessed feature. In fact, because two pillars can be deposited on the sidewalls of each recessed feature, the recessed features can be wider than in conventional techniques. After forming material on the sidewalls, the recessed feature can be backfilled with additional base material. By modifying the formation process itself, the present technology can provide features with larger aspect ratios and also prevent or reduce defects in the final device due to more uniform filling and coverage.

[0018]

[0020] While the remainder of the disclosure will routinely identify particular etching and deposition processes that utilize the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes, such as those that may occur in the described chambers. Accordingly, the present technology should not be considered limited to use with the described etching or deposition processes alone. This disclosure will describe one possible system that may be used with the present technology, before describing systems and methods or steps of an exemplary process sequence according to some embodiments of the present technology. It should be understood that the present technology is not limited to the described apparatus, and the described processes may be performed in any number of processing chambers and systems.

[0019]

[0021] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100 that may be included in or configured in accordance with some embodiments of the present technology. In this illustration, a pair of front-opening unified pods (FOUPs) 102 deliver substrates of various sizes that are received by a robot arm 104 and placed in a low-pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, arranged in tandem sections 109a-c. A second robot arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing steps, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processing, as well as the dry etch processes described herein.

[0020]

[0022] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to cure, anneal, or otherwise process the deposited film. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit and cure a film on a substrate. Any one or more of the described processes may be performed in additional chambers separate from the fabrication system shown in various embodiments. It should be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for material films are contemplated by system 100. Additionally, any number of other processing systems may be utilized with the present techniques, which may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system may provide access to multiple processing chambers while maintaining reduced pressure environments in various sections, such as the holding and transfer areas described above, allowing steps to be performed in multiple chambers while maintaining a particular reduced pressure environment between discrete processes.

[0021]

[0023] System 100, or more specifically, chambers integrated into system 100 or other processing systems, can be used to fabricate structures in accordance with some embodiments of the present technology. FIG. 2 illustrates a method 200 of semiconductor processing in accordance with some embodiments of the present technology. Method 200 can be performed in one or more processing chambers, such as, for example, chambers integrated into system 100. Method 200 may or may not include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the steps described. The method may include several optional steps, as illustrated in the figures, that may or may not be specifically associated with some embodiments of methods in accordance with the present technology. Method 200 describes steps shown generally in FIGS. 3A-3I, which will be described with reference to the steps of method 200. It should be understood that these figures are only partial schematic views with limited detail, and that in some embodiments the substrate may include any number of semiconductor sections having aspects as shown in the figures, as well as alternative structural aspects that can still benefit from any of the aspects of the present technology.

[0022]

[0024] As shown in FIG. 3A , structure 300 can include a substrate 305. In some embodiments, substrate 305 can have a substantially planar or textured surface. Substrate 305 can be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafer, patterned or unpatterned wafer, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. As a non-limiting example, in some embodiments, the substrate can be or include an N+ material, such as N+ silicon. Substrate 305 can have a variety of dimensions, such as a 200 mm or 300 mm diameter wafer, as well as a rectangular or square panel. Substrate 305 can be positioned within a processing region of a semiconductor processing chamber. Although illustrated as a planar substrate, it should be understood that substrate 305 is included merely to represent an underlying structure, which may include any number of layers or features on a wafer or other substrate, upon which structures such as those described below may be formed.

[0023]

[0025] The substrate 305 may include a first n-type silicon-containing material 310. The first n-type silicon-containing material 310 may be disposed along at least a portion or the entirety of the substrate 305. The first n-type silicon-containing material 310 may be n-type silicon and may be doped with phosphorus, arsenic, or a combination of both. In some embodiments, a hard mask, photoresist, or any other mask material may be disposed along the first n-type silicon-containing material 310 to facilitate patterning of the first n-type silicon-containing material 310. As shown in FIG. 3A , a first mask 315 may be formed over the first n-type silicon-containing material 310, and a second mask 320 may be formed over the first mask 315. In some embodiments, either or both masks may be any number of materials to facilitate structure formation, such as oxide, nitride, carbide, or some combination of materials. For example, the first mask 315 may be or include silicon nitride, and the second mask 320 may be or include silicon oxide, or some other mask material. It is contemplated that a single mask may be provided over the first n-type silicon-containing material 310, and that the embodiment shown in FIG. 3A is merely one example structure 300.

[0024]

[0026] As shown in FIG. 3B , a pattern may be etched or formed through the first mask 315 and / or the second mask 320 to form features in optional step 205. The pattern may be etched through the first mask 315 and / or the second mask 320 using any etching process and any etching reactant. The pattern in the first mask 315 and / or the second mask 320 may form features or gaps in the first mask 315 and / or the second mask 320. In some embodiments, once the pattern is transferred into the underlying silicon-containing material 310, the second mask 320 may be completely removed by etching. The pattern may not extend completely through the thickness of the first mask 315 while removing the second mask 320. The first n-type silicon-containing material 310 is thereby at least partially exposed and subsequently etched.

[0025]

[0027] Etching the first n-type silicon-containing material 310 may form one or more features 325 in the material. The features 325 may have a depth-to-width ratio of about 50 or less, about 40 or less, about 30 or less, about 25 or less, about 20 or less, about 15 or less, about 10 or less, or less. Additionally, the features 325 may be formed to a depth of about 10 μm or more, about 15 μm or more, about 20 μm or more, about 25 μm or more, about 30 μm or more, about 35 μm or more, about 40 μm or more, about 45 μm or more, about 50 μm or more, about 55 μm or more, about 60 μm or more, about 65 μm or more, about 70 μm or more, about 75 μm or more, about 80 μm or more, about 85 μm or more, about 90 μm or more, about 95 μm or more, about 100 μm or more, or more. Additionally, features 325 may be formed to widths of about 1.5 μm or greater, about 2.0 μm or greater, about 2.5 μm or greater, about 3.0 μm or greater, about 3.5 μm or greater, about 4.0 μm or greater, about 4.5 μm or greater, about 5.0 μm or greater, about 6.0 μm or greater, about 7.0 μm or greater, about 8.0 μm or greater, about 9.0 μm or greater, about 10.0 μm or greater, or greater.

[0026]

[0028] While conventional methods may have invested in etching higher aspect ratio features to allow for narrower, deeper p-type material regions to be deposited, creating features with higher aspect ratios can make structure formation more difficult. Not only can it be difficult to etch high aspect ratio features with a consistent diameter, it can also be difficult to backfill these features with a uniform material. Instead, the backfill material may have seams and / or voids due to pinch-off at the top of the feature during filling. Conversely, counterintuitively, the present technique may allow for relaxation of the width of the feature 325 to fabricate smaller pitch or higher aspect ratio structures, which may allow for more uniform etching and subsequent backfilling. Furthermore, increasing the diameter of the feature 325 may provide deeper etching of the first n-type silicon-containing material 310. As an added benefit of the deeper etching, and therefore deeper material structures, the breakdown voltage of power devices fabricated by the present technique may be improved compared to conventional methods and techniques.

[0027]

[0029] As shown in FIG. 3C , in step 210, the method 200 may include forming a p-type silicon-containing material 330 on the substrate 405. The p-type silicon-containing material 330 may be deposited or formed on the first n-type silicon-containing material 310. The deposition or formation may be performed in any number of ways, and in some embodiments, the material may be formed conformally around the features. The p-type material may be, for example, p-type silicon, and may be deposited by atomic layer deposition, grown epitaxially, or produced by any number of other processes to produce a conformal coverage around the structure. Having features characterized by a wider pitch may result in more uniform coverage due to the relatively low aspect ratio of the initially formed wider features. The p-type silicon-containing material 330 may be characterized by a thickness of about 200 nm or less, about 150 nm or less, about 100 nm or less, about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 40 nm or less, about 30 nm or less, about 20 nm or less, about 10 nm or less, about 5 nm or less, or less. The p-type silicon-containing material 330 may be a boron-doped silicon-containing material. In some embodiments, the p-type silicon-containing material 330 may also include germanium. The p-type silicon-containing material 330 may be seam- and / or void-free to a depth of several micrometers based on conformal coverage around the structure. This can result in significant improvements in final device performance compared to prior art, where coverage may be reduced or incomplete at greater depths. Additionally, the formation of seams and voids can affect device performance, such as breakdown voltage. However, it is anticipated that some pores may exist within the p-type silicon-containing material depending on its formation and thickness.

[0028]

[0030] The p-type silicon-containing material 330 may be formed conformally along the sidewalls of one or more features 325 defined in the first n-type silicon-containing material 310. The first mask 315 may increase the selectivity and conformality of the p-type silicon-containing material 330. In the absence of the first mask 315, the p-type silicon-containing material 330 may have peaks formed at the top of the first n-type silicon-containing material 310 between the features 325. When the first mask 315, such as a nitride mask, is present, the p-type silicon-containing material 330 may be selective to the first n-type silicon-containing material 310 and may form at a much slower rate on the first mask 315.

[0029]

[0031] As shown in FIG. 3D , the method 200 may include, in optional step 215, forming a passivation layer 335. The passivation layer 335 may be formed by providing an oxygen-containing precursor to the processing region. The oxygen-containing precursor that may be used in step 215 may be or include any number of oxygen-containing precursors. The oxygen-containing precursor may be any number of precursors capable of oxidizing the p-type silicon-containing material 330. As non-limiting examples, in embodiments of the present technology, the oxygen-containing precursor may be or include diatomic oxygen, ozone, nitrous oxide, nitric oxide, sulfur dioxide, or any other oxygen-containing precursor that may be provided with or without plasma enhancement, and may be provided with any other precursor, such as a silicon-containing precursor, to deposit an oxide layer. The passivation layer 335 may be formed using any deposition or growth method. The passivation layer 335 may be formed over at least a portion of the p-type silicon-containing material 330. The oxygen-containing material in the passivation layer 335 may oxidize and passivate at least a portion of the p-type silicon-containing material 330. The passivation layer 335 may serve to protect the p-type silicon-containing material 330 during subsequent etching steps.

[0030]

[0032] 3E, method 200 may include removing a portion of p-type silicon-containing material 330 at step 220. The portion of p-type silicon-containing material 330 that is removed may be located underneath one or more features 325. In addition to the portion of p-type silicon-containing material 330 that is removed, a portion of passivation layer 335 may also be removed. The portion of passivation layer 335 that is removed may be located underneath one or more features 325. In some embodiments, removing the portion of p-type silicon-containing material 330 may include an anisotropic etching process, such as a reactive ion etching process or other directional dry etching process. During step 220, method 200 may include applying a bias power to etch the passivation layer 335 and / or the underlying p-type silicon-containing material 330. Etching of the passivation layer 335 may be due to sputtering of oxide within the passivation layer 335, while more chemical removal occurs through the p-type silicon, or vice versa. The bottom of the passivation layer 335 may be sputtered and removed at a faster rate than the sidewalls of the passivation layer 335 due to the anisotropy of the etch.

[0031]

[0033] 3F, the method 200 may include removing a remaining portion of the passivation layer 335. The portion of the passivation layer 335 that is removed may be disposed along one or more features 325 and the underlying p-type material. In embodiments, removing the portion of the passivation layer 335 may include, as one non-limiting example, a wet etching process using any wet etch reactant(s), such as a halogen-containing material. However, it is contemplated that other forms of etching, including dry etching processes, may alternatively or additionally be utilized.

[0032]

[0034] The remaining p-type silicon-containing material 330 may be present on the sidewalls of the feature 325. The p-type silicon-containing material 330 may be characterized by an aspect ratio of about 50 or greater, about 100 or greater, about 150 or greater, about 200 or greater, about 250 or greater, about 300 or greater, about 350 or greater, about 400 or greater, or more. Power devices formed using this structure, with taller and narrower features than conventional methods, may be characterized by reduced on-resistance due to the separation distance between features and improved breakdown voltage due to the depth and uniformity of the pillars formed. As previously mentioned, the thickness of the remaining p-type silicon-containing material 330 may be about 100 nm or less, and may be less than 50 nm, less than 20 nm or less, less than 10 nm, or less. Again, such a width may lead to enhanced on-resistance reduction in structures including vertical superjunctions due to the reduced separation of the n-regions of material 310.

[0033]

[0035] As shown in FIG. 3G , the method 200 may include providing a silicon-containing material in step 225 and forming a second n-type silicon-containing material 340 on the substrate 305 in step 230. The second n-type silicon-containing material 340 may fill one or more features 325 by backfilling the interior regions of the feature between the sidewalls on which the p-type silicon-containing material 330 was formed. The second n-type silicon-containing material 340 may fill one or more features 325 without any voids and without intermittent etching based on the increased width that may be provided from the initial feature formation. The second n-type silicon-containing material 340 may be the same material as the first n-type silicon-containing material 310. Together, the first n-type silicon-containing material 310 and the second n-type silicon-containing material 340 may at least partially surround the p-type silicon-containing material 330. The ratio of the width of the second n-type silicon-containing material 340 to the width of the p-type silicon-containing material 330 can be about 15 or greater, and can be about 20 or greater, about 22 or greater, about 24 or greater, about 26 or greater, about 28 or greater, about 30 or greater, or higher. This ratio between the two materials can lead to reduced on-resistance in subsequent devices fabricated with these structures, as previously described.

[0034]

[0036] As shown in FIG. 3H, method 200 may include removing a portion of the second n-type silicon-containing material and any remaining mask material by planarizing the structure, such as using a chemical-mechanical polishing process. As shown in FIG. 3I, method 200 may, in optional step 235, form a further or second p-type silicon-containing material 345 over the first n-type silicon-containing material 310 and the second n-type silicon-containing material 340. This step may be part of subsequent processing to fabricate a power diode or other power device structure. The second p-type silicon-containing material 345 may be the same as the p-type silicon-containing material 330 and may connect to previously formed pillars of individual p-type silicon-containing material 330. The second p-type silicon-containing material 345 may serve as a top contact in a power device or superjunction structure. Optional step 235 may also include any further post-processing to form structures such as, but not limited to, a superjunction diode or a metal-oxide-semiconductor field-effect transistor. This may include, but is not limited to, further deposition, forming, etching, processing, or other steps.

[0035]

[0037] Structures according to some embodiments of the present technology, such as power devices, can have any of the features or characteristics described above. In some embodiments, the power device can include a first silicon-containing material. The first silicon-containing material can define one or more features characterized by any of the aspect ratios described above. The first silicon-containing material can be n-type silicon, such as the n-type silicon-containing material described above, or can include n-type silicon. The power device can also include a second silicon-containing material disposed within the one or more features defined by the first silicon-containing material. The second silicon-containing material can be p-type silicon, such as the p-type silicon-containing material described above, or can include p-type silicon. The second silicon-containing material can conformally fill the one or more features. A ratio of the width of the first silicon-containing material to the width of the second silicon-containing material is about 15 or greater. The second silicon-containing material can be void-free within the one or more features. By utilizing structures according to embodiments of the present technique, improved power devices may be fabricated that are characterized by better operational performance and consistency.

[0036]

[0038] In the foregoing description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0037]

[0039] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be construed as limiting the scope of the technology.

[0038]

[0040] Where a range of values ​​is provided, it is to be understood that, unless the context clearly dictates otherwise, each intervening value between the upper and lower limits of that range is specifically disclosed, to the smallest unit of the lower limit. Any subranges between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, are also included. The upper and lower limits of these smaller ranges may be individually included or excluded from the range, and each range in which either, neither, or both limits are included in the subranges is also encompassed within the scope, subject to any explicitly excluded limit in the stated range. When a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0039]

[0041] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a pillar" includes a plurality of such pillars, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so on.

[0040]

[0042] Additionally, the terms "comprises," "comprising," "contains," "containing," "includes," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. Forming a mask in a desired pattern on a first n-type silicon-containing material of a substrate comprising the first n-type silicon-containing material; forming one or more recess features in the first n-type silicon-containing material through the mask; forming a p-type silicon-containing material over the first n-type silicon-containing material with the one or more recessed features formed therein, the p-type silicon-containing material extending along at least a portion of the one or more recessed features defined in the first n-type silicon-containing material; removing a portion of the p-type silicon-containing material, the portion of the p-type silicon-containing material being removed from underneath the one or more recessed features; depositing a second n-type silicon-containing material on the substrate, the second n-type silicon-containing material filling the one or more recessed features formed in the first n-type silicon-containing material and isolating regions of remaining p-type silicon-containing material; and removing a portion of the second n-type silicon-containing material extending above the first n-type silicon-containing material, the p-type silicon-containing material, or both, along with the mask; A semiconductor processing method comprising:

2. 10. The semiconductor processing method of claim 1, wherein the one or more recessed features are characterized by a width of 1.5 [mu]m or greater.

3. 10. The semiconductor processing method of claim 1, wherein the p-type silicon-containing material is characterized by a thickness between 5 nm and 200 nm.

4. After forming the p-type silicon-containing material and before removing the portion of the p-type silicon-containing material, providing an oxygen-containing precursor; 10. The semiconductor processing method of claim 1, further comprising forming an oxygen-containing material over at least a portion of the p-type silicon-containing material, wherein the oxygen-containing precursor passivates at least a portion of the p-type silicon-containing material.

5. 5. The semiconductor processing method of claim 4, further comprising removing the oxygen-containing material from the p-type silicon-containing material before depositing the second n-type silicon-containing material.

6. the first n-type silicon-containing material and the second n-type silicon-containing material are doped with phosphorus, arsenic, or a combination of both; 10. The semiconductor processing method of claim 1, wherein said p-type silicon-containing material is doped with boron.

7. 10. The semiconductor processing method of claim 1, wherein a ratio of a width of the second n-type silicon-containing material to a width of the p-type silicon-containing material is 15 or greater.

8. 10. The semiconductor processing method of claim 1, wherein an aspect ratio of a height of the p-type silicon-containing material to a width of the p-type silicon-containing material is 50 or greater.

9. The p-type silicon-containing material is a first p-type silicon-containing material, and the method further comprises:

10. The semiconductor processing method of claim 1, further comprising forming a second p-type silicon-containing material on the substrate after removing the portions of the second n-type silicon-containing material with the mask, the second p-type silicon-containing material connecting to individual portions of the first p-type silicon-containing material.

10. The semiconductor processing method of claim 9, wherein the second p-type silicon-containing material is the same material as the first p-type silicon-containing material.

11. 10. The semiconductor processing method of claim 1, wherein the p-type silicon-containing material is characterized by a thickness of 150 nm or less.

12. 10. The semiconductor processing method of claim 1, wherein a ratio of a width of the first n-type silicon-containing material or the second n-type silicon-containing material to a width of the p-type silicon-containing material is 15 or greater.

13. 13. The semiconductor processing method of claim 12, wherein the p-type silicon-containing material is formed conformally along sidewalls of the one or more recessed features defined in the first n-type silicon-containing material.

14. 10. The semiconductor processing method of claim 1, wherein the second n-type silicon-containing material fills the one or more recessed features without any voids and without interrupted etching.

15. A semiconductor processing method according to any one of claims 1 to 14, wherein the second n-type silicon-containing material is the same material as the first n-type silicon-containing material.

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