Semiconductor Devices

Abstract

A semiconductor device (1) is a chip-sized square semiconductor device (1) in plan view, the semiconductor device (1) comprising a semiconductor layer (40), a vertical MOS transistor (10) formed in the semiconductor layer (40), and a Schottky barrier diode (20) in which the semiconductor layer (40) functions as an anode or a cathode. The semiconductor device (1) furthermore comprises, on the upper surface thereof, a first pad (51), a second pad (52), a third pad (53), and a fourth pad (54). In plan view of the semiconductor device (1), the center of the first pad (51) and the center of the third pad (53) are positioned on one diagonal line of the semiconductor device (1), the center of the second pad (52) and the center of the fourth pad (54) are positioned on the other diagonal line of the semiconductor device (1), and the first pad (51), the second pad (52), the third pad (53), and the fourth pad (54) are circular and have the same diameter.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices have been commercially available in which a MOS transistor and a Schottky barrier diode are sealed in a single package so that each can function as an independent element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-203966 Summary of the Invention [Problem to be solved by the invention]

[0004] All of the above commercially available semiconductor devices have a size of 2.0 mm×2.0 mm or more in plan view.

[0005] On the other hand, there is a growing demand for high-density mounting of electronic components in a limited space.

[0006] Therefore, an object of the present disclosure is to provide a semiconductor device that includes a MOS transistor and a Schottky barrier diode so that each can function as an independent element, and that can be made smaller in size in a planar view than conventional semiconductor devices. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the present disclosure is a chip-size package type semiconductor device, comprising: a semiconductor layer having a semiconductor substrate of a first conductivity type containing impurities at a first concentration; and a low-concentration impurity layer of the first conductivity type formed in contact with an upper surface of the semiconductor substrate and containing impurities at a second concentration lower than the first concentration; a vertical MOS transistor formed in the semiconductor layer; and a Schottky barrier diode in which the low-concentration impurity layer functions as a cathode when the first conductivity type is N-type and functions as an anode when the first conductivity type is P-type. The semiconductor device further comprises, on the upper surface of the semiconductor device, a first pad functioning as a source pad of the vertical MOS transistor, a second pad functioning as a drain pad of the vertical MOS transistor, and a cathode pad of the Schottky barrier diode when the first conductivity type is N-type and an anode pad of the Schottky barrier diode when the first conductivity type is P-type. a third pad that functions as an anode pad of the Schottky barrier diode when the first conductivity type is P-type, and a fourth pad that functions as a cathode pad of the Schottky barrier diode when the first conductivity type is P-type, and a fourth pad that functions as a gate pad of the vertical MOS transistor, wherein in a plan view of the semiconductor device, the semiconductor device is a square having a first vertex, a second vertex, a third vertex, and a fourth vertex in a counterclockwise direction, the first pad, the second pad, the third pad, and the fourth pad are circles of the same diameter, the centers of the first pad and the third pad are located on a first diagonal line connecting the first vertex and the third vertex, the centers of the second pad and the fourth pad are located on a second diagonal line connecting the second vertex and the fourth vertex, and the distance between the center of the semiconductor device and the center of the first pad, the distance between the center of the semiconductor device and the center of the second pad, the distance between the center of the semiconductor device and the center of the third pad, and the distance between the center of the semiconductor device and the center of the fourth pad are equal. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, a semiconductor device is provided that includes a MOS transistor and a Schottky barrier diode so that each can function as an independent element, and that can have a smaller size in plan view than conventional semiconductor devices. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic plan view showing an example of the structure of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 3A] FIG. 3A is a circuit diagram of a semiconductor device according to an embodiment in which the first conductivity type is N-type. [Figure 3B] FIG. 3B is a circuit diagram of the semiconductor device according to the embodiment when the first conductivity type is P type. [Figure 4] FIG. 4 is a comparison diagram comparing the conduction resistance of a vertical MOS transistor according to a comparative example with the conduction resistance of a vertical MOS transistor according to the embodiment. [Figure 5] FIG. 5 is a correlation diagram schematically showing the relationship between the type of metal material forming the Schottky junction surface and the characteristics of the Schottky barrier diode when the first conductivity type is N-type. [Figure 6] FIG. 6 is a schematic plan view showing another example of the structure of the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a schematic plan view showing an example of the structure of a semiconductor device according to the first modification. [Figure 8] FIG. 8 is a schematic plan view showing an example of the structure of a semiconductor device according to the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0010] (How one aspect of the present disclosure was achieved) A conventional semiconductor device in which a MOS transistor and a Schottky barrier diode are sealed in a single package so that each can function as an independent element has a total of five terminals on the mounting surface where the semiconductor device is mounted on a mounting board or the like: three terminals connected to the gate, source, and drain of the MOS transistor, respectively, and two terminals connected to the anode and cathode of the Schottky barrier diode, respectively.

[0011] In response to this, the inventors have found that when the semiconductor device is used in an application in which the drain of a MOS transistor and the anode or cathode of a Schottky barrier diode are directly connected, the number of terminals of the semiconductor device can be reduced to four by combining the terminal connected to the drain of the MOS transistor and the terminal connected to the anode or cathode of the Schottky barrier diode into a single terminal.

[0012] Based on this finding, the inventors have conducted extensive experiments and studies and have arrived at the semiconductor device according to the present disclosure described below.

[0013] A semiconductor device according to the present disclosure is a chip-size package type semiconductor device, comprising: a semiconductor layer having a semiconductor substrate of a first conductivity type containing impurities at a first concentration; and a low-concentration impurity layer of the first conductivity type formed in contact with an upper surface of the semiconductor substrate and containing impurities at a second concentration lower than the first concentration; a vertical MOS transistor formed in the semiconductor layer; and a Schottky barrier diode in which the low-concentration impurity layer functions as a cathode when the first conductivity type is N-type and functions as an anode when the first conductivity type is P-type. The semiconductor device further comprises, on the upper surface of the semiconductor device, a first pad functioning as a source pad of the vertical MOS transistor, a second pad functioning as a drain pad of the vertical MOS transistor, and a cathode pad of the Schottky barrier diode when the first conductivity type is N-type and an anode pad of the Schottky barrier diode when the first conductivity type is P-type, a third pad that functions as an anode pad and, when the first conductivity type is P-type, functions as a cathode pad of the Schottky barrier diode; and a fourth pad that functions as a gate pad of the vertical MOS transistor, wherein, in a plan view of the semiconductor device, the semiconductor device is a square having a first vertex, a second vertex, a third vertex, and a fourth vertex in a counterclockwise direction, the first pad, the second pad, the third pad, and the fourth pad are circles of the same diameter, the centers of the first pad and the third pad are located on a first diagonal line connecting the first vertex and the third vertex, the centers of the second pad and the fourth pad are located on a second diagonal line connecting the second vertex and the fourth vertex, and the distance between the center of the semiconductor device and the center of the first pad, the distance between the center of the semiconductor device and the center of the second pad, the distance between the center of the semiconductor device and the center of the third pad, and the distance between the center of the semiconductor device and the center of the fourth pad are equal.

[0014] The semiconductor device having the above configuration is an unsealed chip-sized semiconductor device that has four pads, i.e., four terminals, on its top surface, which serves as the mounting surface on which the semiconductor device is mounted on a mounting board or the like, and in which the vertical MOS transistor and the Schottky barrier diode can each function as independent elements.

[0015] Therefore, the semiconductor device having the above configuration can be made smaller in size in plan view than a conventional semiconductor device in which a MOS transistor and a Schottky barrier diode are sealed in a single package so that they can function as independent elements, and which has at least five terminals on the mounting surface.

[0016] Thus, the semiconductor device having the above configuration provides a semiconductor device that includes a MOS transistor and a Schottky barrier diode so that each can function as an independent element, and that can be made smaller in size in plan view than conventional semiconductor devices.

[0017] In this specification, the center in plan view refers to the intersection of the diagonals of a square or rectangular structure in plan view, such as a semiconductor device; the center of a circular structure in plan view, such as the first to fourth pads, refers to the center of the circle; the center of an oval structure in plan view refers to the intersection of the axis of symmetry extending in the longitudinal direction of the oval and the axis of symmetry extending in the lateral direction of the oval; and the center of an elliptical structure in plan view refers to the intersection of the major and minor axes of the ellipse.

[0018] Furthermore, when viewed from above, if the area of ​​the semiconductor device is divided into four equal square regions that do not overlap with one another, namely, a first square region having a diagonal line connecting the first vertex and the center of the semiconductor device, a second square region having a diagonal line connecting the second vertex and the center of the semiconductor device, a third square region having a diagonal line connecting the third vertex and the center of the semiconductor device, and a fourth square region having a diagonal line connecting the fourth vertex and the center of the semiconductor device, the first pad is included in the first square region, and The second pad is included in a second pad-including square region which is either the second square region or the fourth square region, the third pad is included in the third square region, and the fourth pad is included in a fourth pad-including square region which is the other of the second square region and the fourth square region, and the semiconductor layer further includes a drain pull-up region which is entirely included in the second pad-including square region in a plan view of the semiconductor layer, and which extends from the upper surface of the semiconductor layer through the low-concentration impurity layer to the semiconductor substrate. the drain pull-up region of the first conductivity type containing an impurity at a third concentration higher than the second concentration, and the semiconductor device may further include: a first electrode functioning as a source electrode of the vertical MOS transistor, at least a part of which is included in the first square region in a plan view of the semiconductor device; a second electrode functioning as a drain electrode of the vertical MOS transistor, at least a part of which is included in the second intra-pad square region, the second electrode functioning as a cathode electrode of the Schottky barrier diode when the first conductivity type is N-type and the second electrode functioning as an anode electrode of the Schottky barrier diode when the first conductivity type is P-type; a third electrode at least a part of which is included in the third square region, the third electrode functioning as an anode electrode of the Schottky barrier diode when the first conductivity type is N-type and the second electrode functioning as a cathode electrode of the Schottky barrier diode when the first conductivity type is P-type; and a fourth electrode functioning as a gate electrode of the vertical MOS transistor, at least a part of which is included in the fourth intra-pad square region.

[0019] In the semiconductor device having the above configuration, the distance between the anode electrode and the cathode electrode of the Schottky barrier diode is relatively short.

[0020] Therefore, in the semiconductor device having the above configuration, the forward voltage of the Schottky barrier diode can be made relatively small.

[0021] Furthermore, in the semiconductor device having the above configuration, the distance between the source electrode and the drain electrode of the vertical MOS transistor is relatively short.

[0022] Therefore, in the semiconductor device having the above configuration, the conduction resistance of the vertical MOS transistor can be made relatively small.

[0023] The Schottky barrier diode may be a planar type.

[0024] In general, a planar Schottky barrier diode can be formed with fewer processing steps than other types of Schottky barrier diodes.

[0025] Therefore, the semiconductor device having the above configuration provides a semiconductor device that can be manufactured relatively easily.

[0026] Furthermore, the second electrode may have a plurality of metal layers including an ohmic contact metal layer that forms an ohmic contact with the drain pull-up region, and the third electrode may have a plurality of metal layers including a Schottky contact metal layer that forms a Schottky contact with the low-concentration impurity layer, and the metal material of the ohmic contact metal layer and the metal material of the Schottky contact metal layer may be the same.

[0027] This allows the ohmic contact metal layer and the Schottky contact metal layer to be formed in the same processing step.

[0028] Therefore, the semiconductor device having the above configuration provides a semiconductor device that can be manufactured relatively easily.

[0029] Furthermore, the second electrode may have a plurality of metal layers including an ohmic contact metal layer that forms an ohmic contact with the drain pull-up region, and the third electrode may have a plurality of metal layers including a Schottky contact metal layer that forms a Schottky contact with the low-concentration impurity layer, and the metal material of the ohmic contact metal layer and the metal material of the Schottky contact metal layer may be different from each other.

[0030] This allows the Schottky junction metal layer to be a metal layer containing a different type of metal material from that of the ohmic junction metal layer, which is suited to the desired characteristics of the Schottky barrier diode.

[0031] Therefore, according to the semiconductor device having the above configuration, a semiconductor device including a Schottky barrier diode having desired characteristics is provided.

[0032] Furthermore, in a planar view of the semiconductor device, at least a portion of the first electrode may be included in the second pad-containing square region and / or the fourth pad-containing square region, and at least a portion of the second electrode, at least a portion of the third electrode, and at least a portion of the fourth electrode may not be included in the first square region.

[0033] This allows the area of ​​the source electrode of the vertical MOS transistor to be relatively large in plan view of the semiconductor device.

[0034] Therefore, in the semiconductor device having the above configuration, the conduction resistance of the vertical MOS transistor can be made relatively small.

[0035] Furthermore, in a planar view of the semiconductor device, the second electrode may be rectangular having a first opposing side having a portion that is parallel to and opposite a first part of the outer periphery of the first electrode, and a second opposing side having a portion that is parallel to and opposite a second part of the outer periphery of the first electrode.

[0036] This allows the opposing length of the source electrode and the drain electrode of the vertical MOS transistor to be relatively long in plan view of the semiconductor device.

[0037] Therefore, in the semiconductor device having the above configuration, the conduction resistance of the vertical MOS transistor can be made relatively small.

[0038] In addition, in a plan view of the semiconductor device, at least a part of the first electrode may not be included in the second pad-including square region.

[0039] In the semiconductor device having the above configuration, the source electrode of the vertical MOS transistor is not sandwiched between the anode electrode and cathode electrode of the Schottky barrier diode in a plan view of the semiconductor device.

[0040] Therefore, the semiconductor device having the above configuration can prevent the characteristics of the Schottky barrier diode from deteriorating.

[0041] Furthermore, the third electrode and the low-concentration impurity layer form a Schottky junction in a Schottky junction region, the second electrode and the drain pull-up region form an ohmic junction in an ohmic junction region, the first electrode and the semiconductor layer are in contact with each other in a source junction region, and in a plan view of the semiconductor device, the Schottky junction region is contained within the third electrode and has any one of a circle, an ellipse, an oval, and a rectangle with rounded corners, and the shortest distance between the Schottky junction region and the ohmic junction region may be shorter than the shortest distance between the Schottky junction region and the source junction region.

[0042] The semiconductor device having the above structure has no corners in the Schottky junction region when viewed from above.

[0043] This prevents the electric field from concentrating excessively in the Schottky junction region.

[0044] Therefore, the semiconductor device having the above configuration can improve the breakdown voltage characteristics in the Schottky junction region.

[0045] Furthermore, in the semiconductor device having the above configuration, the distance between the Schottky junction region and the ohmic junction region can be made relatively small.

[0046] Therefore, in the semiconductor device having the above configuration, the forward voltage of the Schottky barrier diode can be made relatively small.

[0047] In addition, in a plan view of the semiconductor device, the area of ​​the Schottky junction region may be larger than the area of ​​the third pad.

[0048] This allows the area of ​​the Schottky junction region in a plan view of the semiconductor device to be relatively large.

[0049] Therefore, in the semiconductor device having the above configuration, the forward voltage of the Schottky barrier diode can be made relatively small.

[0050] In addition, in a plan view of the semiconductor device, the area of ​​the Schottky junction region may be smaller than the area of ​​the third pad.

[0051] This allows the area of ​​the Schottky junction region in a plan view of the semiconductor device to be relatively small.

[0052] Therefore, in the semiconductor device having the above configuration, the reverse leakage current of the Schottky barrier diode can be made relatively small.

[0053] Furthermore, the third electrode and the low-concentration impurity layer may form a Schottky junction in a Schottky junction region, the first electrode and the semiconductor layer may be joined in a source junction region, and in a plan view of the semiconductor device, the Schottky junction region may be any one of a circle, an ellipse, an oval, and a rectangle with rounded corners, the source junction region may be a polygon with rounded corners, and a minimum radius of curvature of the outer periphery of the Schottky junction region may be equal to or greater than a minimum radius of curvature of the source junction region.

[0054] This makes it possible to suppress excessive concentration of the electric field in the Schottky junction region more effectively than in the source junction region.

[0055] Therefore, with the semiconductor device having the above configuration, the breakdown voltage characteristics of the semiconductor device can be determined not by excessive concentration of the electric field in the Schottky junction region but by excessive concentration of the electric field in the source junction region.

[0056] Specific examples of semiconductor devices according to an embodiment of the present disclosure will be described below with reference to the drawings. Each of the embodiments shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangement and connection of the components, steps (processes), and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0057] (Embodiment) A semiconductor device according to an embodiment will now be described. This semiconductor device is a chip-size package type semiconductor device that includes a vertical MOS transistor and a Schottky barrier diode.

[0058] <Structure of semiconductor device> Fig. 1 is a plan view schematically illustrating an example of the structure of a semiconductor device 1 according to an embodiment. In Fig. 1, a first electrode 61 (described later), a second electrode 62 (described later), a third electrode 63 (described later), a fourth electrode 64 (described later), a source junction region 91 (described later), an ohmic junction region 92 (described later), and a Schottky junction region 93 (described later) are indicated by dashed lines as if they could be seen from outside the semiconductor device 1. However, in reality, these cannot be seen directly from outside the semiconductor device 1.

[0059] As shown in FIG. 1, the semiconductor device 1 is a square having, in a counterclockwise direction when viewed from above, a first vertex 71, a second vertex 72, a third vertex 73, and a fourth vertex 74.

[0060] Here, in this specification, when the semiconductor device 1 is said to be square, it does not necessarily mean that the semiconductor device 1 is a rectangular shape in which the aspect ratio of the vertical side length to the horizontal side length of the rectangle is exactly 1.0, but rather means that the aspect ratio of the vertical side length to the horizontal side length is within the range of 0.9 to 1.1.

[0061] The semiconductor device 1 includes a first pad 51, a second pad 52, a third pad 53, and a fourth pad 54 on the top surface of the semiconductor device 1.

[0062] In a plan view of the semiconductor device 1, the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 are circular and have the same diameter.

[0063] In this specification, the pad being circular does not necessarily mean that the pad is an exact circle, but means that the pad has an approximately circular shape that is flattened within a range of ±1% from a perfect circle.

[0064] In a planar view of the semiconductor device 1, the center 151 of the first pad 51 and the center 153 of the third pad 53 are located on the first diagonal line 81 connecting the first vertex 71 and the third vertex 73, and the center 152 of the second pad 52 and the center 154 of the fourth pad 54 are located on the second diagonal line 82 connecting the second vertex 72 and the fourth vertex 74.

[0065] When viewed in a plane, the distance between the center 121 of the semiconductor device 1 and the center 151 of the first pad 51, the distance between the center 121 of the semiconductor device 1 and the center 152 of the second pad 52, the distance between the center 121 of the semiconductor device 1 and the center 153 of the third pad 53, and the distance between the center 121 of the semiconductor device 1 and the center 154 of the fourth pad 54 are equal.

[0066] In the following, as shown in Figure 1, when viewed in a plane, the semiconductor device 1 is described as having an area divided into four equal non-overlapping square regions of equal shape: a first square region 41 whose diagonal is a line connecting the first vertex 71 and the center 121 of the semiconductor device 1; a second square region 42 whose diagonal is a line connecting the second vertex 72 and the center 121 of the semiconductor device 1; a third square region 43 whose diagonal is a line connecting the third vertex 73 and the center 121 of the semiconductor device 1; and a fourth square region 44 whose diagonal is a line connecting the fourth vertex 74 and the center 121 of the semiconductor device 1.

[0067] In a planar view of the semiconductor device 1, the first pad 51 is contained within the first square region 41, the second pad 52 is contained within either the second square region 42 or the fourth square region 44, the third pad 53 is contained within the third square region 43, and the fourth pad 54 is contained within the other square region of either the second square region 42 or the fourth square region 44.

[0068] In this embodiment, as an example that is not necessarily limiting, the second pad 52 is described as being contained within the second square region 42, and the fourth pad 54 is described as being contained within the fourth square region 44, as shown in FIG.

[0069] In the following description, the square region that is either the second square region 42 or the fourth square region 44 (here, the second square region 42), that is, in a planar view of the semiconductor device 1, the square region between the second square region 42 and the fourth square region 44 that contains the second pad 52 (here, the second square region 42), will also be referred to as the second pad-containing square region 42.

[0070] In addition, in the following description, the other square region of the second square region 42 and the fourth square region 44 (here, the fourth square region 44), that is, in a planar view of the semiconductor device 1, the square region of the second square region 42 and the fourth square region 44 that contains the fourth pad 54 (here, the fourth square region 44), will also be referred to as the fourth pad-containing square region 44.

[0071] FIG. 2 is a schematic cross-sectional view showing an example of the configuration of the semiconductor device 1, and is a schematic cross-sectional view showing a cross section of the semiconductor device 1 taken along line II in FIG.

[0072] The structure of the semiconductor device 1 will be further described below with reference to FIG. 2 in addition to FIG.

[0073] As shown in FIG. 2, the semiconductor device 1 includes a semiconductor layer 40, an interlayer insulating layer 34, a passivation layer 35, a first electrode 61, a second electrode 62, a third electrode 63, and a fourth electrode 64.

[0074] The semiconductor layer 40 is configured by stacking a semiconductor substrate 32 and a low concentration impurity layer 33.

[0075] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities at a first concentration.

[0076] The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is made of silicon of the first conductivity type containing impurities at a second concentration lower than the first concentration. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0077] Here, the second concentration is a concentration at which, when the low-concentration impurity layer 33 comes into contact with a first metal layer 63A (described later), a Schottky barrier is formed at the contact surface between the low-concentration impurity layer 33 and the first metal layer 63A. In other words, the second concentration is a concentration at which a Schottky junction is formed between the low-concentration impurity layer 33 and the first metal layer 63A at the contact surface between the low-concentration impurity layer 33 and the first metal layer 63A.

[0078] Generally, there are two types of conductivity types for semiconductors: P type and N type. The first conductivity type may be P type or N type. For convenience of explanation, the first conductivity type will be described as N type and the second conductivity type described below as P type. However, the first conductivity type may be P type and the second conductivity type may be N type.

[0079] The interlayer insulating layer 34 is disposed on the upper surface of the semiconductor layer 40 and on the upper surface of the gate conductor 15 inside the gate trench 17 described later, and is formed in contact with the low-concentration impurity layer 33. The interlayer insulating layer 34 is mainly formed of an oxide film.

[0080] The passivation layer 35 is a protective film that covers the upper surfaces of the interlayer insulating layer 34, the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64, and has an opening that exposes the first pad 51 to the outside of the semiconductor device 1, an opening that exposes the second pad 52 to the outside of the semiconductor device 1, an opening that exposes the third pad 53 to the outside of the semiconductor device 1, and an opening that exposes the fourth pad 54 to the outside of the semiconductor device 1.

[0081] Here, the phrase "the passivation layer 35 covers the upper surfaces of the interlayer insulating layer 34, the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64" refers to a state in which the passivation layer 35 is formed on almost the entire surface of the semiconductor device 1, excluding the openings, in a plan view of the semiconductor device 1. Here, "almost the entire surface of the semiconductor device 1" refers to the entire surface of the semiconductor device 1, excluding a small peripheral region that remains on each side of the semiconductor device 1 after dicing, among the areas of the wafer reserved as dicing margins when dicing the semiconductor device 1 from the wafer. Therefore, in this peripheral region, the interlayer insulating layer 34 is exceptionally exposed on the upper surface of the semiconductor device 1.

[0082] Furthermore, the opening in the passivation layer 35 in the present disclosure refers to a shape in which the entire periphery of the opening is closed by the passivation layer 35 in a plan view of the semiconductor device 1. For this reason, a shape in which a part of the periphery in a plan view of the semiconductor device 1 overlaps with the exceptional peripheral region where the interlayer insulating layer 34 is exposed on the top surface of the semiconductor device 1 does not correspond to the opening in the passivation layer 35 in the present disclosure.

[0083] The first electrode 61 is composed of a first metal layer 61A formed in contact with the upper surface of the semiconductor layer 40, a second metal layer 61B formed in contact with the upper surface of the first metal layer 61A, a third metal layer 61C formed in contact with the upper surface of the second metal layer 61B, a fourth metal layer 61D formed in contact with the upper surface of the third metal layer 61C, and a fifth metal layer 61E formed in contact with the upper surface of the fourth metal layer 61D.

[0084] As a non-limiting example, the first metal layer 61A is made of titanium with a thickness of several tens of nm, and functions as a metal member that forms the contact surface where the first electrode 61 and the semiconductor layer 40 come into contact.

[0085] The first metal layer 61A may be formed, for example, by sputtering titanium onto the top surface of the semiconductor layer 40.

[0086] As a non-limiting example, the second metal layer 61B is made of titanium nitride with a thickness of several tens of nm, and functions as a barrier metal that prevents the metal that makes up the third metal layer 61C from diffusing into the semiconductor layer 40.

[0087] The second metal layer 61B may be formed, for example, by sputtering titanium nitride onto the top surface of the first metal layer 61A.

[0088] The third metal layer 61C is, as a non-limiting example, made of aluminum or an alloy containing aluminum as a main component, with a thickness of several μm.

[0089] The third metal layer 61C may be formed, for example, by sputtering aluminum or an alloy containing aluminum as a main component onto the upper surface of the second metal layer 61B.

[0090] As a non-limiting example, the fourth metal layer 61D is made of nickel with a thickness of several μm and functions as a barrier metal that prevents the metal that makes up the third metal layer 61C from diffusing into the fifth metal layer 61E described later.

[0091] The fourth metal layer 61D may be formed, for example, by plating nickel on the top surface of the third metal layer 61C.

[0092] As a non-limiting example, the fifth metal layer 61E is made of gold with a thickness of several hundred nm, and functions as a metal member for increasing wettability when joining the first electrode 61 to a joining material such as solder.

[0093] The fifth metal layer 61E may be formed, for example, by plating gold on the upper surface of the fourth metal layer 61D.

[0094] The upper surface of the fifth metal layer 61E is exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35. The upper surface of the fifth metal layer 61E exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35 serves as a first pad 51.

[0095] That is, the first pad 51 is a portion of the upper surface of the first electrode 61 that is exposed to the upper surface of the semiconductor device 1 through the opening in the passivation layer .

[0096] As shown in FIG. 1, in a plan view of the semiconductor device 1, at least a portion of the first electrode 61 is included within the first square region 41.

[0097] Here, as an example that does not necessarily need to be limited, as shown in FIG. 1, in a plan view of the semiconductor device 1, the first electrode 61 is described as being at least partially contained within the second square region 42, the third square region 43, and the fourth square region 44.

[0098] However, the first electrode 61 does not necessarily have to be at least partially included in the second square region 42, the third square region 43, and the fourth square region 44 in a plan view of the semiconductor device 1.

[0099] The second electrode 62 is composed of a first metal layer 62A formed in contact with the upper surface of the semiconductor layer 40, a second metal layer 62B formed in contact with the upper surface of the first metal layer 62A, a third metal layer 62C formed in contact with the upper surface of the second metal layer 62B, a fourth metal layer 62D formed in contact with the upper surface of the third metal layer 62C, and a fifth metal layer 62E formed in contact with the upper surface of the fourth metal layer 62D.

[0100] As a non-limiting example, the first metal layer 62A is made of titanium with a thickness of several tens of nm, and functions as a metal member that forms the contact surface where the second electrode 62 and the semiconductor layer 40 come into contact.

[0101] The first metal layer 62A may be formed, for example, by sputtering titanium onto the top surface of the semiconductor layer 40.

[0102] As a non-limiting example, the second metal layer 62B is made of titanium nitride with a thickness of several tens of nm, and functions as a barrier metal that prevents the metal that makes up the third metal layer 62C from diffusing into the semiconductor layer 40.

[0103] The second metal layer 62B may be formed, for example, by sputtering titanium nitride onto the top surface of the first metal layer 62A.

[0104] The third metal layer 62C is made of aluminum or an alloy containing aluminum as a main component, as a non-limiting example, and has a thickness of several μm.

[0105] The third metal layer 62C may be formed, for example, by sputtering aluminum or an alloy containing aluminum as a main component onto the upper surface of the second metal layer 62B.

[0106] As a non-limiting example, the fourth metal layer 62D is made of nickel with a thickness of several μm and functions as a barrier metal that prevents the metal that makes up the third metal layer 62C from diffusing into the fifth metal layer 62E described below.

[0107] The fourth metal layer 62D may be formed, for example, by plating nickel on the top surface of the third metal layer 62C.

[0108] As a non-limiting example, the fifth metal layer 62E is made of gold with a thickness of several hundred nm, and functions as a metal member for increasing wettability when joining the second electrode 62 to a joining material such as solder.

[0109] The fifth metal layer 62E may be formed, for example, by plating gold on the top surface of the fourth metal layer 62D.

[0110] The upper surface of the fifth metal layer 62E is exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35. The upper surface of the fifth metal layer 62E exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35 serves as the second pad 52.

[0111] That is, the second pad 52 is a portion of the upper surface of the second electrode 62 that is exposed to the upper surface of the semiconductor device 1 through the opening in the passivation layer 35.

[0112] As shown in FIG. 1, in a plan view of the semiconductor device 1, at least a portion of the second electrode 62 is included in the second square region , that is, the second pad-including square region .

[0113] Here, as an example that does not necessarily need to be limited, the second electrode 62 will be described as being entirely contained within the second square region 42, i.e., the second pad-containing square region 42, in a planar view of the semiconductor device 1, as shown in FIG.

[0114] The third electrode 63 is composed of a first metal layer 63A formed in contact with the upper surface of the semiconductor layer 40, a second metal layer 63B formed in contact with the upper surface of the first metal layer 63A, a third metal layer 63C formed in contact with the upper surface of the second metal layer 63B, a fourth metal layer 63D formed in contact with the upper surface of the third metal layer 63C, and a fifth metal layer 63E formed in contact with the upper surface of the fourth metal layer 63D.

[0115] As a non-limiting example, the first metal layer 63A is made of titanium, vanadium, molybdenum, tungsten, or platinum and has a thickness of several tens of nm, and functions as a metal member that forms the contact surface where the third electrode 63 and the semiconductor layer 40 come into contact.

[0116] The first metal layer 63A may be formed, for example, by sputtering titanium, vanadium, molybdenum, tungsten, or platinum onto the top surface of the semiconductor layer 40.

[0117] As a non-limiting example, the second metal layer 63B is made of titanium nitride with a thickness of several tens of nm, and functions as a barrier metal that prevents the metal that makes up the third metal layer 63C from diffusing into the semiconductor layer 40.

[0118] The second metal layer 63B may be formed, for example, by sputtering titanium nitride onto the top surface of the first metal layer 63A.

[0119] The third metal layer 63C is, as a non-limiting example, made of aluminum or an alloy containing aluminum as a main component, with a thickness of several μm.

[0120] The third metal layer 63C may be formed, for example, by sputtering aluminum or an alloy containing aluminum as a main component onto the upper surface of the second metal layer 63B.

[0121] As a non-limiting example, the fourth metal layer 63D is made of nickel with a thickness of several μm and functions as a barrier metal to prevent the metal constituting the third metal layer 63C from diffusing into the fifth metal layer 63E described later.

[0122] The fourth metal layer 63D may be formed, for example, by plating nickel on the top surface of the third metal layer 63C.

[0123] As a non-limiting example, the fifth metal layer 63E is made of gold with a thickness of several hundred nm, and functions as a metal member for increasing wettability when joining the third electrode 63 to a joining material such as solder.

[0124] The fifth metal layer 63E may be formed, for example, by plating gold on the upper surface of the fourth metal layer 63D.

[0125] The upper surface of the fifth metal layer 63E is exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35. The upper surface of the fifth metal layer 63E exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35 serves as the third pad 53.

[0126] That is, the third pad 53 is a portion of the upper surface of the third electrode 63 that is exposed to the upper surface of the semiconductor device 1 through the opening in the passivation layer 35.

[0127] As shown in FIG. 1, in a plan view of the semiconductor device 1, at least a portion of the third electrode 63 is included within the third square region 43.

[0128] Here, as an example that does not necessarily need to be limited, the third electrode 63 will be described as being entirely contained within the third square region 43 in a plan view of the semiconductor device 1 as shown in FIG.

[0129] The fourth electrode 64 is composed of a first metal layer 64A formed in contact with the upper surface of the interlayer insulating layer 34, a second metal layer 64B formed in contact with the upper surface of the first metal layer 64A, a third metal layer 64C formed in contact with the upper surface of the second metal layer 64B, a fourth metal layer 64D formed in contact with the upper surface of the third metal layer 64C, and a fifth metal layer 64E formed in contact with the upper surface of the fourth metal layer 64D.

[0130] The first metal layer 64A is made of titanium with a thickness of several tens of nm, as a non-limiting example.

[0131] The first metal layer 64A may be formed, for example, by sputtering titanium onto the top surface of the interlayer insulating layer .

[0132] The second metal layer 64B is made of titanium nitride having a thickness of several tens of nm, as a non-limiting example.

[0133] The second metal layer 64B may be formed, for example, by sputtering titanium nitride on top of the first metal layer 64A.

[0134] The third metal layer 64C is made of aluminum or an alloy containing aluminum as a main component, as a non-limiting example, and has a thickness of several μm.

[0135] The third metal layer 64C may be formed, for example, by sputtering aluminum or an aluminum-based alloy onto the top surface of the second metal layer 64B.

[0136] As a non-limiting example, the fourth metal layer 64D is made of nickel with a thickness of several μm, and functions as a barrier metal that prevents the metal that makes up the third metal layer 64C from diffusing into the fifth metal layer 64E described below.

[0137] The fourth metal layer 64D may be formed, for example, by plating nickel on the top surface of the third metal layer 64C.

[0138] As a non-limiting example, the fifth metal layer 64E is made of gold with a thickness of several hundred nm, and functions as a metal member that enhances wettability when joining the fourth electrode 64 to a joining material such as solder.

[0139] The fifth metal layer 64E may be formed, for example, by plating gold on the top surface of the fourth metal layer 64D.

[0140] The upper surface of the fifth metal layer 64E is exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35. The upper surface of the fifth metal layer 64E exposed on the upper surface of the semiconductor device 1 through the opening in the passivation layer 35 serves as the fourth pad 54.

[0141] That is, the fourth pad 54 is a portion of the upper surface of the fourth electrode 64 that is exposed to the upper surface of the semiconductor device 1 through the opening in the passivation layer 35.

[0142] As shown in FIG. 1, in a plan view of the semiconductor device 1, at least a portion of the fourth electrode 64 is included in the fourth square region 44, that is, the fourth pad-including square region 44.

[0143] Here, as an example that does not need to be limited, in a plan view of the semiconductor device 1, as shown in FIG. 1, the fourth electrode 64 will be described as being entirely contained within the fourth square region 44, i.e., the fourth pad-containing square region 44.

[0144] In a plan view of the semiconductor device 1, a body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the region of the low-concentration impurity layer 33 contained within the first electrode 61, in a range from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0145] In the body region 18, a source region 14 of the first conductivity type containing impurities is formed in a range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the body region 18.

[0146] In addition, in a plan view of the semiconductor device 1, a plurality of gate trenches 17 are formed in the region of the low-concentration impurity layer 33 contained within the body region 18, in a range from the upper surface of the semiconductor layer 40 to a third predetermined depth that penetrates through the source region 14 and the body region 18 to a part of the low-concentration impurity layer 33.

[0147] A gate conductor 15 surrounded by a gate insulating film 16 is formed inside each of the gate trenches 17 .

[0148] Each of the gate conductors 15 is electrically connected to a fourth electrode 64 .

[0149] Gate conductor 15 is made of, by way of example and not limitation, impurity-doped polysilicon.

[0150] The upper surface of the semiconductor layer 40 is in contact with the first metal layer 61A in a region enclosed by the first electrode 61 when the semiconductor device 1 is seen in a plan view.

[0151] In the following description, the region where the upper surface of the semiconductor layer 40 and the first metal layer 61A are in contact with each other will be referred to as a source junction region 91.

[0152] In a plan view of the semiconductor device 1, a drain pull-up region 36 of the first conductivity type containing impurities at a third concentration higher than the second concentration is formed in the region of the low-concentration impurity layer 33 that is contained within the second electrode 62, and that extends from the upper surface of the semiconductor layer 40 through the low-concentration impurity layer 33 to the semiconductor substrate 32.

[0153] Here, the third concentration is a concentration at which, when the drain pull-up region 36 comes into contact with the first metal layer 62A, a Schottky barrier is not formed at the contact surface between the drain pull-up region 36 and the first metal layer 62A. In other words, the third concentration is a concentration at which an ohmic junction is formed between the drain pull-up region 36 and the first metal layer 62A at the contact surface between the drain pull-up region 36 and the first metal layer 62A.

[0154] The upper surface of the drain pull-up region 36 is in contact with the first metal layer 62A, thereby forming an ohmic junction between the upper surface of the drain pull-up region 36 and the first metal layer 62A in a region enclosed by the second electrode 62 in a plan view of the semiconductor device 1.

[0155] In the following description, the region where the upper surface of the drain pull-up region 36 and the first metal layer 62A form an ohmic junction, that is, the region where they are in contact, will be referred to as an ohmic junction region 92.

[0156] In the following description, among the metal layers constituting the second electrode 62, the first metal layer 62A in contact with the upper surface of the drain pull-up region 36 in the ohmic contact region 92 is also referred to as the ohmic contact metal layer 62A.

[0157] In a plan view of the semiconductor device 1, the upper surface of the drain pull-up region 36 includes the ohmic junction region 92. Therefore, the semiconductor layer 40 and the first metal layer 62A, that is, the ohmic junction metal layer 62A, are in contact with each other only in the ohmic junction region 92.

[0158] In a region enclosed by the third electrode 63 in a plan view of the semiconductor device 1, the upper surface of the low-concentration impurity layer 33 contacts the first metal layer 63A. As a result, a Schottky junction is formed between the upper surface of the low-concentration impurity layer 33 and the first metal layer 63A in a region enclosed by the third electrode 63 in a plan view of the semiconductor device 1.

[0159] In the following description, the region where the upper surface of the low-concentration impurity layer 33 and the first metal layer 63A form a Schottky junction, that is, the region where they are in contact, will be referred to as a Schottky junction region 93.

[0160] In the following description, among the metal layers constituting the third electrode 63, the first metal layer 63A in contact with the upper surface of the low-concentration impurity layer 33 in the Schottky junction region 93 will also be referred to as the Schottky junction metal layer 63A.

[0161] In a region of the low-concentration impurity layer 33 that surrounds the outer periphery of the Schottky junction region 93 in a plan view of the semiconductor device 1, a guard ring 37 containing impurities of a second conductivity type different from the first conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a fourth predetermined depth.

[0162] With the above configuration, the semiconductor device 1 includes the vertical MOS transistor 10 formed in the semiconductor layer 40, and the Schottky barrier diode 20 in which the low-concentration impurity layer 33 functions as a cathode when the first conductivity type is N-type, and functions as an anode when the first conductivity type is P-type.

[0163] FIG. 3A is a circuit diagram of the semiconductor device 1 when the first conductivity type is N type, i.e., when the second conductivity type is P type, and FIG. 3B is a circuit diagram of the semiconductor device 1 when the first conductivity type is P type, i.e., when the second conductivity type is N type.

[0164] As shown in FIG. 3A , when the first conductivity type is N type, the vertical MOS transistor 10 is a vertical N-channel MOS transistor 10, the first pad 51 is a pad that functions as a source pad of the vertical N-channel MOS transistor 10, the second pad 52 is a pad that functions as a drain pad of the vertical N-channel MOS transistor 10 and as a cathode pad of the Schottky barrier diode 20, the third pad 53 is a pad that functions as an anode pad of the Schottky barrier diode 20, and the fourth pad 54 is a pad that functions as a gate pad of the vertical N-channel MOS transistor 10.

[0165] That is, when the first conductivity type is N type, the first electrode 61 is an electrode that functions as a source electrode of the vertical N-channel MOS transistor 10, the second electrode 62 is an electrode that functions as a drain electrode of the vertical N-channel MOS transistor 10 and as a cathode electrode of the Schottky barrier diode 20, the third electrode 63 is an electrode that functions as an anode electrode of the Schottky barrier diode 20, and the fourth electrode 64 is an electrode that functions as a gate electrode of the vertical N-channel MOS transistor 10.

[0166] As shown in FIG. 3B , when the first conductivity type is P type, the vertical MOS transistor 10 is a vertical P-channel MOS transistor 10, the first pad 51 is a pad that functions as a source pad of the vertical P-channel MOS transistor 10, the second pad 52 is a pad that functions as a drain pad of the vertical P-channel MOS transistor 10 and as an anode pad of the Schottky barrier diode 20, the third pad 53 is a pad that functions as a cathode pad of the Schottky barrier diode 20, and the fourth pad 54 is a pad that functions as a gate pad of the vertical P-channel MOS transistor 10.

[0167] That is, when the first conductivity type is P type, the first electrode 61 is an electrode that functions as a source electrode of the vertical P-channel MOS transistor 10, the second electrode 62 is an electrode that functions as a drain electrode of the vertical P-channel MOS transistor 10 and as an anode electrode of the Schottky barrier diode 20, the third electrode 63 is an electrode that functions as a cathode / node electrode of the Schottky barrier diode 20, and the fourth electrode 64 is an electrode that functions as a gate electrode of the vertical P-channel MOS transistor 10.

[0168] <Consideration> The semiconductor device 1 having the above configuration is an unsealed chip-size package type semiconductor device that has four pads, i.e., four terminals, on its top surface, which serves as the mounting surface on which the semiconductor device 1 is mounted on a mounting board or the like, and enables the vertical MOS transistor 10 and the Schottky barrier diode 20 to function as independent elements.

[0169] Therefore, the semiconductor device 1 having the above configuration can be made smaller in size in plan view than a conventional semiconductor device that has at least five terminals on the mounting surface and in which a MOS transistor and a Schottky barrier diode are sealed in a single package so that they can function as independent elements.

[0170] Thus, the semiconductor device 1 having the above configuration provides a semiconductor device that includes a MOS transistor and a Schottky barrier diode so that each can function as an independent element, and that can be made smaller in size in a planar view than conventional semiconductor devices.

[0171] Conventionally available semiconductor devices that have at least five terminals on the mounting surface and in which a MOS transistor and a Schottky barrier diode are sealed in a single package so that they can function as independent elements all have a size of 2.0 mm × 2.0 mm or more when viewed in a plane, whereas semiconductor device 1 typically has a size of 0.6 mm × 0.6 mm when viewed in a plane.

[0172] In the semiconductor device 1 having the above configuration, when viewed in a plane, at least a portion of the first electrode 61 is contained within the first square region 41, the second electrode 62 is contained within a square region that is either the second square region 42 or the fourth square region 44, the third electrode 63 is contained within the third square region 43, and the fourth electrode 64 is contained within the square region that is the other of the second square region 42 and the fourth square region 44.

[0173] Therefore, the distance between the anode electrode and the cathode electrode of the Schottky barrier diode 20 can be made relatively short, and the distance between the source electrode and the drain electrode of the vertical MOS transistor 10 can be made relatively short.

[0174] Therefore, according to the semiconductor device 1 having the above configuration, the forward voltage of the Schottky barrier diode 20 can be made relatively small, and the conduction resistance of the vertical MOS transistor 10 can be made relatively small.

[0175] FIG. 4 is a comparative diagram comparing the conduction resistance of a vertical MOS transistor in a comparative example semiconductor device 1000, which is configured by swapping the positions of the second electrode 62 and the third electrode 63 in a plan view of the semiconductor device 1, with the conduction resistance of the vertical MOS transistor 10 in the semiconductor device 1.

[0176] That is, as shown in FIG. 4, in a plan view of the semiconductor device 1000 according to the comparative example, at least a portion of the first electrode 1061 according to the comparative example and the first pad 1051 according to the comparative example are contained within the first square region 41, the third electrode 1063 according to the comparative example and the third pad 1053 according to the comparative example are contained within the second square region 42, the second electrode 1062 according to the comparative example and the second pad 1052 according to the comparative example are contained within the third square region 43, and the fourth electrode 1064 according to the comparative example and the fourth pad 1054 according to the comparative example are disposed at positions contained within the fourth square region 44.

[0177] In FIG. 4, VGS is the voltage applied between the gate and source of the vertical MOS transistor according to the comparative example and the vertical MOS transistor 10.

[0178] In addition, in FIG. 4, the values ​​of the conduction resistance of the vertical MOS transistor according to the comparative example and the values ​​of the conduction resistance of the vertical MOS transistor 10 are examples of simulation values ​​when simulations are performed under the same conditions.

[0179] As shown in FIG. 4, the value of the conduction resistance of the vertical MOS transistor 10 is lower than the value of the conduction resistance of the vertical MOS transistor according to the comparative example.

[0180] In this way, in a planar view of the semiconductor device 1, the first electrode 61 is contained within the first square region 41, the second electrode 62 is contained within a square region that is either the second square region 42 or the fourth square region 44, the third electrode 63 is contained within the third square region 43, and the fourth electrode 64 is contained within a square region that is the other of the second square region 42 and the fourth square region 44, thereby making the conduction resistance of the vertical MOS transistor 10 relatively small.

[0181] In the embodiment, the Schottky barrier diode 20 has been described as being of a planar type, as shown in Fig. 2. Here, the planar type Schottky barrier diode refers to a Schottky barrier diode having a structure in which a single impurity semiconductor and a metal form a Schottky junction in a flat portion of the single impurity semiconductor.

[0182] However, the Schottky barrier diode 20 being a planar type is just an example, and the Schottky barrier diode 20 is not necessarily limited to the planar type.

[0183] Generally, a planar Schottky barrier diode can be formed with a relatively small number of processing steps, so if the Schottky barrier diode 20 is a planar type, the semiconductor device 1 can be manufactured relatively easily.

[0184] The metal members of the first metal layer 61A, the first metal layer 62A, the first metal layer 63A, and the first metal layer 64A are the same; the metal members of the second metal layer 61B, the second metal layer 62B, the second metal layer 63B, and the second metal layer 64B are the same; the metal members of the third metal layer 61C, the third metal layer 62C, and the third metal layer 64A are the same; The metal components of metal layer 63C and the third metal layer 64C may be equal, the metal components of fourth metal layer 61D, fourth metal layer 62D, fourth metal layer 63D and fourth metal layer 64D may be equal, and the metal components of fifth metal layer 61E, fifth metal layer 62E, fifth metal layer 63E and fifth metal layer 64E may be equal.

[0185] This allows the first metal layer 61A to the first metal layer 64A to be formed in the same processing step, the second metal layer 61B to the second metal layer 64B to be formed in the same processing step, the third metal layer 61C to the third metal layer 64C to be formed in the same processing step, the fourth metal layer 61D to the fourth metal layer 64D to be formed in the same processing step, and the fifth metal layer 61E to the fifth metal layer 64E to be formed in the same processing step.

[0186] Therefore, the semiconductor device 1 can be manufactured relatively easily.

[0187] On the other hand, the metal material of the first metal layer 62A, that is, the ohmic junction metal layer 62A, and the metal material of the first metal layer 63A, that is, the Schottky junction metal layer 63A may be different from each other.

[0188] This allows the Schottky barrier diode 20 to have desired characteristics that cannot be achieved when the metal material of the ohmic junction metal layer 62A and the metal material of the Schottky junction metal layer 63A are the same.

[0189] In general, the characteristics of a Schottky barrier diode change depending on the type of metal material that forms the Schottky junction surface.

[0190] FIG. 5 is a correlation diagram schematically showing the relationship between the type of metal material forming the Schottky junction surface and the characteristics of the Schottky barrier diode when the first conductivity type is N-type.

[0191] In Figure 5, Φ indicates the size of the Schottky barrier of the Schottky barrier diode, VF indicates the forward voltage of the Schottky barrier diode, and IR indicates the reverse leakage current of the Schottky barrier diode. Also in Figure 5, Ti indicates that the metal material is titanium, V indicates that the metal material is vanadium, Mo indicates that the metal material is molybdenum, W indicates that the metal material is tungsten, and Pt indicates that the metal material is platinum.

[0192] As shown in FIG. 5, in general, there is a trade-off between the forward voltage VF and the reverse leakage current IR in a Schottky barrier diode.

[0193] Therefore, if the metal material of the ohmic junction metal layer 62A and the Schottky junction metal layer 63A is the same, the desired characteristics of the Schottky barrier diode 20 may not be realized. In this case, the metal material of the Schottky junction metal layer 63A may be an appropriate metal material different from the metal material of the ohmic junction metal layer 62A, thereby realizing the desired characteristics of the Schottky barrier diode 20 that cannot be realized if the metal material of the Schottky junction metal layer 63A is the same.

[0194] For example, when the metal member of the ohmic junction metal layer 62A is titanium, if the metal member of the Schottky junction metal layer 63A is titanium, the desired characteristics of the Schottky barrier diode 20 cannot be realized, whereas if the metal member of the Schottky junction metal layer 63A is platinum, the desired characteristics of the Schottky barrier diode 20 can be realized. In this case, the metal member of the Schottky junction metal layer 63A may be platinum, which is different from titanium, which is the metal member of the ohmic junction metal layer 62A.

[0195] As shown in FIG. 1, in a plan view of the semiconductor device 1, the Schottky junction region 93 may be any one of a circle, an ellipse, an oval, and a rectangle with rounded corners (an oval in the example of FIG. 1).

[0196] The Schottky junction region 93 having the above-described configuration has no corners, which alleviates excessive concentration of the electric field in the Schottky junction region 93.

[0197] Therefore, according to the semiconductor device 1 having the above configuration, the breakdown voltage characteristics of the Schottky junction region 93 can be improved.

[0198] As shown in FIG. 1, in a plan view of the semiconductor device 1, the shortest distance dd between the Schottky junction region 93 and the ohmic junction region 92 may be shorter than the shortest distance ds between the Schottky junction region 93 and the source junction region 91.

[0199] In the semiconductor device 1 having the above configuration, the distance between the Schottky junction region 93 and the ohmic junction region 92 can be made relatively small.

[0200] Therefore, according to the semiconductor device 1 having the above configuration, the forward voltage of the Schottky barrier diode 20 can be made relatively small.

[0201] As shown in FIG. 1 , the relationship in size between the area of ​​the Schottky junction region 93 and the area of ​​the third pad 53 in the plan view of the semiconductor device 1 may be such that the area of ​​the Schottky junction region 93 is smaller than the area of ​​the third pad 53, or conversely, the area of ​​the Schottky junction region 93 is larger than the area of ​​the third pad 53.

[0202] When the area of ​​the Schottky junction region 93 is larger than the area of ​​the third pad 53 in a plan view of the semiconductor device 1, the area of ​​the Schottky junction region 93 can be made relatively large.

[0203] This allows the conduction resistance of the Schottky barrier diode 20 in the forward direction to be relatively small.

[0204] Therefore, according to the semiconductor device 1 having the above configuration, the forward voltage of the Schottky barrier diode 20 can be made relatively small.

[0205] Furthermore, when the area of ​​the Schottky junction region 93 is smaller than the area of ​​the third pad 53 in a plan view of the semiconductor device 1, the area of ​​the Schottky junction region 93 can be made relatively small.

[0206] Therefore, according to the semiconductor device 1 having the above configuration, the reverse leakage current of the Schottky barrier diode 20 can be made relatively small.

[0207] As shown in FIG. 1 , in a plan view of the semiconductor device 1, the Schottky junction region 93 is any one of a circle, an ellipse, an oval, and a rectangle with rounded corners, and the source junction region 91 is a polygon with rounded corners (in the embodiment, it is exemplified as a rectangle with rounded corners, and in Modifications 1 and 2 described below, it is exemplified as a polygon with more corners than a rectangle with rounded corners), and the minimum radius of curvature on the outer periphery of the Schottky junction region 93 may be equal to or greater than the minimum radius of curvature of the source junction region 91.

[0208] This makes it possible to suppress excessive concentration of the electric field in the Schottky junction region 93 more effectively than the suppression of excessive concentration of the electric field in the source junction region 91 .

[0209] Therefore, according to the semiconductor device 1 having the above configuration, the breakdown voltage characteristics of the semiconductor device 1 can be determined not by excessive concentration of the electric field in the Schottky junction region 93 but by excessive concentration of the electric field in the source junction region 91.

[0210] As mentioned above, in the embodiment, the first electrode 61 has been described as being at least partially contained within the second square region 42, the third square region 43, and the fourth square region 44 in a planar view of the semiconductor device 1, as an example that does not necessarily need to be limited to this, as shown in FIG.

[0211] In this case, as shown in FIG. 1, in a plan view of the semiconductor device 1, the first square region 41 may not include at least a portion of the second electrode 62, at least a portion of the third electrode 63, and at least a portion of the fourth electrode 64.

[0212] This allows the semiconductor device 1 to have a relatively large active region, which is a region that includes all the locations where channels are formed when a voltage equal to or greater than the threshold voltage is applied to the gate conductor 15 of the vertical MOS transistor 10. This allows the semiconductor device 1 to have a relatively small on-resistance of the vertical MOS transistor 10.

[0213] On the other hand, as mentioned above, the first electrode 61 does not necessarily have to be at least partially contained within the second square region 42, the third square region 43, and the fourth square region 44 when viewed in a plan view of the semiconductor device 1.

[0214] FIG. 6 is a schematic plan view showing another example of the structure of the semiconductor device 1. As shown in FIG.

[0215] As shown in FIG. 6, the first electrode 61 may be entirely contained within the first square region 41 when the semiconductor device 1 is seen in plan view, for example.

[0216] (Variation 1) Hereinafter, a semiconductor device according to Modification 1 will be described, in which the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64 of the semiconductor device 1 according to the embodiment are changed to the first electrode according to Modification 1, the second electrode according to Modification 1, the third electrode according to Modification 1, and the fourth electrode according to Modification 1, respectively, and the source junction region 91, the ohmic junction region 92, and the Schottky junction region 93 are changed to the source junction region according to Modification 1, the ohmic junction region according to Modification 1, and the Schottky junction region according to Modification 1, respectively.

[0217] Here, for the semiconductor device of variant 1, the components that are similar to those of semiconductor device 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor device 1.

[0218] FIG. 7 is a schematic plan view showing an example of the structure of a semiconductor device 1A according to the first modification.

[0219] As shown in FIG. 7, the semiconductor device 1A is configured by changing the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64 of the semiconductor device 1 according to the embodiment to a first electrode 161, a second electrode 162, a third electrode 163, and a fourth electrode 164, respectively, and changing the source junction region 91, the ohmic junction region 92, and the Schottky junction region 93 to a source junction region 191, an ohmic junction region 192, and a Schottky junction region 193, respectively.

[0220] In FIG. 7, as in FIG. 1, the first electrode 161, the second electrode 162, the third electrode 163, the fourth electrode 164, the source junction region 191, the ohmic junction region 192, and the Schottky junction region 193 are shown by dashed lines as if they could be seen from outside the semiconductor device 1A, but in reality, they cannot be seen directly from outside the semiconductor device 1A.

[0221] As shown in Figure 7, in a planar view of the semiconductor device 1A, a portion of the first electrode 161 is contained within the first square region 41, and another portion is also contained within the second square region 42 so as to protrude between the second electrode 162 and the third electrode 163, and another portion is also contained within the fourth square region 44 so as to protrude between the third electrode 163 and the fourth electrode 164.

[0222] Accordingly, in a planar view of the semiconductor device 1A, a portion of the source junction region 191 is contained within the first square region 41, and another portion thereof is also contained within the second square region 42 so as to protrude between the second electrode 162 and the third electrode 163, and another portion thereof is also contained within the fourth square region 44 so as to protrude between the third electrode 163 and the fourth electrode 164.

[0223] Also, as shown in FIG. 7, in a plan view of the semiconductor device 1A, the first square region 41 does not include at least a portion of the second electrode 162, at least a portion of the third electrode 163, and at least a portion of the fourth electrode 164.

[0224] With the above configuration, the semiconductor device 1A can have a relatively large active region, which is a region of the vertical MOS transistor 10 that includes all the locations where a channel is formed when a voltage equal to or greater than the threshold voltage is applied to the gate conductor 15. This allows the semiconductor device 1A to have a relatively small on-resistance of the vertical MOS transistor 10.

[0225] Also, as shown in Figure 7, in a plan view of the semiconductor device 1A, the second electrode 162 is rectangular having a first opposing side 621 having a portion that is parallel to and opposite a first part 611 of the outer periphery of the first electrode 161, and a second opposing side 622 having a portion that is parallel to and opposite a second part 612 of the outer periphery of the first electrode 161.

[0226] With the above configuration, the semiconductor device 1A can make the opposing length between the first electrode 161 functioning as the source electrode of the vertical MOS transistor 10 and the second electrode 162 functioning as the drain electrode of the vertical MOS transistor 10 relatively long. Therefore, the semiconductor device 1A can make the conduction resistance of the vertical MOS transistor 10 relatively small.

[0227] (Variation 2) Hereinafter, in the semiconductor device 1A according to the first modification, the first electrode 161 and the fourth electrode 164 are arranged such that, in a plan view of the semiconductor device 1A, a part of the first electrode 161 protrudes between the third electrode 163 and the fourth electrode 164, while another part of the first electrode 161 does not protrude between the second electrode 162 and the third electrode 163, and a part of the source junction region 191 protrudes between the third electrode 163 and the fourth electrode 164, while another part of the source junction region 191 does not protrude between the second electrode 162 and the third electrode 163. The following describes a semiconductor device according to Modification 2, in which the second electrode 162, the third electrode 163, and the fourth electrode 164 are changed to the first electrode according to Modification 2, the second electrode according to Modification 2, the third electrode according to Modification 2, and the fourth electrode according to Modification 2, respectively, and the source junction region 191, the ohmic junction region 192, and the Schottky junction region 193 are changed to the source junction region according to Modification 2, the ohmic junction region according to Modification 2, and the Schottky junction region according to Modification 2, respectively.

[0228] Here, for the semiconductor device of variant 2, the components that are similar to those of semiconductor device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor device 1A.

[0229] FIG. 8 is a schematic plan view showing an example of the structure of a semiconductor device 1B according to the second modification.

[0230] As shown in FIG. 8, the semiconductor device 1B is configured by changing the first electrode 161, the second electrode 162, the third electrode 163, and the fourth electrode 164 of the semiconductor device 1A of the first modification example to a first electrode 261, a second electrode 262, a third electrode 263, and a fourth electrode 264, respectively, and changing the source junction region 191, the ohmic junction region 192, and the Schottky junction region 193 to a source junction region 291, an ohmic junction region 292, and a Schottky junction region 293, respectively.

[0231] In Figure 8, as in Figures 1 and 7, the first electrode 261, the second electrode 262, the third electrode 263, the fourth electrode 264, the source junction region 291, the ohmic junction region 292, and the Schottky junction region 293 are shown by dashed lines as if they could be seen from outside the semiconductor device 1B, but in reality, they cannot be seen directly from outside the semiconductor device 1B.

[0232] As shown in Figure 8, in a plan view of the semiconductor device 1B, a portion of the first electrode 261 is contained within the first square region 41, and another portion of the first electrode 261 is also contained within the fourth square region 44 so as to protrude between the third electrode 263 and the fourth electrode 264, while not including a portion that protrudes between the second electrode 262 and the third electrode 263.

[0233] Accordingly, in a planar view of the semiconductor device 1B, a portion of the source junction region 291 is contained within the first square region 41, and another portion of the source junction region 291 is also contained within the fourth square region 44 so as to protrude between the third electrode 263 and the fourth electrode 264, while not including a portion that protrudes between the second electrode 262 and the third electrode 263.

[0234] In the semiconductor device 1B having the above configuration, unlike the semiconductor device 1A according to the first modification, the first electrode 261 functioning as the source electrode of the vertical MOS transistor 10 is not sandwiched between the second electrode 262 functioning as the cathode electrode of the Schottky barrier diode 20 and the third electrode 263 functioning as the anode electrode of the Schottky barrier diode 20.

[0235] Therefore, according to the semiconductor device 1B having the above configuration, it is possible to prevent the characteristics of the Schottky barrier diode 20 from deteriorating.

[0236] (supplement) The semiconductor device according to one aspect of the present disclosure has been described above based on the embodiment, Modification 1, and Modification 2, but the present disclosure is not limited to these, the embodiment, Modification 1, and Modification 2. Various modifications that would occur to a person skilled in the art may be applied to the embodiment, Modification 1, or Modification 2 without departing from the spirit of the present disclosure, and may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0237] The present disclosure is widely applicable to semiconductor devices. [Explanation of symbols]

[0238] 1, 1A, 1B, 1000 Semiconductor device 10 Vertical MOS transistor, vertical N-channel MOS transistor, vertical P-channel MOS transistor 14 Source Region 15 Gate conductor 16 Gate insulating film 17 Gate Trench 18 Body Region 20 Schottky barrier diode 32 Semiconductor substrate 33 Low concentration impurity layer 34 Interlayer insulating layer 35 Passivation Layer 36 Drain pull-up region 37 Guard Ring 40 Semiconductor layer 41 First square area 42 Second square area, second pad-enclosed square area 43 Third Square Area 44 4th square area, 4th pad-enclosed square area 51, 1051 First Pad 52, 1052 Second Pad 53, 1053 Third Pad 54, 1054 4th pad 61, 161, 261, 1061 First electrode 61A, 64A First metal layer 62A First metal layer, ohmic contact metal layer 63A First Metal Layer, Schottky Junction Metal Layer 61B, 62B, 63B, 64B Second metal layer 61C, 62C, 63C, 64C Third metal layer 61D, 62D, 63D, 64D Fourth metal layer 61E, 62E, 63E, 64E Fifth metal layer 62, 162, 262, 1062 Second electrode 63, 163, 263, 1063 Third electrode 64, 164, 264, 1064 4th electrode 71 First Peak 72 Second Peak 73 The Third Vertex 74 The Fourth Vertex 81 First Diagonal 82 Second Diagonal 91, 191, 291 Source junction area 92, 192, 292 Ohmic junction region 93, 193, 293 Schottky junction region 121, 151, 152, 153, 154 center 611 Part 1 612 Part 2 621 First opposing side 622 Second opposite side

Claims

1. A chip size package type semiconductor device, a semiconductor layer including a semiconductor substrate of a first conductivity type containing an impurity at a first concentration, and a low-concentration impurity layer of the first conductivity type formed in contact with an upper surface of the semiconductor substrate and containing an impurity at a second concentration lower than the first concentration; a vertical MOS transistor formed in the semiconductor layer; a Schottky barrier diode in which the low-concentration impurity layer functions as a cathode when the first conductivity type is N-type and functions as an anode when the first conductivity type is P-type, Furthermore, on the top surface of the semiconductor device, a first pad that functions as a source pad of the vertical MOS transistor; a second pad that functions as a drain pad of the vertical MOS transistor, and functions as a cathode pad of the Schottky barrier diode when the first conductivity type is N-type, and functions as an anode pad of the Schottky barrier diode when the first conductivity type is P-type; a third pad that functions as an anode pad of the Schottky barrier diode when the first conductivity type is N-type, and functions as a cathode pad of the Schottky barrier diode when the first conductivity type is P-type; a fourth pad that functions as a gate pad of the vertical MOS transistor; In a plan view of the semiconductor device, the semiconductor device is a square having, in counterclockwise order, a first vertex, a second vertex, a third vertex, and a fourth vertex; the first pad, the second pad, the third pad, and the fourth pad are circular and have the same diameter; a center of the first pad and a center of the third pad are located on a first diagonal line connecting the first vertex and the third vertex; a center of the second pad and a center of the fourth pad are located on a second diagonal line connecting the second vertex and the fourth vertex; The distance between the center of the semiconductor device and the center of the first pad, the distance between the center of the semiconductor device and the center of the second pad, the distance between the center of the semiconductor device and the center of the third pad, and the distance between the center of the semiconductor device and the center of the fourth pad are equal. Semiconductor device.

2. In a plan view of the semiconductor device, If the area of ​​the semiconductor device is divided into four equal non-overlapping square regions, namely a first square region having a diagonal line connecting the first vertex and the center of the semiconductor device, a second square region having a diagonal line connecting the second vertex and the center of the semiconductor device, a third square region having a diagonal line connecting the third vertex and the center of the semiconductor device, and a fourth square region having a diagonal line connecting the fourth vertex and the center of the semiconductor device, the first pad is contained within the first square area; the second pad is contained within a second pad-containing square area, which is either the second square area or the fourth square area; the third pad is contained within the third square area, the fourth pad is included in a fourth pad-including square area which is the other of the second square area and the fourth square area, the semiconductor layer further includes a drain pull-up region of the first conductivity type that is entirely included in the second pad-including square region in a plan view of the semiconductor layer, the drain pull-up region extending from an upper surface of the semiconductor layer through the low-concentration impurity layer to the semiconductor substrate and containing impurities at a third concentration higher than the second concentration; The semiconductor device further has, in a plan view of the semiconductor device, a first electrode that functions as a source electrode of the vertical MOS transistor, at least a portion of which is included in the first square region; a second electrode, at least a part of which is included in the second pad-included square region, which functions as a drain electrode of the vertical MOS transistor, and which functions as a cathode electrode of the Schottky barrier diode when the first conductivity type is N-type, and which functions as an anode electrode of the Schottky barrier diode when the first conductivity type is P-type; a third electrode at least a part of which is included in the third square region, which functions as an anode electrode of the Schottky barrier diode when the first conductivity type is N-type, and which functions as a cathode electrode of the Schottky barrier diode when the first conductivity type is P-type; a fourth electrode, at least a part of which is included in the fourth pad-including square region, which functions as a gate electrode of the vertical MOS transistor; The semiconductor device according to claim 1 .

3. The Schottky barrier diode is a planar type. The semiconductor device according to claim 2 .

4. the second electrode has a plurality of metal layers including an ohmic contact metal layer that forms an ohmic contact with the drain pull-up region; the third electrode has a plurality of metal layers including a Schottky junction metal layer that forms a Schottky junction with the low-concentration impurity layer; The metal material of the ohmic contact metal layer and the metal material of the Schottky contact metal layer are the same. The semiconductor device according to claim 2 .

5. the second electrode has a plurality of metal layers including an ohmic contact metal layer that forms an ohmic contact with the drain pull-up region; the third electrode has a plurality of metal layers including a Schottky junction metal layer that forms a Schottky junction with the low-concentration impurity layer; The metal material of the ohmic contact metal layer and the metal material of the Schottky contact metal layer are different from each other. The semiconductor device according to claim 2 .

6. In a plan view of the semiconductor device, the first electrode is at least partially included in the second pad-including square region and / or the fourth pad-including square region; The first square region does not include at least a part of the second electrode, at least a part of the third electrode, and at least a part of the fourth electrode. The semiconductor device according to claim 2 .

7. In a plan view of the semiconductor device, the second electrode is a rectangle having a first opposing side having a portion that is parallel to and opposed to a first part of the outer periphery of the first electrode, and a second opposing side having a portion that is parallel to and opposed to a second part of the outer periphery of the first electrode. The semiconductor device according to claim 6.

8. In a plan view of the semiconductor device, at least a part of the first electrode is not included in the second pad-including square region. The semiconductor device according to claim 6.

9. the third electrode and the low-concentration impurity layer form a Schottky junction in a Schottky junction region; the second electrode and the drain pull-up region form an ohmic junction in an ohmic junction region; the first electrode and the semiconductor layer are in contact with each other at a source junction region; In a plan view of the semiconductor device, the Schottky junction region is contained in the third electrode and has a shape selected from a circle, an ellipse, an oval, and a rectangle with rounded corners; The shortest distance between the Schottky junction region and the ohmic junction region is shorter than the shortest distance between the Schottky junction region and the source junction region. The semiconductor device according to claim 2 .

10. In a plan view of the semiconductor device, the area of ​​the Schottky junction region is larger than the area of ​​the third pad. The semiconductor device according to claim 9 .

11. In a plan view of the semiconductor device, the area of ​​the Schottky junction region is smaller than the area of ​​the third pad. The semiconductor device according to claim 9 .

12. the third electrode and the low-concentration impurity layer form a Schottky junction in a Schottky junction region; the first electrode and the semiconductor layer are joined at a source junction region; In a plan view of the semiconductor device, the Schottky junction region is any one of a circle, an ellipse, an oval, and a rectangle with rounded corners; the source junction region is a polygon with rounded corners, The minimum radius of curvature of the outer periphery of the Schottky junction region is equal to or greater than the minimum radius of curvature of the source junction region. The semiconductor device according to claim 2 .

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