Semiconductor light emitting device and method for manufacturing the same

Abstract

To provide a semiconductor light emitting element and a method for manufacturing a semiconductor light emitting element capable of increasing light out-coupling in the main or back surface direction even in a semiconductor light emitting element having a columnar semiconductor layer.SOLUTION: A semiconductor light emitting element (10) has a growth substrate (11), a plurality of columnar semiconductor layers (14-16) formed on the growth substrate (11), and an embedding layer (18) formed over the columnar semiconductor layers (14-16), and a side reflection portion (17) is formed on a side of the columnar semiconductor layers (14-16), which reflects at least part of light from the columnar semiconductor layers (14-16).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device having a structure in which a plurality of columnar semiconductor layers are buried in a burying layer, and a method for manufacturing the same. [Background technology]

[0002] In recent years, rapid advances have been made in crystal growth methods for nitride-based semiconductors, leading to the practical application of high-brightness blue and green light-emitting devices using these materials. By combining existing red light-emitting devices with these blue and green light-emitting devices, all three primary colors of light can be achieved, making full-color display devices possible. In other words, mixing all three primary colors of light makes it possible to obtain white light, which can also be applied to lighting devices.

[0003] It is desirable for semiconductor light-emitting elements used as light sources for lighting applications to achieve high energy conversion efficiency and high optical output in high current density regions, and for the light distribution characteristics of the emitted light to be stable.To solve these problems, Patent Document 1 proposes a semiconductor light-emitting element in which an n-type nanowire core, an active layer, and a p-type layer are grown on a growth substrate, and tunnel junction layers are formed on the side surfaces of the p-type layer, which are then buried with an n-type buried layer.

[0004] Figure 8 is a schematic diagram showing a semiconductor light-emitting device with a columnar semiconductor layer that has been proposed in the past, where Figure 8(a) is a schematic cross-sectional view and Figure 8(b) is a schematic perspective view showing the light extraction direction. As shown in Figure 8(a), the semiconductor light-emitting device includes a growth substrate 1, an underlayer 2, a mask 3, a nanowire layer 4, an active layer 5, a p-type layer 6, a buried layer 7, a cathode electrode 8n, and an anode electrode 8p. Here, the nanowire layer 4, the active layer 5, and the p-type layer 6 are formed to stand at a predetermined angle with respect to the main surface of the growth substrate 1, and form a columnar semiconductor layer with a double heterostructure.

[0005] In such a semiconductor light-emitting device, when a voltage is applied between the anode electrode 8p and the cathode electrode 8n, holes are injected from the buried layer 7 into the p-type layer 6, and electrons are injected from the underlayer 2 into the nanowire layer 4, resulting in light emission of a predetermined wavelength by radiative recombination in the active layer 5. In such a semiconductor light-emitting device, fewer crystal defects and threading dislocations occur in each semiconductor layer than in a device in which the active layer is formed over the entire surface of the growth substrate 1, resulting in higher-quality crystals. In addition, because the active layer has a facet in the m-plane, which is a nonpolar plane along the side surface of the columnar semiconductor layer, the external quantum efficiency at high current densities can be improved. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-077817 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in such conventional technology, the active layer 5 is formed along the side surface of the pillar-shaped semiconductor layer, and the double heterostructure is also formed along the side surface, so that the light emitted from the active layer 5 tends to be extracted in the in-plane direction rather than the main surface direction, as shown in Figure 8(b). Such in-plane light extraction is not desirable for surface-emitting semiconductor light-emitting devices. In addition, light emitted from each pillar-shaped semiconductor layer may be absorbed by other pillar-shaped semiconductor layers as it travels in the plane, which makes it difficult to improve the external quantum efficiency.

[0008] Therefore, the present invention has been made in consideration of the above-mentioned conventional problems, and aims to provide a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element that can increase the amount of light extracted in the main surface direction or the back surface direction, even in a semiconductor light-emitting element having a columnar semiconductor layer. [Means for solving the problem]

[0009] In order to solve the above problems, the semiconductor light emitting element of the present invention comprises: The semiconductor device includes a growth substrate, a plurality of pillar-shaped semiconductor layers formed on the growth substrate, and a buried layer formed to cover the pillar-shaped semiconductor layers, and a side surface reflector that reflects at least a part of light from the pillar-shaped semiconductor layers is formed on a side surface of the pillar-shaped semiconductor layers, the side surface reflector being a light-reflecting film formed in contact with the side surface of the pillar-shaped semiconductor layers, and the light-reflecting film is made of HfO 2 ,TiO 2 ,Ta 2 O 5 ,Al 2 O 3 ,SiO 2 ,MgF 2 The dielectric multilayer film is characterized by including any one of the above. In order to solve the above-mentioned problems, the semiconductor light-emitting element of the present invention comprises a growth substrate, a plurality of pillar-shaped semiconductor layers formed on the growth substrate, and a buried layer formed to cover the pillar-shaped semiconductor layers, wherein a side surface reflector that reflects at least a part of the light from the pillar-shaped semiconductor layer is formed on a side surface of the pillar-shaped semiconductor layer, the buried layer is made of a material having a refractive index different from that of the pillar-shaped semiconductor layer, the side surface of the pillar-shaped semiconductor layer has an inclined side surface that is inclined with respect to the main surface of the growth substrate, and the side surface reflector is made of an interface between the inclined side surface and the buried layer. In order to solve the above problems, the semiconductor light-emitting element of the present invention comprises: The semiconductor device comprises a growth substrate, a plurality of pillar-shaped semiconductor layers formed on the growth substrate, and a buried layer formed to cover the pillar-shaped semiconductor layers, wherein a side surface reflector that reflects at least a portion of light from the pillar-shaped semiconductor layer is formed on a side surface of the pillar-shaped semiconductor layer, and a top surface reflector that reflects the light toward the growth substrate is formed on a surface of the buried layer opposite to the growth substrate.

[0010] In such a semiconductor light-emitting element of the present invention, a side reflector is formed on the side surface of the pillar-shaped semiconductor layer, so that a portion of the light emitted from the pillar-shaped semiconductor layer is reflected in a direction perpendicular to the growth substrate, thereby making it possible to increase the amount of light extracted in the direction of the main surface.

[0011] In one aspect of the present invention, the side surface reflector is a light reflecting film formed in contact with the side surface of the pillar-shaped semiconductor layer.

[0012] In one aspect of the present invention, the light reflecting film is made of a metal material containing any one of Al, Au, Ag, and Cr as a main component.

[0013] In one aspect of the present invention, the light reflecting film is made of a semiconductor material having a band gap larger than the wavelength of the light, and has an optical thickness larger than the wavelength of the light.

[0016] In one aspect of the present invention, the reflectance of the light from the side reflecting portion is in the range of 30 to 90%.

[0018] In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor light-emitting element, comprising: a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate; a side surface reflector formation step of forming a side surface reflector on a side surface of each of the pillar-shaped semiconductor layers; and a buried layer formation step of forming a buried layer covering the pillar-shaped semiconductor layers, the side surface reflector is a light reflecting film formed in contact with a side surface of the pillar-shaped semiconductor layer, The light reflecting film is a dielectric multilayer film containing any one of HfO2, TiO2, Ta2O5, Al2O3, SiO2, and MgF2. In order to solve the above-mentioned problems, the manufacturing method of the semiconductor light-emitting element of the present invention includes a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate, a side surface reflector formation step of forming side surface reflectors on side surfaces of the pillar-shaped semiconductor layers, and an embedded layer formation step of forming an embedded layer covering the pillar-shaped semiconductor layers, wherein the embedded layer is made of a material having a refractive index different from that of the pillar-shaped semiconductor layers, the side surfaces of the pillar-shaped semiconductor layers have inclined side surfaces that are inclined with respect to the main surface of the growth substrate, and the side surface reflectors are made of an interface between the inclined side surfaces and the embedded layer. In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor light-emitting device, comprising the steps of: growing a plurality of pillar-shaped semiconductor layers on a growth substrate; , reflecting at least a part of the light from the pillar-shaped semiconductor layer. The method is characterized by comprising a side reflector forming step of forming a side reflector, a buried layer forming step of forming a buried layer covering the pillar-shaped semiconductor layer, and a step of forming a top reflector on the surface of the buried layer opposite the growth substrate, which reflects the light toward the growth substrate. [Effects of the Invention]

[0019] The present invention can provide a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element that can increase the amount of light extracted in the main surface direction or the back surface direction, even in a semiconductor light-emitting element having a columnar semiconductor layer. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams showing a semiconductor light emitting device 10 according to a first embodiment, in which FIG. 1A is a schematic cross-sectional view and FIG. 1B is a partially enlarged cross-sectional view showing a columnar semiconductor layer in an enlarged manner. [Figure 2] 1 is a graph showing the relationship between the number of layers of a DBR and reflectance. [Figure 3] 3(a) and 3(d) are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 10, in which FIG. 3(a) shows a mask formation process, FIG. 3(b) shows a nanowire growth process, FIG. 3(c) shows a growth process of an active layer 15 and a p-type layer 16, and FIG. 3(d) shows a side reflector formation process. [Figure 4] 4A and 4B are schematic diagrams showing a method for manufacturing the semiconductor light emitting device 10, in which FIG. 4E shows a buried layer forming step, FIG. 4F shows a mesa forming step, and FIG. 4G shows an electrode forming step. [Figure 5] FIG. 4 is a schematic cross-sectional view showing a semiconductor light emitting device 10 according to a second embodiment. [Figure 6] 6A and 6B are diagrams showing a semiconductor light emitting device 30 according to a third embodiment, in which FIG. 6A is a schematic cross-sectional view and FIG. 6B is a partially enlarged cross-sectional view showing a columnar semiconductor layer in an enlarged manner. [Figure 7] 7A and 7B are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 30 according to the third embodiment, in which FIG. 7A shows a mask formation process, FIG. 7B shows a nanowire growth process, FIG. 7C shows a growth process of an active layer 35 and a p-type layer 36, and FIG. 7D shows a side reflector formation process. [Figure 8] 8A and 8B are schematic diagrams showing a semiconductor light emitting device having a columnar semiconductor layer that has been proposed in the past, where FIG. 8A is a schematic cross-sectional view and FIG. 8B is a schematic perspective view showing the light extraction direction. DETAILED DESCRIPTION OF THE INVENTION

[0021] (First embodiment) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. Figure 1 shows a semiconductor light emitting device 10 according to this embodiment, with Figure 1(a) being a schematic cross-sectional view and Figure 1(b) being a partially enlarged cross-sectional view showing a columnar semiconductor layer.

[0022] As shown in Fig. 1, semiconductor light-emitting element 10 includes growth substrate 11, underlayer 12, mask 13, nanowire layer 14, active layer 15, p-type layer 16, side surface reflector 17, buried layer 18, cathode electrode 19n, and anode electrode 19p. Nanowire layer 14, active layer 15, and p-type layer 16 are selectively grown in a direction perpendicular to growth substrate 11 to form a columnar shape, constituting the columnar semiconductor layer of the present invention. As shown in Fig. 1(b), the columnar semiconductor layer has a side surface perpendicular to the major surface of growth substrate 11, and active layer 15 along the side surface forms a double heterostructure sandwiched between nanowire layer 14 and p-type layer 16.

[0023] 1, in a portion of the semiconductor light emitting element 10, the buried layer 18 is removed from the surface down to the underlayer 12 to form a mesa groove (mesa structure), and the surface of the underlayer 12 is exposed, where a cathode electrode 19n is formed. In addition, an anode electrode 19p is formed on the buried layer 18. Here, the mesa structure refers to a structure in which a groove is formed through multiple semiconductor layers so as to surround a predetermined region, and a cross section of the stacked structure of each semiconductor layer is exposed from the side.

[0024] The growth substrate 11 is a substantially flat plate-shaped member made of a material on which a semiconductor material can be grown as a crystal. When the semiconductor light-emitting element 10 is made of a nitride-based semiconductor, a GaN substrate is preferably used as the growth substrate 11. For laser oscillation, a c-plane GaN substrate, which has a cavity plane that is easily formed by cleavage, may be used. Alternatively, a heterogeneous substrate, such as a c-plane sapphire substrate or a Si substrate, made of a material different from the semiconductor material grown on the growth substrate 11 may be used.

[0025] The underlayer 12 is a single-crystal semiconductor layer formed on the growth substrate 11. When the growth substrate 11 and the underlayer 12 are made of different materials, it is preferable to grow a buffer layer on the surface of the growth substrate 11 and then form the underlayer 12 on the buffer layer. The underlayer 12 may be formed, for example, by forming undoped GaN to a thickness of several μm and then forming an n-type semiconductor layer such as an n-type contact layer thereon, in a multi-layer configuration. The n-type contact layer is a semiconductor layer doped with n-type impurities, for example, Si-doped n-type Al 0.05 Ga 0.95 N. A mask 13 is formed on the main surface side of the base layer 12. A part of the base layer 12 is exposed and a cathode electrode 19n is formed thereon.

[0026] The buffer layer is a layer formed between the growth substrate 11 and the underlayer 12 to reduce lattice mismatch between them. When a c-plane sapphire substrate is used as the growth substrate 11, it is preferable to use GaN for the buffer layer, but AlN, AlGaN, or the like may also be used. When the growth substrate 11 and the underlayer 12 are made of the same material, a configuration without providing a buffer layer is also possible. Furthermore, when a single crystal substrate such as a GaN substrate is used as the growth substrate 11, the cathode electrode 19n may be formed on the surface of the growth substrate without providing a buffer layer and underlayer 12.

[0027] The mask 13 is a layer made of a dielectric material formed on the surface of the underlayer 12. The material constituting the mask 13 is selected from those from which it is difficult to grow semiconductor crystals, such as SiO2 or SiN. x Suitable materials include Al2O3 and the like. A plurality of openings 13a, which will be described later, are formed in the mask 13, and a semiconductor layer can be grown on the surface of the base layer 12 that is partially exposed through the openings 13a.

[0028] The pillar-shaped semiconductor layer is a semiconductor layer grown in the openings 13a formed in the mask 13, and is formed as a substantially pillar-shaped semiconductor layer standing vertically relative to the main surface of the growth substrate 11. Such a pillar-shaped semiconductor layer is obtained by setting appropriate growth conditions according to the semiconductor material and performing selective growth that grows a specific crystal plane orientation. In the example shown in FIG. 1, a plurality of openings 13a are formed in the mask 13 at two-dimensional periodic intervals, and therefore the pillar-shaped semiconductor layer is also formed at two-dimensional periodic intervals on the growth substrate 11.

[0029] The nanowire layer 14 is a columnar semiconductor layer selectively grown on the base layer 12 exposed through the opening 13a of the mask 13, and is made of, for example, GaN doped with n-type impurities. When GaN is used as the nanowire layer 14, the nanowire layer 14 selectively grown on the growth substrate 11 has a roughly hexagonal columnar shape with six m-planes formed as facets. In FIG. 1, it appears that the nanowire layer 14 is grown only in the region where the opening 13a is formed, but in reality, crystal growth proceeds on the mask 13 by lateral growth, resulting in the formation of an enlarged hexagonal column around the opening 13a. For example, if the opening 13a is formed as a circle with a diameter of about 150 nm, a nanowire layer 14 can be formed as a hexagonal columnar shape with a height of about 1 to 2 μm, with a base that is a hexagon inscribed in a circle with a diameter of about 240 nm. When the base layer 12 and the nanowire layer 14 are made of GaN, for example, the electron concentration is 10 18 atoms / cm -3 It is preferable that the n-type semiconductor layer be of this order.

[0030] Although this embodiment shows an example in which GaN is used for the nanowire layer 14, when the In composition of the active layer 15 is increased to lengthen the emission wavelength, GaInN may be used for the nanowire layer 14 to reduce misfit dislocations due to lattice mismatch. Similarly, when shortening the wavelength of the semiconductor light emitting element 10, it is also possible to use AlGaN for the nanowire layer 14, or to change the well layer and barrier layer of the active layer 15 to AlGaN with different compositions.

[0031] The active layer 15 is a semiconductor layer grown on the outer periphery of the nanowire layer 14. For example, it may be a multi-quantum well active layer formed by stacking five periods of 3-10 nm thick GaInN quantum well layers and 5-20 nm thick GaN barrier layers. While a multi-quantum well active layer is used here, a single quantum well structure or a bulk active layer may also be used. Because the active layer 15 is formed on the side and top surfaces of the nanowire layer 14, a sufficient area for the active layer 15 can be ensured. The higher the proportion of In incorporated into the active layer, the longer the emission wavelength of the semiconductor light-emitting device 10 becomes. By setting the In composition ratio to 0.10 or greater, the emission wavelength can be increased to 480 nm or greater. Furthermore, by setting the In composition ratio to 0.12 or greater, the emission wavelength can be increased to 500 nm or greater. Furthermore, because the side surfaces of the nanowire layer 14 are formed from the m-plane, the active layer 15 formed on the side surfaces is also a nonpolar plane having the m-plane, improving droop characteristics.

[0032] The p-type layer 16 is a semiconductor layer grown on the outer periphery of the active layer 15, and is made of, for example, GaN doped with p-type impurities. As shown in FIG. 1, the p-type layer 16 is formed so as to cover the side and top surfaces of the active layer 15. This forms a double heterostructure with the nanowire layer 14, the active layer 15, and the p-type layer 16, which can effectively confine carriers in the active layer 15 and improve the probability of radiative recombination. While FIG. 1 shows an example in which the p-type layer 16 is made up of a single layer, it may also have a multi-layer structure covering the side surfaces of the active layer 15.

[0033] 1, the nanowire layer 14, the active layer 15, and the p-type layer 16 are provided upright on the main surface of the growth substrate 11, and constitute the pillar-shaped semiconductor layer of the present invention. The active layer 15 and the p-type layer 16 are also formed along the side surfaces of the pillar-shaped semiconductor layer.

[0034] Side surface reflector 17 is a film-like member formed in contact with the outer periphery of the side surface of p-type layer 16, and reflects at least a portion of the light emitted from active layer 15. There are no limitations on the material that constitutes side surface reflector 17, and for example, a metal material, a semiconductor material, or a dielectric material can be used. As will be described in detail later, side surface reflector 17 preferably has a reflectance in the range of 30 to 90% for the light emitted from active layer 15, and more preferably has a reflectance in the range of 40 to 75%.

[0035] When a metal material is used for the side reflector 17, it is preferable to use a material that effectively reflects the wavelength of light emitted in the active layer 15, and for example, a metal material containing any one of Al, Au, Ag, and Cr as a main component can be used. An alloy or a layered structure of these materials may also be used. When a metal material is used for the side reflector 17, it is preferable that the film thickness be in the range of 10 to 80 nm. By adjusting the thickness of the metal film within the above range, the above reflectance for light emitted in the active layer 15 can be obtained.

[0036] When a semiconductor material is used for the side reflector 17, it is preferable to use a semiconductor material with a band gap larger than the wavelength of light emitted by the active layer 15 in order to suppress absorption of light emitted in the active layer 15. Examples include compound semiconductor materials such as GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. When a semiconductor material is used for the side reflector 17, the film thickness of the side reflector 17 needs to have an optical film thickness larger than the wavelength of light emitted in the active layer 15. This is because, by making the optical film thickness larger than the wavelength of light, reflection and refraction of light due to the difference in refractive index are utilized at the interface between the p-type layer 16 and the side reflector 17 and at the interface between the side reflector 17 and the buried layer 18.

[0037] When a dielectric material is used for the side reflector 17, it is preferable to form a distributed Bragg reflector (DBR) using a dielectric multilayer film in which multiple types of materials with different refractive indices are alternately stacked. One example is a combination of dielectric materials such as HfO2, TiO2, Ta2O5, Al2O3, SiO2, and MgF2. When the side reflector 17 is formed from a dielectric or semiconductor multilayer film to form a DBR, the reflectivity can be controlled by configuring each layer at 1 / 4 wavelength and adjusting the number of layers.

[0038] Figure 2 is a graph showing the relationship between the number of layers in a DBR and the reflectance. The graph in Figure 2 shows the relationship between the number of layers in a DBR and the reflectance of a GaN / Al 0.27 Ga 0.73 This shows the relationship between the number of layers and reflectivity of the DBR in a multilayer film of N, and it can be seen that the reflectivity can be controlled in the range of 60 to 80% by adjusting the number of layers (the number of pairs of low refractive index layers and high refractive index layers). The reflectivity can be increased by increasing the number of layers beyond that shown in Figure 2, but if the number of layers is too large, the number of steps required to form the side reflector 17 increases, so it is preferable to keep the number of layers in the range of 2 to 12 pairs.

[0039] The buried layer 18 is a layer that fills the spaces between the plurality of side reflectors 17 and on the top surfaces of the columnar semiconductor layers. Examples of materials that can be used to form the buried layer 18 include semiconductor materials such as GaN and transparent electrodes such as ITO (Indium Tin Oxide). An anode electrode 19p is formed on a portion of the surface of the buried layer 18. While FIG. 1 shows an example in which the buried layer 18 is formed as a single layer, it may have a multi-layer structure that is embedded from the surface of the base layer 12 to the top surface of the columnar semiconductor layer. Furthermore, when the buried layer 18 is made of a semiconductor material, a p-type semiconductor layer or an n-type semiconductor layer may be used to include functions such as a tunnel junction layer, a contact layer, and a current diffusion layer.

[0040] The mesa groove is a groove formed penetrating each semiconductor layer from the buried layer 18 to the underlayer 12, and forms a mesa structure by dividing the light emitting region of the semiconductor light emitting element 10. Element isolation grooves are further formed in the mesa groove to individually separate the semiconductor light emitting elements 10.

[0041] The cathode electrode 19n is an electrode formed in the region where the base layer 12 is exposed in the mesa groove, and is composed of a laminated structure of a metal material that makes ohmic contact with the exposed semiconductor layer and a pad electrode. The anode electrode 19p is an electrode formed on a portion of the buried layer 18, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the buried layer 18 and a pad electrode. Although not shown in FIG. 1, a known structure may be applied, such as covering the surface of the semiconductor light emitting element 10 with a passivation film, if necessary. Alternatively, a transparent electrode that extends the anode electrode 19p over the entire buried layer 18 may be formed.

[0042] Figure 3 is a schematic diagram showing a method for manufacturing the semiconductor light-emitting element 10, with Figure 3(a) showing a mask formation step, Figure 3(b) showing a nanowire growth step, Figure 3(c) showing a growth step of the active layer 15 and the p-type layer 16, and Figure 3(d) showing a side reflector formation step. Figure 4 is a schematic diagram showing a method for manufacturing the semiconductor light-emitting element 10, with Figure 4(e) showing a buried layer formation step, Figure 4(f) showing a mesa formation step, and Figure 4(g) showing an electrode formation step.

[0043] First, as shown in FIG. 3(a), a growth substrate 11 is prepared on which an underlayer 12 made of n-type GaN is formed. In the mask formation process, a mask 13 made of SiO2 is deposited on the underlayer 12 by sputtering to a thickness of approximately 30 nm, and an opening 13a with a diameter of approximately 150 nm is formed. A fine pattern formation method such as nanoimprinting lithography can be used to form the opening 13a. When a heterogeneous substrate such as sapphire is used as the growth substrate 11, a buffer layer, underlayer 12, and an n-type semiconductor layer may be formed on the sapphire substrate, and the surface of the n-type semiconductor layer may be used as the surface of the growth substrate 11. The buffer layer growth conditions are, for example, TMA (Trimethylaluminium), TMG (Trimethylgallium), and ammonia as source gases, a growth temperature of 1100°C, a V / III ratio of 1000, and a pressure of 10 hPa using hydrogen as a carrier gas. The growth conditions for the underlayer and the n-type semiconductor layer are, for example, a growth temperature of 1050° C., a V / III ratio of 1000, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0044] 3(b), a nanowire layer 14 made of GaN is grown on the base layer 12 exposed from the opening 13a by selective growth using the MOCVD method. The growth conditions for the nanowire layer 14 are, for example, TMG and ammonia as source gases, a growth temperature of 1050°C, a V / III ratio of 10, hydrogen as carrier gas, and a pressure of 100 hPa.

[0045] Next, in the growth process of the active layer 15 and p-type layer 16 shown in Figure 3(c), the active layer 15 and p-type layer 16 are grown on the side and top surfaces of the nanowire layer 14 using MOCVD. The active layer 15 may have a multiple quantum well structure in which, for example, a 5-nm-thick GaInN quantum well layer and a 10-nm-thick GaN barrier layer are stacked five times. The nanowire growth process shown in Figure 3(b) and the growth process of the active layer 15 and p-type layer 16 shown in Figure 3(c) correspond to the columnar semiconductor layer growth process in this invention.

[0046] The growth conditions for the active layer 15 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, a pressure of 1000 hPa using nitrogen as a carrier gas, and raw material gases of TMG, TMI (TriMethylIndium), and ammonia. The p-type layer 16 may be, for example, p-type GaN made of GaN doped with p-type impurities. The growth conditions for the p-type layer 16 are, for example, a growth temperature of 950°C, a V / III ratio of 4000, a pressure of 300 hPa using hydrogen as a carrier gas, and raw material gases of TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia.

[0047] Next, in the side surface reflector formation step shown in FIG. 3(d), the side surface reflector 17 is formed along the side surface of the p-type layer 16. Here, if the side surface reflector 17 is made of a semiconductor material, it can be grown on the side surface of the p-type layer 16 in the same reaction chamber following the growth of the p-type layer 16. If a metal or dielectric material is used as the side surface reflector 17, it can be formed on the side surface of the p-type layer 16 using a sputtering method or a vapor deposition method after the p-type layer 16 is grown. In this case, by arranging the growth substrate 11 at an angle with respect to the supply direction of the film material, it is possible to form a film of the metal or dielectric material with an appropriate thickness on the side surface of the p-type layer 16. Furthermore, by forming the film on the growth substrate 11 in multiple inclination directions, it is possible to form a film of the metal or dielectric material on the entire side surface of the p-type layer 16. Furthermore, it is preferable to remove the metal or dielectric material adhering to the top of the columnar semiconductor layer using dry etching or the like.

[0048] 4(e), a buried layer 18 is formed so as to cover the spaces between the side reflectors 17 formed in the plurality of columnar semiconductor layers and the upper surface of the p-type layer 16. When the buried layer 18 is formed of a p-type semiconductor layer, the growth conditions for the buried layer 18 can be, for example, a growth temperature of 950°C, a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, CpMg, and ammonia as source gases. When the buried layer 18 is formed of a transparent electrode such as ITO, a known method such as sputtering can be used.

[0049] As described above, the burying layer 18 must be grown on the mask 13 between the pillar-shaped semiconductor layers. During growth of the burying layer 18, voids may form beneath the pillar-shaped semiconductor layers. Therefore, the burying layer 18 is preferably grown using TMG, silane, and ammonia as source gases at a low temperature and a low V / III ratio, which promotes lateral m-plane growth in the initial stage. Examples of low temperatures and low V / III ratios include a temperature of 800°C or lower, a V / III ratio of 100 or less, and a pressure of 200 hPa using hydrogen as a carrier gas. After the lateral growth of the burying layer 18 completely fills the mask 13 beneath the pillar-shaped semiconductor layers, the burying layer 18 is preferably grown at a high temperature and a high V / III ratio, which promotes vertical c-plane growth. Examples of high temperatures and high V / III ratios include a temperature of 1000°C or higher, a V / III ratio of 2000 or more, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0050] 4(f), a mesa groove is formed by selectively removing a portion of the substrate from the buried layer 18 to the underlayer 12 by dry etching to expose the upper surface of the underlayer 12. By forming the mesa groove, the area surrounded by the mesa groove is defined as the light-emitting region of the semiconductor light-emitting element 10.

[0051] 4(g), a cathode electrode 19n is formed on the surface of the base layer 12 exposed in the mesa groove, and an anode electrode 19p is formed on the buried layer 18. After the electrode formation, annealing, formation of a passivation film, and element division are performed as necessary to obtain the semiconductor light emitting element 10.

[0052] In semiconductor light emitting element 10 of this embodiment, when a voltage is applied between cathode electrode 19n and anode electrode 19p, a current flows through buried layer 18, p-type layer 16, active layer 15, nanowire layer 14, and underlayer 12 in this order, and light is generated by radiative recombination in active layer 15. Light emitted from active layer 15 reaches side reflector 17 and is partially reflected, but the reflected light travels in the vertical direction depending on the incident angle, and is thus extracted in the direction of the principal surface of semiconductor light emitting element 10 by repeated reflections multiple times.

[0053] As described above, the side surface reflector 17 preferably has a reflectance in the range of 30 to 90% for light emitted from the active layer 15, and more preferably a reflectance in the range of 40 to 75%. If the reflectance is too high, the light emitted from the active layer 15 is repeatedly reflected inside the columnar semiconductor layer and absorbed at a high rate, making it difficult to improve the amount of light extracted to the outside. On the other hand, if the reflectance is too low, the amount of light extracted from the side surfaces of the semiconductor light emitting element 10 increases, making it difficult to improve the light extraction efficiency in the direction of the main surface.

[0054] A portion of the light emitted in the active layer 15 in one pillar-shaped semiconductor layer is reflected upward by the side surface reflectors 17 formed on the side surfaces of the pillar-shaped semiconductor layer, and the remaining portion of the light is transmitted through the side surface reflectors 17. The light transmitted through the side surface reflectors 17 propagates through the buried layer 18 and reaches another side surface reflector 17 provided in another pillar-shaped semiconductor layer, where a portion of the light is reflected upward. Therefore, by setting the reflectance of the side surface reflectors 17 within the above range, the light emitted in one active layer 15 is reflected upward by multiple side surface reflectors 17, and the amount of light extracted in the main surface direction of the entire semiconductor light emitting element 10 can be improved.

[0055] Furthermore, because the side surfaces of the nanowire layer 14 are m-planes formed by selective growth, the active layer 15 and p-type layer 16 formed on the outer periphery are also in contact with each other at the m-plane. The m-plane is a nonpolar plane and does not generate polarization, so the light emission efficiency of the active layer 15 is high. Moreover, because all of the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light emitting element 10 can be improved. Furthermore, because the film thickness of the active layer can be increased, the volume of the active layer 15 can be increased by approximately 3 to 10 times that of conventional semiconductor light emitting elements, reducing the injected carrier density and significantly reducing efficiency droop.

[0056] As described above, in the semiconductor light-emitting element and the method for manufacturing the semiconductor light-emitting element of this embodiment, the side reflector 17 is formed in contact with the side surface of the columnar semiconductor layer consisting of the nanowire layer 14, the active layer 15, and the p-type layer 16, so that a portion of the light emitted by the active layer 15 is reflected, making it possible to increase the amount of light extracted in the direction of the main surface.

[0057] Furthermore, by setting the reflectivity of the side reflectors 17 to the range of 30 to 90% for the light emitted from the active layer 15, the light emitted from one active layer 15 is reflected by multiple side reflectors 17, thereby improving the amount of light extracted in the direction of the main surface of the entire semiconductor light-emitting element 10.

[0058] (Second embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. 5. Description of content that overlaps with the first embodiment will be omitted. FIG. 5 is a schematic cross-sectional view showing a semiconductor light-emitting device 10 according to this embodiment. This embodiment differs from the first embodiment in that the semiconductor light-emitting device 10 is flip-chip mounted. As shown in FIG. 5, the semiconductor light-emitting device 10 includes a growth substrate 11, an underlayer 12, a mask 13, a nanowire layer 14, an active layer 15, a p-type layer 16, a side reflector 17, a buried layer 18, a cathode electrode 19n, an anode electrode 19p, a mounting portion 20, an upper reflector 21, and solder 22.

[0059] The mounting part 20 is a member for mounting the semiconductor light emitting element 10 by flip-chip connection, and has a wiring pattern and lands formed on its upper surface for supplying current to the semiconductor light emitting element 10. The specific configuration of the mounting part 20 is not limited, and a known submount or printed wiring board can be used. The material from which the mounting part 20 is made is also not limited, and ceramic, insulator, glass epoxy resin, a composite substrate of metal and insulating film, etc. can be used.

[0060] The top surface reflector 21 is a film-like member provided on the surface of the buried layer 18 opposite the growth substrate 11, and reflects light toward the growth substrate 11. It is a film-like member that reflects light emitted from the active layer 15 toward the growth substrate 11. The top surface reflector 21 may be formed on the buried layer 18 of the semiconductor light emitting element 10, or on the surface of the mounting portion 20, as long as it is formed between the buried layer 18 and the mounting portion 20. The material constituting the top surface reflector 21 is not limited, and metal materials such as Al, Au, Ag, and Cr can be used, for example.

[0061] The solder 22 is a member for electrically connecting the cathode electrode 19n to the wiring pattern on the mounting portion 20. Although not shown in Fig. 5, solder 22 is also provided between the anode electrode 19p and the mounting portion 20, and the two are electrically connected to each other.

[0062] In this embodiment, part of the light emitted from the active layer 15 is reflected by the side surface reflectors 17 and extracted from the back surface of the growth substrate 11. Part of the light is reflected by the side surface reflectors 17 and travels toward the mounting portion 20, and reaches the top surface reflector 21. The light that reaches the top surface reflector 21 is totally reflected by the top surface reflector 21 and extracted to the outside from the back surface of the growth substrate 11. The light that has transmitted through the side surface reflectors 17 propagates within the buried layer 18 and reaches and is reflected by another side surface reflector 17 provided in another columnar semiconductor layer, and is similarly extracted from the back surface of the growth substrate 11.

[0063] As described above, in the semiconductor light-emitting element 10 of this embodiment, the side reflector 17 is formed in contact with the side surface of the columnar semiconductor layer consisting of the nanowire layer 14, the active layer 15, and the p-type layer 16, and the top reflector 21 is formed in the embedded layer 18, making it possible to increase the amount of light extracted from the back surface of the growth substrate 11.

[0064] (Third embodiment) Next, a third embodiment of the present invention will be described with reference to Fig. 6 and Fig. 7. Description of content that overlaps with the first embodiment will be omitted. Fig. 6 shows a semiconductor light emitting device 30 according to this embodiment, with Fig. 6(a) being a schematic cross-sectional view and Fig. 6(b) being a partially enlarged cross-sectional view showing an enlarged columnar semiconductor layer.

[0065] 6, the semiconductor light-emitting element 30 of this embodiment includes a growth substrate 31, an underlayer 32, a mask 33, a nanowire layer 34, an active layer 35, a p-type layer 36, a buried layer 37, a cathode electrode 38n, an anode electrode 38p, a mounting portion 20, an upper reflector 21, and solder 22. As shown in FIG. 6(b), the side surface of the p-type layer 36 has an inclined side surface that is inclined with respect to the main surface of the growth substrate 31.

[0066] First, as shown in Figure 7(a), a growth substrate 31 on which an underlayer 32 is formed is prepared, and a mask 33 having an opening 33a is formed in a mask formation step. Next, as shown in Figure 7(b), a nanowire layer 34 is formed in a nanowire growth step. Next, an active layer 35 and a p-type layer 36 are formed as shown in Figure 7(c). Here, specific examples of the mask formation step, nanowire growth step, and the steps of forming the active layer 35 and p-type layer 36 are the same as those in the first embodiment.

[0067] Next, as shown in FIG. 7(d), the side surface reflector forming step is performed by continuing growth of the p-type layer 36 under growth conditions that result in the side surfaces of the p-type layer 36 being inclined relative to the main surface of the growth substrate 31. Conditions for forming the inclined side surfaces of the p-type layer 36 include lowering the growth temperature or lowering the V / III ratio compared to the growth conditions under which the m-plane grows as a facet. For example, if the growth conditions for the vertical m-plane p-type layer 36 in FIG. 7(c) are a growth temperature of 950°C and a V / III ratio of 4000, the following conditions can be used: a V / III ratio of 2000 at a growth temperature of 950°C, a V / III ratio of 4000 at a growth temperature of 900°C, and a V / III ratio of 3000 at a growth temperature of 900°C.

[0068] 7(c) and 7(d), an example is shown in which the growth conditions for the p-type layer 36 are changed in two stages, but ultimately, m-plane side faces are not formed in the p-type layer 36. Therefore, the p-type layer 36 may be grown with the side faces as inclined side faces under one-stage growth conditions by using the growth conditions that form the inclined side faces described above after the active layer 35 is formed.

[0069] After the side reflector formation process shown in Figure 7(d), as in Figures 4(e) to 4(g), a buried layer 37 is formed in a buried layer formation process, a top reflector 21 is formed on the buried layer 37, a mesa formation process and an electrode formation process are performed, and element division is performed to obtain a semiconductor light-emitting element 30.

[0070] In this embodiment, the side surface reflector is formed at the interface between the inclined side surface of the p-type layer 36 and the buried layer 37, and has a spire shape with a diameter that tapers away from the growth substrate 31. The buried layer 37 is made of a material with a refractive index different from that of the p-type layer 36 of the columnar semiconductor layer. Therefore, part of the light emitted in the active layer 35 is reflected at the interface (side surface reflector) between the p-type layer 36 and the buried layer 37 due to the difference in refractive index and is extracted to the outside from the back surface of the growth substrate 31. Part of the light travels toward the mounting portion 20 and reaches the top surface reflector 21. The light that reaches the top surface reflector 21 is totally reflected by the top surface reflector 21 and is extracted to the outside from the back surface of the growth substrate 31.

[0071] Furthermore, light transmitted from the p-type layer 36 to the buried layer 37 propagates within the buried layer 37 and reaches the interface between the buried layer 37 and another p-type layer 36 provided in another columnar semiconductor layer, where it is reflected or refracted, and is similarly extracted from the back surface of the growth substrate 31.

[0072] 7(a) shows a mask formation step, FIG. 7(b) shows a nanowire growth step, FIG. 7(c) shows a growth step of the active layer 35 and the p-type layer 36, and FIG. 7(d) shows a side reflector formation step. This embodiment differs from the first embodiment in that, instead of the side reflector formation step shown in FIG. 3(d), the side surfaces of the p-type layer 36 are formed to be inclined.

[0073] As described above, in the semiconductor light emitting device 30 of this embodiment, the p-type layer 36 and the buried layer 37 are made of materials with different refractive indices, and the side surface of the p-type layer 36 has an inclined side surface that is inclined with respect to the main surface of the growth substrate 31. As a result, a side surface reflector is formed at the interface between the p-type layer 36 and the buried layer 37, and light emitted in the active layer 35 is reflected and refracted due to the difference in refractive index and extracted from the back surface of the growth substrate 31. Therefore, it is possible to increase the amount of light extracted from the back surface of the growth substrate 31.

[0074] The present invention is not limited to the above-described embodiments, and various modifications within the scope of the claims are possible. Modifications are possible, and the technical means disclosed in the different embodiments may be appropriately combined. The resulting embodiments are also within the scope of the present invention. [Explanation of symbols]

[0075] 10, 30...Semiconductor light emitting element 11,31...Growth substrate 12,32…base layer 13,33...Mask 13a,33a...opening 14,34…nanowire layer 15,35…active layer 16,36…p-type layer 17…Side reflection section 18,37...Buried layer 19n, 38n...Cathode electrode 19p, 38p...Anode electrode 20...Mounting section 21...Top reflection section 22...Solder

Claims

1. a growth substrate; a plurality of pillar-shaped semiconductor layers formed on the growth substrate; a buried layer formed to cover the pillar-shaped semiconductor layer, a side surface reflector that reflects at least a part of the light from the pillar-shaped semiconductor layer is formed on a side surface of the pillar-shaped semiconductor layer, the side surface reflector is a light reflecting film formed in contact with a side surface of the pillar-shaped semiconductor layer, The light-reflecting film is made of HfO ２ , TiO ２ , Ta ２ O ５ , Al ２ O ３ , SiO ２ , MgF ２ A semiconductor light-emitting device comprising a dielectric multilayer film including any one of the above.

2. a growth substrate; a plurality of pillar-shaped semiconductor layers formed on the growth substrate; a buried layer formed to cover the pillar-shaped semiconductor layer, a side surface reflector that reflects at least a part of the light from the pillar-shaped semiconductor layer is formed on a side surface of the pillar-shaped semiconductor layer, the buried layer is made of a material having a refractive index different from that of the pillar-shaped semiconductor layer, a side surface of the pillar-shaped semiconductor layer has an inclined side surface inclined with respect to a major surface of the growth substrate, The semiconductor light-emitting element, wherein the side surface reflector is formed by an interface between the inclined side surface and the buried layer.

3. a growth substrate; a plurality of pillar-shaped semiconductor layers formed on the growth substrate; a buried layer formed to cover the pillar-shaped semiconductor layer, a side surface reflector that reflects at least a part of the light from the pillar-shaped semiconductor layer is formed on a side surface of the pillar-shaped semiconductor layer, A semiconductor light emitting device, characterized in that an upper surface reflecting portion that reflects the light toward the growth substrate is formed on the surface of the buried layer opposite to the growth substrate.

4. The semiconductor light emitting device according to claim 3, The semiconductor light-emitting element, wherein the side surface reflector is a light-reflecting film formed in contact with the side surface of the pillar-shaped semiconductor layer.

5. The semiconductor light emitting device according to claim 4, The semiconductor light-emitting element is characterized in that the light-reflecting film is made of a metal material containing one of Al, Au, Ag, and Cr as a main component.

6. The semiconductor light emitting device according to claim 4, The light-reflecting film is made of a semiconductor material having a band gap larger than the wavelength of the light, and has an optical thickness larger than the wavelength of the light.

7. 7. The semiconductor light emitting device according to claim 1, The semiconductor light emitting element is characterized in that the reflectance of the light from the side reflecting portion is in the range of 30 to 90%.

8. a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate; a side surface reflector forming step of forming a side surface reflector on a side surface of the pillar-shaped semiconductor layer; a buried layer forming step of forming a buried layer covering the pillar-shaped semiconductor layer, the side surface reflector is a light reflecting film formed in contact with a side surface of the pillar-shaped semiconductor layer, The light-reflecting film is made of HfO ２ , TiO ２ , Ta ２ O ５ , Al ２ O ３ , SiO ２ , MgF ２ 10. A method for manufacturing a semiconductor light-emitting element, comprising: forming a dielectric multilayer film including any one of the above.

9. a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate; a side surface reflector forming step of forming a side surface reflector on a side surface of the pillar-shaped semiconductor layer; a buried layer forming step of forming a buried layer covering the pillar-shaped semiconductor layer, the buried layer is made of a material having a refractive index different from that of the pillar-shaped semiconductor layer, a side surface of the pillar-shaped semiconductor layer has an inclined side surface inclined with respect to a major surface of the growth substrate, The method for manufacturing a semiconductor light-emitting element, wherein the side surface reflector is formed by the interface between the inclined side surface and the buried layer.

10. a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate; a side surface reflector forming step of forming a side surface reflector on a side surface of the pillar-shaped semiconductor layer, the side surface reflecting at least a part of light from the pillar-shaped semiconductor layer; a buried layer forming step of forming a buried layer to cover the pillar-shaped semiconductor layer; and forming an upper surface reflector on a surface of the buried layer opposite to the growth substrate, the upper surface reflecting part reflecting the light toward the growth substrate.

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