Integral Side Via

Abstract

A diode semiconductor structure is described. In one example, the diode device includes a substrate, a layer of a first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of a second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without requiring an additional metal connection to the metal contact, such as a metal air bridge.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 16 / 838,114, filed April 2, 2020. This application is also a continuation of and claims the benefit of the filing date of U.S. Patent Application No. 16 / 838,114, filed April 2, 2020, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] Diodes are often used as switching elements in a variety of military and commercial applications. Applications include automotive collision avoidance systems (CAS), passive radiation imaging and radar systems, and switch matrix devices for computer networking applications. Many diodes used in such radio frequency (RF) and microwave applications were fabricated as homojunction devices. These devices were used in both discrete and integrated component form for their useful switching functions at high frequencies ranging from approximately 1 megahertz (MHz) to well over 100 gigahertz (GHz). Summary of the Invention

[0003] In one example, a diode semiconductor structure is described. The diode semiconductor structure includes a substrate, a layer of a first semiconductor material of a first doping type formed on the substrate, a layer of intrinsic semiconductor material formed on the layer of first semiconductor material, and a layer of a second semiconductor material of a second doping type formed on the layer of intrinsic semiconductor material. The diode semiconductor structure also includes a first metal contact formed on the layer of first semiconductor material and a second metal contact formed on the layer of second semiconductor material. The diode semiconductor structure also includes a metal via formed from a back surface of the substrate, through the substrate, and through the layer of first semiconductor material. The metal via contacts a bottom surface of the first metal contact.

[0004] In another aspect, the layer of first semiconductor material may be embodied as a cathode layer of a diode semiconductor structure, with the layer of first semiconductor material formed as a cathode mesa extending above an undercut formed in the substrate. A metal via is formed below the cathode mesa. In yet another aspect, the layer of intrinsic semiconductor material and the layer of second semiconductor material are formed as an anode mesa extending above an undercut formed in the layer of first semiconductor material.

[0005] In another embodiment, the first metal contact of the diode includes a first cathode contact and a second cathode contact, and the second metal contact of the diode includes an anode contact. The first cathode contact is formed on the cathode mesa on one side of the anode metal contact, and the second cathode contact is formed on the cathode mesa on the other side of the anode metal contact. Additionally, the metal via includes a first metal via and a second metal via. The first metal via is formed under the cathode mesa on one side of the anode metal contact, and the second metal via is formed under the cathode mesa on the other side of the anode metal contact. In another example, two or more metal vias can be formed under the cathode mesa of the diode on either or both sides of the anode metal contact of the diode.

[0006] In one example, the layer of first semiconductor material comprises a layer of gallium arsenide (GaAs) semiconductor material, and the first doping type comprises N+ doping, and the layer of second semiconductor material comprises a layer of aluminum gallium arsenide (AlGaAs) semiconductor material, and the second doping type comprises P+ doping.

[0007] In another embodiment, the layer of first semiconductor material comprises a cathode layer of a diode semiconductor structure, the first metal contact comprises a cathode contact of the diode semiconductor structure, the layer of second semiconductor material comprises an anode layer of the diode semiconductor structure, and the second metal contact comprises an anode contact of the diode semiconductor structure.

[0008] In another example, the metal via comprises one of a plurality of metal vias that extend through the substrate, through the layer of first semiconductor material, and contact the bottom surface of the first metal contact. [Brief explanation of the drawings]

[0009] Aspects of the present disclosure may be better understood with reference to the following drawings: Note that the elements in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present embodiments.

[0010] [Figure 1] FIG. 1 shows a cross-sectional view of an example diode semiconductor structure.

[0011] [Figure 2] FIG. 2 shows a top view of an example of the diode semiconductor structure shown in FIG.

[0012] [Figure 3] FIG. 3 illustrates a cross-sectional view of an example diode semiconductor structure according to various aspects of the present invention.

[0013] [Figure 4] FIG. 4 illustrates a top view of an example of the diode semiconductor structure shown in FIG. 3 according to various aspects of the present embodiment.

[0014] [Figure 5] FIG. 5 is a photograph including a cross-sectional view of an example of the diode semiconductor structure shown in FIG.

[0015] [Figure 6] FIG. 6 is a photograph including a cross-sectional view of an example diode semiconductor structure shown in FIG. 3 according to various aspects of the present embodiment.

[0016] [Figure 7A] , [Figure 7B] , [Figure 7C]7A-7C illustrate top views of a diode semiconductor structure including alternative arrangements of unibody vias according to various aspects of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] The need for more highly integrated semiconductor devices, such as transistor and diode devices, is expected to increase significantly with the emergence of new fields of technology. For example, monolithic microwave integrated circuit (MMIC) devices are commonly deployed in radar systems and communications front-end modules, such as switches, phase shifters, current and voltage control components, and limiters, among other circuit components. For example, the emergence of metamaterial scanned arrays is reshaping the radar industry by opening up new possibilities for radar systems with significantly lower cost, size, weight, and power requirements than traditional electronically scanned arrays. New metamaterial scanned arrays rely heavily on diodes embedded within the array's unit cells to actively tune the metamaterial between absorbing and reflecting states.

[0018] In the field of diode devices, aluminum gallium arsenide (AlGaAs) PIN diodes are good candidates for both maturing and emerging applications. The wide bandgap of AlGaAs results in AlGaAs PIN diodes with very low RF on-state resistance and off-state capacitance. AlGaAs PIN diodes offer lower insertion loss at all frequencies up to 110 GHz (and beyond), surpassing many other commercially available products. As with other semiconductor devices, it is desirable to optimize the yield of AlGaAs PIN diodes, improve their reliability and performance, and optimize the processes for their fabrication to meet future needs.

[0019] In one process for forming AlGaAs PIN diodes, a shunt diode is formed using one or more bridges or air bridges formed of metal to electrically connect the cathode of the PIN diode to the ground pad. Metal bridges are traditionally used for such ground connections because the etch rate of the N+ gallium arsenide (GaAs) cathode layer varies with the crystal orientation within the PIN diode, allowing metal bridges to be formed regardless of the orientation of the PIN diode. Thus, the use of metal bridges facilitates various circuit orientations and configurations of PIN diodes.

[0020] However, the use of metal bridges has several drawbacks. First, a minimum distance is required between the side via and the PIN diode in order for the metal bridge to form properly. This minimum distance requirement, along with several other limitations inherent in the metal bridge structure, significantly limits the level of integration and thermal performance that can be achieved. Additionally, the additional series resistance and inductance that can be attributed to the metal bridge can degrade the quality of the ground connection and limit the high-frequency response of the PIN diode. Metal bridges also pose reliability concerns, especially in high-power applications, due to the occurrence of cracks that can form in the metal bridge.

[0021] According to aspects of the embodiments described herein, a unibody side via configuration is introduced to eliminate the drawbacks associated with the use of metal bridges. To implement a unibody via in a PIN diode, the cathode mesa of the PIN diode is extended and a via is formed directly underneath it. The configuration of this new structure is described in further detail herein.

[0022] In one example embodiment, a diode device includes a substrate, a layer of a first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of a second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material, and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without requiring an additional metal connection to the metal contact, such as a metal air bridge.

[0023] Compared to conventional PIN diodes of similar size with metal bridges, PIN diodes with integral side vias according to the present embodiments exhibit reduced separation between the centers of the vias across the diode, resulting in a significant reduction in overall size. In one example, the separation between the centers of the vias across the diode was reduced from 208 μm to 115 μm. Other advantages of PIN diodes incorporating integral side vias include improved manufacturing yields due to the elimination of metal bridges, improved thermal behavior due to metal vias being closer to the anode of the PIN diode (facilitating heat dissipation), reduced overall size potentially resulting in higher density circuitry, improved high frequency performance and ground coupling, fewer limitations for high power product designs with current handling capabilities limited only by the anode of the PIN diode, and no limitations on the orientation of the PIN diode.

[0024] Referring to the drawings, FIG. 1 shows a cross-sectional view of an exemplary diode semiconductor structure 100 (“diode 100”). Diode 100 is shown in FIG. 1 as a representative example. The shapes and relative sizes of the various layers of diode 100 are not necessarily drawn to scale in FIG. 1. The layers shown in FIG. 1 are not exhaustive, and diode 100 may, in some cases, include other layers and elements not separately shown. Additionally, diode 100 may be combined with other devices and circuit elements to form part of a larger integrated circuit device.

[0025] Diode 100 is a two-terminal heterojunction device suitable for use as a switch. Diode 100 includes a substrate 102, a layer 104 of a first semiconductor material of a first doping type (“first layer 104”) formed on substrate 102, a layer 106 of an intrinsic semiconductor material (“intrinsic layer 106”) formed on first layer 104, and a layer 108 of a second semiconductor material of a second doping type (“second layer 108”) formed on intrinsic layer 106. Although a particular example is shown in FIG. 1 and described below, diode 100 may be embodied in a variety of ways, including as any of the diode devices shown and described in U.S. Patent No. 6,794,734, the entire contents of which are incorporated herein by reference.

[0026] In one example, the substrate 102 may be embodied as a GaAs semiconductor substrate of an appropriate thickness. The first layer 104 is the cathode layer of the diode 100. The first layer 104 may be embodied as a layer of GaAs semiconductor material, and the first doping type may be N+ doping (for a layer of N+ GaAs semiconductor material) with an appropriate concentration of silicon (Si), but may depend on other types of semiconductor materials and doping types. The first layer 104 may be formed directly on the substrate 102 by epitaxial deposition with an appropriate thickness. As shown in FIG. 1 , the first layer 104 is etched to form a cathode mesa 160 extending above an undercut 109 formed in the substrate 102.

[0027] Intrinsic layer 106 may be embodied as a layer of intrinsic (e.g., undoped or unintentionally doped) GaAs semiconductor material. Intrinsic layer 106 may be formed directly on first layer 104 by epitaxial deposition to an appropriate thickness. Intrinsic layer 106, in part, establishes the breakdown voltage and capacitance of diode 100.

[0028] The second layer 108 is the anode layer of the diode 100. The second layer 108 may be embodied as a layer of AlGaAs semiconductor material, and the second doping type may include P+ doping (for a layer of P+ AlGaAs semiconductor material) with an appropriate concentration of carbon (C), but may depend on other types of semiconductor materials and doping types. The second layer 108 may be formed directly on the intrinsic layer 106. As shown in FIG. 1 , the intrinsic layer 106 and the second layer 108 are etched as a mesa extending above the undercut formed in the first layer 104.

[0029] The diode 100 also includes metal contacts 110, 112, and 120. The metal contacts 110 and 112 are formed on the first layer 104, and the metal contact 120 is formed on the second layer 108. The metal contacts 110 and 112 are disposed on the top surface of the first layer 104 to provide ohmic contact to the cathode of the diode 100. The metal contact 120 is disposed on the top surface of the second layer 108 to provide ohmic contact to the anode of the diode 100. Additionally, metal pads 140 and 142 are formed on the top surface of the substrate 102 for electrical connection to the cathode of the diode 100. In particular, metal bridges 130 and 132 are formed to electrically connect the metal pads 140 and 142 to the metal contacts 110 and 112, respectively, as described in further detail below.

[0030] In diode 100, the P+ AlGaAs semiconductor material of second layer 108 has a wider bandgap than the intrinsic GaAs semiconductor material of intrinsic layer 106. The energy difference between the conduction band and valence band in the semiconductor materials of second layer 108 and intrinsic layer 106 results in an appropriate barrier height difference that promotes forward injection of holes from the anode region into the intrinsic region and retards backward injection of electrons from the intrinsic region into the anode region. Injected carriers at the junction are confined due to the bandgap difference, effectively reducing the series resistance in the intrinsic region of diode 100. Increasing the carrier concentration in the intrinsic region reduces the resistance in the intrinsic region, which also results in reduced insertion loss without compromising isolation.

[0031] Diode 100 can operate as a high-frequency switch. The resistance of the intrinsic region can vary by many orders of magnitude as a function of the application of a direct current (DC) bias to diode 100. When diode 100 is in the "off" state (e.g., no forward DC bias), diode 100 operates as an electrical open circuit, and coupling occurs only through capacitance. Therefore, by reducing the off-state capacitance of diode 100, coupling is minimized, resulting in high impedance at high frequencies without a forward DC bias. At the same time, by reducing the on-state resistance of diode 100, the series resistance of diode 100 is also low when a forward DC bias is applied.

[0032] Many diodes similar to diode 100 may be formed on substrate 102, and the diodes may be electrically connected in various ways to each other and to other passive components, such as resistors, capacitors, and inductors, to form larger circuits. The electrical connections for series and shunt-connected diodes may affect the process steps and structures used to interconnect the diodes. For example, for the fabrication of series-connected diodes, substrate 102 may be approximately 8 mils thick. For the fabrication of shunt-connected diodes, substrate 102 may be reduced to a thickness of 4 mils, although other suitable thicknesses may be employed, and via holes may be etched from the backside of substrate 102.

[0033] 1, via holes are etched to form metal vias 150, 152 through the backside of the substrate 102. The metal vias 150, 152 extend through the substrate 102 and electrically connect to the metal pads 140, 142, respectively, formed on the top surface of the substrate 102. Additionally, as shown in FIG. 1, metal bridges 130, 132 are formed to electrically connect the metal pads 140, 142 to the metal contacts 110, 112, respectively. In this manner, the cathode metal contacts 110, 112 of the diode 100 can be connected to ground by an electrical connection underneath the substrate 102, particularly in the case of a shunt-connected diode.

[0034] The use of metal bridges 130, 132 for electrical connection to diode 100 has several drawbacks. First, a minimum distance is required between metal vias 150, 152 and diode 100 in order for metal bridges 130, 132 to be properly formed. This minimum distance requirement, along with several other limitations inherent in the structure of metal bridges 130, 132, limits the level of integration and thermal performance that can be achieved for diode 100 among other diodes formed on substrate 102. Additionally, the additional series resistance and inductance potentially caused by metal bridges 130, 132 can degrade the quality of the ground connection to the shunt-connected diode and limit the high-frequency response of diode 100. Metal bridges 130, 132 also present reliability concerns due to the occurrence of cracks that can form in metal bridges 130, 132, particularly where they contact metal pads 140, 142.

[0035] Figure 2 shows a top view of the diode 100 shown in Figure 1. In Figure 2, metal contacts 110, 112 are shown formed on the first layer 104 and extend toward the edge of the cathode mesa 160. Metal pads 140, 142 are also shown on the top surface of the substrate 102, and the locations of metal vias 150, 152 are indicated below the metal pads 140, 142 using hidden lines. The diode 100, including the metal pads 140, 142, may be measured in size along one dimension as "W1."

[0036] 2, electrically connecting the metal pads 140, 142 to the metal contacts 110, 112, respectively, of the cathode of the diode 100. The metal bridges 130, 132 are shown to include several fingers extending from the metal pads 140, 142 to the metal contacts 110, 112. In some cases, when the metal bridges 130, 132 are formed, the metal bridges 130, 132 fail to adhere to or make contact with the metal contacts 110, 112 on the first layer 104. Additionally, cracks may develop in the metal bridges 130, 132, particularly where the metal bridges 130, 132 contact the metal pads 140, 142.

[0037] Semiconductor devices, including but not limited to diode devices incorporating one or more integral side vias, are described herein to provide several improvements. For example, PIN diodes incorporating one or more integral side vias may be relied upon to overcome the drawbacks of using metal bridges, improve device performance, reduce cost, increase reliability, and achieve other benefits.

[0038] FIG. 3 illustrates a cross-sectional view of an example diode semiconductor structure 200 (“diode 200”) according to various aspects of the present embodiments. Diode 200 is shown in FIG. 3 (and FIG. 4) as a representative example. The shapes and relative sizes of the various layers of diode 200 are not necessarily drawn to scale in FIG. 3. The layers shown in FIG. 3 are not exhaustive, and diode 200 may, in some cases, include other layers and elements not separately shown. Additionally, diode 200 may be combined with other devices and circuit elements to form part of a larger integrated circuit device.

[0039] Similar to diode 100, diode 200 is a two-terminal heterojunction device suitable for use as a switch. Diode 200 includes a substrate 202, a layer 204 of a first semiconductor material of a first doping type (“first layer 204”) formed on substrate 202, a layer 206 of an intrinsic semiconductor material (“intrinsic layer 206”) formed on first layer 204, and a layer 208 of a second semiconductor material of a second doping type (“second layer 208”) formed on intrinsic layer 206. An example of diode 200 is shown in FIG. 3 and described below. In more particular cases, diode 200 may be embodied as several layers of semiconductor material, some of which may be similar to, but are not limited to, those described in U.S. Pat. No. 6,794,734.

[0040] In one example, substrate 202 may be embodied as a GaAs semiconductor substrate of an appropriate thickness, although other types of semiconductor substrates may be utilized. First layer 204 is the cathode layer of diode 200. First layer 204 may be embodied as a layer of GaAs semiconductor material, and the first doping type may be N+ doping (for a layer of N+ GaAs semiconductor material) with an appropriate concentration of silicon (Si), although other types of semiconductor materials and doping types may be utilized. First layer 204 may be formed directly on substrate 202 with an appropriate thickness by epitaxial deposition or another appropriate technique. As shown in FIG. 3 , first layer 204 is etched to form a cathode mesa 260 extending above an undercut 209 formed in substrate 202.

[0041] Intrinsic layer 206 may be embodied, for example, as a layer of intrinsic (e.g., undoped or unintentionally doped) GaAs semiconductor material among other semiconductor materials. Intrinsic layer 206 may be formed directly on first layer 204 by epitaxial deposition or another suitable technique with a suitable thickness. Intrinsic layer 206, in part, establishes the breakdown voltage and capacitance of diode 200.

[0042] The second layer 208 is the anode layer of the diode 200. The second layer 208 may be embodied, for example, as a layer of AlGaAs semiconductor material, and the second doping type may include P+ doping (for a layer of P+ AlGaAs semiconductor material) with an appropriate concentration of carbon (C), but may depend on other types of semiconductor materials and doping types. The second layer 208 may be formed directly on the intrinsic layer 206 by epitaxial deposition or another suitable technique. As shown in FIG. 3 , the intrinsic layer 206 and the second layer 208 are etched as a mesa extending above the undercut formed in the first layer 204.

[0043] Diode 200 also includes metal contacts 210, 212, and 220. Metal contacts 210 and 212 are formed on first layer 204, and metal contact 220 is formed on second layer 208. Metal contacts 210 and 212 are disposed on the top surface of first layer 204 to provide ohmic contact to the cathode of diode 200. Metal contact 220 is disposed on the top surface of second layer 208 to provide ohmic contact to the anode of diode 200. However, diode 200 does not rely on metal pads 140 and 142 shown in FIG. 1 for electrical connection to the cathode of diode 200. Similarly, diode 200 does not rely on metal bridges 130 and 132 shown in FIG. 1.

[0044] Similar to diode 100, diode 200 can operate as a high-frequency switch. The resistance of the intrinsic region can vary by many orders of magnitude as a function of the application of a DC bias to diode 200. When diode 200 is in the "off" state (e.g., no forward DC bias), diode 200 operates as an electrical open circuit, and coupling occurs only through capacitance. Therefore, by reducing the off-state capacitance of diode 200, coupling is minimized, resulting in high impedance at high frequencies without a forward DC bias. At the same time, by reducing the on-state resistance of diode 200, the series resistance of diode 200 is also low when a forward DC bias is applied.

[0045] Many diodes similar to diode 200 may be formed on substrate 202, and the diodes may be electrically connected in various ways to each other and to other passive components, such as resistors, capacitors, and inductors, to form larger circuits. The electrical connections for series and shunt-connected diodes may affect the process steps and structures used for the interconnections between the diodes. For example, for the fabrication of series-connected diodes, substrate 202 may be 8 mils thick. For the fabrication of shunt-connected diodes, substrate 202 may be reduced to a thickness of 4 mils, and via holes may be etched from the backside of substrate 202.

[0046] As shown in FIG. 3 , via holes are etched to form metal vias 250, 252 extending from the backside of the substrate 202 through the substrate. The metal vias 250, 252 extend through the substrate 202 and electrically connect to the metal contacts 210, 212, respectively, at the bottom surfaces of the metal contacts. In particular, the metal via 250 is formed from the backside of the substrate 202 through the substrate 202 and through the first layer 204. The metal via 250 contacts the bottom surface of the metal contact 210. Additionally, the metal via 252 is formed from the backside of the substrate 202 through the substrate 202 and through the first layer 204. The metal via 250 contacts the bottom surface of the metal contact 210. In this manner, the cathode metal contacts 210, 212 of the diode 200 can be connected to ground by an electrical connection underneath the substrate 202, particularly in the case of a shunt-connected diode.

[0047] In comparison to diode 100, diode 200 is designed to avoid the need for a metal bridge. Although diode 200's cathode mesa 260 is larger than diode 100's cathode mesa 160, diode 200's overall size is smaller than diode 100's. Additionally, diode 200's metal contacts 210, 212 may, in some cases, be larger than diode 100's metal contacts 110, 112. While the specific size and shape of cathode mesa 260 may vary depending on the embodiment, cathode mesa 260 is generally formed large enough to accommodate one or more metal vias formed from below substrate 202. The size and shape of metal contacts 210, 212 may also vary, but are formed to allow contact with one or more metal vias formed from below substrate 202.

[0048] FIG. 4 shows a top view of the diode 200 shown in FIG. 3. The metal contacts 210, 212 formed on the first layer 204 extend toward the edge of the cathode mesa 260, as shown in FIG. 4. The locations of the metal vias 250, 252 are shown below the metal contacts 210, 212 using hidden lines. A metal trace 270 is relied upon to provide electrical contact with the anode metal contact 220 of the diode 200. The diode 200, including the metal contacts 210, 212, can be measured in size along one dimension, designated "W2." Compared to the diode 100 shown in FIG. 2, "W2" is smaller than "W1," making the diode 200 shown in FIG. 4 significantly smaller. In one example, the via center-to-via separation between vias 150, 152 across diode 100 was reduced from 208 μm to 115 μm due to the via center-to-via separation between vias 250, 252 across diode 200.

[0049] Metal vias 250, 252 are integral with diode 200 and are formed below cathode mesa layer 204 of diode 200. Metal vias 250, 252 extend through substrate 202 and electrically connect to metal contacts 210, 212, respectively, at the bottom surfaces of metal contacts 210, 212. In particular, metal via 250 contacts the bottom surface of metal contact 210, and metal via 250 contacts the bottom surface of metal contact 210. The structural configuration of diode 200 shown in FIGS. 5 and 6 does not rely on metal bridges to provide electrical connection between metal vias 250, 252 and metal contacts 210, 212. Therefore, failure modes inherent in metal bridges are not attributed to diode 200.

[0050] Overall, among other advantages, diode 200 exhibits a significant reduction in overall size with reduced via center-to-center separation for higher density MMICs. Diode 200 can be manufactured with improved yields by eliminating metal bridges. Diode 200 exhibits improved thermal behavior with metal vias closer to the anode. Diode 200 exhibits improved high frequency performance and ground coupling, resulting in fewer limitations for high-power product designs based on higher current handling capabilities. Diode 200 can also be manufactured without limitations regarding substrate orientation.

[0051] FIG. 5 is a photograph including a cross-sectional view of an example of the diode 100 shown in FIG. 1. As shown, via holes are etched to form metal vias 150, 152 through the backside of the substrate 102. The metal vias 150, 152 extend through the substrate 102 and electrically connect to the metal pads 140, 142, respectively, formed on the top surface of the substrate 102. Additionally, metal bridges 130, 132 are formed to electrically connect the metal pads 140, 142 to the metal contacts 110, 112, respectively. In this manner, the cathode metal contacts 110, 112 of the diode 100 can be connected to ground through an electrical connection underneath the substrate 102, particularly in the case of a shunt-connected diode. Both metal vias 150, 152 are formed outside (i.e., not underneath) the first layer 104 of the diode 100, away from the anode of the diode 100.

[0052] 6 is a photograph including a cross-sectional view of the diode 200 shown in FIG. 3 in accordance with various aspects of the present embodiment. As shown, via holes are etched to form metal vias 250 and 252 extending from the backside of the substrate 202 through the substrate. The metal vias 250 and 252 extend through the substrate 202 and electrically connect with the metal contacts 210 and 212, respectively, at the bottom surfaces of the metal contacts. In particular, the metal via 250 is formed from the backside of the substrate 202 through the substrate 202 and through the first layer 204. The metal via 250 contacts the bottom surface of the metal contact 210. Additionally, the metal via 252 is formed from the backside of the substrate 202 through the substrate 202 and through the first layer 204. The metal via 250 contacts the bottom surface of the metal contact 210. Both metal vias 250, 252 are formed under first layer 204 and closer to the anode of diode 200, and metal vias 250 and 252 are referred to herein as integral side vias due to their structural configuration. Metal vias 250, 252 are better able to conduct heat away from the anode of diode 200 compared to diode 100.

[0053] Diode 200 includes a first metal via 250 on one side of anode metal contact 220 and a second metal via 252 on the other side of anode metal contact 220, although other arrangements of integral vias are within the scope of the present embodiments. In that context, Figures 7A-7C show top views of diode semiconductor structures including alternative arrangements of integral vias according to various aspects of the present embodiments. Figures 7A-7B show examples of different shapes and configurations of diodes including integral side vias, although the examples are not limiting as other shapes, styles, and configurations are within the scope of the present embodiments.

[0054] 7A , diode 300 is shown including a cathode metal contact 310, an anode metal contact 320, and a cathode mesa 360. Additionally, the location of one integral metal via 350 is shown below cathode metal contact 310 using hidden lines. The top of metal via 350 contacts the bottom surface of cathode metal contact 310, consistent with embodiments described herein. In the illustrated example, the anode and cathode layers of diode 300 are formed as rectangles with curved corners, rather than circles. Also, diode 300 includes only one cathode metal contact 310 and only one metal via 350 on one side of anode metal contact 320.

[0055] 7B, a diode 400 is shown including a cathode metal contact 410, an anode metal contact 420, and a cathode mesa 460. Additionally, the locations of two integral metal vias 450, 452 are shown below the cathode metal contact 410 using hidden lines. The metal vias 350, 352 contact the bottom surface of the cathode metal contact 410, consistent with embodiments described herein. In the illustrated example, the anode and cathode layers of the diode 400 are formed as rectangles with curved corners rather than circles. Additionally, the diode 100 includes one cathode metal contact 310, but two metal vias 450, 452 on either side of the anode metal contact 420.

[0056] 7C, a diode 500 is shown including cathode metal contacts 510 and 512, an anode metal contact 520, and a cathode mesa 560. Additionally, the locations of three integral metal vias 551-553 are shown using hidden lines below the cathode metal contact 510, and the locations of three integral metal vias 554-556 are shown using hidden lines below the cathode metal contact 512. Metal vias 551-553 contact the bottom surface of cathode metal contact 510, and metal vias 554-556 contact the bottom surface of cathode metal contact 512. In the illustrated example, the anode and cathode layers of diode 500 are formed as rectangles with curved corners rather than circles. The diode 500 includes two cathode metal contacts 510, 512 on opposite sides of the anode metal contact 520, and three metal vias 551-553, 554-556 on opposite sides of the anode metal contact 520, respectively.

[0057] The PIN diode structures and devices described herein can be used to fabricate a wide variety of useful integrated circuits, including limiters, switches, and other circuits. PIN diode structures can also be integrated with various components in monolithic circuit formats suitable for microwave circuit applications. Although detailed embodiments have been described herein, the description is by way of example. The concepts described herein are not limited to improvements in PIN diodes. The concepts can also be applied to other types of semiconductor devices, such as various types of diodes, transistors, controlled rectifiers, thyristors, semiconductor lasers, photocells, and other devices.

[0058] The features of the embodiments described herein are exemplary, and alternative embodiments may add or omit certain features and elements. Additionally, modifications to aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the invention as defined in the following claims, which should be accorded the broadest interpretation so as to encompass modifications and equivalent structures.

Claims

1. A semiconductor device comprising: A substrate; a layer of a first semiconductor material over the substrate; a layer of a second semiconductor material over the layer of first semiconductor material, the layer of second semiconductor material including a mesa; a first ohmic contact on the layer of first semiconductor material on one side of the mesa, and a second ohmic contact on the layer of first semiconductor material on the other side of the mesa; a metal contact on the layer of second semiconductor material; a first metal via extending from the backside of the substrate, through the substrate, through the first layer of semiconductor material, and contacting a bottom surface of the first ohmic contact on the one side of the mesa; a second metal via extending from the back surface of the substrate, through the substrate, through the first layer of semiconductor material, and contacting a bottom surface of the second ohmic contact on the other side of the mesa.

2. 10. The semiconductor device of claim 1, the first semiconductor material includes a first dopant; The second semiconductor material comprises a second dopant.

3. 10. The semiconductor device of claim 1, wherein the first layer of semiconductor material includes a cathode mesa extending above an undercut in the substrate.

4. 10. The semiconductor device of claim 1, wherein the mesa of the second layer of semiconductor material comprises an anode mesa on the first layer of semiconductor material.

5. 10. The semiconductor device of claim 1, wherein the mesa of the second layer of semiconductor material comprises a circular mesa on the first layer of semiconductor material.

6. 10. The semiconductor device of claim 1, wherein the mesa of the second layer of semiconductor material comprises a rectangular mesa with rounded corners on the layer of first semiconductor material.

7. 10. The semiconductor device of claim 1, wherein the first ohmic contact and the second ohmic contact comprise a shared electrode of the semiconductor device.

8. 10. The semiconductor device of claim 1, further comprising a layer of intrinsic semiconductor material between the layer of first semiconductor material and the layer of second semiconductor material.

9. 10. The semiconductor device of claim 1, the first metal vias include at least two vias extending from the back surface of the substrate, through the substrate, through the first layer of semiconductor material, and contacting bottom surfaces of the first ohmic contacts on the one side of the mesa; the second metal vias include at least two vias that extend from the back surface of the substrate, through the substrate, through the first layer of semiconductor material, and contact a bottom surface of the second ohmic contact on the other side of the mesa.

10. 10. The semiconductor device of claim 1, further comprising a layer of a third semiconductor material between the layer of the first semiconductor material and the layer of the second semiconductor material.

11. 10. The semiconductor device of claim 1, wherein the first metal via and the second metal via are integral with and located below the semiconductor device.

12. 1. A semiconductor structure comprising: a layer of a first semiconductor material over a substrate; a first metal contact on the first layer of semiconductor material; a layer of a second semiconductor material over the layer of first semiconductor material and on one side of the first metal contact; a first metal via extending from the backside of the substrate to the bottom surface of the first metal contact; a second metal via extending from the backside of the substrate to the bottom surface of the first metal contact.

13. 13. The semiconductor structure of claim 12, wherein the layer of first semiconductor material includes a mesa that extends above an undercut in the substrate.

14. 13. The semiconductor structure of claim 12, wherein the layer of second semiconductor material includes a mesa located on the one side of the first metal contact over the layer of first semiconductor material.

15. 13. The semiconductor structure of claim 12, wherein the layer of second semiconductor material comprises a circular mesa on the layer of first semiconductor material.

16. 13. The semiconductor structure of claim 12, wherein the layer of second semiconductor material comprises a rectangular mesa with rounded corners above the layer of first semiconductor material.

17. 13. The semiconductor structure of claim 12, wherein the first metal contact comprises a first ohmic contact and a second ohmic contact of a shared electrode of the semiconductor structure.

18. 20. The semiconductor structure of claim 17, wherein the layer of second semiconductor material includes a mesa on the layer of first semiconductor material between the first ohmic contact and the second ohmic contact.

19. 20. The semiconductor structure of claim 18, the first metal via and the second metal via extend from the backside of the substrate to a bottom surface of the first ohmic contact on one side of the mesa; The semiconductor structure comprises: a third metal via extending from the backside of the substrate to a bottom surface of the second ohmic contact on the other side of the mesa; a fourth metal via extending from the backside of the substrate to a bottom surface of the second ohmic contact on the other side of the mesa; The semiconductor structure further comprises:

20. 13. The semiconductor structure of claim 12, wherein the first metal via and the second metal via are integral with and located below the semiconductor structure.

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