Imaging device and imaging method

Abstract

[Problem] To provide an imaging device capable of reducing an unnecessary region on a substrate. [Solution] This imaging device having a plurality of stacked substrates comprises: a read-dedicated circuit that is disposed on a substrate different from a substrate on which a pixel array unit having a plurality of photoelectric conversion elements is disposed, and that executes an operation of reading electrical signals which are obtained through photoelectric conversion by the plurality of photoelectric conversion elements; and a circuit that is disposed on a substrate different from the substrate on which the read-dedicated circuit is disposed, and that executes operations other than the operation of the read-dedicated circuit on the basis of the electrical signals.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and an imaging method. [Background technology]

[0002] Conventionally, imaging devices equipped with synchronous solid-state imaging elements that capture image data (frames) in synchronization with a synchronization signal such as a vertical synchronization signal have been widely used. Synchronous solid-state imaging elements can only acquire image data at synchronization signal intervals (e.g., 1 / 60 seconds), making it difficult to meet the demand for faster processing in fields such as transportation and robotics. Therefore, asynchronous solid-state imaging elements have been proposed in which an address event detection circuit is provided for each pixel, which detects in real time, for each pixel address, that the light intensity of that pixel exceeds a threshold value as an address event (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-533140 Summary of the Invention [Problem to be solved by the invention]

[0004] The asynchronous solid-state imaging device described above can generate and output data much faster than a synchronous solid-state imaging device. This allows for faster image recognition of people and obstacles in the traffic sector, improving safety. However, the address event detection circuit is larger in circuit scale than the pixel circuit in a synchronous imaging device. Therefore, providing such a circuit for each pixel results in a larger mounting area than a synchronous imaging device.

[0005] In recent years, advances in semiconductor integrated circuit technology have made it possible to stack two substrates and transmit and receive signals at high speed between the upper and lower substrates. Therefore, it is also possible to configure an imaging device by stacking a substrate on which the address event detection circuit described above is arranged and a substrate on which a pixel array unit is arranged.

[0006] However, if there is a significant difference in the circuit area mounted on the two stacked substrates, the external size of the solid-state imaging device will be determined by the size of the substrate with the larger circuit area, which may prevent miniaturization. Furthermore, because the circuit components constituting the solid-state imaging device are interconnected and each circuit component has a different circuit area, it is not easy to allocate each circuit component so that the mounting areas of the two stacked substrates are equal. It is possible that one of the two stacked substrates has a large circuit area and the other has a small circuit area, resulting in a large amount of empty space. Having a large amount of empty space on a substrate means a lot of wasted space, which leads to increased chip costs.

[0007] Therefore, the present disclosure provides an imaging device and an imaging method that can reduce wasted space on a substrate. [Means for solving the problem]

[0008] In order to solve the above-described problems, according to the present disclosure, there is provided an imaging device including a plurality of stacked substrates, a read-only circuit that is disposed on a substrate different from a substrate on which a pixel array unit having a plurality of photoelectric conversion elements is disposed, and that reads out an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements; and a circuit that is arranged on a substrate different from the substrate on which the read-only circuit is arranged, and that performs an operation other than that of the read-only circuit based on the electrical signal.

[0009] the read-only circuit is a circuit that converts the electrical signal photoelectrically converted by the photoelectric conversion element into a voltage signal and performs gain adjustment; The substrate on which a circuit that performs operations other than the operation of the read-only circuit is arranged may perform at least one of the following: a process of converting a voltage signal output from the read-only circuit into a digital signal in units of two or more pixel groups arranged in a first direction of the pixel array section; a predetermined signal processing of the digital signal; and a process of driving the multiple photoelectric conversion elements in units of two or more pixel groups arranged in a second direction.

[0010] Of the circuits that perform operations other than the operation of the read-only circuit, a circuit portion whose power supply voltage exceeds a predetermined reference voltage may be disposed on the same substrate as the plurality of photoelectric conversion elements.

[0011] The pixel array unit may include at least a part of an AD unit that is disposed on a substrate on which the pixel array unit is disposed and that digitally converts pixel signals read out from the read-only circuit.

[0012] The AD unit may digitally convert pixel signals read out from the read-only circuit in units of two or more pixel groups arranged in a first direction of the pixel array unit.

[0013] The AD section may be arranged separately on a substrate on which the pixel array section is arranged and on another substrate.

[0014] The display device may further include a pixel group driving section that is disposed on a substrate on which the pixel array section is disposed, and that drives the pixel array section in units of two or more pixel groups disposed in the second direction.

[0015] The pixel group driving section may be divided and arranged on one substrate on which the pixel array section is arranged and on another substrate.

[0016] a first substrate on which the read-only circuit is disposed; a second substrate stacked on the first substrate and on which the pixel array unit is disposed; The semiconductor device may further comprise a third substrate that is stacked on the first substrate at the same layer height as the second substrate, and on which at least a part of a circuit that performs an operation other than that of the read-only circuit is disposed.

[0017] the first substrate is larger than the second substrate; The second substrate may be larger than the third substrate.

[0018] a first substrate on which the read-only circuit is disposed; a second substrate stacked on the first substrate and on which the pixel array unit is disposed; The semiconductor memory device may further comprise a third substrate stacked below the first substrate, on which at least a part of a circuit that performs an operation other than that of the read-only circuit is disposed.

[0019] a fourth substrate disposed at the same layer height as the third substrate; A part of a circuit that performs an operation other than the operation of the read-only circuit may be disposed on each of the third substrate and the fourth substrate.

[0020] The second substrate may be larger than the third and fourth substrates.

[0021] The read-only circuit may be disposed on the first substrate and the second substrate so as to overlap at least a portion of the read-only circuit with the pixel array section when viewed in a plan view in a stacking direction of the first substrate and the second substrate.

[0022] The read-only circuit may be provided for each of the plurality of photoelectric conversion elements.

[0023] The read-only circuits may be provided in correspondence with two or more of the photoelectric conversion elements.

[0024] The pixel array unit and the read-only circuit may each include a change amount detection unit that outputs a detection signal indicating whether or not a change amount of the electrical signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold.

[0025] The pixel array unit and the read-only circuit may each include a pixel AD unit that converts an electrical signal photoelectrically converted by each of the photoelectric conversion elements into a digital signal.

[0026] The pixel array section and the read-only circuit may each include a light detection section that detects the incident position and the incident time of light incident on the plurality of photoelectric conversion elements.

[0027] a first output unit that outputs a first signal from the pixel array unit; The read-only circuit may further include a second output section that outputs a second signal from the read-only circuit.

[0028] The plurality of substrates may be bonded together by at least one of Cu-Cu bonding, TSV (Through Silicon Via), and bump bonding.

[0029] The substrate may be a wafer or a semiconductor chip.

[0030] According to another aspect of the present disclosure, there is provided an imaging method including a plurality of stacked substrates, the method comprising: a step of reading out an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements in a read-only circuit disposed on a substrate different from a substrate on which a pixel array unit having the plurality of photoelectric conversion elements is disposed; and performing an operation other than the operation of the read-only circuit based on the electrical signal in a circuit disposed on a substrate different from the substrate on which the read-only circuit is disposed. [Brief explanation of the drawings]

[0031] [Figure 1] 1 is a block diagram showing a schematic configuration of an imaging device 1 according to a first embodiment. [Figure 2A] FIG. 2 is a diagram showing a first layout example of one of the substrates to be stacked. [Figure 2B] FIG. 10 is a diagram showing a first layout example of the other substrate to be stacked. [Figure 3A] FIG. 10 is a diagram showing a second layout example of one of the substrates to be stacked. [Figure 3B] FIG. 10 is a diagram showing a second layout example of the other substrate to be stacked. [Figure 4A] FIG. 10 is a diagram showing a third layout example of one of the substrates to be stacked. [Figure 4B] FIG. 10 is a diagram showing a third layout example of the other substrate to be stacked. [Figure 5A] FIG. 10 is a diagram showing a fourth layout example of one of the substrates to be stacked. [Figure 5B] FIG. 10 is a diagram showing a fourth layout example of the other substrate to be stacked. [Figure 6] FIG. 2 is a diagram showing the positional relationship between a pixel array unit and a pixel AFE unit. [Figure 7A] FIG. 3 is a schematic perspective view when the layout arrangement of FIGS. 2A and 2B is adopted. [Figure 7B] FIG. 4 is a schematic perspective view when the layout arrangement of FIGS. 3A and 3B is adopted. [Figure 8A] FIG. 2B is a layout diagram of a modified example of FIG. 2A. [Figure 8B] FIG. 2C is a layout diagram of a modified example of FIG. 2B. [Figure 8C] FIG. 3B is a layout diagram of a modified example of FIG. 3A. [Figure 8D] FIG. 3C is a layout diagram of a modified example of FIG. 3B. [Figure 9A] FIG. 7B is a perspective view showing a modified example of FIG. 7A. [Figure 9B] FIG. 7C is a perspective view showing a modified example of FIG. 7B. [Figure 10A] FIG. 2 is a diagram showing a connection between each pixel circuit and each sub-AFE unit. [Figure 10B] FIG. 2 is a diagram showing a connection between each pixel circuit and each sub-AFE unit. [Figure 10C] FIG. 2 is a diagram showing a connection between each pixel circuit and each sub-AFE unit. [Figure 10D] FIG. 2 is a diagram showing a connection between each pixel circuit and each sub-AFE unit. [Figure 11] FIG. 2 is a block diagram showing an example of the internal configuration of a column processing unit. [Figure 12] FIG. 3 is a block diagram showing an example of the internal configuration of a row driver. [Figure 13A] Layout diagram of the second board using the CoW method. [Figure 13B] Layout diagram of the first board using the CoW method. [Figure 14A] FIG. 13B is a layout diagram of a second substrate in which chips are arranged in a direction different from that of FIG. 13A. [Figure 14B] FIG. 13B is a layout diagram of the first substrate in which the chips are arranged in a direction different from that of FIG. 13A. [Figure 15A] First layout diagram of the third substrate with a three-layer structure. [Figure 15B] FIG. 10 is a first layout diagram of the second substrate having a three-layer structure. [Figure 15C] FIG. 1 is a first layout diagram of a first substrate having a three-layer structure. [Figure 16A] Second layout diagram of the third substrate with a three-layer structure. [Figure 16B] FIG. 2 is a second layout diagram of a second substrate having a three-layer structure. [Figure 16C] FIG. 2 is a second layout diagram of the first substrate having a three-layer structure. [Figure 17A] 3. A third layout diagram of the third substrate with a three-layer structure. [Figure 17B] FIG. 3 is a third layout diagram of the second substrate having a three-layer structure. [Figure 17C] FIG. 3 is a third layout diagram of the first substrate with a three-layer structure. [Figure 18] FIG. 1 is a block diagram showing a schematic configuration of an imaging device that does not have a column processing unit. [Figure 19A] FIG. 4 is a diagram schematically showing generation of an address event detection signal. [Figure 19B] FIG. 1 is a diagram showing a schematic diagram of the generation of a SPAD signal. [Figure 19C] FIG. 2 is a diagram illustrating the generation of a grayscale signal. [Figure 20A] FIG. 10 is a diagram showing an example in which one pixel circuit corresponds to one sub-AFE unit. [Figure 20B] FIG. 10 is a diagram showing an example in which a plurality of pixel circuits correspond to one sub-AFE unit. [Figure 20C] FIG. 10 is a diagram showing an example in which one pixel circuit corresponds to a plurality of sub-AFE units. [Figure 21A]FIG. 10 is a first layout diagram of the second substrate when it does not have a column processing section. [Figure 21B] FIG. 10 is a first layout diagram of the first substrate when it does not have a column processing section. [Figure 22A] FIG. 10 is a second layout diagram of the second substrate when it does not have a column processing section. [Figure 22B] FIG. 10 is a second layout diagram of the first substrate when it does not have a column processing section. [Figure 23A] FIG. 2 is a diagram showing a first example of a pixel array section. [Figure 23B] FIG. 10 is a diagram showing a second example of a pixel array section. [Figure 23C] FIG. 10 is a diagram showing a third example of a pixel array section. [Figure 24] FIG. 2 is a block diagram showing an example of an address event detection circuit. [Figure 25] FIG. 2 is a circuit diagram showing an example of the internal configuration of a current-voltage conversion circuit. [Figure 26] FIG. 3 is a circuit diagram showing an example of the internal configuration of a subtractor and a quantizer. [Figure 27] FIG. 1 is a circuit diagram of a pixel circuit in a global shutter imaging device. [Figure 28] FIG. 1 is a circuit diagram of a pixel circuit in a rolling shutter imaging device. [Figure 29] Circuit diagram of the pixel circuit and its surroundings for the Area AD method, which performs A / D conversion on a pixel area basis. [Figure 30] 4 is a flowchart showing a processing procedure performed by the imaging device 1 according to the first embodiment. [Figure 31] FIG. 10 is a block diagram showing another example of the configuration of the address event detection circuit. [Figure 32] FIG. 10 is a block diagram showing the configuration of an imaging device according to a second configuration example. [Figure 33] FIG. 1 is a block diagram showing a schematic configuration example of a vehicle control system. [Figure 34] 3A and 3B are diagrams showing examples of installation positions of an imaging unit and an outside-vehicle information detection unit; DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, an embodiment of an imaging device will be described with reference to the drawings. The following description will focus on the main components of the imaging device, but the imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0033] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration of an image pickup device 1 according to a first embodiment. The image pickup device 1 in Fig. 1 includes a pixel array unit 2, a row driver unit 3, a column processor 4, a pixel AFE unit 5, a column driver unit 6, a signal processor 7, and a system controller 8. In some cases, the image pickup device 1 in Fig. 1 may include an additional signal processor 9.

[0034] The pixel array unit 2 has a plurality of pixel circuits 2a arranged in row and column directions. Each pixel circuit 2a has a photoelectric conversion element and a readout circuit that reads out an electrical signal photoelectrically converted by the photoelectric conversion element. The readout circuit is a circuit that transfers the photoelectrically converted electrical signal to a pixel AFE (Analog Front End) unit described later. More specifically, the readout circuit has a transfer transistor and the like.

[0035] The row driver 3 sequentially drives each row in the pixel array section 2. The row driver 3 drives, row by row, a plurality of pixel circuits 2a (hereinafter referred to as a pixel group) connected to each row in the pixel array section 2. As will be described later, the row driver 3 has a circuit portion supplied with a high power supply voltage and a circuit portion supplied with a low power supply voltage.

[0036] The column processing unit 4 performs analog-to-digital conversion by sequentially reading out output signals from a plurality of pixel circuits 2a (hereinafter referred to as a pixel group) connected to each column in the pixel array unit 2. As will be described later, the column processing unit 4 has a circuit portion supplied with a high power supply voltage and a circuit portion supplied with a low power supply voltage.

[0037] The pixel AFE unit 5 reads out electrical signals photoelectrically converted by the multiple photoelectric conversion elements. More specifically, the pixel AFE unit 5 is a read-only circuit that compares the voltage signals output from each pixel circuit 2a with a reference signal and quantizes them. The pixel AFE unit 5 includes, for example, a reset transistor, an amplification transistor, and a selection transistor. The power supply voltage supplied to the pixel circuit 2a and the power supply voltage supplied to the pixel AFE unit 5 may be different; for example, the pixel AFE unit 5 may be supplied with a power supply voltage at a lower voltage level than the pixel circuit 2a.

[0038] The pixel AFE unit 5 is provided in correspondence with the pixel array unit 2. As will be described later, in this embodiment, it is assumed that the pixel AFE unit 5 will be arranged on a substrate separate from the substrate on which the pixel array unit 2 is arranged, and the pixel AFE unit 5 and the pixel array unit 2 are arranged in positions where they overlap one another vertically. This allows the pixel AFE unit 5 and the pixel array unit 2 to be joined by Cu-Cu bonding, TSV (Through Silicon Via), microbump bonding, or the like, thereby enabling high-speed signal transmission and reception.

[0039] The pixel AFE unit 5 has multiple sub-AFE units 5a arranged in the row and column directions, similar to the pixel array unit 2. Each sub-AFE unit 5a converts the electrical signal output from the corresponding pixel circuit 2a into a voltage signal and performs gain adjustment. Each sub-AFE unit 5a may also perform processing to quantize the voltage signal.

[0040] The column driver 6 sequentially drives each column in the pixel AFE unit 5. The column driver 6 sequentially outputs voltage signals or quantized data output from the multiple sub-AFE units 5a connected to each column in the pixel AFE unit 5, and inputs them to the signal processor 7. As will be described later, the column driver 6 has a circuit portion supplied with a high power supply voltage and a circuit portion supplied with a low power supply voltage.

[0041] The signal processing unit 7 performs various signal processing operations on the output signal of the pixel AFE unit 5. The signal processing unit 7 performs, for example, CDS (Correlated Double Sampling) processing and image recognition processing. If the signal processing unit 7 alone cannot perform all of the signal processing operations, an additional signal processing unit 9 may be used to perform further signal processing. Furthermore, a memory (not shown in FIG. 1 ) may be provided for storing data indicating the results of the signal processing performed by the signal processing unit 7 or the additional signal processing unit 9.

[0042] The system control unit 8 controls each unit within the imaging device 1. For example, the system control unit 8 controls the timing at which the row driving unit 3 drives each row of the pixel array unit 2 and the timing at which the column processing unit 4 reads out the output of the pixel circuits 2a of each column of the pixel array unit 2. The system control unit 8 also controls the timing at which the column driving unit 6 drives the pixel AFE unit 5 and the timing at which the signal processing unit 7 performs signal processing.

[0043] Each component within the imaging device 1 according to this embodiment is arranged on a plurality of stacked substrates. This embodiment is characterized by minimizing the free space on each substrate. The substrate in this embodiment may be a wafer or a semiconductor chip (hereinafter simply referred to as a chip). This embodiment may use any of the following methods: a WoW (Wafer on Wafer) method in which wafers are stacked on top of each other; a CoW (Chip on Wafer) method in which wafers and chips are stacked on top of each other; and a CoC (Chip on Chip) method in which chips are stacked on top of each other.

[0044] Since the imaging device 1 uses different power supply voltages for the various circuits within it, it is conceivable to separate the circuit boards depending on the power supply voltage level used by each circuit. For example, separate boards may be used to mount circuits with power supply voltages higher than a predetermined reference voltage level and boards to mount circuits with power supply voltages equal to or lower than the reference voltage level.

[0045] The imaging device 1 also includes a circuit for handling analog signals and a circuit for handling digital signals. Generally, circuits for handling analog signals are difficult to miniaturize because they are susceptible to noise and other factors. On the other hand, miniaturization of circuits for handling digital signals is unlikely to result in a degradation of electrical characteristics. Therefore, the substrate may be divided into one on which the circuits for handling analog signals are arranged and one on which the circuits for handling digital signals are arranged, and the circuit on the substrate on which the circuits for handling digital signals are arranged may be formed using a miniaturization process. Miniaturization of the circuit allows larger circuits to be implemented on the substrate while also reducing power consumption.

[0046] 2A and 2B are diagrams showing a first layout example of two stacked substrates 11 and 12. An example is shown in which substrate 12 of FIG. 2A is stacked on substrate 11 of FIG. 2B. Substrate 11 of FIG. 2B may be a wafer or a chip. Substrate 12 of FIG. 2A may be a wafer or a chip if substrate 11 of FIG. 2B is a wafer, but it is a chip if substrate 11 of FIG. 2B is a chip. Thus, substrate 11 of FIG. 2B has the same size as or a larger size than substrate 12 of FIG. 2A.

[0047] The pixel array section 2 and the column processing section 4 are arranged on the substrate 12 of FIG. 2A. The substrate 12 of FIG. 2A and the substrate 11 of FIG. 2B are bonded together at a plurality of bonding sections 13. The bonding sections 13 may bond the two substrates together using an adhesive or the like, or they may be bonded together using Cu-Cu bonding, TSV, microbump bonding, or the like. Because the substrate 12 of FIG. 2A is stacked on the substrate 11 of FIG. 2B, hereinafter the substrate 11 of FIG. 2B may be referred to as the first substrate 11, and the substrate 12 of FIG. 2A may be referred to as the second substrate 12.

[0048] 2A shows an example in which the pixel array unit 2 is arranged in approximately the center of the second substrate 12 and the column processing unit 4 is arranged nearby, but the specific locations of the pixel array unit 2 and the column processing unit 4 are arbitrary. However, as will be described later, the pixel array unit 2 transmits and receives signals to and from the pixel AFE unit 5 arranged on a separate substrate, so it is desirable to arrange the pixel array unit 2 and the pixel AFE unit 5 as close as possible to each other. Ideally, when the substrates 11 and 12 are stacked, it is desirable to arrange the pixel array unit 2 and the pixel AFE unit 5 so that they overlap one above the other. Furthermore, it is desirable to arrange the column processing unit 4 near the pixel array unit 2 from the viewpoint of reducing parasitic capacitance and parasitic resistance.

[0049] 2B, the first substrate 11 is provided with a pixel AFE unit 5, a column driver unit 6, a row driver unit 3, a signal processor 7, and an additional signal processor 9. The additional signal processor 9 may be omitted.

[0050] With the two substrates 11 and 12 stacked, the pixel AFE unit 5 is disposed in a position that vertically overlaps the pixel array unit 2 when viewed in a plan view from the normal direction to the substrate surfaces. A row driver 3 is disposed along a first end face of the pixel AFE unit 5, a column driver 6 is disposed along a second end face of the pixel AFE unit 5, a signal processor 7 is disposed along a third end face of the pixel AFE unit 5, and an additional signal processor 9 is disposed along a fourth end face of the pixel AFE unit 5. In addition, a system controller 8 is disposed along a corner of the pixel AFE unit 5.

[0051] 1, the signal processing unit 7 performs signal processing using the output of the column processing unit 4, so the signal processing unit 7 in the first substrate 11 in FIG. 2B is arranged in a position that vertically overlaps the column processing unit 4 in the second substrate 12 in FIG. 2A. The signal processing unit 7 and the column processing unit 4 are joined by Cu-Cu bonding, TSV, microbump bonding, or the like, and send and receive various signals. As a result, even if the column processing unit 4 and the signal processing unit 7 are arranged on separate substrates, the signal processing unit 7 can quickly perform signal processing using the output of the column processing unit 4 without being affected by parasitic capacitance or parasitic resistance.

[0052] 2A, by arranging not only the pixel array section 2 but also the column processing section 4 on the first substrate 11, it is possible to reduce the free space on the first substrate 11 and bring the circuit mounting area of ​​the first substrate 11 closer to the circuit mounting area of ​​the second substrate 12. Furthermore, because the circuit mounting area of ​​the second substrate 12 can be reduced, the substrate sizes of both the first substrate 11 and the second substrate 12 can be reduced, thereby achieving a miniaturization of the imaging device 1. Furthermore, because the circuits on both substrates 11 and 12 are arranged in the order in which signals flow, it is possible to shorten the signal propagation delay time and reduce the influence of noise.

[0053] 3A and 3B are diagrams showing a second layout example of two stacked substrates 11 and 12. The column processing unit 4 performs A / D conversion processing for each column, requiring multiple comparators, counters, switches, memories, and the like. Therefore, the circuit scale of the column processing unit 4 increases as the number of columns increases. Furthermore, the comparators and counters in the column processing unit 4 may use different power supply voltages. Therefore, the column processing unit 4 is divided into two parts, partially disposed on the first substrate 11 and partially disposed on the second substrate 12. More specifically, the circuit parts of the column processing unit 4 that use a high power supply voltage, such as the comparators, are disposed on the second substrate 12, and the circuit parts that use a low power supply voltage, such as the counters, are disposed on the first substrate 11. This reduces the number of power supply voltages supplied to each of the first substrate 11 and the second substrate 12.

[0054] Since the signal processing unit 7 receives signals from both the pixel AFE unit 5 and the column processing unit 4, in FIG. 3B the signal processing unit 7 is disposed between the pixel AFE unit 5 and the column processing unit 4 on the first substrate 11.

[0055] 3A and 3B , when the circuit scale of the column processing unit 4 is large or when the power supply voltage level used by the column processing unit 4 differs depending on the internal circuits thereof, the column processing unit 4 is divided and arranged on the first substrate 11 and the second substrate 12, thereby suppressing variations in the circuit mounting area between the first substrate 11 and the second substrate 12 and enabling the supplied power supply voltage to be divided for each substrate. Furthermore, by arranging the signal processing unit 7 between the pixel AFE unit 5 and the column processing unit 4, it is possible to speed up the transmission and reception of signals between the signal processing unit 7 and the column processing unit 4 and between the signal processing unit 7 and the pixel AFE unit 5.

[0056] 4A and 4B are diagrams showing a third layout example of two stacked substrates 11 and 12. In the third layout example, of the circuits constituting the row driver 3, circuit parts that are driven at a high voltage, such as level shifters (for example, level shifters), and circuit parts that are driven at a low voltage are arranged on separate substrates.

[0057] 4A, row driver units 3 are provided at positions where the first substrate 11 and the second substrate 12 overlap one another. The row driver unit 3 in the second substrate 12 includes circuit parts such as level shifters that are driven at a high voltage, while the row driver unit 3 in the first substrate 11 includes circuit parts such as shift registers that are driven at a low voltage. The row driver units 3 on each substrate are bonded together using Cu-Cu bonding, TSV, microbump bonding, or the like.

[0058] 4A and 4B, the column processing section 4 is disposed on the second substrate 12, but similarly to FIGS. 3A and 3B, the column processing section 4 may be divided and disposed on the first substrate 11 and the second substrate 12. Alternatively, the column processing section 4 may be disposed on the first substrate 11 instead of the second substrate 12.

[0059] 5A and 5B are diagrams showing a fourth layout example of two stacked substrates 11 and 12. In the fourth layout example, the row driver 3 and column processor 4 are arranged on the second substrate 12. This makes it possible to further reduce the difference in circuit mounting area between the first substrate 11 and the second substrate 12.

[0060] Various layout examples other than the first to fourth layout examples described above are possible. The first to fourth layouts described above have in common that the pixel array section 2 on the second substrate 12 and the pixel AFE section 5 on the first substrate 11 are arranged in positions that vertically overlap, as shown in FIG. 6. This allows for efficient readout from each pixel of the pixel array section 2. Note that the pixel array section 2 and the pixel AFE section 5 only need to partially overlap vertically, and do not necessarily need to entirely overlap vertically. Furthermore, the circuit mounting areas of the pixel array section 2 and the pixel AFE section 5 do not necessarily need to be the same.

[0061] FIG. 7A is a schematic perspective view of the layout shown in FIGS. 2A and 2B. In the cases of FIGS. 2A and 2B, the column processing unit 4 is disposed on the second substrate 12, and the signal processing unit 7 is disposed on the first substrate 11. As shown in FIG. 7A, the column processing unit 4 and the signal processing unit 7 are disposed one above the other. This allows digital pixel data converted from analog to digital by the column processing unit 4 to be transmitted to the signal processing unit 7 in the second substrate 12 via Cu-Cu bonding or the like over the shortest distance, enabling rapid signal processing without being affected by parasitic capacitance or parasitic resistance of the signal wiring. Furthermore, in the layout shown in FIG. 7A, the second substrate 12 primarily handles analog signals, and the first substrate 11 primarily handles digital signals, allowing the circuitry on the first substrate 11 to be formed using a microfabrication process.

[0062] 7B is a schematic perspective view of the layout shown in FIGS. 3A and 3B. In the cases of FIGS. 3A and 3B, the column processing units 4 are arranged on both the first substrate 11 and the second substrate 12. Therefore, for example, the first half of the processing, which uses the high power supply voltage of the column processing units 4, can be performed in the column processing units 4 on the second substrate 12, and the second half of the processing, which uses the low power supply voltage, can be performed in the column processing units 4 on the first substrate 11. As shown in FIG. 7B, the column processing units 4 on the first substrate 11 and the column processing units 4 on the second substrate 12 are arranged so as to overlap one another vertically, allowing signals to be quickly transmitted and received between the column processing units 4 on both substrates.

[0063] In the first to fourth layout examples described above, the pixel array section 2 is arranged in the approximate center of the second substrate 12, but the location of the pixel array section 2 is arbitrary. In addition, the number and locations of the bonding sections 13 are also arbitrary.

[0064] Figures 8A and 8B are modifications of Figures 2A and 2B. Figures 8C and 8D are modifications of Figures 3A and 3B. In the second substrate 12 shown in Figures 8A and 8C, the pixel array section 2 is arranged along one edge of the second substrate 12, and the bonding section 13 is arranged along another edge opposite to this edge. In the first substrate 11 shown in Figures 8B and 8D, the pixel AFE section 5 is arranged so as to vertically overlap the pixel array section 2 of the second substrate 12, and the bonding section 13 is also arranged so as to vertically overlap the first substrate 11 and the second substrate 12.

[0065] As described above, various modifications are possible for the layout arrangement of the circuits in the first substrate 11 and the second substrate 12.

[0066] FIG. 9A is a perspective view showing a modified example of FIG. 7A, and FIG. 9B is a perspective view showing a modified example of FIG. 7B. In FIG. 9A, the column processing unit 4 of the second substrate 12 is divided into two parts and arranged along two opposing edges of the second substrate 12. Hereinafter, these two divided column processing units 4 will be referred to as divided column processing units 4a. Accordingly, the signal processing unit 7 of the first substrate 11 is also divided into two parts and arranged along two opposing edges of the first substrate 11. Hereinafter, these two divided signal processing units 7 will be referred to as divided signal processing units 7a. The divided column processing units 4a and divided signal processing units 7a on each edge are arranged so as to overlap one another. The divided column processing units 4a and divided signal processing units 7a are joined by Cu-Cu bonding, TSV, microbump bonding, or the like to transmit and receive various signals.

[0067] FIG. 9B is similar to FIG. 9A, and two division column processing sections 4a are arranged along two opposing edges of both the first substrate 11 and the second substrate 12.

[0068] In this way, by dividing the column processing section 4 into two and arranging them along two opposing edges of the second substrate 12, it is possible to make the distance from the pixel array section 2 to the column processing section 4 as uniform as possible. Similarly, by dividing the signal processing section 7 into two and arranging them along two opposing edges of the second substrate 12, it is possible to make the distance from the pixel AFE section 5 to the signal processing section 7 as uniform as possible.

[0069] 6, in this embodiment, the pixel array unit 2 and the pixel AFE unit 5 are arranged in positions that overlap one another on separate substrates, allowing various signals to be quickly transmitted and received between the pixel array unit 2 and the pixel AFE unit 5. The pixel array unit 2 and the pixel AFE unit 5 transmit and receive various signals via Cu-Cu bonding, TSV or microbump bonding.

[0070] 10A, 10B, 10C, and 10D are diagrams showing connection modes between each pixel circuit 2a in the pixel array unit 2 and each sub-AFE unit 5a in the pixel AFE unit 5. The connection mode in FIG. 10A shows an example in which each pixel circuit 2a in the pixel array unit 2 and a corresponding sub-AFE unit 5a in the pixel AFE unit 5 transmit and receive various signals. FIG. 10B shows an example in which multiple pixel circuits 2a in the pixel array unit 2 and a corresponding sub-AFE unit 5a in the pixel AFE unit 5 transmit and receive various signals. FIG. 10C shows an example in which each pixel circuit 2a in the pixel array unit 2 and a corresponding multiple sub-AFE unit 5a in the pixel AFE unit 5 transmit and receive various signals. FIG. 10D shows an example in which only some pixel circuits 2a in the pixel array unit 2 transmit and receive various signals and a corresponding sub-AFE unit 5a in the pixel AFE unit 5 transmit and receive various signals.

[0071] The pixel array unit 2 and the pixel AFE unit 5 may be connected in any of the modes shown in Fig. 10A to Fig. 10D. As shown in Fig. 10D, depending on the pixel circuit 2a in the pixel array unit 2, transmission and reception of signals with the pixel AFE unit 5 may not be performed.

[0072] Fig. 11 is a block diagram showing an example of the internal configuration of the column processing unit 4. As shown in Fig. 11, the column processing unit 4 has, for each column signal line extending in the column direction, a comparator 21, an up / down counter (hereinafter simply referred to as a counter) 23, and a memory 24. The column processing unit 4 also has a DAC 22.

[0073] The DAC 22 generates a reference signal. The comparator 21 compares the voltage signal on the column signal line with the reference signal. The counter 23 counts the count value over a period until the comparison result by the comparator 21 is inverted. The count value of the counter 23 is held in the memory 24. The digital signal representing the count value of the counter 23 held in the memory 24 is sent to the signal processing unit 7.

[0074] 11 in the column processing unit 4 is supplied with a high power supply voltage to the circuit portion above the dashed line Ln1 (such as the comparator 21), whereas a low power supply voltage is supplied to the circuit portion below the dashed line Ln1 (such as the counter 23 and memory 24). For this reason, in the above-mentioned FIGS. 2A and 3A, the high power supply voltage supply circuit portion (such as the comparator 21), which is part of the column processing unit 4, is arranged on the second substrate 12.

[0075] 12 is a block diagram showing an example of the internal configuration of the row driver 3. As shown in Fig. 12, the row driver 3 has an address selection logic unit 25, a plurality of decoders 26, a plurality of memories 27, a plurality of level shifters 28, and a plurality of drivers 29. Each driver 29 is connected to a respective row selection line of the pixel array unit 2.

[0076] The address selection logic unit 25 sends an address signal sent from the system control unit 8 to each decoder 26. The decoder 26 decodes the address signal. The signal decoded by the decoder 26 is temporarily stored in a memory 27. A level shifter 28 shifts the voltage level of the data stored in the memory 27 and supplies it to a driver 29. The driver 29 drives a corresponding column selection line at a timing according to the address signal. Signals may be transmitted and received between multiple drivers 29 and multiple memories 27.

[0077] A low power supply voltage is supplied to the address selection logic unit 25, decoder 26, and memory 27 in the row driver 3. A high power supply voltage is supplied to the level shifter 28 and driver 29. For this reason, in FIG. 4A and other figures described above, part of the column driver 6 is arranged on the second substrate 12.

[0078] As described above, the substrate in this embodiment is a wafer or a chip. When the substrate is made up of chips, multiple chips may be arranged at the same layer height. More specifically, the first substrate 11 may be a wafer, the second substrate 12 may be multiple chips, and the multiple chips may be stacked on the wafer using CoW (Chip on Wafer).

[0079] 13A and 13B are layout diagrams showing an example of CoW. FIG. 13A shows the layout of the second substrate 12, and FIG. 13B shows the layout of the first substrate 11. The first substrate 11 is a base wafer. A pixel AFE unit 5, a row driver unit 3, a column driver unit 6, a column processor 4, a signal processor 7, and a system controller 8 are arranged on the first substrate 11. The second substrate 12 is composed of two chips. A pixel array unit 2 is arranged on one chip (hereinafter referred to as the first chip) 15. A signal processor 7 is arranged on the other chip (hereinafter referred to as the second chip) 16. The signal processor 7 on the second chip 16 is arranged so as to vertically overlap the signal processor 7 on the first substrate 11. Similarly, the pixel array unit 2 on the first chip 15 is arranged so as to vertically overlap the pixel AFE unit 5 on the first substrate 11. The pixel array unit 2 that handles analog signals is arranged on the first chip 15, while the signal processing unit 7 that handles digital signals is arranged on the second chip 16. Therefore, the signal processing unit 7 can be formed on the second chip 16 using a microprocess, and even if the circuit scale of the signal processing unit 7 is large, it can be mounted on the second chip 16 that is smaller than the first chip 15. In addition, the types of power supply voltages supplied to the first chip 15 and the second chip 16 can be different.

[0080] The placement locations and sizes of the first chip 15 and second chip 16 constituting the first substrate 11 are arbitrary. Figures 14A and 14B are layout diagrams showing examples in which the first chip 15 and the second chip 16 are placed in a direction different from that shown in Figures 13A and 13B. The layouts of the first substrate 11 and the second substrate 12 in Figures 14A and 14B are the same as those shown in Figures 13A and 13B.

[0081] In the above description, an example has been shown in which the imaging device 1 is configured with two stacked substrates 11, 12, but the imaging device 1 may also be configured with three or more stacked substrates. Figures 15A, 15B, and 15C are diagrams showing a first layout example of an imaging device 1 with a three-layer structure. Figure 15A shows the layout arrangement of the third substrate 14 in the top layer, Figure 15B shows the layout arrangement of the second substrate 12 in the second layer, and Figure 15C shows the layout arrangement of the first substrate 11 in the bottom layer.

[0082] The pixel array section 2 is arranged on the third substrate 14. The pixel AFE section 5 is arranged on the second substrate 12 at a position that vertically overlaps the pixel array section 2. The row driver 3, the column driver 6, the column processor 4, the signal processor 7, and the system controller 8 are arranged on the first substrate 11. In the first layout example, the first substrate 11 has the largest amount of free space, followed by the second substrate 12. Thus, there is variation in the amount of free space among the first to third substrates 14.

[0083] 16A, 16B, and 16C are diagrams showing a second layout example of an imaging device 1 having a three-layer structure. In the second layout example, as shown in FIG. 16B, the row driver 3 and column processor 4 that were arranged on the first substrate 11 in the first layout example are arranged on the second substrate 12. This makes it possible to suppress variations in the free space between the second substrate 12 and the third substrate 14. Furthermore, because the column processor 4 and the column driver 6 use a high power supply voltage, the circuit parts that use the high power supply voltage are concentrated on the second substrate 12, while only logic circuits can be arranged on the first substrate 11, and the first substrate 11 can be formed using a fine process, thereby achieving low power consumption.

[0084] 17A, 17B, and 17C are diagrams showing a third layout example of an imaging device 1 having a three-layer structure. In the third layout example, the first substrate 11 is composed of a first chip 15 and a second chip 16. The column processing unit 4 is arranged on the first chip 15, and the signal processing unit 7 and the system control unit 8 are arranged on the second chip 16. In the third layout example, if there is no free space on the second substrate 12 to arrange the column processing unit 4 and row driver unit 3, which use a high power supply voltage, the first substrate 11 can be divided into two chips, with the column processing unit 4, which uses a high power supply voltage, arranged on the first chip 15, and only the logic circuit portion arranged on the second chip 16. This allows the second chip 16 to be formed using a fine process, thereby reducing power consumption.

[0085] In the above description, an example of the imaging device 1 having the column processing unit 4 has been given, but it is also possible to have an imaging device 1 that does not have the column processing unit 4. This embodiment is also applicable to such an imaging device 1.

[0086] FIG. 18 is a block diagram showing a schematic configuration of an imaging device 1 that does not have a column processing unit 4. The imaging device 1 in FIG. 18 has a configuration in which the column processing unit 4 is omitted from that in FIG. 1. The pixel array unit 2 in FIG. 18 is driven row by row by a row driving unit 3. Electrical signals photoelectrically converted by multiple pixel circuits 2a connected to each row are sent in sequence to the pixel AFE unit 5. Furthermore, if an address event detection circuit (described later) is provided in the pixel circuit 2a, an event detection signal detected by the address event detection unit is also sent to the pixel AFE unit 5.

[0087] The pixel array section 2 is used for imaging purposes, as well as for address event detection, detection of the light receiving position and light receiving timing of an optical signal, and A / D conversion for each pixel.

[0088] 19A is a diagram schematically illustrating generation of an address event detection signal (hereinafter referred to as a DVS (Dynamic Vision Sensor) signal) when the pixel array unit 2 is used for address event detection. When an address event is detected by a pixel circuit 2b for address event detection (hereinafter referred to as a DVS pixel circuit 2b) in the pixel array unit 2, a DVS signal is output from the pixel AFE unit 5.

[0089] 19B is a diagram schematically illustrating generation of a SPAD (Single Photon Avalanche Diode) signal when the pixel array unit 2 is used to detect the light-receiving position and light-receiving timing of an optical signal. When an optical signal is detected by the SPAD pixel circuit 2c in the pixel array unit 2, a digitized SPAD signal is output from the pixel AFE unit 5. The pixel AFE unit 5 performs A / D conversion processing.

[0090] FIG. 19C is a diagram schematically illustrating generation of a gradation signal when A / D conversion is performed for each pixel in the pixel array unit 2. At least a portion of the pixel array unit 2 is provided with, for example, a pixel 2d for detecting a phase difference. The pixel 2d for detecting a phase difference is configured by dividing a single pixel into left and right halves, performing photoelectric conversion for each divided pixel, and detecting the difference between the electrical signals photoelectrically converted by both divided pixels. This difference corresponds to the defocus amount and can be used for automatic focus adjustment, etc. The difference or gradation signal described above is A / D converted by the pixel AFE unit 5 and output.

[0091] When the column processing unit 4 is not provided, there are several possible correspondence relationships between the pixel circuits 2a in the pixel array unit 2 and the sub-AFE units 5a in the pixel AFE unit 5. Fig. 20A shows an example in which one pixel circuit 2a in the pixel array unit 2 corresponds to one sub-AFE unit 5a in the pixel AFE unit 5. Fig. 20B shows an example in which multiple pixel circuits 2a in the pixel array unit 2 correspond to one sub-AFE unit 5a in the pixel AFE unit 5. Fig. 20C shows an example in which one pixel circuit 2a in the pixel array unit 2 corresponds to multiple sub-AFE units 5a in the pixel AFE unit 5.

[0092] 21A and 21B are diagrams showing a first layout example of an imaging device 1 that does not have a column processing unit 4. FIG. 21A shows the layout arrangement of a second substrate 12, and FIG. 21B shows the layout arrangement of a first substrate 11. A pixel AFE unit 5, a row driver unit 3, a column driver unit 6, a signal processing unit 7, and a system control unit 8 are arranged on the first substrate 11. The second substrate 12 has a first chip 15 and a second chip 16. A pixel array unit 2 is arranged on the first chip 15. A signal processing unit 7 is arranged on the second chip 16. The signal processing unit 7 in the second chip 16 is arranged so as to vertically overlap the signal processing unit 7 on the first substrate 11. Because the second chip 16 can be formed using a microprocess, the size of the second chip 16 can be smaller than that of the first chip 15.

[0093] 22A and 22B are diagrams showing a second layout example of an imaging device 1 that does not have a column processing unit 4. This differs from FIG. 21A in that a memory 27 is arranged in the signal processing unit 7 arranged on the second chip 16 in the second substrate 12 shown in FIG. 22A, but the rest is the same as FIG. 21A and 21B, including the layout of the first substrate 11. By using a microprocess for the second chip 16, even circuits that require a large mounting area, such as the memory 27, can be realized on a relatively small chip.

[0094] At least a part of the pixel array unit 2 may be provided with a DVS pixel circuit 2b, a SPAD pixel circuit 2c, or a pixel circuit 2a that performs A / D conversion on a pixel-by-pixel basis. That is, the pixel array unit 2 may include at least two of the following: an imaging pixel circuit 2a, a DVS pixel circuit 2b, a SPAD pixel circuit 2c, and a pixel A / D pixel circuit 2d. The internal configuration of the pixel AFE unit 5 may vary depending on the type of pixel circuit in the pixel array unit 2.

[0095] Fig. 23A is a diagram showing a first example of the pixel array unit 2. The pixel array unit 2 in Fig. 23A shows an example in which a DVS pixel circuit 2b is provided in a part of an imaging pixel circuit 2a. In this case, when an address event is detected in the DVS pixel circuit 2b, an address event detection signal (DVS signal) is output from the pixel AFE unit 5.

[0096] Fig. 23B is a diagram showing a second example of the pixel array unit 2. The pixel array unit 2 in Fig. 23B shows an example in which a SPAD pixel circuit 2c is provided in a part of the imaging pixel circuit 2a. In this case, when a light signal is detected by the SPAD pixel circuit 2c, a SPAD signal indicating the detection location and detection timing is output from the pixel AFE unit 5.

[0097] Fig. 23C is a diagram showing a third example of the pixel array unit 2. The pixel array unit 2 in Fig. 23C shows an example in which pixel circuits 2a that perform A / D conversion on a pixel-by-pixel basis are provided in some of the pixel circuits 2a for imaging. In this case, the electrical signals photoelectrically converted by the pixel circuits 2a that perform A / D conversion on a pixel-by-pixel basis are sent to the pixel AFE unit 5, which outputs A / D converted digital pixel data.

[0098] When detecting an address event in the pixel array unit 2 and the pixel AFE unit 5, at least one of the pixel array unit 2 and the pixel AFE unit 5 is provided with an address event detection circuit.

[0099] 24 is a block diagram showing an example of an address event detection circuit 300. The address event detection circuit 300 in FIG.

[0100] The current-voltage conversion circuit 310 converts the photocurrent from the corresponding photodiode 221 into a voltage signal. The current-voltage conversion circuit 310 supplies the voltage signal to a buffer 320.

[0101] The buffer 320 corrects the voltage signal from the current-voltage conversion circuit 310. The buffer 320 outputs the corrected voltage signal to the subtractor 330.

[0102] The subtractor 330 reduces the level of the voltage signal from the buffer 320 in accordance with the row drive signal from the row drive circuit 251. The subtractor 330 supplies the reduced voltage signal to the quantizer 340.

[0103] The quantizer 340 quantizes the voltage signal from the subtractor 330 into a digital signal and outputs it to the transfer circuit 350 as a detection signal.

[0104] The transfer circuit 350 transfers the detection signal from the quantizer 340 to the signal processing circuit 240 in accordance with the column drive signal from the column drive circuit 252 .

[0105] The current-voltage conversion circuit 310 and buffer 320 in FIG. 24 are implemented in the pixel array unit 2, for example, and the subtractor 330, quantizer 340, and transfer circuit 350 are implemented in the pixel AFE unit 5.

[0106] Fig. 25 is a circuit diagram showing an example of the internal configuration of current-voltage conversion circuit 310. Current-voltage conversion circuit 310 in Fig. 25 includes N-type transistors 311 and 313 and a P-type transistor 312. These transistors may be, for example, MOS (Metal-Oxide-Semiconductor) transistors.

[0107] The source of N-type transistor 311 is connected to the cathode of photodiode 221, and the drain is connected to a power supply terminal. P-type transistor 312 and N-type transistor 313 are connected in series between the power supply terminal and a ground terminal. The connection point of P-type transistor 312 and N-type transistor 313 is connected to the gate of N-type transistor 311 and the input terminal of buffer 320. A predetermined bias voltage Vbias1 is applied to the gate of P-type transistor 312.

[0108] The drains of N-type transistors 311 and 313 are connected to the power supply, and this type of circuit is called a source follower. These two source followers connected in a loop convert the photocurrent from photodiode 221 into a voltage signal. In addition, P-type transistor 312 supplies a constant current to N-type transistor 313.

[0109] Furthermore, the ground of the light receiving chip 201 and the ground of the detection chip 202 are separated from each other to prevent interference.

[0110] 26 is a circuit diagram showing an example of the internal configuration of the subtractor 330 and the quantizer 340. The subtractor 330 includes capacitors 331 and 333, a comparator 332, and a switch 334.

[0111] One end of the capacitor 331 is connected to the output terminal of the buffer 320, and the other end is connected to the input terminal of the inverter 332. The capacitor 333 is connected in parallel with the inverter 332. The switch 334 opens and closes the path connecting both ends of the capacitor 333 in accordance with the row drive signal.

[0112] The inverter 332 inverts the voltage signal input via the capacitor 331. The inverter 332 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 332.

[0113] Incidentally, in the rolling shutter imaging device 1, the photoelectric conversion results are transferred while scanning the pixel array unit 2 row by row, resulting in an image in which fast-moving objects appear distorted. For this reason, a global shutter imaging device 1 has been proposed in which the photoelectric conversion results for one frame are stored in the memory 27 and read out from the memory 27 to generate a captured image.

[0114] Fig. 27 is a circuit diagram of a pixel circuit 2a in a global shutter type imaging device 1. The pixel circuit 2a in Fig. 27 has a photoelectric conversion element 31, a transfer transistor 32, a reset transistor 33, a buffer 34, and a memory 35. The memory 35 has a P-phase storage unit 35a and a D-phase storage unit 35b.

[0115] The P-phase memory unit 35a stores the potential at the time of reset. The D-phase memory unit 35b stores the potential corresponding to the photoelectrically converted electrical signal. By detecting the difference between the potential stored in the P-phase memory unit 35a and the potential stored in the D-phase memory unit 35b, fluctuations in the potential can be offset. The potentials in the P-phase memory unit 35a and the D-phase memory unit 35b are re-stored each time an image is captured.

[0116] In this embodiment, the photoelectric conversion element 31, transfer transistor 32, and reset transistor 33 are arranged to the left of the dashed line in Figure 27, i.e., in the pixel array section 2 of the second substrate 12, and the memory 35 is arranged to the right of the dashed line, i.e., in the pixel AFE section 5 in the first substrate 11.

[0117] 28 is a circuit diagram of a pixel circuit 2a in the rolling shutter imaging device 1. The pixel circuit 2a in FIG.

[0118] In this embodiment, the photoelectric conversion element 31 and the transfer transistor 32 are arranged to the left of the dashed line in FIG. 28, i.e., in the pixel array section 2 of the second substrate 12, and the reset transistor 33, the amplification transistor 36, and the selection transistor 37 are arranged to the right of the dashed line, i.e., in the pixel AFE section 5 in the first substrate 11.

[0119] Fig. 29 is a circuit diagram of a pixel circuit 2a and its surroundings that uses an area AD system in which A / D conversion is performed on a pixel area basis. In the pixel circuit 2a shown in Fig. 29, multiple pixel circuits 2a are connected to one A / D converter (hereinafter referred to as ADC). Each pixel circuit 2a has a photoelectric conversion element 31, a transfer transistor 32, a reset transistor 33, an amplification transistor 36, and a selection transistor 37.

[0120] In this embodiment, the left side of the dashed line in FIG. 29 is arranged in the pixel array section 2 of the second substrate 12, and the ADC on the right side of the dashed line is arranged in the pixel AFE section 5 in the first substrate 11.

[0121] 30 is a flowchart showing the processing procedure performed by the imaging device 1 according to the first embodiment. First, the pixel AFE unit 5 (read-only circuit), which is arranged on a substrate different from the substrate on which the pixel array unit 2 having the plurality of photoelectric conversion elements 31 is arranged, performs a read operation of the electrical signals photoelectrically converted by the plurality of photoelectric conversion elements 31 (step S1). Next, an operation other than that of the pixel AFE unit 5 is performed in a circuit on a substrate different from the substrate on which the pixel AFE unit 5 is arranged (step S2).

[0122] As described above, in this embodiment, the pixel array unit 2 and the pixel AFE unit 5 are arranged on separate boards, and circuits in the imaging device 1 that perform operations other than those of the pixel AFE unit 5 are arranged on a board separate from the board on which the pixel AFE unit 5 is arranged. This makes it possible to suppress variations in the circuit mounting area arranged on each board, reduce the free space on each board, and reduce power consumption.

[0123] For example, by separating the boards on which circuits using a high power supply voltage are arranged from the boards on which circuits using a low power supply voltage are arranged, the number of types of power supply voltages supplied to each board can be reduced, the wiring pattern for supplying the power supply voltages can be shortened, and power supply noise can be reduced. More specifically, for circuits that include circuit parts using a high power supply voltage and circuit parts using a low power supply voltage, such as the column processing unit 4, row driving unit 3, and column driving unit 6, the board size and power consumption can be reduced by dividing the circuit parts and arranging them on multiple boards.

[0124] Furthermore, when multiple circuit parts that send and receive signals are arranged on multiple substrates, the circuit parts are arranged in a vertically overlapping position and are joined using Cu-Cu bonding, TSV, microbump bonding, etc., which makes them less susceptible to the effects of parasitic resistance and parasitic capacitance and also shortens signal propagation delay time.

[0125] Furthermore, by separating the boards on which circuits including analog circuits are placed from the boards on which digital circuits are placed, the circuitry on the boards on which digital circuits are placed can be formed using cutting-edge micro-processes, which allows for the board size to be reduced and power consumption on the board to be reduced.

[0126] The pixel array section 2 can be used not only for imaging purposes, but also for detecting address events, detecting the light receiving position and timing of an optical signal, and performing A / D conversion on a pixel-by-pixel basis, and the circuits that make up the imaging device 1 can be distributed across multiple boards to suit each purpose.

[0127] (Second embodiment) In the first embodiment described above, for example, an image pickup device 1 including the address event detection circuit 300 of FIG. 24 has been described, but the internal configuration of the address event detection circuit 300 is not necessarily limited to that of FIG. 24. FIG. 31 is a block diagram showing another configuration example of the address event detection circuit 300. The address event detection circuit 300 according to the configuration example of FIG. 31 includes a current-voltage conversion circuit 310, a buffer 320, a subtractor 330, a quantizer 340, and a transfer circuit 350, as well as a storage unit 360 and a control unit 370. Hereinafter, the image pickup device 1 including the address event detection circuit 300 of FIG. 24 will be referred to as a first configuration example, and the image pickup device 1 including the address event detection circuit 300 of FIG. 31 will be referred to as a second configuration example.

[0128] The storage unit 360 is provided between the quantizer 340 and the transfer circuit 350, and stores the output of the quantizer 340, i.e., the comparison result of the comparator 3341 in the quantizer 340, based on the sample signal supplied from the control unit 370. The storage unit 360 may be a sampling circuit such as a switch, a plastic, or a capacitor, or may be a digital memory circuit such as a latch or a flip-flop.

[0129] The control unit 370 applies a predetermined threshold voltage V to the inverting (-) input terminal of the comparator 3341. th The control unit 370 supplies the threshold voltage V th For example, the control unit 370 may set a threshold voltage V corresponding to an ON event indicating that the amount of change in the photocurrent has exceeded the upper threshold. th1 , and a threshold voltage V corresponding to an OFF event indicating that the amount of change has fallen below the lower limit threshold. th2 By supplying these signals at different timings, one comparator 3341 can detect multiple types of address events.

[0130] For example, the storage unit 360 receives a threshold voltage V corresponding to an OFF event from the control unit 370 to the inverting (−) input terminal of the comparator 3341. th2 During the period when th1 The comparison result of the comparator 3341 using the above may be stored. The storage unit 360 may be located inside the pixel 216 or outside the pixel 216. The storage unit 360 is not an essential component of the address event detection circuit 300. In other words, the storage unit 360 may be omitted.

[0131] [Imaging device 1 according to the second configuration example (scanning method)] The imaging device 210 including the first exemplary configuration of the address event detection circuit 300 shown in Fig. 24 described above is an asynchronous imaging device 1 that reads events using an asynchronous reading method. However, the event reading method is not limited to the asynchronous reading method, and may be a synchronous reading method. The imaging device 1 to which the synchronous reading method is applied is a scanning imaging device 1, the same as a normal imaging device 1 that captures images at a predetermined frame rate.

[0132] FIG. 32 is a block diagram showing an example of the configuration of an imaging device 1 according to a second configuration example, that is, a scanning type imaging device 1, which is used as an imaging device 210 in an imaging system to which the technology according to the present disclosure is applied.

[0133] As shown in FIG. 32, an imaging device 210 according to a second configuration example as the imaging device 1 of the present disclosure is configured to include a pixel array section 211, a signal processing section 212, a driving section 213, a readout area selection section 214, and a signal generation section 215.

[0134] The pixel array unit 211 includes a plurality of pixels 216. The plurality of pixels 216 output an output signal in response to a selection signal from the readout region selection unit 214. Each of the plurality of pixels 216 may be configured to have a quantizer within the pixel, as shown in FIG. 24, for example. The plurality of pixels 216 output an output signal corresponding to the amount of change in light intensity. The plurality of pixels 216 may be arranged two-dimensionally in a matrix, as shown in FIG. 32.

[0135] The driving unit 213 drives each of the multiple pixels 216 to output a pixel signal generated by each pixel 216 to the signal processing unit 212. The driving unit 213 and the signal processing unit 212 are circuit units for acquiring gradation information. Therefore, when only event information is to be acquired, the driving unit 213 and the signal processing unit 212 may be omitted.

[0136] The readout region selection unit 214 selects a portion of the plurality of pixels 216 included in the pixel array unit 211. For example, the readout region selection unit 214 selects one or more rows from among the rows included in the two-dimensional matrix structure corresponding to the pixel array unit 211. The readout region selection unit 214 sequentially selects one or more rows according to a preset cycle. The readout region selection unit 214 may also determine the selection region in response to a request from each pixel 216 in the pixel array unit 211.

[0137] The signal generation unit 215 generates an event signal corresponding to an active pixel that has detected an event among the selected pixels, based on the output signals of the pixels selected by the readout region selection unit 214. An event is an event in which the intensity of light changes. An active pixel is a pixel in which the amount of change in the intensity of light corresponding to the output signal exceeds or falls below a predetermined threshold. For example, the signal generation unit 215 compares the output signal of the pixel with a reference signal, detects an active pixel that outputs an output signal when the output signal is greater or smaller than the reference signal, and generates an event signal corresponding to the active pixel.

[0138] The signal generation unit 215 may be configured to include, for example, a column selection circuit that arbitrates signals coming into the signal generation unit 215. The signal generation unit 215 may also be configured to output information not only from active pixels that detect an event, but also from inactive pixels that do not detect an event.

[0139] The signal generating unit 215 outputs address information and timestamp information (e.g., (X, Y, T)) of the active pixel in which an event is detected through an output line 218. However, the data output from the signal generating unit 215 may be not only address information and timestamp information but also frame format information (e.g., (0, 0, 1, 0, . . .)).

[0140] [Column processing unit configuration example] 11 illustrates an example of a configuration in which analog-to-digital converters (ADCs) each consisting of a comparator 21, a counter 23, and a memory 27 are arranged in one-to-one correspondence with the pixel columns of the pixel array section 2 within the column processing section 4, but the present invention is not limited to this example of a configuration. For example, an analog-to-digital converter (ADC) may be arranged for each of a plurality of pixel columns, and the analog-to-digital converter (ADC) may be used in a time-division manner among the plurality of pixel columns.

[0141] The analog-to-digital converter (ADC) converts the analog pixel signal SIG supplied via the vertical signal line VSL into a digital signal with a larger number of bits than the aforementioned address event detection signal. For example, if the address event detection signal is 2 bits, the pixel signal is converted into a digital signal with 3 bits or more (e.g., 16 bits). The analog-to-digital converter (ADC) supplies the digital signal generated by the analog-to-digital conversion to the signal processing unit 212.

[0142] [About noise events] The imaging device 1 according to the first configuration example is an asynchronous imaging device 1 in which a detection unit (i.e., an address event detection circuit 300) can be provided in at least some of the pixel circuits 2a, which detects in real time for each pixel address that the light amount of that pixel has exceeded a predetermined threshold as an address event.

[0143] In the asynchronous imaging device 1 according to the first configuration example, when some event (i.e., a true event) occurs in a scene, data resulting from the occurrence of the true event is acquired. However, in the asynchronous imaging device 1, even in a scene in which no true event occurs, data may be acquired unnecessarily due to a noise event (false event) such as sensor noise. This not only results in a noise signal being read out, but also reduces the throughput of signal output.

[0144] <Application Examples of the Technology According to the Present Disclosure> The technology according to the present disclosure can be applied to various products. More specific application examples are described below. For example, the technology according to the present disclosure may be realized as a distance measuring device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0145] [Moving object] 33 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 33, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0146] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various devices to be controlled. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 33 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a storage unit 7690. Similarly, the other control units also include a microcomputer, a communication I / F, a storage unit, and the like.

[0147] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a driving force generating device for generating driving force for the vehicle, such as an internal combustion engine or a drive motor, a driving force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0148] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0149] Body system control unit 7200 controls the operation of various devices mounted on the vehicle body in accordance with various programs. For example, body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 7200. Body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0150] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like provided in the battery device.

[0151] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0152] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0153] 34 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0154] 34 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0155] The vehicle exterior information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, and corners of the vehicle 7900 and above the windshield inside the vehicle cabin may be, for example, ultrasonic sensors or radar devices. The vehicle exterior information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These vehicle exterior information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0156] Returning to FIG. 33 , the explanation will be continued. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. The outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, text on the road, etc. based on the received information. The outside-vehicle information detection unit 7400 may also perform environment recognition processing for recognizing rainfall, fog, road conditions, etc. based on the received information. The outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle based on the received information.

[0157] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, characters on the road, etc., based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0158] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the state of the driver is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing, based on the detection information input from the driver state detection unit 7510. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0159] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 in accordance with various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information by gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger or the like using the input unit 7800 and outputs the input signal to the integrated control unit 7600. By operating this input unit 7800, passengers and the like input various data to the vehicle control system 7000 and instruct processing operations.

[0160] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0161] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication between various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX, LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to devices (e.g., application servers or control servers) present on an external network (e.g., the Internet, a cloud network, or a carrier-specific network) via, for example, a base station or an access point. The general-purpose communication I / F 7620 may also connect to terminals present near the vehicle (e.g., terminals of drivers, pedestrians, or stores, or machine-type communication (MTC) terminals) using, for example, P2P (Peer to Peer) technology.

[0162] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE802.11p and an upper layer IEEE1609, a dedicated short range communications (DSRC), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0163] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0164] The beacon receiver 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiver 7650 may be included in the dedicated communication I / F 7630 described above.

[0165] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). The in-vehicle device I / F 7660 may also establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried or installed in the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to a desired destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760 .

[0166] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0167] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0168] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0169] The audio / video output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 33 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may be other devices besides these devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals consisting of reproduced audio data or acoustic data into analog signals and audibly outputs the analog signals.

[0170] In the example shown in FIG. 33 , at least two control units connected via the communication network 7010 may be integrated into one control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In addition, in the above description, some or all of the functions performed by one control unit may be assigned to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.

[0171] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging units 7910, 7912, 7914, 7916, and 7918, the outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930, and the driver state detection unit 7510, among the above-described configurations. Specifically, the imaging system 10 shown in FIG. 1 , which includes the imaging device 1 according to the present disclosure, can be applied to these imaging units and detection units. Furthermore, by applying the technology according to the present disclosure, the influence of noise events such as sensor noise can be mitigated, and the occurrence of a true event can be reliably and quickly detected, thereby enabling safe vehicle driving.

[0172] The present technology can be configured as follows: (1) An imaging device having a plurality of stacked substrates, a read-only circuit that is disposed on a substrate different from a substrate on which a pixel array unit having a plurality of photoelectric conversion elements is disposed, and that reads out an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements; a circuit that is arranged on a substrate different from the substrate on which the read-only circuit is arranged, and that performs an operation other than the operation of the read-only circuit based on the electrical signal. (2) the read-only circuit is a circuit that converts the electrical signal photoelectrically converted by the photoelectric conversion element into a voltage signal and performs gain adjustment; The imaging device described in (1), wherein the substrate on which a circuit that performs operations other than the operation of the read-only circuit is arranged performs at least one of the following: converting a voltage signal output from the read-only circuit into a digital signal in units of two or more pixel groups arranged in a first direction of the pixel array section; performing predetermined signal processing on the digital signal; and driving the multiple photoelectric conversion elements in units of two or more pixel groups arranged in a second direction. (3) An imaging device described in (1) or (2), in which, among the circuits that perform operations other than the operation of the read-only circuit, the circuit portion whose power supply voltage exceeds a predetermined reference voltage is arranged on the same substrate as the plurality of photoelectric conversion elements. (4) The imaging device according to (3), further comprising at least a part of an AD section arranged on a substrate on which the pixel array section is arranged, for digitally converting pixel signals read out from the read-only circuit. (5) The imaging device described in (4), wherein the AD unit digitally converts pixel signals read out from the read-only circuit in units of two or more pixel groups arranged in the first direction of the pixel array unit. (6) The imaging device according to (4) or (5), wherein the AD section is arranged separately on a substrate on which the pixel array section is arranged and on another substrate. (7) An imaging device described in any one of (4) to (6), further comprising a pixel group driving unit arranged on a substrate on which the pixel array unit is arranged, which drives the pixel array unit in units of two or more pixel groups arranged in a second direction. (8) The imaging device according to (7), wherein the pixel group driving section is arranged separately on a substrate on which the pixel array section is arranged and on another substrate. (9) a first substrate on which the read-only circuit is disposed; a second substrate stacked on the first substrate and on which the pixel array unit is disposed; An imaging device described in any one of (1) to (8), comprising: a third substrate stacked on the first substrate at the same layer height as the second substrate, and on which at least a portion of a circuit that performs operations other than the operation of the read-only circuit is arranged. (10) The first substrate is larger than the second substrate; The imaging device according to (9), wherein the second substrate is larger than the third substrate. (11) a first substrate on which the read-only circuit is disposed; a second substrate stacked on the first substrate and on which the pixel array unit is disposed; An imaging device described in any one of (1) to (8), comprising: a third substrate stacked below the first substrate and on which at least a portion of a circuit that performs operations other than the operation of the read-only circuit is arranged. (12) A fourth substrate is provided which is disposed at the same layer height as the third substrate, The imaging device according to (11), wherein a part of a circuit that performs an operation other than the operation of the read-only circuit is disposed on each of the third substrate and the fourth substrate. (13) The imaging device according to (12), wherein the second substrate is larger than the third substrate and the fourth substrate. (14) An imaging device described in any one of (9) to (13), wherein the read-only circuit is arranged on one substrate so as to overlap at least a portion of the pixel array section when the first substrate and the second substrate are viewed in a plane from the stacking direction. (15) The imaging device according to any one of (9) to (14), wherein the read-only circuits are provided one for each of the plurality of photoelectric conversion elements. (16) The imaging device according to any one of (9) to (14), wherein the read-only circuits are provided in association with two or more of the photoelectric conversion elements. (17) An imaging device described in any one of (1) to (16), wherein the pixel array unit and the read-only circuit have a change amount detection unit that outputs a detection signal indicating whether the change amount of the electrical signal of each of the multiple photoelectric conversion elements exceeds a predetermined threshold. (18) An imaging device described in any one of (1) to (16), wherein the pixel array section and the read-only circuit have a pixel AD section that converts the electrical signals photoelectrically converted by each of the photoelectric conversion elements into digital signals. (19) An imaging device described in any one of (1) to (16), wherein the pixel array section and the read-only circuit have a light detection section that detects the incident position and incident time of light incident on the multiple photoelectric conversion elements. (20) a first output unit that outputs a first signal from the pixel array unit; The imaging device according to any one of (1) to (19), further comprising: a second output section that outputs a second signal from the read-only circuit. (21) The imaging device according to any one of (1) to (20), wherein the plurality of substrates are bonded together by at least one of Cu-Cu bonding, TSV (Through Silicon Via), and bump bonding. (22) The imaging device according to any one of (1) to (21), wherein the substrate is a wafer or a semiconductor chip. (23) An imaging method using a plurality of stacked substrates, a step of reading out an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements in a read-only circuit disposed on a substrate different from a substrate on which a pixel array unit having the plurality of photoelectric conversion elements is disposed; and performing an operation other than the operation of the read-only circuit based on the electrical signal in a circuit disposed on a substrate different from the substrate on which the read-only circuit is disposed.

[0173] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0174] 1 imaging device, 2 pixel array section, 3 row driver section, 4 column processing section, 5 pixel AFE section, 6 column driver section, 7 signal processing section, 8 system control section, 9 signal processing section, 11 first substrate, 12 second substrate, 21 comparator, 23 up / down counter, 24 memory, 25 address selection logic section, 26 decoder, 27 memory, 28 level shifter, 29 driver, 300 address event detection circuit, 31 photoelectric conversion element, 32 transfer transistor, 33 reset transistor, 36 amplification transistor, 37 selection transistor, 210 imaging device, 211 pixel array section, 212 signal processing section, 213 driver section, 214 readout area selection section, 215 signal generation section, 310 current-voltage conversion circuit, 320 buffer, 330 subtractor, 340 quantizer, 350 transfer circuit, 400 address event detection section, 410 Current-voltage conversion unit, 420 buffer, 430 subtractor, 431, 433 capacitor, 432 inverter, 434 switch, 440 quantizer, 441 comparator, 450 transfer unit, 12031 imaging unit

Claims

1. An imaging device including a plurality of stacked substrates, a first circuit that is disposed on a substrate different from a substrate on which a pixel array unit having a plurality of photoelectric conversion elements is disposed, and that performs a readout operation of an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements; a second circuit that is disposed on a substrate different from the substrate on which the first circuit is disposed, and that performs an operation other than the operation of the first circuit based on the electrical signal; the first circuit includes a change amount detection unit that outputs a detection signal indicating whether or not a change amount of the electrical signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold; The second circuit performs predetermined signal processing on the detection signal.

2. An imaging device including a plurality of stacked substrates, a first circuit that is disposed on a substrate different from a substrate on which a pixel array unit having a plurality of photoelectric conversion elements is disposed, and that performs a readout operation of an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements; a second circuit that is disposed on a substrate different from the substrate on which the first circuit is disposed, and that performs an operation other than the operation of the first circuit based on the electrical signal; the first circuit has a plurality of pixel AD units that convert the electrical signals photoelectrically converted by the individual photoelectric conversion elements into digital signals; The second circuit performs predetermined signal processing on the digital signals output from the pixel AD units.

3. An imaging device including a plurality of stacked substrates, a first circuit that is disposed on a substrate different from a substrate on which a pixel array unit having a plurality of photoelectric conversion elements is disposed, and that performs a readout operation of an electrical signal photoelectrically converted by the plurality of photoelectric conversion elements; a second circuit that is disposed on a substrate different from the substrate on which the first circuit is disposed, and that performs an operation other than the operation of the first circuit based on the electrical signal; the first circuit has a light detection unit that detects an incident position and an incident time of light incident on the plurality of photoelectric conversion elements, The second circuit performs predetermined signal processing on the detection signal output from the light detection unit.

4. 4. The imaging device according to claim 1, wherein a circuit portion of a second circuit that performs an operation other than that of the first circuit, and whose power supply voltage exceeds a predetermined reference voltage, is arranged on the same substrate as the plurality of photoelectric conversion elements.

5. The imaging device according to claim 4 , further comprising: at least a part of an AD section that is arranged on a substrate on which the pixel array section is arranged and that digitally converts pixel signals read out from the first circuit.

6. The imaging device according to claim 5 , wherein the AD unit converts pixel signals read out from the first circuit into digital signals in units of two or more pixel groups arranged in the first direction of the pixel array unit.

7. The imaging device according to claim 5 , wherein the AD section is arranged separately on a substrate on which the pixel array section is arranged and on another substrate.

8. 8. The imaging device according to claim 5, further comprising: a pixel group driving section that is arranged on a substrate on which the pixel array section is arranged, and that drives the pixel array section in units of two or more pixel groups arranged in a second direction.

9. The imaging device according to claim 8 , wherein the pixel group driving section is arranged separately on a substrate on which the pixel array section is arranged and on another substrate.

10. a first substrate on which the first circuit is disposed; a second substrate stacked on the first substrate and on which the pixel array unit is disposed; 10. The imaging device according to claim 1, further comprising: a third substrate that is stacked on the first substrate at the same layer height as the second substrate, and on which at least a portion of a second circuit that performs an operation other than an operation of the first circuit is arranged.

11. the first substrate is larger than the second substrate; The imaging device of claim 10 , wherein the second substrate is larger than the third substrate.

12. a first substrate on which the first circuit is disposed; a second substrate stacked on the first substrate and on which the pixel array unit is disposed; 10. The imaging device according to claim 1, further comprising: a third substrate stacked below the first substrate and on which at least a portion of a second circuit that performs an operation other than that of the first circuit is disposed.

13. a fourth substrate disposed at the same layer height as the third substrate; The imaging device according to claim 12 , wherein a part of a second circuit that performs an operation other than that of the first circuit is disposed on each of the third substrate and the fourth substrate.

14. The imaging device of claim 13 , wherein the second substrate is larger than the third substrate and the fourth substrate.

15. 15. The imaging device according to claim 10, wherein the first circuit is arranged on the first substrate so as to overlap at least a portion of the pixel array section when the first substrate and the second substrate are viewed in a plan view from a stacking direction.

16. The imaging device according to claim 10 , wherein the first circuit is provided for each of the plurality of photoelectric conversion elements.

17. The imaging device according to claim 10 , wherein the first circuits are provided in association with two or more of the photoelectric conversion elements.

18. a first output unit that outputs a first signal from the pixel array unit; The imaging device according to claim 1 , further comprising: a second output section that outputs a second signal from the first circuit.

19. 19. The imaging device according to claim 1, wherein the plurality of substrates are bonded together by at least one of Cu-Cu bonding, TSV (Through Silicon Via), and bump bonding.

20. The imaging device according to claim 1 , wherein the substrate is a wafer or a semiconductor chip.

21. An imaging method comprising stacking a plurality of substrates, performing a readout operation of electrical signals photoelectrically converted by the plurality of photoelectric conversion elements in a first circuit disposed on a substrate different from a substrate on which a pixel array unit having the plurality of photoelectric conversion elements is disposed; and performing an operation other than the operation of the first circuit based on the electrical signal in a second circuit disposed on a substrate different from the substrate on which the first circuit is disposed; the first circuit includes a change amount detection unit that outputs a detection signal indicating whether or not a change amount of the electrical signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold; The second circuit performs predetermined signal processing on the detection signal.

Images