Imaging device

Abstract

An imaging device according to the present invention comprises: a photoelectric conversion unit which generates electric charge by photoelectric conversion; an electric charge storage unit in which the electric charge is stored; and a metal-oxide-semiconductor capacitor which comprises a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region. During exposure, the first terminal is electrically connected to the electric charge storage unit, the gate is electrically connected to the first terminal, the at least one semiconductor region is electrically connected to the second terminal, and the oxide layer is located between the gate and the at least one semiconductor region.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Image sensors are used in digital cameras, etc. Examples of image sensors include CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors.

[0003] In one example of an image sensor, a photodiode is provided on a semiconductor substrate.

[0004] In another example of an image sensor, a photoelectric conversion layer is provided above a semiconductor substrate. An imaging device having such a structure is sometimes called a stacked imaging device. Patent Documents 1 and 2 describe stacked imaging devices.

[0005] In a stacked-type imaging device according to a specific example, signal charges are generated by photoelectric conversion. The generated charges are accumulated in a charge accumulation section. A signal corresponding to the amount of charge accumulated in the charge accumulation section is read out via a CCD circuit or a CMOS circuit formed on a semiconductor substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-171439 [Patent Document 2] Japanese Patent Application Publication No. 2018-117347 Summary of the Invention [Problem to be solved by the invention]

[0007] The present disclosure provides a technique suitable for realizing a wide dynamic range while ensuring a good signal-to-noise (S / N) ratio at intermediate illumination levels. [Means for solving the problem]

[0008] The present disclosure provides: a photoelectric conversion unit that generates charges by photoelectric conversion; a charge storage section in which the charge is stored; a metal-oxide-semiconductor capacitor including a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region; During exposure, the first terminal is electrically connected to the charge accumulation unit; the gate is electrically connected to the first terminal; the at least one semiconductor region is electrically connected to the second terminal; The oxide layer is located between the gate and the at least one semiconductor region, providing an imager. [Effects of the Invention]

[0009] The technology according to the present disclosure is suitable for achieving a wide dynamic range while ensuring a good S / N ratio at intermediate illuminance levels. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram showing the circuit configuration of the imaging device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Figure 3] FIG. 3 is a configuration diagram of a photoelectric conversion unit according to the first embodiment. [Figure 4] FIG. 4 is a graph showing the relationship between the capacitance value and the inter-terminal voltage of the MOS capacitor according to the first embodiment. [Figure 5] FIG. 5 is a graph showing the relationship between the S / N ratio and the illuminance. [Figure 6]FIG. 6 is a graph showing the relationship between the capacitance value and the inter-terminal voltage of the MOS capacitor according to the second embodiment. [Figure 7] FIG. 7 is a circuit diagram of a pixel according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Summary of one aspect of the present disclosure) An imaging device according to a first aspect of the present disclosure includes: a photoelectric conversion unit that generates charges by photoelectric conversion; a charge storage section in which the charge is stored; a metal-oxide-semiconductor capacitor including a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region, wherein during exposure, the first terminal is electrically connected to the charge storage portion; the gate is electrically connected to the first terminal; the at least one semiconductor region is electrically connected to the second terminal; The oxide layer is located between the gate and the at least one semiconductor region.

[0012] The technology according to the first aspect is suitable for realizing a wide dynamic range while ensuring an S / N ratio at intermediate illuminance levels.

[0013] In a second aspect of the present disclosure, for example, in the imaging device according to the first aspect, The capacitance value of the MOS capacitor may be continuously changed according to the potential of the charge storage section.

[0014] The technology according to the second aspect is suitable for realizing a wide dynamic range while ensuring an S / N ratio at intermediate illuminance levels.

[0015] In a third aspect of the present disclosure, for example, in the imaging device according to the first or second aspect, a CV characteristic defined as a relationship between a terminal voltage, which is a voltage between the first terminal and the second terminal, and a capacitance value of the MOS capacitor may have an inflection point; When the potential of the charge storage section changes continuously, the inter-terminal voltage and the capacitance value may change continuously across the inflection point.

[0016] According to the third aspect, it is easy to greatly change the capacitance value of the MOS capacitor in response to a change in the potential of the charge storage section.

[0017] In a fourth aspect of the present disclosure, for example, the imaging device according to the third aspect may further include a setting device that sets a range in which the potential of the charge accumulation unit changes to a range from a first potential to a second potential, The CV characteristics may include a first band having the inflection point, When the potential of the charge storage section changes from the first potential to the second potential, the terminal-to-terminal voltage and the capacitance value may change from the terminal-to-terminal voltage and the capacitance value at one end of the first band to the terminal-to-terminal voltage and the capacitance value at the other end of the first band.

[0018] The fourth aspect is an example of the configuration of an imaging device.

[0019] In a fifth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fourth aspects, A first DC potential may be applied to the second terminal such that the capacitance value of the MOS capacitor changes continuously according to a terminal-to-terminal voltage, which is a voltage between the first terminal and the second terminal.

[0020] According to the fifth aspect, the imaging device can have a simple structure.

[0021] In a sixth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fifth aspects, The CV characteristic defined as a relationship between a terminal voltage, which is a voltage between the first terminal and the second terminal, and a capacitance value of the MOS capacitor may include a first band and a second band, the capacitance value in the second band is smaller than the capacitance value in the first band, an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the second band may be smaller than an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the first band; The imaging modes of the imaging device may include a first mode and a second mode, In the first mode, a potential may be applied to the second terminal such that the inter-terminal voltage changes within the first band when the potential of the charge storage unit changes; In the second mode, a potential may be applied to the second terminal such that the inter-terminal voltage changes within the second band when the potential of the charge storage unit changes.

[0022] In the second mode of the sixth aspect, it is easy to suppress at least one selected from the noise variation and the signal variation.

[0023] The charge may be a positive charge, and the potential of the second terminal in the second mode may be higher than the potential of the second terminal in the first mode, or the charge may be a negative charge, and the potential of the second terminal in the second mode may be lower than the potential of the second terminal in the first mode.

[0024] In a seventh aspect of the present disclosure, for example, in the imaging device according to any one of the first to sixth aspects, a CV characteristic defined as a relationship between a terminal voltage, which is a voltage between the first terminal and the second terminal, and a capacitance value of the MOS capacitor may have a first band and a third band; the capacitance value in the third band is greater than the capacitance value in the first band, an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the third band may be smaller than an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the first band; The imaging modes of the imaging device may include a first mode and a third mode, In the first mode, a potential may be applied to the second terminal such that the inter-terminal voltage changes within the first band when the potential of the charge storage unit changes; In the third mode, a potential may be applied to the second terminal such that the inter-terminal voltage changes within the third band when the potential of the charge storage unit changes.

[0025] In the third mode of the seventh aspect, it is easy to suppress at least one selected from the noise variation and the signal variation.

[0026] The charge may be a positive charge, and the potential of the second terminal in the third mode may be lower than the potential of the second terminal in the first mode, or the charge may be a negative charge, and the potential of the second terminal in the third mode may be higher than the potential of the second terminal in the first mode.

[0027] In an eighth aspect of the present disclosure, for example, an imaging device according to any one of the first to seventh aspects, The power supply may further include an amplifying transistor that outputs an output signal according to the potential of the charge storage section, The imaging device may switch the potential applied to the second terminal in response to the output signal.

[0028] According to the eighth aspect, the photographing mode can be switched.

[0029] In a ninth aspect of the present disclosure, for example, the imaging device according to any one of the first to eighth aspects may further include a voltage source that applies a potential to the second terminal.

[0030] The ninth aspect is a configuration example of an imaging device.

[0031] In a tenth aspect of the present disclosure, for example, the imaging device according to any one of the first to ninth aspects may further include a semiconductor substrate including the at least one semiconductor region, The photoelectric conversion portion may be located at a position away from the semiconductor substrate.

[0032] According to the configuration of the tenth aspect, the photoelectric conversion unit is less likely to affect the capacitance value of the MOS capacitor, compared to a configuration in which the photoelectric conversion unit is a photodiode provided on a semiconductor substrate.

[0033] An imaging device according to an eleventh aspect of the present disclosure includes: a charge accumulation section in which charges generated by photoelectric conversion are accumulated; a transistor having a source region and a drain region electrically connected to each other, the transistor functioning as a MOS capacitor during exposure including a first terminal electrically connected to the charge storage portion.

[0034] The technique according to the eleventh aspect is suitable for realizing a wide dynamic range while ensuring a good S / N ratio at intermediate illuminance levels. An imaging device according to a twelfth aspect of the present disclosure includes: a charge accumulation section in which charges generated by photoelectric conversion are accumulated; A metal-oxide-semiconductor capacitor including a first terminal electrically connected to the charge storage portion during exposure, an oxide layer, and source / drain regions.

[0035] In the embodiments, terms such as "upper" and "lower" are used merely to specify the relative positions of components, and are not intended to limit the orientation of the imaging device when in use.

[0036] In the embodiment, adjustments of each element due to the difference in the positive and negative polarities of the signal charges, such as changing the conductivity type of the impurity regions, can be made as appropriate. Furthermore, terminology can be replaced as appropriate due to the difference in the positive and negative polarities of the signal charges.

[0037] In the following embodiments, it is possible to use the expression "the charge accumulation unit is electrically connected to element X." Specifically, in the following embodiments, the above expression can be used even when the charge accumulation unit is composed of part or all of element X. Therefore, the above expression should be interpreted as including the case where the charge accumulation unit is composed of part or all of element X. Furthermore, in the following embodiments, it is possible to list the charge accumulation unit and other elements, such as "having / comprising a charge accumulation unit and element X." Specifically, in the following embodiments, such a list can be used even when the charge accumulation unit is composed of part or all of element X. In such a list, it should be acceptable for the charge accumulation unit to be composed of part or all of element X. For example, in the following embodiments, one of the source and drain of the overflow transistor can constitute the charge accumulation unit. One of the source and drain of the reset transistor can constitute the charge accumulation unit. The photoelectric conversion unit can constitute the charge accumulation unit.

[0038] In the following embodiments, the expression "having / comprising a MOS capacitor and a specific transistor" can be used. This expression should be interpreted as including the case where the MOS capacitor is configured using a specific transistor. In other words, this expression should be interpreted as including the case where the MOS capacitor and the specific transistor partially or entirely overlap.

[0039] In the embodiments, ordinal numbers such as 1st, 2nd, 3rd, etc. may be used. When an element is assigned an ordinal number, it is not necessary that an element of the same type with a lower number exists. For example, the term "third mode" is not used with the intention that the second mode always exists along with the third mode. Furthermore, the numbers of ordinal numbers can be changed, or ordinal numbers can be deleted or added as needed.

[0040] A generic or specific aspect may be realized by an element, a device, a module, a system, or a method. Also, a generic or specific aspect may be realized by any combination of an element, a device, a module, a system, and a method.

[0041] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and / or advantages are provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of them.

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, step orders, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components that are not recited in independent claims that represent the highest concept will be described as optional components. In the following description, components having substantially the same functions will be designated by common reference symbols, and their description may be omitted.

[0043] (First embodiment) FIG. 1 is a schematic diagram showing the circuit configuration of an imaging device 1 according to the first embodiment.

[0044] In this embodiment, the imaging device 1 is a stacked solid-state imaging device and includes a plurality of pixels 14, a drive circuit unit, a photoelectric conversion control line 16, a plurality of vertical signal lines 17, a plurality of power supply lines 62, a power supply line 21, a voltage line 75, and a plurality of feedback lines 23.

[0045] The plurality of pixels 14 are arranged two-dimensionally on the semiconductor substrate 9. Specifically, the plurality of pixels 14 are arranged in row and column directions. The plurality of pixels 14 form a photosensitive region. The photosensitive region is also referred to as a pixel region. The imaging device 1 may be a line sensor. In that case, the plurality of pixels 14 may be arranged one-dimensionally.

[0046] The drive circuit section sequentially drives the plurality of pixels 14 and reads out signals obtained by photoelectric conversion. The drive circuit section includes a vertical scanning section 15, a horizontal signal readout section 20, a plurality of column signal processing sections 19, a plurality of load sections 18, and a plurality of differential amplifiers 22. The vertical scanning section 15 is also referred to as a row scanning circuit. The horizontal signal readout section 20 is also referred to as a column scanning circuit. The column signal processing section 19 is also referred to as a row signal storage section. The differential amplifier 22 is also referred to as a feedback amplifier.

[0047] Each pixel 14 includes a photoelectric conversion unit 10, an amplification transistor 11, a reset transistor 12, an address transistor 13, an overflow transistor 60, and a MOS (Metal Oxide Semiconductor) capacitor 70. The address transistor 13 is also called a row selection transistor. The overflow transistor 60 is also called a burn-in prevention transistor.

[0048] In this embodiment, the transistors 11, 12, 13, and 60 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Specifically, in this embodiment, the transistors 11, 12, 13, and 60 are N-type MOSFETs. However, the transistors 11, 12, 13, and 60 may also be P-type MOSFETs. The transistors 11, 12, 13, and 60 may also be transistors of a type other than MOSFETs, such as bipolar transistors. The same applies to the band control transistor 56 in the third embodiment.

[0049] The power supply wiring 21 is a wiring for a source follower power supply, and supplies a predetermined power supply voltage to each pixel 14.

[0050] A signal line is provided for each row of pixels 14. The pixels 14 in each row are electrically connected to a vertical scanning unit 15 via the corresponding signal line.

[0051] A vertical signal line 17 is provided for each column of pixels 14. The pixels 14 in each column are electrically connected to the corresponding vertical signal line 17.

[0052] A load section 18 is provided for each vertical signal line 17. Each load section 18 is electrically connected to the corresponding vertical signal line 17. The load section 18 cooperates with the amplifying transistor 11 to form a source follower circuit.

[0053] A column signal processing unit 19 is provided for each vertical signal line 17. Each column signal processing unit 19 is electrically connected to the corresponding vertical signal line 17. These column signal processing units 19 are electrically connected to a horizontal signal readout unit 20. These column signal processing units 19 are arranged in the horizontal direction, i.e., the row direction.

[0054] A differential amplifier 22 is provided for each vertical signal line 17. The negative input terminal of the differential amplifier 22 is electrically connected to the corresponding vertical signal line 17. A predetermined potential is applied to the positive input terminal of the differential amplifier 22. The output terminal of the differential amplifier 22 is electrically connected to the pixels 14 via feedback lines 23 corresponding to each column.

[0055] FIG. 2 is a circuit diagram of the pixel 14 according to the first embodiment.

[0056] The photoelectric conversion unit 10 is electrically connected to one of the source and drain of the reset transistor 12, one of the source and drain of the overflow transistor 60, a first terminal Cv of a MOS (Metal Oxide Semiconductor) capacitor 70, and a gate electrode of the amplification transistor 11. One of the source and drain of the amplification transistor 11 is electrically connected to a power supply wiring 21. The other of the source and drain of the amplification transistor 11 is electrically connected to one of the source and drain of the address transistor 13. The other of the source and drain of the address transistor 13 is electrically connected to a vertical signal line 17. The other of the source and drain of the reset transistor 12 is electrically connected to a feedback line 23.

[0057] The photoelectric conversion unit 10 converts light into electric charges. In this way, the photoelectric conversion unit 10 generates electric charges according to the illuminance of the incident light. The electric charges generated by photoelectric conversion in the photoelectric conversion unit 10 in this way are called signal charges.

[0058] In this embodiment, the signal charge is a positive charge, but the signal charge may also be a negative charge.

[0059] FIG. 3 is a configuration diagram of a photoelectric conversion unit 10 according to the first embodiment. The photoelectric conversion unit 10 is provided above a semiconductor substrate 9. The photoelectric conversion unit 10 has a photoelectric conversion layer 10a, a pixel electrode 10b, and a counter electrode 10c. The photoelectric conversion layer 10a is disposed between the pixel electrode 10b and the counter electrode 10c. The photoelectric conversion layer 10a generates electric charges through photoelectric conversion. The pixel electrode 10b collects these electric charges.

[0060] Charges generated by photoelectric conversion are accumulated in the charge accumulation section 24. Specifically, charges generated in the photoelectric conversion section 10 are accumulated in the charge accumulation section 24. The potential of the charge accumulation section 24 changes depending on the amount of charge accumulated in the charge accumulation section 24. In this embodiment, the charge accumulation section 24 is a diffusion region provided in the semiconductor substrate 9.

[0061] In this embodiment, the counter electrodes 10c in the plurality of pixels 14 form a continuous electrode, and the photoelectric conversion layers 10a in the plurality of pixels 14 form a continuous film.

[0062] The MOS capacitor 70 has a first terminal Cv and a second terminal TT. The first terminal Cv is electrically connected to the charge accumulation unit 24. Since the MOS capacitor 70 and the charge accumulation unit 24 are electrically connected, the charge accumulation by the MOS capacitor 70 and the charge accumulation unit 24 can be shared smoothly and without disturbance for each pixel. Specifically, the first terminal Cv and the charge accumulation unit 24 are connected to each other without the intervention of a switch such as a switching element.

[0063] The MOS capacitor 70 is a variable capacitor. Specifically, the capacitance value of the MOS capacitor 70 changes depending on the potential difference between the first terminal Cv and the second terminal TT.

[0064] The imaging device 1 includes a voltage source 77. The voltage source 77 applies a potential to the second terminal TT. Specifically, the voltage source 77 applies the potential to the second terminal TT via a voltage line 75. The voltage source 77 can be included in a drive circuit unit.

[0065] During exposure, the photoelectric conversion unit 10, the charge accumulation unit 24, and the first terminal Cv are electrically connected. In this configuration, there is no need to place a transistor between them. This is advantageous from the viewpoint of suppressing variations in output characteristics among the pixels 14. Note that, in the case where the photoelectric conversion unit 10 has a photoelectric conversion layer 10a, a pixel electrode 10b, and a counter electrode 10c, "exposure" can be achieved by applying a voltage to the counter electrode 10c.

[0066] The MOS capacitor 70 is provided on the semiconductor substrate 9. The photoelectric conversion unit 10 is located at a distance from the semiconductor substrate 9. According to this configuration, the photoelectric conversion unit 10 is less likely to affect the capacitance value of the MOS capacitor 70 than in a configuration in which the photoelectric conversion unit 10 is a photodiode provided on the semiconductor substrate 9.

[0067] The amplifier transistor 11 outputs an output signal according to the potential of the charge storage section 24. Specifically, the output signal is a signal voltage.

[0068] The address transistor 13 selectively outputs the output signal from the amplifier transistor 11. In this way, the output signal is read out from the amplifier transistor 11 to the vertical signal line 17 via the address transistor 13.

[0069] The reset transistor 12 resets the potential of the charge storage section 24. In other words, the reset transistor 12 resets the signal charge stored in the charge storage section 24.

[0070] The overflow transistor 60 is turned on when the potential of the charge storage unit 24 reaches a threshold potential. When the overflow transistor 60 is turned on, excess charge stored in the charge storage unit 24 is released to the power supply wiring 62 via the overflow transistor 60. This prevents malfunctions such as burn-in. The threshold potential is, for example, the power supply potential VDD.

[0071] As can be understood from the above description, this embodiment is configured to include a setter 65. The setter 65 sets the range in which the potential of the charge accumulation section 24 changes to a range from a first potential to a second potential.

[0072] The setter 65 may include the reset transistor 12. In this case, the reset transistor 12 may reset the potential of the charge storage unit 24 to the first potential.

[0073] The setter 65 may include an overflow transistor 60. In this case, the overflow transistor 60 may discharge the charge stored in the charge storage unit 24 when the potential of the charge storage unit 24 reaches the second potential.

[0074] The setting unit 65 may include the photoelectric conversion unit 10. In this case, a second potential may be applied to the counter electrode 10c.

[0075] The difference between the first potential and the second potential is, for example, 0 V or more and 6 V or less, and in one specific example, 0.5 V or more and 4 V or less. Typically, the absolute value of the first potential is smaller than the absolute value of the second potential. When the signal charge is a positive charge, the second potential can be a potential higher than the first potential. In this case, for example, the first potential is 0 V or more and 1 V or less, and the second potential is 3 V or more and 6 V or less. When the signal charge is a negative charge, the overflow transistor 60 can be omitted.

[0076] In this embodiment, the charge storage unit 24 is either the source or the drain of the reset transistor 12. The charge storage unit 24 is also either the source or the drain of the overflow transistor 60. In other words, the charge storage unit 24 has the function of storing signal charge, the function of serving as either the source or the drain of the reset transistor 12, and the function of serving as either the source or the drain of the overflow transistor 60.

[0077] The operation of the imaging device 1 will now be described.

[0078] The vertical scanning unit 15 applies a row selection signal to the gate electrode of the address transistor 13. The row selection signal controls the on / off of the address transistor 13. The row selection signal scans the row to be read out in the vertical direction, i.e., the column direction, and selects the row to be read out. Output signals are read out to vertical signal lines 17 from the pixels 14 in the selected row.

[0079] The vertical scanning unit 15 applies a reset signal to the gate electrode of the reset transistor 12. The reset signal controls the on / off of the reset transistor 12. The reset signal selects a row of pixels 14 that is to be subjected to the reset operation.

[0080] The photoelectric conversion control line 16 is electrically connected to all of the pixels 14. The same constant voltage is applied to all of the photoelectric conversion units 10 in the imaging device 1 by the photoelectric conversion control line 16. As described above, in this embodiment, the counter electrodes 10c of multiple pixels form a continuous electrode. A constant voltage is applied to this continuous electrode by the photoelectric conversion control line 16. In this embodiment, this constant voltage is a positive constant voltage.

[0081] As described above, the vertical signal line 17 is electrically connected to the other of the source and drain of the address transistor 13 in the pixels 14 in the corresponding column. The vertical signal line 17 transmits the output signal read out from the pixels 14 in the column direction, i.e., the vertical direction.

[0082] The column signal processing unit 19 performs noise suppression signal processing, analog-to-digital conversion (AD conversion), etc. The noise suppression signal processing is, for example, correlated double sampling.

[0083] The horizontal signal readout section 20 sequentially reads out signals from the plurality of column signal processing sections 19 to a horizontal common signal line (not shown).

[0084] The power supply wiring 21 is wired in the vertical direction of the pixels 14 in the photosensitive region. The vertical direction is the vertical direction on the plane of the paper in FIG. 1. The reason for the vertical wiring is as follows: the pixels 14 are selected row by row. Therefore, if the power supply wiring 21 were wired in the row direction, all of the pixel drive current for one row would flow through a single wiring, resulting in a large voltage drop. Wiring in the vertical direction can avoid this situation. A common source follower power supply voltage is applied to the amplification transistors 11 of all of the pixels 14 by the power supply wiring 21.

[0085] When the address transistor 13 and the reset transistor 12 are in a conductive state, the output signal of the address transistor 13 is supplied to the negative input terminal of the differential amplifier 22. The differential amplifier 22 performs a feedback operation so that the gate potential of the amplifying transistor 11 becomes a predetermined feedback voltage. The feedback voltage is the output voltage of the differential amplifier 22. In this embodiment, the output voltage of the differential amplifier 22 is a positive voltage.

[0086] In the imaging device 1, one row of pixels 14 is selected by a vertical scanning unit 15. Signal charges photoelectrically converted by the photoelectric conversion units 10 in the selected pixels 14 are amplified by the amplification transistors 11. Output signals corresponding to the signal charges are output from the amplification transistors 11 to vertical signal lines 17 via address transistors 13. The output signals are then input to a horizontal signal readout unit 20 via a column signal processing unit 19, and are selected and output by the horizontal signal readout unit 20.

[0087] The signal charge in the pixel 14 is discharged by turning on the reset transistor 12. At this time, thermal noise called kTC noise is generated from the reset transistor 12. This thermal noise remains even when the reset transistor 12 is turned off and the charge storage unit 24 starts storing the signal charge.

[0088] This thermal noise is suppressed as follows. Specifically, the vertical signal line 17 is electrically connected to the negative input terminal of a differential amplifier 22. The voltage of the vertical signal line 17, i.e., the input voltage to the negative input terminal, is inverted and amplified by the differential amplifier 22. The inverted and amplified voltage is fed back to the other of the source and drain of the reset transistor 12 via a feedback line 23. This makes it possible to suppress the thermal noise generated in the reset transistor 12 by negative feedback control. Specifically, the AC component of the thermal noise can be fed back to the other of the source and drain of the reset transistor 12. In this embodiment, the DC component is between 0 V and 1 V, as described above.

[0089] The following describes the MOS capacitor 70. Fig. 4 is a graph showing the relationship between the capacitance value and the inter-terminal voltage of the MOS capacitor 70 according to the first embodiment.

[0090] In FIG. 4, the horizontal axis represents the terminal voltage of the MOS capacitor 70. More specifically, the terminal voltage is the difference between the potential of the first terminal Cv and the potential of the second terminal TT. The horizontal axis is in volts (V). The vertical axis represents the capacitance value of the MOS capacitor 70. The vertical axis is in arbitrary units (au). These points also apply to FIG. 6, which will be described later.

[0091] Hereinafter, the voltage between the terminals of the MOS capacitor 70 may be referred to as the Cv-TT voltage. The capacitance value of the MOS capacitor 70 may be referred to as the capacitance value C. The relationship of the capacitance value C with respect to the Cv-TT voltage may be referred to as the CV characteristic. As can be seen from FIG. 4, the capacitance value C can change depending on the Cv-TT voltage. In this embodiment, the MOS capacitor 70 is a variable capacitance due to such a CV characteristic.

[0092] In this embodiment, the capacitance value C changes continuously according to the Cv-TT voltage. Specifically, when the Cv-TT voltage changes continuously, the capacitance value C changes continuously. These characteristics are suitable for achieving a wide dynamic range while maintaining an S / N ratio at intermediate illuminance. In this context, intermediate illuminance means illuminance that is greater than the minimum illuminance at which the image capture device 1 exhibits sensitivity and lower than the maximum illuminance at which the image capture device 1 exhibits sensitivity. The reason why such an advantage is obtained will be explained below.

[0093] FIG. 5 is a graph showing the relationship between illuminance and S / N ratio. In FIG. 5, the horizontal axis represents illuminance. The horizontal axis is measured in lux. The vertical axis represents S / N ratio. The solid line represents the relationship between illuminance and S / N ratio for the imaging device 1 of this embodiment. The dotted line represents the relationship between illuminance and S / N ratio for a conventional one-pixel-two-cell imaging device. An example of a one-pixel-two-cell imaging device is described in Patent Document 2.

[0094] In the 1-pixel, 2-cell system, a first imaging cell and a second imaging cell are configured within one pixel. The first imaging cell is used when the illuminance is low and has high sensitivity and low saturation. The second imaging cell is used when the illuminance is high and has low sensitivity and high saturation. The 1-pixel, 2-cell system achieves a wide dynamic range using the first imaging cell and the second imaging cell. However, the 1-pixel, 2-cell system has a problem in that the S / N ratio is low under intermediate illuminance, which can easily degrade image quality. Specifically, in the 1-pixel, 2-cell system, data based on a signal from the first imaging cell for low illuminance and data based on a signal from the second imaging cell for high illuminance are joined by software at an illuminance corresponding to the intermediate illuminance. At the intermediate illuminance where this joining portion is formed, the S / N ratio for the signal from the first imaging cell is high, while the S / N ratio for the signal from the second imaging cell is low. As can be seen from Figure 5, the S / N ratio drops sharply at intermediate illuminance.

[0095] In contrast, in this embodiment, the capacitance value C can be increased continuously with increasing illuminance, which makes it possible to realize a wide dynamic range while achieving a "seamless" S / N ratio without a sudden drop in the S / N ratio at intermediate illuminance levels.

[0096] The advantage of this embodiment can be explained from another perspective.

[0097] In a typical stacked imaging device, the charge stored in the charge storage unit cannot be completely transferred. For this reason, a configuration that performs noise cancellation using a feedback loop is sometimes adopted. Reducing the capacitance value of the charge storage unit makes it easier to ensure noise cancellation efficiency. Furthermore, reducing the capacitance value of the charge storage unit makes it easier to ensure conversion gain. A configuration with a small capacitance value of the charge storage unit is suitable for imaging in dark scenes. On the other hand, increasing the capacitance value of the charge storage unit can make the change in the potential of the charge storage unit relative to changes in the amount of signal charge stored in the charge storage unit more gradual. This means that the imaging device is highly saturated. A configuration with a large capacitance value of the charge storage unit is suitable for imaging in bright scenes. It can also be said that a configuration with a large capacitance value of the charge storage unit makes it possible to achieve a wide dynamic range. As such, there are advantages and disadvantages to both a configuration with a small capacitance value of the charge storage unit and a configuration with a large capacitance value of the charge storage unit.

[0098] In contrast, in this embodiment, the capacitance value C of the MOS capacitor 70 can be reduced when performing a feedback operation. When capturing an image in a dark scene, the conversion gain can be ensured by reducing the capacitance value C. On the other hand, when capturing an image in a bright scene, the saturation level of the image capturing device 1 can be increased by increasing the capacitance value C. According to this embodiment, an image capturing device 1 having both of these advantages can be realized. Specifically, by continuously changing the capacitance value C of the MOS capacitor 70, a wide dynamic range can be achieved while suppressing the effects of noise.

[0099] In this embodiment, the capacitance value C continuously changes according to the potential of the charge accumulation unit 24. Specifically, when the potential of the charge accumulation unit 24 continuously changes, the capacitance value C continuously changes. These characteristics are suitable for realizing a wide dynamic range while ensuring an S / N ratio at intermediate illuminance.

[0100] Specifically, a potential is applied to the second terminal TT so that the capacitance value C changes continuously according to the potential of the charge accumulation unit 24. Also, specifically, a potential is applied to the second terminal TT so that the capacitance value C changes continuously when the potential of the charge accumulation unit 24 changes continuously.

[0101] In this embodiment, the CV characteristics of the MOS capacitor 70 have an inflection point IP. When the potential of the charge storage unit 24 changes continuously, the Cv-TT voltage and the capacitance value C change continuously across the inflection point IP. This configuration makes it easy to significantly change the capacitance value C of the MOS capacitor 70 in response to changes in the potential of the charge storage unit 24. Specifically, a potential is applied to the second terminal TT so that when the potential of the charge storage unit 24 changes continuously, the Cv-TT voltage and the capacitance value C change continuously across the inflection point IP. In this context, the inflection point IP is the point at which the sign of the value obtained by second-order differentiation of the capacitance value C with respect to the Cv-TT voltage changes.

[0102] In this embodiment, the CV characteristic of the MOS capacitor 70 has a first band B1. The first band B1 has an inflection point IP. When the potential of the charge storage unit 24 changes from a first potential to a second potential, the Cv-TT voltage and the capacitance value C change from one end value to the other end value of the first band B1. Specifically, a potential is applied to the second terminal TT so that when the potential of the charge storage unit 24 changes from the first potential to the second potential, the Cv-TT voltage and the capacitance value C change from one end value to the other end value of the first band B1.

[0103] In this embodiment, a first DC potential is applied to the second terminal TT so that the capacitance value C changes continuously in response to the voltage between Cv and TT. This configuration is simple. The first DC potential is, for example, between 0 V and 2 V. Specifically, the first DC potential is applied to the second terminal TT so that the capacitance value C changes continuously as the potential of the charge storage unit 24 changes continuously.

[0104] In the first band B1 according to the example shown in FIG. 4, the capacitance value C changes continuously and monotonically as the Cv-TT voltage increases. Here, "monotonically changing" means that the capacitance value C always increases or always decreases. The first band B1 may be referred to as a variable capacitance band. Specifically, in the first band B1 according to this embodiment, the capacitance value C increases continuously and monotonically as the Cv-TT voltage increases.

[0105] In the specific example shown in Figure 4, the first potential is 1 V. The second potential is 3 V. The potential applied to the second terminal TT is 0 V. The variable capacitance band is a band in which the voltage between Cv and TT is equal to or greater than 1 V and less than 3 V.

[0106] In this embodiment, the imaging device 1 includes a specific transistor 80. The specific transistor 80 is typically a MOSFET including a gate, an oxide layer, and at least one semiconductor region. The MOS capacitor 70 is configured using the specific transistor 80. The source region and drain region of the specific transistor 80 are electrically connected to each other. Electrically connecting the source region and drain region of the specific transistor 80 is suitable for achieving the CV characteristics of the MOS capacitor 70 shown in FIG. 4. The source region and drain region of the specific transistor 80 can be electrically connected by wiring or the like. Instead of the source region and drain region, the specific transistor 80 may include a source / drain region that is a single semiconductor region in which the source region and drain region are integrated.

[0107] In this embodiment, one of the first terminal Cv and the second terminal TT is electrically connected to the source and drain of the specific transistor 80. The other of the first terminal Cv and the second terminal TT is electrically connected to the gate electrode of the specific transistor 80. In the example of FIGS. 1 and 2, the second terminal TT is electrically connected to the source and drain of the specific transistor 80. The first terminal Cv is electrically connected to the gate electrode of the specific transistor 80. The specific transistor 80 can be provided on a semiconductor substrate 9.

[0108] In this embodiment, the imaging mode of the imaging device 1 includes a first mode. In the first mode, the capacitance value C of the MOS capacitor 70 changes continuously as the potential of the charge accumulation unit 24 changes continuously. Specifically, in the first mode, a potential is applied to the second terminal TT so that the capacitance value C of the MOS capacitor 70 changes continuously as the potential of the charge accumulation unit 24 changes continuously.

[0109] Several other embodiments will be described below. In the following, elements common to the embodiments already described and the embodiments to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applicable unless technically inconsistent. The respective embodiments may be combined with each other unless technically inconsistent.

[0110] (Second embodiment) 1 and 2 can be used in the second embodiment, as in the first embodiment. In the second embodiment, the imaging device 1 has a first mode, a second mode, and a third mode as shooting modes.

[0111] 6 is a graph showing the relationship between the capacitance value and the inter-terminal voltage of the MOS capacitor 70 according to the second embodiment. The CV characteristics include a first band B1, a second band B2, and a third band B3.

[0112] 6, the second band B2 is a band where the Cv-TT voltage is lower than the first band B1, and the third band B3 is a band where the Cv-TT voltage is higher than the first band B1.

[0113] In the example of Figure 6, the second band B2 is connected to the first band B1. The third band B3 is connected to the first band B1. However, the second band B2 may be separated from the first band B1. The third band B3 may be separated from the first band B1.

[0114] In the first mode, a potential is applied to the second terminal TT so that the Cv-TT voltage changes within a first band B1 when the potential of the charge storage unit 24 changes. In the second mode, a potential is applied to the second terminal TT so that the Cv-TT voltage changes within a second band B2 when the potential of the charge storage unit 24 changes. In the third mode, a potential is applied to the second terminal TT so that the Cv-TT voltage changes within a third band B3 when the potential of the charge storage unit 24 changes.

[0115] In the second band B2, the capacitance C is smaller than in the first band B1. Furthermore, in the second band B2, the absolute value of the ratio of the change in capacitance C to the change in Cv-TT voltage is smaller than in the first band B1. Therefore, in the second mode, it is easy to perform high-sensitivity, low-saturation imaging while suppressing at least one selected from noise variation and signal variation. Specifically, the ratio of the change in capacitance C to the change in Cv-TT voltage is the value obtained by differentiating the capacitance C with respect to the Cv-TT voltage.

[0116] In the third band B3, the capacitance C is larger than in the first band B1. Furthermore, in the third band B3, the absolute value of the ratio of the change in capacitance C to the change in the Cv-TT voltage is smaller than in the first band B1. Therefore, according to the third mode, it is easy to perform low-sensitivity, highly saturated imaging while suppressing at least one selected from noise variation and signal variation.

[0117] In this embodiment, the charge accumulated in the charge accumulation unit 24 is positive. The potential of the second terminal TT in the second mode is higher than the potential of the second terminal TT in the first mode. The potential of the second terminal TT in the third mode is lower than the potential of the second terminal TT in the first mode.

[0118] In the modified example, the charge stored in the charge storage unit 24 is negative charge. The potential of the second terminal TT in the second mode is lower than the potential of the second terminal TT in the first mode. The potential of the second terminal TT in the third mode is higher than the potential of the second terminal TT in the first mode.

[0119] In the first mode, a first DC potential is applied to the second terminal TT so that the Cv-TT voltage changes within a first band B1 when the potential of the charge storage unit 24 changes. In the second mode, a second DC potential is applied to the second terminal TT so that the Cv-TT voltage changes within a second band B2 when the potential of the charge storage unit 24 changes. In the third mode, a third DC potential is applied to the second terminal TT so that the Cv-TT voltage changes within a third band B3 when the potential of the charge storage unit 24 changes. This configuration is simple.

[0120] In the first band B1 according to the example shown in FIG. 6, the capacitance value C changes continuously and monotonically as the Cv-TT voltage increases. The first band B1 may be referred to as a variable capacitance band. Specifically, in the first band B1 of this embodiment, the capacitance value C increases continuously and monotonically as the Cv-TT voltage increases. Meanwhile, the second band B2 may be referred to as a low capacitance stable band. The third band B3 may be referred to as a high capacitance stable band.

[0121] The Cv-TT voltage corresponding to the first band B1 in the second embodiment is different from the Cv-TT voltage corresponding to the first band B1 in the first embodiment. The Cv-TT voltage corresponding to the first band B1 can be adjusted by adjusting the amount of impurities implanted into the MOS capacitor 70, for example. The same applies to the Cv-TT voltage corresponding to the second band B2 and the Cv-TT voltage corresponding to the third band B3. However, the Cv-TT voltage corresponding to the first band B1 in the second embodiment may be the same as the Cv-TT voltage corresponding to the first band B1 in the first embodiment.

[0122] In the second embodiment, the first DC potential is, for example, 1 V or more and 3 V or less, the second DC potential is, for example, 3 V or more and 5 V or less, and the third DC potential is, for example, 0 V or more and 1 V or less.

[0123] In the specific example shown in FIG. 6, the first potential is 1 V. The second potential is 3 V. In the first mode, the potential applied to the second terminal TT is 2 V. In the second mode, the potential applied to the second terminal TT is 4 V. In the third mode, the potential applied to the second terminal TT is 0 V. The variable capacitance band is a band in which the Cv-TT voltage is equal to or greater than -1 V and less than 1 V. The low capacitance stability band is a band in which the Cv-TT voltage is equal to or greater than -3 V and less than -1 V. The high capacitance stability band is a band in which the Cv-TT voltage is equal to or greater than 1 V and less than 3 V.

[0124] In this embodiment, the imaging device 1 switches the potential applied to the second terminal TT in accordance with the output signal output from the amplifying transistor 11. In this way, the imaging device 1 switches the shooting mode.

[0125] As described with reference to FIG. 6, various potentials can be applied to the second terminal TT of the MOS capacitor 70. Strictly speaking, the CV characteristics change due to the back bias effect of the MOS capacitor 70 depending on the potential applied to the second terminal TT. In a typical example, when the potential applied to the second terminal TT is increased, the CV characteristic curve in FIG. 6 shifts overall to the right. However, by setting the potential applied to the second terminal TT while taking this shift into consideration, it is possible to adjust the capacitance value C of the MOS capacitor 70 to a desired value.

[0126] In one example, the photosensitive region is divided into multiple zones. A common potential applied to the second terminals TT of the MOS capacitors 70 of multiple pixels 14 belonging to one zone and a common potential applied to the second terminals TT of the MOS capacitors 70 of multiple pixels 14 belonging to another zone can be set independently of each other. For example, a first common potential is applied to the second terminals TT of the MOS capacitors 70 of multiple pixels 14 belonging to a first zone. A second common potential is applied to the second terminals TT of the MOS capacitors 70 of multiple pixels 14 belonging to a second zone. A third common potential is applied to the second terminals TT of the MOS capacitors 70 of multiple pixels 14 belonging to a third zone. The first common potential, the second common potential, and the third common potential can be set independently of each other. This configuration allows the use of a specific band of the CV characteristics of the MOS capacitors 70 for each zone to be determined. For example, the imaging device 1 can be operated so that the first band B1 is used in the first zone, the second band B2 is used in the second zone, and the third band B3 is used in the third zone.

[0127] In the above example, the photosensitive region is divided into multiple zones, and a common potential is applied to the second terminals TT of the MOS capacitors 70 of the multiple pixels 14 belonging to each zone. In this way, the sensitivity and saturation level can be adjusted for each zone while avoiding excessively complicated control. However, it is also possible to apply independent potentials to the second terminals TT of the MOS capacitors 70 in each pixel 14.

[0128] (Third embodiment) 7 is a circuit diagram of a pixel 94 according to the third embodiment. The pixel 94 includes an amplifier transistor 11, an address transistor 13, a reset transistor 12, and an overflow transistor 60, as well as a bandwidth control transistor 56, a first capacitance element 51, and a second capacitance element 52.

[0129] The gate electrode of the amplifier transistor 11, the charge storage unit 24, the first terminal Cv of the MOS capacitor 70, the photoelectric conversion unit 10, and one end of the first capacitive element 51 are electrically connected. One of the source and drain of the amplifier transistor 11 is electrically connected to the power supply wiring 21. In this embodiment, the charge storage unit 24 is also one of the source and drain of the reset transistor 12 and one of the source and drain of the overflow transistor 60. The other of the source and drain of the reset transistor 12, one of the source and drain of the band control transistor 56, the other end of the first capacitive element 51, and one end of the second capacitive element 52 are electrically connected. A DC potential is applied to the other end of the second capacitive element 52. The other of the source and drain of the amplifier transistor 11, one of the source and drain of the address transistor 13, and the other of the source and drain of the band control transistor 56 are electrically connected. The other of the source and drain of the address transistor 13 is electrically connected to the vertical signal line 17.

[0130] The band control transistor 56, the first capacitance element 51, and the second capacitance element 52 are used to suppress kTC noise that occurs when the reset transistor 12 is turned off. For details of the technology for suppressing kTC noise, see Patent Document 2, etc.

[0131] The CV characteristics of the MOS capacitor 70 of the third embodiment are similar to those of the MOS capacitor 70 of the second embodiment described with reference to FIG. 6. In the third embodiment, a potential can be applied to the second terminal TT, as in the second embodiment. However, in the circuit configuration of the third embodiment shown in FIG. 7, the MOS capacitor 70 may be used similarly to the first embodiment.

[0132] Various modifications can be applied to the techniques described in the first to third embodiments.

[0133] Some of the elements shown may be omitted, for example, the overflow transistor 60 may be omitted.

[0134] The photoelectric conversion unit 10 may be a photodiode provided on the semiconductor substrate 9. The imaging device 1 may include a transfer transistor.

[0135] Here, the expression "charge accumulation section in which charges generated by photoelectric conversion are accumulated" will be explained. The charge accumulation section 24 described with reference to FIGS. 1, 2, and 7 may correspond to the charge accumulation section according to this expression. Furthermore, in a configuration in which the photoelectric conversion section 10 is a photodiode, the photodiode may accumulate charges generated by photoelectric conversion. Therefore, in this configuration, the photodiode that is the photoelectric conversion section 10 may correspond to the charge accumulation section according to the above expression. The first terminal Cv of the MOS capacitor 70 may be electrically connected to this photodiode.

[0136] The relationship between the capacitance C of the MOS capacitor 70 and the potential of the charge storage unit 24 is defined as the CE characteristic. The expression "the capacitance C changes continuously depending on the potential of the charge storage unit 24" will be explained. This expression means that, in the CE characteristic, the capacitance C of the MOS capacitor 70 changes continuously depending on the potential of the charge storage unit 24 as the photoelectric conversion in the photoelectric conversion unit 10 progresses. This expression is not intended to require that the potential of the photoelectric conversion unit 10 change continuously over time as photoelectric conversion in the photoelectric conversion unit 10 progresses. For example, consider a configuration in which the photoelectric conversion unit 10 and the charge storage unit 24 are connected via a transfer transistor, and when the transfer transistor is turned on, the charge in the photoelectric conversion unit 10 is transferred to the charge storage unit 24, causing the potential of the charge storage unit 24 to change stepwise. Even in this configuration, the characteristic that "the capacitance C of the MOS capacitor 70 changes continuously depending on the potential of the charge storage unit 24" can be realized. The same applies to the characteristic that "the capacitance C of the MOS capacitor 70 changes continuously when the potential of the charge storage unit 24 changes continuously."

[0137] The expression "the capacitance value C changes continuously depending on the potential of the charge accumulation section 24" will be further explained. This expression means that, in at least a part of the CE characteristics, the capacitance value C changes continuously depending on the potential of the charge accumulation section 24. The same applies to the expression "the capacitance value C changes continuously when the potential of the charge accumulation section 24 changes continuously."

[0138] The expression "the capacitance value C changes continuously in response to the Cv-TT voltage" will now be explained. This expression means that the capacitance value C changes continuously in response to the Cv-TT voltage in at least a part of the CV characteristics of the MOS capacitor 70. The same applies to the expression "the capacitance value C changes continuously when the Cv-TT voltage changes continuously." [Industrial Applicability]

[0139] The imaging device of the present disclosure is useful for, for example, an image sensor, a digital camera, etc. The imaging device of the present disclosure can be used for a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc. [Explanation of symbols]

[0140] 1. Imaging device 9. Semiconductor substrate 10 Photoelectric conversion unit 10a Photoelectric conversion layer 10b Pixel electrode 10c Counter electrode 11 Amplifying transistor 12 Reset transistor 13 Address transistor 14,94 pixels 15 Vertical scanning section 16 Photoelectric conversion control line 17 Vertical signal line 18 Load section 19 Column signal processing section 20 Horizontal signal readout section 21 Power wiring 22 Differential Amplifier 23 Feedback Line 24 Charge storage section 51 first capacitance element 52 second capacitance element 56 Bandwidth control transistor 60 Overflow transistor 62 Power wiring 65 Setting device 70 MOS capacity Cv 1st terminal TT Terminal 2 75 Voltage line 77 Voltage Source 80 Specific Transistors B1 1st band B2 Second band B3 3rd band IP inflection point

Claims

1. A photoelectric conversion unit that generates electric charges by photoelectric conversion; a charge storage section in which the charge is stored; a metal-oxide-semiconductor capacitor including a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region; During exposure, the first terminal is electrically connected to the charge storage portion; the gate is electrically connected to the first terminal; the at least one semiconductor region is electrically connected to the second terminal; an imaging device, the oxide layer being located between the gate and the at least one semiconductor region, a CV characteristic defined as a relationship between a terminal voltage, which is a voltage between the first terminal and the second terminal, and a capacitance value of the metal-oxide-semiconductor capacitor includes a first band and a second band; the capacitance value in the second band is smaller than the capacitance value in the first band, an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the second band is smaller than an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the first band; the imaging modes of the imaging device include a first mode and a second mode; In the first mode, a potential is applied to the second terminal such that the inter-terminal voltage changes within the first band when the potential of the charge storage portion changes; In the second mode, a potential is applied to the second terminal such that the inter-terminal voltage changes within the second band when the potential of the charge storage unit changes. Imaging device.

2. A photoelectric conversion unit that generates electric charges by photoelectric conversion; a charge storage section in which the charge is stored; a metal-oxide-semiconductor capacitor including a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region; During exposure, the first terminal is electrically connected to the charge storage portion; the gate is electrically connected to the first terminal; the at least one semiconductor region is electrically connected to the second terminal; an imaging device, the oxide layer being located between the gate and the at least one semiconductor region, a CV characteristic defined as a relationship between a terminal voltage, which is a voltage between the first terminal and the second terminal, and a capacitance value of the metal-oxide-semiconductor capacitor includes a first band and a third band; the capacitance value in the third band is greater than the capacitance value in the first band, an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the third band is smaller than an absolute value of a ratio of a change in the capacitance value to a change in the inter-terminal voltage in the first band; the imaging modes of the imaging device include a first mode and a third mode; In the first mode, a potential is applied to the second terminal such that the inter-terminal voltage changes within the first band when the potential of the charge storage portion changes; In the third mode, a potential is applied to the second terminal such that the inter-terminal voltage changes within the third band when the potential of the charge storage unit changes. Imaging device.

3. the capacitance value changes continuously depending on the potential of the charge storage section; 3. The imaging device according to claim 1.

4. the CV characteristics have an inflection point, When the potential of the charge storage section changes continuously, the inter-terminal voltage and the capacitance value change continuously across the inflection point. The imaging device according to claim 1 .

5. a setting unit for setting a range in which the potential of the charge storage unit changes to a range from a first potential to a second potential; the CV characteristic includes the first band having the inflection point, When the potential of the charge storage section changes from the first potential to the second potential, the inter-terminal voltage and the capacitance value change from the inter-terminal voltage and the capacitance value at one end of the first band to the inter-terminal voltage and the capacitance value at the other end of the first band. The imaging device according to claim 4 .

6. a first DC potential is applied to the second terminal such that the capacitance value continuously changes in response to the inter-terminal voltage; The imaging device according to claim 1 .

7. further comprising a voltage source applying a potential to the second terminal; The imaging device according to claim 1 .

8. a semiconductor substrate including the at least one semiconductor region; the photoelectric conversion unit is spaced apart from the semiconductor substrate; The imaging device according to claim 1 .

Images