Semiconductor Devices

Abstract

To provide a semiconductor device with a small switching loss and a large breakdown resistance.SOLUTION: A semiconductor device comprises: a semiconductor part that includes a first semiconductor layer of a first conductivity type and second and third semiconductor layers of a second conductivity type; a first electrode; a second electrode; and a plurality of third electrodes provided in the semiconductor part. The semiconductor part is provided between the first electrode and the second electrode. The first semiconductor layer extends between the first electrode and the second electrode. The second semiconductor layer is provided between the first semiconductor layer and the second electrode. The third semiconductor layers are provided between the second semiconductor layer and the second electrode. Between adjacent two of the third electrodes, the second electrode has a contact part extending in the second semiconductor layer. The third semiconductor layers are separated from each other, each being provided between the contact part and any one of the two third electrodes while facing the one of the two third electrodes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Semiconductor devices used in power conversion devices such as inverters are required to have low switching loss and high breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-103456 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device with low switching loss and high breakdown resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor section including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and multiple third semiconductor layers of the second conductivity type; a first electrode electrically connected to the first semiconductor layer of the semiconductor section; a second electrode electrically connected to the second semiconductor layer and the third semiconductor layer of the semiconductor section; and multiple third electrodes provided in the semiconductor section and electrically insulated from the semiconductor section by a first insulating film. The semiconductor section is provided between the first electrode and the second electrode, and the first semiconductor layer extends between the first electrode and the second electrode. The second semiconductor layer is provided between the first semiconductor layer and the second electrode. The multiple third semiconductor layers are each partially provided on the second semiconductor layer between the second semiconductor layer and the second electrode, and contain second conductivity type impurities at a concentration higher than the concentration of second conductivity type impurities in the second semiconductor layer. Each of the multiple third electrodes is provided inside a first trench extending from the surface of the semiconductor section facing the second electrode into the first semiconductor layer. Between two adjacent third electrodes of the plurality of third electrodes, the second semiconductor layer faces each of the two third electrodes via the first insulating film, and the second electrode has a contact portion extending from the surface of the semiconductor portion into a second trench extending into the second semiconductor layer. The plurality of third semiconductor layers are spaced apart from each other, and each is provided between the contact portion of the second electrode and one of the two third electrodes, facing one of the two third electrodes via the first insulating film. The second semiconductor layer has a first portion extending between the contact portion of the second electrode and the other of the two third electrodes, and each of the plurality of third semiconductor layers is arranged to face the first portion of the second semiconductor layer via the contact portion of the second electrode. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic plan view showing a semiconductor device according to an embodiment; [Figure 3]FIG. 2 is another schematic plan view showing the semiconductor device according to the embodiment. [Figure 4] FIG. 10 is a schematic plan view showing a semiconductor device according to a first modified example of the embodiment. [Figure 5] FIG. 10 is a schematic plan view showing a semiconductor device according to a second modified example of the embodiment. [Figure 6] FIG. 10 is a schematic plan view showing a semiconductor device according to a third modified example of the embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a fourth modified example of the embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a fifth modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is a diode. For example, the semiconductor device 1 functions as an FWD (Free Wheeling Diode) in a power conversion device. Furthermore, the semiconductor device 1 may be integrated with, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0010] 1, the semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, and a second electrode 30. The semiconductor portion 10 is located between the first electrode 20 and the second electrode 30. The first electrode 20 is a cathode electrode. The second electrode 30 is an anode electrode. The semiconductor portion 10 is made of, for example, silicon. The first electrode 20 is provided on a back surface 10B of the semiconductor portion 10. The second electrode 30 is provided on a front surface 10F of the semiconductor portion 10.

[0011] The semiconductor portion 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the second conductivity type, and a fourth semiconductor layer 17. In the following description, the first conductivity type is referred to as n-type and the second conductivity type is referred to as p-type.

[0012] The first semiconductor layer 11 is, for example, an n-type low concentration layer. The first semiconductor layer 11 contains a low concentration of n-type impurities. The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30.

[0013] The second semiconductor layer 13 is, for example, a p-type anode layer. The second semiconductor layer 13 is provided between the first semiconductor layer 11 and the second electrode 30. The second electrode 30 is in contact with the second semiconductor layer 13. The second electrode 30 is provided in the second semiconductor layer 13 by, for example, a Schottky barrier layer. - Connected.

[0014] The third semiconductor layer 15 is, for example, a p-type high concentration layer. The third semiconductor layer 15 contains a second conductivity type impurity at a concentration higher than the concentration of the second conductivity type impurity in the second semiconductor layer 13. The third semiconductor layer 15 is provided partially between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 is provided on the second semiconductor layer 13, contacts the second electrode 30, and is electrically connected to the second electrode 30. The second electrode 30 is, for example, ohmically connected to the third semiconductor layer 15.

[0015] The fourth semiconductor layer 17 is, for example, an n-type cathode layer. The fourth semiconductor layer 17 is provided between the first semiconductor layer 11 and the first electrode 20. The fourth semiconductor layer 17 contains a first conductivity type impurity at a concentration higher than the concentration of the first conductivity type impurity in the first semiconductor layer 11. The first electrode 20 is in contact with the fourth semiconductor layer 17 and is electrically connected to the fourth semiconductor layer 17. The first electrode 20 is, for example, ohmic-connected to the fourth semiconductor layer 17.

[0016] 1, the semiconductor device 1 further includes a plurality of third electrodes 40. The third electrodes 40 are provided in the semiconductor portion 10, for example, between the first electrode 20 and the second electrode 30. A plurality of trenches TR are provided on the front surface 10F side of the semiconductor portion 10. The plurality of third electrodes 40 are provided in the plurality of trenches TR, respectively. The third electrodes 40 are electrically insulated from the semiconductor portion 10 by a first insulating film 43.

[0017] The third electrodes 40 are aligned in a direction along the surface 10F of the semiconductor portion 10, for example, in the X direction. The second semiconductor layer 13 is provided between two adjacent third electrodes 40. The second semiconductor layer 13 faces each of the two third electrodes 40 with a first insulating film 43 interposed therebetween. In this example, the third electrode 40 is provided between the first electrode 20 and the second electrode 30, and is electrically insulated from the second electrode 30 by a second insulating film 45. By being electrically insulated from the second electrode 30, the third electrode 40 can be configured to function as a control electrode (gate electrode).

[0018] The second electrode 30 has a trench contact 30C. The trench contact 30C extends into a contact trench CT that extends from the surface 10F of the semiconductor portion 10 into the second semiconductor layer 13. The third semiconductor layer 15 is provided between one of two adjacent third electrodes 40 and the trench contact 30C. The contact trench CT is provided so that its depth in the Z direction is deeper than the thickness of the third semiconductor layer 15 in the Z direction.

[0019] The third semiconductor layer 15 faces the third electrode 40 via the first insulating film and is provided so as to be in contact with the trench contact 30C. The third semiconductor layer 15 is in contact with the trench contact 30C and is also in contact with the second electrode 30, for example, on the front surface 10F of the semiconductor portion 10. Note that the embodiment is not limited to this example, and the third semiconductor layer 15 may be provided so as to be spaced apart from the trench contact 30C.

[0020] Fig. 2 is a schematic plan view showing the semiconductor device 1 according to the embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 1 is a cross-sectional view taken along line BB in Fig. 2.

[0021] 2, the third electrode 40 extends, for example, in the Y direction. The trench contact 30C extends, for example, between two adjacent third electrodes 40 in the Y direction.

[0022] The third semiconductor layer 15 is disposed between one third electrode 40a of two adjacent third electrodes 40 and the trench contact 30C, and is spaced apart in the Y direction. The second semiconductor layer 13 has a first portion 13a located between the other third electrode 40b of the two adjacent third electrodes 40 and the trench contact 30C. The third semiconductor layer 15 is provided to face the first portion 13a of the second semiconductor layer 13 via the trench contact 30C.

[0023] The second portion 13b of the second semiconductor layer 13 is located between two third semiconductor layers 15 adjacent to each other in the Y direction. The second portion 13b of the second semiconductor layer 13 contacts each of the two adjacent third semiconductor layers 15. The width Wb of the third semiconductor layer 15 in the Y direction is narrower than, for example, the width Wa of the second portion 13b of the second semiconductor layer 13 located between the third semiconductor layers 15 in the Y direction.

[0024] In this example, the two third semiconductor layers 15 that are arranged closest to each other in the X direction face each other via the third electrode 40 and the first insulating film 43. That is, the two third semiconductor layers 15 that are arranged to face each other on both sides of the third electrode 40 do not have part of the second semiconductor layer 13 interposed between them.

[0025] 3(a) to 3(c) are other schematic plan views showing the semiconductor device 1 according to the embodiment. 3(a) and 3(b) are schematic plan views showing semiconductor devices 2a and 2b according to comparative examples. 3(c) is a schematic plan view showing the semiconductor device 1.

[0026] 3(a), the third semiconductor layers 15 are provided so as to face both of the adjacent third electrodes 40 with the first insulating films 43 interposed therebetween. The third semiconductor layers 15 are also provided spaced apart from each other in the Y direction. A part of the second semiconductor layer 13 is provided between the adjacent third semiconductor layers 15.

[0027] The second electrode 30 is formed on the second semiconductor layer 13 by, for example, a Schottky barrier. - Connected 3 For example, the third semiconductor layer 15 is ohmically connected to the first electrode 20. Therefore, when a forward voltage is applied between the first electrode 20 and the second electrode 30 (see FIG. 1), No. The number of holes injected from the second electrode 30 into the second semiconductor layer 13 is greater than the number of holes injected directly from the second electrode 30 into the second semiconductor layer 13. Therefore, the amount of holes injected into the second semiconductor layer 13 can be controlled by adjusting the ratio of the areas of the second semiconductor layer 13 and the third semiconductor layer 15 that are in contact with the second electrode 30.

[0028] For example, in order to reduce switching loss during the turn-off process, it is preferable to suppress hole injection from the second semiconductor layer 13 to the first semiconductor layer 11 during turn-on. On the other hand, excessive suppression of hole injection into the first semiconductor layer 11 increases the on-resistance. For this reason, it is necessary to suitably control the ratio of the contact area of ​​the third semiconductor layer 15 to the contact area of ​​the second semiconductor layer 13 with respect to the second electrode 30.

[0029] In the semiconductor device 2a, for example, the hole concentration in the second semiconductor layer 13 can be controlled by controlling the ratio between the width Wa in the Y direction of the portion of the second semiconductor layer 13 that contacts the second electrode 30 and the width Wb in the Y direction of the third semiconductor layer 15. In other words, the hole concentration in the second semiconductor layer 13 can be controlled by controlling the interval La (= Wa) between adjacent third semiconductor layers 15 in the Y direction. However, if the interval La1 in the Y direction between the second semiconductor layers 13 is made too wide in order to reduce hole injection into the second semiconductor layer 13, forward current will concentrate in the portion where the third semiconductor layer 15 is arranged, reducing the breakdown resistance against overcurrent.

[0030] In a semiconductor device 2b shown in FIG. 3(b), a third semiconductor layer 15 is provided to face one of adjacent third electrodes 40 with a first insulating film 43 interposed therebetween. The width of the third semiconductor layer 15 in the X direction is, for example, half that of the example shown in FIG. 3(a). Therefore, without changing the ratio of the contact areas of the second semiconductor layer 13 and the third semiconductor layer 15, the distance La2 between adjacent third semiconductor layers 15 in the Y direction can be set to half the distance La1 in FIG. 3(a). This makes it possible to alleviate forward current concentration and improve breakdown resistance.

[0031] However, when the third semiconductor layer 15 is formed by ion implantation, the implanted second-conductivity-type impurities are activated by heat treatment. Therefore, as shown by the dashed line in FIG. 3( b ), the second-conductivity-type impurities undergo thermal diffusion, unavoidably increasing the area of ​​the third semiconductor layer 15. This changes the ratio of the contact areas of the second semiconductor layer 13 and the third semiconductor layer 15, resulting in increased hole injection into the second semiconductor layer 13. While it is possible to determine the mask size for ion implantation in advance, taking the diffusion of the second-conductivity-type impurities into consideration, variations in the manufacturing process inevitably result in changes in the amount of holes injected into the second semiconductor layer 13 depending on the manufacturing conditions. Furthermore, there is a limit to how fine the implantation mask used for ion implantation can be, and it may be difficult to form a mask pattern that takes thermal diffusion into account.

[0032] As shown in FIG. 3(c), in the semiconductor device 1, a contact trench CT is formed between adjacent third electrodes 40. This makes it possible to remove the diffusion region in the X direction of the third semiconductor layer 15. In addition, by forming the contact trench CT after ion implantation and then performing heat treatment, it is possible to prevent the diffusion region of the second conductivity type impurity in the X direction. In this way, in the semiconductor device 1, it is possible to suppress an increase in the area of ​​the third semiconductor layer 15 due to thermal diffusion of the second conductivity type impurity and to avoid an increase in hole injection into the second semiconductor layer 13. 3(c), the third semiconductor layer 15 is shown to be in contact with the contact trench CT, but this is not intended to be limiting. For example, due to manufacturing conditions or the accuracy of the mask pattern, the third semiconductor layer 15 may be formed to be spaced apart from the contact trench CT.

[0033] 4(a) and 4(b) are schematic plan views showing semiconductor devices 3a and 3b according to a first modified example of the embodiment, and are cross-sectional views taken along line AA in FIG.

[0034] In the semiconductor device 3a shown in Figure 4(a), between adjacent third electrodes 40, a third semiconductor layer 15 is arranged between one third electrode 40 and the trench contact 30C, and no third semiconductor layer 15 is provided between the other third electrode 40 and the trench contact 30C.

[0035] 4(b) differs from the arrangement of the third semiconductor layers 15 shown in FIG. 2 in that adjacent third semiconductor layers 15 in the X direction do not face each other with the third electrode 40 interposed therebetween. That is, a part of the second semiconductor layer 13 and the third electrode 40 are located between two third semiconductor layers 15 that are closest to each other in the X direction. In other words, the third semiconductor layer 15 is arranged so as to face each other with the third electrode 40 interposed therebetween with the second semiconductor layer 13 interposed therebetween in the X direction.

[0036] 5(a) and 5(b) are schematic plan views showing semiconductor devices 4a and 4b according to a second modification of the embodiment, and are cross-sectional views taken along line AA in FIG.

[0037] In the semiconductor device 4a shown in FIG. 5(a), a plurality of trench contacts 30C are provided between adjacent third electrodes 40. The plurality of trench contacts 30C are aligned in the Y direction and spaced apart from one another. A third semiconductor layer 15 is provided between each of the plurality of trench contacts 30C and the third electrode 40. The third semiconductor layer 15 is provided to face the second semiconductor layer 13 in the X direction, with the trench contacts 30C interposed therebetween.

[0038] 5(b), the third semiconductor layer 15 is provided between one of adjacent third electrodes 40 and each of the plurality of trench contacts 30C. The third semiconductor layer 15 is not provided between the other third electrode 40 and each of the plurality of trench contacts 30C.

[0039] 6(a) and 6(b) are schematic plan views showing semiconductor devices 5a and 5b according to a third modification of the embodiment, and are cross-sectional views taken along line AA in FIG.

[0040] 6(a) also has a plurality of trench contacts 30C arranged side by side in the Y direction and spaced apart from one another. The semiconductor device 5a differs from the arrangement of the third semiconductor layers 15 shown in FIG. 5(a) in that adjacent third semiconductor layers 15 in the X direction do not face each other with the third electrode 40 interposed therebetween. That is, a portion of the second semiconductor layer 13 and the third electrode 40 are located between the two third semiconductor layers 15 that are closest to one another in the X direction.

[0041] 6(b), the plurality of trench contacts 30C include trench contacts 30C that are not in contact with the third semiconductor layer 15. That is, in the X direction, there is a region between the third electrode 40 and the trench contact 30C where the third semiconductor layer 15 is not provided.

[0042] While the above describes examples of the arrangement of multiple third semiconductor layers 15 and trench contacts 30C between two adjacent third electrodes 40, the present invention is not limited to these examples. For example, a different arrangement that combines the features of each arrangement may be applied. In addition, in all examples, it is possible to narrow the interval La between adjacent third semiconductor layers 15 in the Y direction while maintaining a constant ratio of the contact area of ​​the second semiconductor layer 13 and the third semiconductor layer 15 to the second electrode 30. This makes it possible to suppress forward current concentration and improve breakdown resistance.

[0043] 7(a) and 7(b) are schematic cross-sectional views showing semiconductor devices 6a and 6b according to a fourth modification of the embodiment, taken along line BB in FIG.

[0044] In the semiconductor device 6a shown in FIG. No. 2 The insulating film 45 extends between the second semiconductor layer 13 and the second electrode 30, and between the third semiconductor layer 15 and the second electrode 30. The second semiconductor layer 13 and the third semiconductor layer 15 are electrically connected to the second electrode 30 via contact surfaces that contact the trench contacts 30C of the second electrode 30.

[0045] 7(b), the second electrode 30 includes a trench contact 30C and a planar contact 30D. The trench contact 30C extends into the semiconductor portion 10 and is provided so as to contact the second semiconductor layer 13 and the third semiconductor layer 15. The planar contact 30D is provided on the trench contact 30C.

[0046] The flat contact 30D is No. 2 The planar contact 30D is provided to fill a contact hole provided in the insulating film 45. The width of the planar contact 30D in the X direction is set wider than the width of the trench contact 30C in the X direction. As a result, the planar contact 30D includes portions in contact with the upper surfaces of the second semiconductor layer 13 and the third semiconductor layer 15.

[0047] The second semiconductor layer 13 and the third semiconductor layer 15 are provided so that the contact areas in contact with the trench contact 30C and the planar contact 30D of the second electrode 30 have a predetermined area ratio. In these examples, too, the concentration of forward current can be suppressed by narrowing the interval La between the adjacent third semiconductor layers 15 in the Y direction.

[0048] 8(a) and 8(b) are schematic cross-sectional views showing semiconductor devices 7a and 7b according to a fifth modified example of the embodiment, taken along line BB in FIG.

[0049] 8(a), the third electrode 40 of the semiconductor device 7a is connected to the second electrode 30 and is provided to have the same potential as the second electrode 30. The second electrode 30 is electrically connected to the second semiconductor layer 13 and the third semiconductor layer 15 via the surface 10F of the semiconductor portion 10 and the trench contact 30C.

[0050] 8(b), an insulator 47 is provided inside the trench TR instead of the third electrode 40. The insulator 47 is provided, for example, in contact with the second electrode 30 and extending into the first semiconductor layer 11. The insulator 47 is, for example, silicon oxide.

[0051] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0052] 1, 2a, 2b, 3a, 3b, 4a, 4b, 5a, 5b, 6a, 6b, 7a, 7b...semiconductor device, 10...semiconductor portion, 10B...back surface, 10F...front surface, 11...first semiconductor layer, 13...second semiconductor layer, 13a...first portion, 13b...second portion, 15...third semiconductor layer, 17...fourth semiconductor layer, 20...first electrode, 30...second electrode, 30C...trench contact, 30D...planar contact, 40, 40a, 40b...third electrode, 43...first insulating film, 45...interlayer insulating film, 47...insulator, CT...contact trench, TR...trench

Claims

1. a semiconductor portion including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of third semiconductor layers of the second conductivity type; a first electrode electrically connected to the first semiconductor layer of the semiconductor portion; a second electrode electrically connected to the second semiconductor layer and the third semiconductor layer of the semiconductor portion; a plurality of third electrodes provided in the semiconductor portion and electrically insulated from the semiconductor portion by a first insulating film; Equipped with the semiconductor portion is provided between the first electrode and the second electrode, the first semiconductor layer extends between the first electrode and the second electrode; the second semiconductor layer is provided between the first semiconductor layer and the second electrode, the plurality of third semiconductor layers are each partially provided on the second semiconductor layer between the second semiconductor layer and the second electrode, and contain a second conductivity type impurity at a concentration higher than a concentration of the second conductivity type impurity of the second semiconductor layer; the plurality of third electrodes are provided inside first trenches extending from the surface of the semiconductor portion on the second electrode side into the first semiconductor layer, Between two adjacent third electrodes among the plurality of third electrodes, the second semiconductor layer faces each of the two third electrodes via the first insulating film; the second electrode has a contact portion extending from the surface of the semiconductor portion into a second trench extending into the second semiconductor layer; the plurality of third semiconductor layers are spaced apart from one another, and are each provided between a contact portion of the second electrode and one of the two third electrodes, and face one of the two third electrodes via the first insulating film; the second semiconductor layer has a first portion extending between the contact portion of the second electrode and the other of the two third electrodes; the plurality of third semiconductor layers are arranged to face the first portion of the second semiconductor layer via the contact portion of the second electrode, the plurality of third electrodes further includes another third electrode adjacent to the one of the two third electrodes, the semiconductor portion further includes another third semiconductor layer provided between the one of the two third electrodes and the another third electrode, A semiconductor device, wherein a third semiconductor layer disposed between one of the two third electrodes and the contact portion of the second electrode among the plurality of third semiconductor layers faces another third semiconductor layer via the one of the two third electrodes.

2. The semiconductor device according to claim 1 , wherein said second semiconductor layer includes a second portion extending between said plurality of third semiconductor layers.

3. each of the plurality of third electrodes extends in a first direction along the surface of the semiconductor portion; the second portion of the second semiconductor layer is in contact with two third semiconductor layers adjacent to each other in the first direction among the plurality of third semiconductor layers; The semiconductor device according to claim 2 , wherein the width of the second portion of the second semiconductor layer in the first direction is greater than the width of the plurality of third semiconductor layers in the first direction.

4. the contact portion of the second electrode extends in the first direction, The semiconductor device according to claim 3 , wherein said plurality of third semiconductor layers are in contact with said contact portion.

5. the second electrode has a plurality of the contact portions arranged in the first direction, The semiconductor device according to claim 3 , wherein said third semiconductor layers are in contact with said contact portions, respectively.

6. The semiconductor device according to claim 1 , wherein the plurality of third semiconductor layers are disposed between the one of the two third electrodes and the contact portion of the second electrode.

7. A semiconductor part including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of third semiconductor layers of the second conductivity type; a first electrode electrically connected to the first semiconductor layer of the semiconductor portion; a second electrode electrically connected to the second semiconductor layer and the third semiconductor layer of the semiconductor portion; a plurality of third electrodes provided in the semiconductor portion and electrically insulated from the semiconductor portion by a first insulating film; Equipped with the semiconductor portion is provided between the first electrode and the second electrode, the first semiconductor layer extends between the first electrode and the second electrode; the second semiconductor layer is provided between the first semiconductor layer and the second electrode, the plurality of third semiconductor layers are each partially provided on the second semiconductor layer between the second semiconductor layer and the second electrode, and contain a second conductivity type impurity at a concentration higher than a concentration of the second conductivity type impurity of the second semiconductor layer; the plurality of third electrodes are provided inside first trenches extending from the surface of the semiconductor portion on the second electrode side into the first semiconductor layer, Between two adjacent third electrodes among the plurality of third electrodes, the second semiconductor layer faces each of the two third electrodes via the first insulating film; the second electrode has a contact portion extending from the surface of the semiconductor portion into a second trench extending into the second semiconductor layer; the plurality of third semiconductor layers are spaced apart from one another, and are each provided between a contact portion of the second electrode and one of the two third electrodes, and face one of the two third electrodes via the first insulating film; the second semiconductor layer has a first portion extending between the contact portion of the second electrode and the other of the two third electrodes; the plurality of third semiconductor layers are arranged to face the first portion of the second semiconductor layer via the contact portion of the second electrode, the plurality of third electrodes and the contact portion each extend in a first direction along the surface of the semiconductor portion, The second semiconductor layer includes a second portion extending between the plurality of third semiconductor layers in the first direction.

8. the plurality of third electrodes further includes another third electrode adjacent to the one of the two third electrodes, the semiconductor portion further includes another third semiconductor layer provided between the one of the two third electrodes and the another third electrode, 8. The semiconductor device according to claim 7, wherein a third semiconductor layer disposed between one of the two third electrodes and the contact portion of the second electrode among the plurality of third semiconductor layers faces another third semiconductor layer via the one of the two third electrodes.

9. the plurality of third electrodes further includes another third electrode adjacent to the one of the two third electrodes, the semiconductor portion further includes another first portion of the second semiconductor layer provided between the one of the two third electrodes and the other third electrode, 8. The semiconductor device according to claim 7, wherein a third semiconductor layer disposed between one of the two third electrodes and the contact portion of the second electrode among the plurality of third semiconductor layers faces the other first portion of the second semiconductor layer via the one of the two third electrodes.

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