Lateral surface-gate vertical field-effect transistor with adjustable output capacitance.

Abstract

A lateral surface-gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface-gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate adjusts the surface channel, and the trench gate includes a controllable depth. The controllable depth can be varied to beneficially adjust the output capacitance.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 087,433, filed October 5, 2020, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to vertical field effect transistors, and more particularly to vertical field effect transistors that include trenches. [Background technology]

[0003] A field-effect transistor allows the flow of majority carriers through a channel, i.e., majority carrier current. The conductivity of the channel is controlled by the gate bias. Under forward bias conditions, the channel conducts current, and under reverse bias conditions, the channel blocks current. In lateral field-effect transistors, the channel is formed at the surface and current flows laterally.

[0004] In a vertical trench-gate field-effect transistor, a trench gate is fabricated in the field-effect transistor by etching a trench in the active region. A gate channel region is formed vertically along the walls of the trench to gate current vertically. The gate channel blocks current under a reverse-biased gate potential and facilitates current under a forward-biased gate potential. The advantage of a vertical trench gate is vertical current confinement.

[0005] A field effect transistor can be characterized by its input capacitance, output capacitance, and reverse transfer capacitance. The input capacitance is determined by the gate-to-drain capacitance and the gate-to-source capacitance. The output capacitance is determined by the drain-to-source capacitance and the gate-to-drain capacitance, and the reverse transfer capacitance is determined by the gate-to-drain capacitance. Summary of the Invention

[0006] Non-limiting and non-exhaustive embodiments of lateral surface-gate vertical field effect transistors with adjustable output capacitance are described with reference to the following figures, in which like reference numerals in different figures refer to like parts unless otherwise specified: [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 shows a schematic diagram of a cascode device comprising a lateral surface-gate vertical field-effect transistor with adjustable output capacitance in accordance with the teachings herein. [Figure 2] FIG. 2 shows a cross section of an active cell of a lateral front-gate vertical field effect transistor with adjustable output capacitance according to an embodiment. [Figure 3] FIG. 3 shows a plan view of a partial stripe cell layout according to the lateral surface gate vertical field effect transistor embodiment of FIG. [Figure 4A] FIG. 4A shows a plan view of a closed cell layout according to the lateral surface gate vertical field effect transistor embodiment of FIG. [Figure 4B] FIG. 4B shows a plan view illustrating the cell arrangement pattern of the closed cell layout of FIG. 4A. [Figure 5A] FIG. 5A shows a plan view of a closed cell layout according to another embodiment of the lateral front-gate vertical field effect transistor of FIG. [Figure 5B] FIG. 5B is a plan view showing the cell arrangement pattern of the closed cell layout of FIG. 5A. [Figure 6] FIG. 6 shows a cross section of an active cell of a lateral front-gate vertical field effect transistor with adjustable output capacitance according to another embodiment. [Figure 7A] FIG. 7A shows a plan view of a closed cell layout according to the lateral front-gate vertical field effect transistor embodiment of FIG. [Figure 7B] FIG. 7B is a plan view showing the cell arrangement pattern of the closed cell layout of FIG. 7A. [Figure 7C] FIG. 7C shows a plan view of a partial stripe cell layout according to the lateral surface gate vertical field effect transistor embodiment of FIG. [Figure 8] FIG. 8 shows a simulated active cell of a lateral front-gate vertical field effect transistor according to an embodiment. [Figure 9] FIG. 9 shows simulation results for the embodiment of FIG. [Figure 10A] FIG. 10A shows a simulated active cell according to the first embodiment. [Figure 10B] FIG. 10B shows a simulated active cell according to the second embodiment. [Figure 10C] FIG. 10C shows a simulated active cell according to the third embodiment. [Figure 10D] FIG. 10D shows simulated output capacitance versus voltage for the embodiment of FIGS. 10A-10C. [Figure 11] FIG. 11 shows simulated reverse recovery characteristics versus time for the trench depth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will understand that the elements in the figures are drawn for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements and layers in the figures may be exaggerated relative to other elements to facilitate a better understanding of various embodiments of the teachings herein. Furthermore, common but well-understood elements, layers, and / or process steps useful or necessary in commercially viable embodiments are often not shown in the drawings so as not to obscure the views of these various embodiments of lateral surface-gate vertical field-effect transistors with adjustable output capacitance.

[0009] In the following description, numerous specific details are set forth to provide a thorough understanding of the lateral surface-gate vertical field-effect transistor with adjustable output capacitance. However, it will be apparent to those skilled in the art that the specific details may not be used to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0010] References herein to "one embodiment," "embodiment," "one example," or "example" mean that the particular feature, structure, method, process, and / or characteristic described in connection with the embodiment or example is included in at least one embodiment of a lateral surface-gate vertical field-effect transistor with adjustable output capacitance. Thus, the use of the phrases "one embodiment," "in an embodiment," "one example," or "example" in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, methods, steps, and / or characteristics may be combined in any suitable combination and / or subcombination in one or more embodiments or examples. Additionally, it is understood that the figures provided herewith are for explanatory purposes to persons skilled in the art and that the drawings are not necessarily drawn to scale.

[0011] In the context of this application, when a transistor, including a field effect transistor, is in the "off state" or "off," the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in the "on state" or "on," the transistor can substantially conduct current. Furthermore, for purposes of this disclosure, "ground" or "ground potential" refers to the reference voltage or potential relative to which all other voltages or potentials in an electronic circuit, device, or integrated circuit (IC) are defined or measured.

[0012] Field effect transistors may be further categorized by the maximum voltage at which they can operate and block current. For example, field effect transistors designed to block and / or operate at high voltages (e.g., hundreds of volts) may be classified as high voltage field effect transistors, while field effect transistors designed to block and / or operate at low voltages (e.g., 30 to 50 volts) may be classified as low voltage field effect transistors.

[0013] Furthermore, a field effect transistor (FET) can be enhancement-mode or depletion-mode. An enhancement-mode device can refer to a transistor (e.g., a field effect transistor) that blocks current (i.e., is off) when no gate bias is applied (i.e., when the gate-to-source bias is zero). In contrast, a depletion-mode device can refer to a transistor that passes current (i.e., is on) when the gate-to-source bias is zero.

[0014] Furthermore, in the context of this application, a field effect transistor may be realized as a metal oxide semiconductor field effect transistor (MOSFET). Field effect transistors and MOSFETs, including low-voltage MOSFETs, may be combined with high-voltage depletion-mode gallium nitride (GaN) or silicon carbide (SiC) devices to create high-voltage cascode devices. For example, a high-voltage cascode device may comprise a high-voltage depletion-mode GaN high-electron mobility transistor (HEMT) cascoded with a low-voltage enhancement-mode MOSFET.

[0015] Compared to discrete high-voltage field-effect transistors, high-voltage cascode devices can beneficially have improved reverse recovery characteristics. For example, a cascode device including a low-voltage enhancement-mode field-effect transistor and / or a MOSFET can contribute to the body diode in a low-voltage MOSFET (i.e., a low-voltage field-effect transistor). The body diode of a low-voltage MOSFET can contribute to an ultra-low reverse recovery charge Qrr and excellent reverse recovery characteristics that would not be achievable from a single discrete high-voltage field-effect transistor.

[0016] Furthermore, it is desirable to reduce the on-resistance Rdson and control the output capacitance Coss of the low-voltage field-effect transistor in the high-voltage cascode device. For example, reducing the on-resistance of the low-voltage field-effect transistor improves the overall on-state performance of the high-voltage cascode device.

[0017] Furthermore, controlling the output capacitance Coss can improve switching performance. For example, the output capacitance Coss affects switching together with the drain-to-source capacitance Cds of high-voltage depletion-mode GaN or SiC devices. Controlling the output capacitance Coss can be beneficial in controlling voltage excursions at the source of high-voltage cascode devices.

[0018] Modern high-voltage cascode devices use lateral low-voltage enhancement-mode field-effect transistors. Unfortunately, lateral low-voltage enhancement-mode field-effect transistors are typically metal-limited due to non-scaling back-end metal resistance. For example, a typical lateral low-voltage enhancement-mode field-effect transistor may be limited to a minimum on-resistance of approximately 15 milliohms (mohm) due to metal resistance.

[0019] Furthermore, lateral low-voltage enhancement-mode field-effect transistors do not allow for control of the output capacitance, Coss. Therefore, there is a need for improved low-voltage enhancement-mode field-effect transistors that have lower on-resistance and help control the output capacitance, Coss.

[0020] A lateral surface-gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface-gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate adjusts the surface channel, and the trench gate includes a controllable depth. The controllable depth can be varied to beneficially adjust the output capacitance.

[0021] 1 shows a schematic diagram of a cascode device 100 comprising a lateral, front-gate, vertical field-effect transistor 102 with adjustable output capacitance in accordance with the teachings herein. The cascode device 100 further comprises a high-voltage device 101. The high-voltage device 101 may be a depletion-mode gallium nitride high electron mobility transistor. Alternatively, the high-voltage device 101 may be a depletion-mode silicon carbide field-effect transistor or a silicon carbide junction field-effect transistor.

[0022] As mentioned above, advantages of the high-voltage cascode device 100 may include a low or ultra-low reverse recovery charge Qrr and excellent reverse recovery characteristics provided by the body diode of the lateral surface-gate vertical field-effect transistor 102. As further described herein, another important parameter is the output capacitance Coss of the lateral surface-gate vertical field-effect transistor 102. The output capacitance Coss, together with the drain-to-source capacitance Cds of the high-voltage device 101, may determine how high the source voltage of the high-voltage device 101 rises during switching.

[0023] According to the teachings herein, the lateral surface-gate vertical field effect transistor 102 can offer better on-resistance Rdson than a lateral low-voltage metal-oxide field effect transistor (MOSFET). For example, the on-resistance Rdson can be less than fifteen milliohms (15 mohm). In other applications, the on-resistance Rdson can be less than ten milliohms (10 mohm).

[0024] 2 illustrates a cross-section of an active cell 200 of a lateral, front-gate, vertical field-effect transistor 102 with adjustable output capacitance according to an embodiment. The active cell 200 includes a heavily doped N-type (N+) substrate 222, an N-type epitaxial (N-EPI) layer 220, a P-type body (PBODY) diffusion 206, a heavily doped P-type (P+) body contact diffusion 202, and a heavily doped N-type (N+) source diffusion 204. The N-EPI layer 220 can be grown on the substrate 222 with a graded or constant doping profile.

[0025] Active cell 200 includes trenches 211a-b that extend through N-EPI layer 220 and into N+ substrate 222. Trench 211a includes oxide 214a and trench gate 212a, and trench 211b includes oxide 214b and trench gate 212b. Further, oxide 214a-b may have a thickness tox2, and trench gates 212a-b may extend a depth d through N-EPI layer 220. According to an embodiment of active cell 200, trenches 211a-b extend a depth d through N-EPI layer 220 into N+ substrate 222.

[0026] Active cell 200 further includes a lateral gate 208 located on a surface gate oxide 210 having a thickness tox1. The lateral gate 208 extends laterally over the surface gate oxide 210 to facilitate field control at interface 216. According to an embodiment, lateral gate 208 and trench gates 212a-b may include polycrystalline silicon (e.g., N-type polycrystalline silicon). In another embodiment, gate oxide 210 and oxides 214a-b may be of the same material and of the same thickness (i.e., thickness tox1 may be equal to or substantially equal to thickness tox2).

[0027] A gate voltage may be applied to the lateral gate 208 to modulate a channel (i.e., a surface channel) formed at an interface 216 between the N-type source diffusion 204 and the N-EPI layer 220. According to the teachings herein, the active cell 200 may be an active cell in a lateral surface-gate vertical field effect transistor 102 operating as an enhancement mode. Thus, for gate-to-source voltages above the enhancement threshold (e.g., positive 2 volts), current may flow along the channel at the interface 216, and conversely, for gate-to-source voltages below the enhancement threshold, current may be blocked.

[0028] According to semiconductor device physics, the drain of the lateral front-gate vertical field-effect transistor 102 may include an N-EPI layer 220 and an N+ substrate 222. Current flow in the N-EPI layer 220 and the N+ substrate 222 may be vertical. Furthermore, the trenches 211a-b may be electrically coupled to the lateral gate 208 such that the voltage applied to the lateral gate 208 is substantially equal to the voltage applied to the trench gates 212a-b. This approach may improve the on-resistance Rdson by achieving conductivity tuning at the trench interfaces 218a-b. For example, when a positive gate potential is applied to the trench gates 212a-b, a low-resistance accumulation region may be formed along the trench interfaces 218a-b.

[0029] Furthermore, depending on semiconductor device physics and device design, active cell 200 may be designed for low voltage (i.e., for low drain-to-source voltage). For example, a typical maximum drain-to-source voltage may be 40 volts. In some applications, the maximum drain-to-source breakdown voltage may be 50 to 60 volts.

[0030] FIG. 3 illustrates a plan view of a partial striped cell layout 300 according to an embodiment of a lateral, front-gate, vertical field-effect transistor 102. The partial striped cell layout 300 includes trenches 211a-b and PBODY diffusion 206 drawn relative to N-EPI layer 220. For reference, the cross section drawn from point X to point Y may correspond to the cross section of active cell 200 shown in FIG. 2. As shown, trenches 211a-b, along with PBODY diffusion 206, extend across distance LS, and trench 211a may have a width W. In some embodiments, width W may be between 300 nanometers (300 nm) and 1.2 micrometers (1.2 um). For example, in one embodiment, width W may be 750 nanometers (750 nm).

[0031] 4A illustrates a plan view of a closed cell layout 400 according to an embodiment of a lateral front-gate vertical field effect transistor 102. The closed cell layout 400 includes trenches 211a-b and PBODY diffusion 206 drawn relative to the N-EPI layer 220. For reference, the cross section drawn from point X to point Y may correspond to the cross section of the active cell 200 shown in FIG. 2. As illustrated, the trench 211a may have a width W (e.g., a width W between 300 nm and 1.2 um).

[0032] 4B illustrates a plan view of a cell placement pattern 450 of the closed cell layout 400 of FIG. 4A. The cell placement pattern 450 includes closed cell layout instances 400a-f that replicate the cell layout 400. As indicated by ellipses 460 and 462, there may be more than six instances 400a-f. As one skilled in the art will appreciate, there may be more or fewer than six instances 400a-f based at least in part on a maximum specified drain-source current and / or a maximum specified on-resistance Rdson.

[0033] Figure 5A shows a plan view of a closed cell layout 500 according to another embodiment of the lateral front-gate vertical field effect transistor of Figure 2. Unlike closed cell layout 400, in closed cell layout 500, PBODY 220 and trench 211b are formed around trench 211a. For completeness, a width W is drawn for trench 211a, and a cross section drawn between points X and Y is drawn from the midpoint of trench 211a.

[0034] 5B illustrates a plan view of a cell placement pattern 550 of the closed cell layout 500 of FIG. 5A. The cell placement pattern 550 includes closed cell layout instances 500a-f that replicate the cell layout 500. As indicated by ellipses 560 and 562, there may be more than six instances 500a-f. As one skilled in the art will appreciate, there may be more or fewer than six instances 500a-f based at least in part on a maximum specified drain-source current and / or a maximum specified on-resistance Rdson.

[0035] 6 shows a cross section of an active cell 600 of a lateral front-gate vertical field effect transistor 102 according to another embodiment. Active cell 600 is similar to active cell 200, except that active cell 600 does not include trench 211b.

[0036] 7A shows a plan view of a closed cell layout 700 according to the lateral front-gate vertical field effect transistor embodiment of FIG. 6. The closed cell layout 400 includes a trench 211a of width W and a PBODY diffusion 206 drawn relative to the N-EPI layer 220. For reference, the cross section drawn from point Z to point Y may correspond to the cross section of the active cell 600.

[0037] 7B illustrates a plan view of a cell placement pattern 750 of closed cell layout 700. Cell placement pattern 750 includes closed cell layout instances 700a-f that replicate cell layout 700. There may be more than six instances 700a-f, as indicated by ellipses 770 and 762. As one skilled in the art will appreciate, there may be more or fewer than six instances 700a-f based at least in part on a maximum specified drain-source current and / or a maximum specified on-resistance Rdson.

[0038] FIG. 7C illustrates a plan view of a partial striped cell layout 770 according to an embodiment of a lateral, front-gate, vertical field-effect transistor 102. The partial striped cell layout 770 includes trenches 211a-b and PBODY diffusion 206 drawn relative to N-EPI layer 220. For reference, the cross section drawn from point Z to point Y may correspond to the cross section of active cell 600 shown in FIG. 6. As shown, trenches 211a-b, along with PBODY diffusion 206, extend across distance LS, and trench 211a may have a width W. In some embodiments, width W may be between 300 nanometers (300 nm) and 1.2 micrometers (1.2 um). For example, in one embodiment, width W may be 750 nanometers (750 nm).

[0039] 8 illustrates a simulated active cell 200 of a lateral, front-gate vertical field-effect transistor according to an embodiment. The simulated active cell 200 includes a front polysilicon gate (e.g., a lateral gate 208 and a gate oxide 210 having a thickness tox1). The gate oxide thickness (i.e., thickness tox1) may have a value between 100 angstroms and 250 angstroms (e.g., 140 angstroms), and the oxide thickness tox2 of oxides 214a-b may be between 0.2 micrometers and 0.3 micrometers. The active cell 200 may be configured for 40-volt operation (i.e., a maximum drain-to-source voltage of 40 volts).

[0040] Figure 9 shows simulation results 900 for the embodiment of Figure 8. Simulation results 900 include plots 910 and 912 of total drain current in amperes per micrometer (A / um) as a function of applied gate-to-source voltage in volts (V). Furthermore, the simulated drain-to-source voltage can be constant, while the gate-to-source voltage is varied.

[0041] Plot 910 corresponds to an embodiment in which the lateral gate 208 and the trench gates 212a-b are electrically coupled such that a gate-to-source voltage is applied to both the lateral gate 208 and the trench gates 212a-b. Plot 912 corresponds to an embodiment in which the trench gates 212a-b have a constant potential equal to or substantially equal to ground (i.e., 0 volts) that is independent of the applied gate-to-source voltage.

[0042] As shown in simulation results 900, the embodiment of plot 910 may provide more current than the embodiment of plot 912. Alternatively, and additionally, plot 910 may exhibit improved on-resistance Rdson. For example, a comparison of plots 910 and 912 may show a simulated improvement (i.e., reduction) in on-resistance Rdson of approximately 30 percent when lateral gate 208 is electrically coupled to trench gates 212a-b.

[0043] 10A shows a simulated active cell 200 according to a first embodiment, which may correspond to an active cell 200 in which trench gates 212a-b extend into N-EPI layer 220 to a depth d of 1.5 micrometers (1.5 um).

[0044] 10B shows a simulated active cell 200 according to a second embodiment, which may correspond to an active cell 200 in which trench gates 212a-b extend into N-EPI layer 220 to a depth d of three micrometers (3 um) to the N+ substrate 222.

[0045] 10C shows a simulated active cell according to a third embodiment, which may correspond to an active cell 200 in which trench gates 212a-b extend into the N-EPI layer 220 and further into the N+ substrate 222 a depth d of five micrometers (5 um).

[0046] FIG. 10D shows simulated output capacitance Coss versus drain voltage Vd according to the embodiment of FIGS. 10A-10C. Plots 1064, 1062, and 1060 may correspond to the first, second, and third embodiments of FIGS. 10A, 10B, and 10C, respectively. Plots 1060, 1062, and 1064 show that the output capacitance Coss, expressed in farads per micrometer (F / um), can be adjusted by varying the depth d. For example, when the drain voltage Vd is 10 volts, the output capacitance Coss can be adjusted to approximately 1.0E-15 farads per micrometer by varying the depth d to equal 5 micrometers. Alternatively, Coss can be adjusted to much less than 5.0E-16 farads per micrometer by varying the depth d to equal 1.5 micrometers.

[0047] For completeness, FIG. 10D also includes plots 1070 and 1072 corresponding to lateral and vertical field effect transistors, respectively.

[0048] 11 shows simulated reverse recovery characteristics of current versus time according to the embodiments of Figures 10A-10C. Plots 1162, 1164, and 1166 may correspond to the first, second, and third embodiments of Figures 10A, 10B, and 10C, respectively.

[0049] For completeness, FIG. 11 also includes plots 1160 and 1168 corresponding to vertical and lateral field effect transistors, respectively.

[0050] The foregoing description of illustrated examples of the present disclosure, including those described in the Abstract, is not intended to be exhaustive or to be limited to the precise form disclosed. While specific embodiments of lateral, front-gate, vertical field-effect transistors with adjustable output capacitance are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it will be understood that specific example device cross sections are presented for illustrative purposes, and that other embodiments, materials, and both N-channel and P-channel processes may be used in accordance with the teachings herein.

[0051] In one embodiment, a vertical field effect transistor (e.g., lateral front-gate vertical field effect transistor 102) comprises a substrate (e.g., N+ substrate 222), a drift region (e.g., N-EPI layer 220), and at least one active cell (e.g., at least one active cell 200 and / or 600). The drift region can be N-EPI layer 220. N-EPI layer 220 is formed on a substrate (e.g., N+ substrate 222).

[0052] At least one active cell includes a trench gate (e.g., trench gate 212a and / or trench gate 212b) and a lateral gate (e.g., lateral gate 208). The trench gate is configured to adjust the conductivity of the drift region. For example, trench gate 212a can adjust the conductivity of N-EPI layer 220 at trench interface 218a. The trench gate has a controllable depth (e.g., depth d) that can be adjusted to at least partially determine the output capacitance (see, e.g., FIGS. 10A-10D). Lateral gate 208 is configured to adjust the surface channel (i.e., the surface channel formed at interface 216 in PBODY diffusion 206).

[0053] 10A-10C, the trench gate can extend into the drift region (i.e., into the N-EPI layer 220). For example, the depth d can be 1.5 micrometers as shown in FIG. 10A and / or 5 micrometers as shown in FIG. 10C. Additionally, the trench gate can extend further into the substrate (i.e., the N+ substrate 222) as shown in at least FIG. 10C.

[0054] At least one active cell may have a closed cell pattern (e.g., any one of closed cell layouts 400, 500, 700). The vertical field effect transistor may include a second trench gate 212b. The second trench gate may further adjust the conductivity of the drift region (N-EPI layer 220) at the trench interface 218b.

[0055] The trench gate and the lateral gate may be electrically coupled.

[0056] The trench gate oxide thickness (ie, oxide thickness tox2) may be greater than the lateral gate oxide thickness (ie, gate oxide thickness tox1).

[0057] The lateral gate may be configured to create an inversion region in the surface channel formed at interface 216. The trench gate may be configured to create an accumulation region in N-EPI layer 220.

[0058] The substrate (i.e., N+ substrate 222) may include heavily doped N-type material. The drift region (i.e., N-EPI layer 220) may include lightly doped N-type material. The lightly doped N-type material may be graded. The N-EPI layer 220 may have a graded doping profile.

[0059] In another embodiment, a field effect transistor (i.e., a lateral front-gate vertical field effect transistor 102) includes a drift region (e.g., an N-EPI layer 220), a body (e.g., a PBODY diffusion 206), a source (e.g., an N-type source diffusion 204), a trench gate 212a, and a lateral gate 208. The drift region (i.e., the N-EPI layer 220) is stacked between a substrate (e.g., an N+ substrate 222) and a surface of the active cell (e.g., a surface of the active cell 200, 600). The body is diffused at the surface. The source is diffused into the body. The trench gate extends into the drift region and is configured to adjust the conductivity of the drift region. The trench gate has an adjustable depth d. The lateral gate is located above the body at the surface and extends laterally between the source and the trench gate 212a.

[0060] The adjustable depth d can be configured to vary the output capacitance Coss as a function of the depth d (eg, plots 1060, 1062, 1064).

[0061] The field effect transistor (i.e., the lateral front-gate vertical field effect transistor 102) may be an N-channel field effect transistor. As one skilled in the art will appreciate, the concept may be applied to a complementary P-channel process, and the field effect transistor may alternatively be a P-channel field effect transistor. The field effect transistor may be a silicon field effect transistor.

[0062] In another embodiment, the cascode device 100 comprises a high-voltage depletion-mode device (i.e., high-voltage device 101) and a low-voltage metal-oxide field effect transistor (i.e., lateral surface-gate vertical field effect transistor 102). The low-voltage metal-oxide field effect transistor is electrically cascode-coupled to the high-voltage depletion-mode device. The low-voltage metal-oxide field effect transistor comprises at least one trench gate 212a and at least one lateral gate 208. The at least one trench gate has a controllable depth (i.e., depth d). The depth d is varied to adjust the output capacitance Coss. The at least one lateral gate is configured to adjust a surface channel formed at the interface 216.

[0063] The high voltage depletion mode device may be a gallium nitride high electron mobility transistor. The high voltage depletion mode device may be a silicon carbide field effect transistor. The high voltage depletion mode device may be a silicon carbide junction field effect transistor.

[0064] While the present invention is defined in the claims, it should be understood that the invention may alternatively be defined by the following examples.

[0065] Example 1. A vertical field effect transistor comprising a substrate, a drift region formed on the substrate, and at least one active cell. The at least one active cell comprises a trench gate and a lateral gate. The trench gate is configured to adjust the conductivity of the drift region, the trench gate having a controllable depth adjusted to at least partially determine the output capacitance of the at least one active cell. The lateral gate is configured to adjust a surface channel of the at least one active cell.

[0066] Example 2. A vertical field effect transistor as described in Example 1, wherein the trench gate extends into the drift region.

[0067] Example 3. The vertical field effect transistor of any one of the preceding examples, wherein the trench gate extends into the substrate.

[0068] Example 4. The vertical field effect transistor of any one of the preceding examples, wherein at least one active cell comprises a closed cell pattern.

[0069] Example 5. The vertical field effect transistor of any one of the preceding examples, further comprising a second trench gate configured to adjust the conductivity of the drift region.

[0070] Example 6. The vertical field effect transistor of any one of the previous examples, wherein the trench gate and the lateral gate are electrically coupled.

[0071] Example 7. The vertical field effect transistor of any one of the preceding examples, wherein the trench gate oxide thickness is greater than the lateral gate oxide thickness.

[0072] Example 8. The vertical field effect transistor of any one of the preceding examples, wherein the lateral gate is configured to create an inversion region.

[0073] Example 9. The vertical field effect transistor of any one of the preceding examples, wherein the trench gate is configured to create an accumulation region.

[0074] Example 10. The vertical field effect transistor of any one of the preceding examples, wherein the substrate comprises a heavily doped N-type material and the drift region comprises a lightly doped N-type material.

[0075] Example 11. The vertical field effect transistor of any one of the previous examples, wherein the lightly doped N-type material is graded.

[0076] Example 12. A field effect transistor comprising a drift region deposited between a substrate and a surface of an active cell, a body diffused into the surface, a source diffused into the body, a trench gate extending into the drift region, and a lateral gate located above the body at the surface and extending laterally between the source and the trench gate, the trench gate configured to adjust the conductivity of the drift region, the trench gate having an adjustable depth.

[0077] Example 13. The field effect transistor of any one of the preceding examples, wherein the lateral gate and the trench gate are electrically coupled.

[0078] Example 14. The field effect transistor of any one of the preceding examples, wherein the adjustable depth is configured to vary the output capacitance of the active cell as a function of the adjustable depth.

[0079] Example 15. The field effect transistor of any one of the preceding examples, wherein the trench gate extends into the substrate.

[0080] Example 16. The field effect transistor of any one of the previous examples, wherein the field effect transistor is an N-channel field effect transistor.

[0081] Example 17. The field effect transistor of any one of the preceding examples, wherein the field effect transistor is a P-channel field effect transistor.

[0082] Example 18. The field effect transistor of any one of the preceding examples, wherein the field effect transistor is a silicon field effect transistor.

[0083] Example 19. A cascode device comprising a high-voltage depletion mode device and a low-voltage metal-oxide field effect transistor electrically cascode-coupled to the high-voltage depletion mode device. The low-voltage metal-oxide field effect transistor comprises at least one trench gate and at least one lateral gate. The at least one trench gate has a controllable depth that is varied to adjust the output capacitance of the low-voltage metal-oxide field effect transistor. The at least one lateral gate is configured to adjust the surface channel of the low-voltage metal-oxide field effect transistor.

[0084] Example 20. The cascode device of any one of the preceding examples, wherein the high voltage depletion mode device is a gallium nitride high electron mobility transistor.

[0085] Example 21. The cascode device of any one of the preceding examples, wherein the high voltage depletion mode device is a silicon carbide field effect transistor.

[0086] Example 22. The cascode device of any one of the preceding examples, wherein the high voltage depletion mode device is a silicon carbide junction field effect transistor. (Additional note 1) A vertical field effect transistor, comprising: A substrate; a drift region formed on the substrate; at least one active cell; Equipped with The at least one active cell: a trench gate configured to adjust the conductivity of the drift region, the trench gate having a controllable depth adjusted to at least partially determine an output capacitance of the at least one active cell; a lateral gate configured to modulate a surface channel of the at least one active cell; Equipped with Vertical field-effect transistor. (Additional note 2) the trench gate extends into the drift region; Item 1. A vertical field-effect transistor according to item 1. (Additional note 3) the trench gate extending into the substrate; Item 1. A vertical field-effect transistor according to item 1. (Additional note 4) the at least one active cell comprises a closed cell pattern. Item 1. A vertical field-effect transistor according to item 1. (Additional note 5) a second trench gate configured to adjust the conductivity of the drift region. Item 1. A vertical field-effect transistor according to item 1. (Additional note 6) the trench gate and the lateral gate are electrically coupled; Item 1. A vertical field-effect transistor according to item 1. (Additional note 7) The trench gate oxide thickness is greater than the lateral gate oxide thickness; Item 1. A vertical field-effect transistor according to item 1. (Additional note 8) the lateral gate is configured to produce an inversion region; Item 1. A vertical field-effect transistor according to item 1. (Additional note 9) the trench gate is configured to create an accumulation region; Item 1. A vertical field-effect transistor according to item 1. (Additional note 10) the substrate comprises a heavily doped N-type material; the drift region comprises lightly doped N-type material; Item 1. A vertical field-effect transistor according to item 1. (Additional note 11) the lightly doped N-type material is graded; Item 11. The vertical field effect transistor according to item 10. (Additional note 12) a drift region laminated between the substrate and a surface of the active cell; a body diffused on said surface; a source diffused within the body; a trench gate extending into the drift region and configured to adjust the conductivity of the drift region, the trench gate having an adjustable depth; a lateral gate positioned above the body at the surface and extending laterally between the source and the trench gate; A field effect transistor comprising: (Additional note 13) the lateral gate and the trench gate are electrically coupled; Item 13. The field-effect transistor according to item 12. (Additional note 14) the adjustable depth is configured to vary the output capacitance of the active cell as a function of the adjustable depth; Item 13. The field-effect transistor according to item 12. (Additional note 15) the trench gate extends into the substrate; Item 13. The field-effect transistor according to item 12. (Additional note 16) The field effect transistor is an N-channel field effect transistor. Item 13. The field-effect transistor according to item 12. (Additional note 17) The field effect transistor is a P-channel field effect transistor. Item 13. The field-effect transistor according to item 12. (Additional note 18) The field effect transistor is a silicon field effect transistor. Item 13. The field-effect transistor according to item 12. (Additional note 19) A cascode device, the cascode device comprising: a high voltage depletion type device; a low voltage metal-oxide field effect transistor electrically cascode coupled to said high voltage depletion mode device; Equipped with the low voltage metal-oxide field effect transistor at least one trench gate having a controllable depth, the controllable depth being varied to adjust an output capacitance of the low-voltage metal-oxide field effect transistor; at least one lateral gate configured to modulate a surface channel of the low voltage metal-oxide field effect transistor; Equipped with Cascode device. (Additional note 20) the high voltage depletion mode device is a gallium nitride high electron mobility transistor; Item 20. The cascode device according to item 19. (Additional note 21) the high voltage depletion mode device is a silicon carbide field effect transistor; Item 20. The cascode device according to item 19. (Additional note 22) the high voltage depletion mode device is a silicon carbide junction field effect transistor; Item 20. The cascode device according to item 19.

Claims

1. A lateral surface-gate vertical field effect transistor, comprising: A substrate; a drift region formed on the substrate; at least one active cell; Equipped with Each of the active cells is a trench extending into the substrate through the drift region, the trench including a trench gate oxide and a trench gate, the trench gate configured to adjust the conductivity of the drift region, the trench gate having a depth adjusted to at least partially determine an output capacitance of the active cell; a lateral gate located on a lateral gate oxide, the lateral gate configured to modulate a surface channel of the active cell, the trench gate and the lateral gate being electrically coupled such that a gate-to-source voltage is applied to both the lateral gate and the trench gate, the lateral gate oxide having a thickness between 10 nanometers and 25 nanometers, and the trench gate oxide having a thickness between 200 nanometers and 300 nanometers; Equipped with Lateral surface-gate vertical field-effect transistor.

2. the trench gate extends into the drift region; 2. The lateral front-gate vertical field effect transistor of claim 1.

3. the trench gate extending into the substrate; 2. The lateral front-gate vertical field effect transistor of claim 1.

4. the at least one active cell comprises a closed cell pattern; 2. The lateral front-gate vertical field effect transistor of claim 1.

5. a second trench extending through the drift region into the substrate, the second trench comprising a second trench gate oxide and a second trench gate configured to adjust the conductivity of the drift region.

2. The lateral front-gate vertical field effect transistor of claim 1.

6. the lateral gate is configured to produce an inversion region; 2. The lateral front-gate vertical field effect transistor of claim 1.

7. the trench gate is configured to create an accumulation region; 2. The lateral front-gate vertical field effect transistor of claim 1.

8. the substrate comprises a heavily doped N-type material; the drift region comprises lightly doped N-type material; 2. The lateral front-gate vertical field effect transistor of claim 1.

9. the lightly doped N-type material is graded; 9. The lateral front-gate vertical field effect transistor of claim 8.

10. A cascode device, the cascode device comprising: a high voltage depletion type device; a low voltage metal-oxide field effect transistor electrically cascode coupled to said high voltage depletion mode device; Equipped with The low voltage metal-oxide field effect transistor comprises a lateral front-gate vertical field effect transistor according to any one of claims 1 to 9. Cascode device.

11. the high voltage depletion mode device is a gallium nitride high electron mobility transistor; The cascode device of claim 10.

12. the high voltage depletion mode device is a silicon carbide field effect transistor; The cascode device of claim 10.

13. the high voltage depletion mode device is a silicon carbide junction field effect transistor; The cascode device of claim 10.

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