optoelectronic devices

Abstract

The present disclosure relates to an optoelectronic device (11) comprising a first circuit (13), a second circuit (15), and a conductive layer (17). The first circuit (13) comprises at least one light-emitting diode (LED) that emits light through a first surface (13i) of the first circuit and comprises first and second electrodes (23, 24). The second circuit (15) is used to control the light-emitting diode and is disposed on a second surface (13s) opposite the first surface of the first circuit and comprises first and second conductive pads (31). The conductive layer (17) is located at the interface between the first and second circuits and is divided into first and second portions in a direction perpendicular to the stack of the first and second circuits. The first electrode is electrically coupled to the first conductive pad via the first portion of the conductive layer, and the second electrode is electrically coupled to the second conductive pad via the second portion of the conductive layer.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to optoelectronic devices and methods of making the same, for example, to image display devices comprising light emitting diodes and methods of making the same. [Background technology]

[0002] It is known to form optoelectronic devices that include at least one light emitting diode and circuitry for controlling the light emitting diode.

[0003] Document US10468452 describes a method for manufacturing such devices, which includes simultaneously manufacturing a plurality of optoelectronic devices on the same substrate and separating the thus manufactured optoelectronic devices. A drawback of such a method is that it includes a step of forming electrodes covering the sides of the optoelectronic devices, which step may be difficult to implement. Summary of the Invention

[0004] There is a need for improved optoelectronic devices and methods for their manufacture.

[0005] SUMMARY OF THE INVENTION The embodiments overcome all or some of the drawbacks of known optoelectronic devices and methods for fabricating the same.

[0006] An embodiment provides an optoelectronic device comprising a stack of a first circuit and a second circuit, the first circuit comprising at least one inorganic light-emitting diode emitting light through a first surface of the first circuit and first and second electrodes, the second circuit for controlling the light-emitting diode being located on a second surface opposite the first surface of the first circuit and comprising first and second conductive pads, a conductive layer comprising a stack of a first conductive sublayer of the first circuit and a second conductive sublayer of the second circuit and located at an interface between the first circuit and the second circuit, the conductive layer being divided into a first portion and a second portion in a direction perpendicular to the stacking direction of the first circuit and the second circuit, the first electrode electrically coupled to the first conductive pad via the first portion of the conductive layer, and the second electrode electrically coupled to the second conductive pad via the second portion of the conductive layer.

[0007] According to an embodiment, the device comprises at least two connectors located on opposite sides of the second circuit from the first circuit for electrically coupling the device to an external object.

[0008] According to an embodiment, the first and second portions of the conductive layer are separated by an electrically insulating groove.

[0009] According to an embodiment, the first and second conductive pads are separated by said electrically insulating groove.

[0010] According to an embodiment, the second circuit comprises a metal oxide gate field effect transistor and comprises two parts electrically separated by said electrical isolation trench.

[0011] According to an embodiment, the portions of the second circuit are electrically coupled by connections made by conductive tracks located on the opposite side of the metal oxide gate field effect transistor from the first circuit.

[0012] According to an embodiment, the electrically insulating groove has a closed shape in a plane parallel to the second face.

[0013] According to an embodiment, the electrically insulating groove has, in a plane parallel to the second face, an open shape with its two free ends emerging at one or more side faces of the device.

[0014] According to an embodiment, the first circuit comprises a substrate on a first surface side.

[0015] According to an embodiment, the substrate is made of sapphire or glass.

[0016] According to an embodiment, the conductive layer is made of a metal or a conductive polymer.

[0017] According to an embodiment, the light emitting diode is wire-shaped or pyramidal-shaped.

[0018] An embodiment provides a structure comprising a plurality of optoelectronic devices as described above.

[0019] An embodiment provides a method of manufacturing a plurality of such optoelectronic devices, the method comprising step a) assembling a first wafer comprising a plurality of the first circuits to a second wafer comprising a plurality of the second circuits.

[0020] According to an embodiment, the assembling step a) is carried out by bringing the first and second sub-layers of the conductive layer into full plate contact.

[0021] According to an embodiment, in step b) prior to step a), each first circuit is partially etched to identify a first cavity at the location of the second electrode.

[0022] According to an embodiment, in a step b') prior to step a), each first circuit is partially etched to form a second cavity in which the edges of said light-emitting diode can be defined.

[0023] According to an embodiment, the method comprises, between step a) and step b) or step b'), a step c) of covering each light-emitting diode on the second face side of the first circuit with a dielectric layer having openings at the level of the first and second electrodes.

[0024] According to an embodiment, between step c) and step a), a first conductive sub-layer covers each light emitting diode on the second surface side of the first circuit.

[0025] According to an embodiment, before step a), each second circuit is covered with a second conductive sub-layer.

[0026] According to an embodiment, the assembly step a) is carried out by non-hybrid bonding of the first and second conductive sub-layers.

[0027] According to an embodiment, step a) is followed by a step d) of etching, for each optoelectronic device b, a trench in the second wafer, extending through the conductive layer down to the dielectric layer.

[0028] According to an embodiment, step d) is followed by a step of filling the trenches with an insulating material. [Brief explanation of the drawings]

[0029] These and other features and advantages are described in detail in the following particular embodiments, given as non-limiting illustrations of the invention with reference to the accompanying drawings, in which: [Figure 1A] 1 is a partial schematic cross-sectional view illustrating an embodiment of an optoelectronic device. [Figure 1B] 1B is a partial schematic cross-sectional view illustrating a variation of the optoelectronic device shown in FIG. 1A. [Figure 2] 1 is a partial schematic top view illustrating an embodiment of an optoelectronic device. [Figure 3] FIG. 10 is a partial schematic top view illustrating another embodiment of an optoelectronic device. [Figure 4]1A-1B illustrate steps of an embodiment of a method for manufacturing the device shown in FIG. 1A or 1B. [Figure 5] FIG. 4 illustrates another step of the method. [Figure 6] FIG. 4 illustrates another step of the method. [Figure 7] FIG. 4 illustrates another step of the method. [Figure 8] FIG. 4 illustrates another step of the method. [Figure 9] FIG. 4 illustrates another step of the method. [Figure 10] FIG. 4 illustrates another step of the method. [Figure 11] FIG. 4 illustrates another step of the method. [Figure 12] FIG. 4 illustrates another step of the method. [Figure 13] FIG. 4 illustrates another step of the method. [Figure 14] FIG. 14 is a detailed view of a portion of FIG. 13. [Figure 15] FIG. 4 illustrates another step of the method. [Figure 16] FIG. 4 illustrates another step of the method. [Figure 17] 1A and 1B show steps of another embodiment of a method for manufacturing the device shown in FIGS. [Figure 18] FIG. 4 illustrates another step of the method. DETAILED DESCRIPTION OF THE INVENTION

[0030] Similar features are designated by similar reference numerals in the various drawings. In particular, structural and / or functional features that are common among various embodiments may have the same reference numerals and may have identical structural, dimensional, and material characteristics.

[0031] For clarity, only those steps and elements useful for understanding the embodiments described herein are shown and described in detail, and in particular, the circuitry controlling the light emitting diodes of the optoelectronic devices is only briefly detailed.

[0032] Unless otherwise specified, when two elements are referred to as being connected, it means that they are directly electrically connected with no intermediate elements other than conductors, and when two elements are referred to as being coupled, it means that the two elements may be electrically connected or may be electrically coupled through one or more other elements.

[0033] In the following disclosure, unless otherwise specified, when referring to terms that qualify absolute positions such as "front," "back," "top," "bottom," "left," and "right," or terms that qualify relative positions such as "above," "below," "upper," and "lower," or terms that qualify orientations such as "horizontal" and "vertical," they refer to the orientations shown in the figures.

[0034] The terms "about," "approximately," "substantially," and "to the extent," unless otherwise specified, represent within 10% of the applicable value, preferably within 5%. The terms "about," "approximately," "substantially," and "to the extent," unless otherwise specified, represent within 10% of the applicable value, preferably within 5%.

[0035] Figure 1A shows a partial schematic cross-sectional view of an embodiment of an optoelectronic device 11, and Figure 1B shows a cross-sectional view of a variation of the optoelectronic device 11 of Figure 1A. Figure 2 is a partial schematic top view of the optoelectronic device 11 of Figure 1A.

[0036] 1A and 1B show some of the internal elements of device 11.

[0037] The device 11 comprises a first portion 13 and a second portion 15. The first portion 13, also called an optoelectronic circuit, comprises in particular at least one inorganic light emitting diode LED that emits radiation toward a bottom surface 13i of the first portion 13, and the first portion 13 further comprises a top surface 13s opposite the bottom surface 13i. The second portion 15, also called a logic circuit, comprises a circuit for controlling the light emitting diode LED and comprises a bottom surface 15i and a top surface 15s opposite the bottom surface 15i, the bottom surface 15i of the second portion 15 being the top surface 13s of the first portion 13.

[0038] 1A and 1B, device 11 comprises a layer 17 that is segmented horizontally, i.e., in the plane of top surface 13s, at the interface between optoelectronic circuitry 13 and logic circuitry 15. Layer 17 comprises a stack of a first sub-layer 173 located in optoelectronic circuitry 13 and a second sub-layer 175 located in logic circuitry 15. As will be described in more detail below, in the orientation of FIG. 1A, layer 17 is split horizontally, i.e., in the plane of top surface 13s, into two parts.

[0039] Layer 17 is made of an electrically conductive material, such as a metallic material or a conductive polymer. Preferably, layer 17 is made of titanium, aluminum, nickel, silver, copper, gold, or an alloy or combination of all or part of these materials.

[0040] The upper surface of the sub-layer 173 corresponds to the upper surface 13 s of the optoelectronic circuit 13 , and the lower surface of the sub-layer 175 corresponds to the lower surface 15 i of the logic circuit 15 .

[0041] The light emitting diode LED of the optoelectronic circuit 13 comprises, according to the embodiment shown in FIGS. 1A and 1B, at least two semiconductor layers of opposite conductivity type, defining for example a PN junction.

[0042] Thus, the light emitting diode LED comprises a semiconductor layer 19 of a first conductivity type (for example, N-type) and a semiconductor layer 21 of a second conductivity type (for example, P-type) different from the first conductivity type. 15 ~10 20 dopant / cm 3The layer 19 may have a dopant concentration in the range of 10 nm to 2 μm and a thickness in the range of 5 nm to 2 μm. 17 ~10 20 dopant / cm 3 The layers 19 and 21 may have a dopant concentration in the range of 100 nm to 2 μm and a thickness in the range of 50 nm to 2 μm. The layers 19 and 21 may be made of, for example, a III-V compound or a II-VI compound, such as GaN (gallium nitride). Each of the layers 19 and 21 may have a single-layer structure or a multi-layer structure.

[0043] The light-emitting diode LED of the optoelectronic circuit 13 further comprises an active layer 25 located between the layer 19 and the layer 21. The active layer 25 is the layer in which most of the radiative coupling that causes the light emission of the light-emitting diode LED occurs. The active layer 25 has, for example, a multiple quantum well structure.

[0044] According to the embodiment shown in FIGS. 1A and 1B, layer 19 rests on substrate 27. More specifically, layer 19 completely covers the top surface of substrate 27. Substrate 27 may correspond to the growth substrate of the material forming layer 19 and may be made of, for example, sapphire. Alternatively, substrate 27 may correspond to a transfer substrate, such as a glass transfer substrate for replacing a silicon growth substrate. Layer 25 preferably covers layer 19 and is covered by layer 21. Layer 17 covers layer 21. The side edges of layers 21 and 25 may exhibit recesses 26 relative to layer 19. Device 11 further comprises conductive vias 28 that traverse layers 21 and 25, are electrically insulated from layers 21 and 25, and electrically couple sublayer 173 of layer 17 to layer 19. According to another embodiment, conductive vias 28 are located at the edges of layers 21 and 25. Sublayer 173 has a thickness of, for example, greater than 1.5 μm. 1A and 1B show via 28 stopping at the top surface of layer 19. Alternatively, via 28 may extend into layer 19 over part of its thickness.

[0045] The optoelectronic circuit 13 further comprises a first electrode 23 (e.g., an anode of an LED) disposed on the layer 21 so as to contact the layer 21, and a second electrode 24 (e.g., a cathode of an LED) corresponding to the contact portion of the via 28 and the layer 19.

[0046] The first electrode 23 is made of, for example, a metal material such as nickel, silver, gold, aluminum, copper, or titanium, or an alloy or combination of all or part of these materials. The first electrode 23 has a thickness in the range of, for example, 200 nm to 900 nm. The first electrode 23 may have a single-layer structure or a multi-layer structure.

[0047] 1A and 1B, the optoelectronic circuit 13 further comprises a dielectric layer 29. The dielectric layer 29 preferably covers the contour of the first electrode 23, the part of layer 21 not covered by the first electrode 23, the lateral edges of layers 21, 25 at the level of the via 28 and the recess 26, layer 19 at the level of the recess 26 and only a part of layer 19 at the level of the via 28. The dielectric layer 29 serves not only as an electrical insulator but also as a passivation of the lateral edges of the active layer 25, which may in particular comprise a quantum well.

[0048] The layer 29 has a thickness for example in the range 0.1 μm to 1 μm and is made of a dielectric material such as silicon nitride or silicon dioxide, or a combination of these two materials.

[0049] In the embodiment shown in Figures 1A and 1B, the light-emitting diode has a so-called planar structure, since it corresponds to a stack of layers. According to other specific embodiments, the optoelectronic circuit 13 may comprise one or more three-dimensional light-emitting diodes, for example in the form of a wire or a pyramid. In particular, the light-emitting diode LED may comprise one or more three-dimensional semiconductor elements, for example nanowires or microwires, each of which is of a first conductivity type and is covered by an active region, which in turn is covered by a semiconductor element of a second conductivity type. Electrodes 23 may contact the semiconductor elements of the second conductivity type, and the semiconductor elements of the first conductivity type may be mounted on a conductive layer that contacts vias 28.

[0050] Logic circuit 15 comprises a region 33, referred to as MOS circuitry, which comprises a first portion 331, which comprises a substrate having insulated gate field effect transistors (also referred to as MOS transistors) formed therein and thereon. The substrate may correspond to a semiconductor substrate or may have a silicon-on-insulator (SOI) structure. MOS circuit 33 further comprises an interconnect network 333, which is located between first portion 331 and layer 17 and comprises a stack of insulating layers with conductive tracks and conductive vias passing therebetween. In particular, first interconnect network 333 comprises conductive pads 31 and 32.

[0051] The logic circuit 15 further comprises a second interconnection network 30, which is located on the opposite side of the MOS circuit 33 from the optoelectronic circuit 13 and may extend through the MOS circuit 33.

[0052] Pads 32 are for electrically coupling MOS circuitry 33 to interconnect network 30. Pads 31 are each for electrically coupling to an electrode of a light emitting diode of optoelectronic circuit 13 through layer 17. Conductive pads 31, 32 are preferably made of titanium, aluminum, silver, nickel, copper, gold, or alloys or combinations of all or part of these materials.

[0053] The device 11 further comprises an electrical insulating structure 39. The electrical insulating structure 39 comprises an electrical insulating groove 391 capable of ensuring horizontal electrical insulation, i.e. insulation between two parts of the MOS circuit 33 and between two parts of the layer 17 in a plane parallel to the face 15i. Optionally, the electrical insulating structure 39 covers the MOS circuit 33 on its side opposite the optoelectronic circuit 13 and comprises an insulating layer 393 of the same composition as the insulating groove 391.

[0054] Preferably, insulating layer 393 is located at the interface with MOS circuit 33 in interconnect network 30. Layer 393 and trench 391 may have a multi-layer or single-layer structure. Preferably, all or part of layer 393 and trench 391 are made of a dielectric material. By way of example, electrically insulating trench 391 may comprise an electrically insulating wall and a core made of a filling material, such as a conductive or semiconducting material. For illustrative purposes, insulating trench 391 is shown in FIGS. 2 and 3 .

[0055] 1A , trench 391 extends from the top surface of MOS circuit 33, through MOS circuit 33 and layer 17, and emerges above dielectric layer 29. Trench 391 may be filled with a material having a multi-layer or single-layer structure. Preferably, trench 391 is filled with a dielectric material.

[0056] Preferably, there is at least one pad 31 on each side of the groove 391 .

[0057] 2, groove 391 has an open shape that appears on at least one side of device 11, here two sides of device 11. Groove 391 insulates, among other things, lateral portions of MOS circuitry 33 and lateral portions of conductive layer 17 that are coupled to second electrode 24 of the light-emitting diode. By way of example, in the orientation of FIG. 2, groove 391 is "L" shaped and appears on the top side of device 11 and on the right side of device 11.

[0058] 1A and 1B, the interconnect network 30 comprises a stack of insulating layers 37 covering the MOS circuit 33 on its side opposite the optoelectronic circuit 13, the stack including a layer 393 in which, if present, conductive elements, in particular conductive tracks 35 and conductive vias 36, are formed inside and through the layer 393. According to an embodiment, each conductive via 36 is connected to one track, for example one pad 32, of the first interconnect network 333 and may therefore extend through the first portion 331.

[0059] According to an embodiment, there are conductive elements 35, 35 on each side of the electrically insulating groove 391. These elements on each side of the electrically insulating groove 391 may be electrically coupled by a single conductive track 35, for example, as shown in FIG.

[0060] According to the embodiment shown in FIGS. 1A and 1B, logic circuit 15 further comprises connectors 41, at least one of which is coupled to first electrode 23 and at least one of which is coupled to layer 19.

[0061] By way of example, connector 41 may be made from titanium, aluminum, silver, nickel, copper, gold, tin, a tin-silver alloy, or a combination or alloy of all or part of these materials.

[0062] According to the embodiment shown in FIG. 1A, the connectors 41 may be located on both sides of the insulating groove 391. However, the position of the connectors 41 does not depend on the position of the electrical insulating groove 391. Also, since the connectors 41 are not necessarily aligned with the conductive vias 36, the connectors 41 may be located on the same side of the insulating groove 391, as shown in FIG. 1B. The conductor 35 may, for example, couple the connector 41 located on one side of the insulating groove 391 and the conductive vias 36 located on the other side of the groove 391. Furthermore, as shown in FIG. 1B, the conductor 35 may electrically couple the two conductive vias 36 located on both sides of the insulating groove 391 and electrically couple the pads 32 of the first interconnect network 333 of the MOS circuit 33. The conductive tracks 35 may also serve as a redistribution layer, also called a RDL, i.e., correspond to an additional metal layer covering the MOS circuit 33, electrically coupling the connectors 41 to other locations on the MOS circuit 33 and, in particular, relieving the positioning constraints of the connectors 41. The conductive tracks 35 make it possible to electrically couple, in particular, the connectors 41 located on the part of the MOS circuit 33 located on one side of the groove 391 to the part of the MOS circuit 33 located on the other side of the groove 391 .

[0063] According to an embodiment not shown, the MOS circuit 33 comprises transistors on only one side of the isolation trench 391. The pads 31 located in the part of the MOS circuit 33 that does not comprise transistors are then coupled to the second interconnection network 30 without any intermediate connection by a MOS transistor.

[0064] FIG. 3 shows a top view of a variant of the device 11 shown in FIG.

[0065] According to the embodiment shown in FIG. 3, the groove 391 has a ring shape in top view, as it follows a closed curve, and therefore in particular isolates the central island of the MOS circuit 33 from the central island of the conductive layer 17 coupled to the second electrode 24 of the light-emitting diode.

[0066] 4-16 illustrate steps in an embodiment of a method for manufacturing device 11 shown in FIGS. 1A and 1B.

[0067] 4 to 7 are schematic partial cross-sectional views of structures obtained in successive steps of an embodiment of a method for manufacturing a wafer comprising a plurality of optoelectronic circuits 13 as shown in FIG. 1A and / or FIG. 1B.

[0068] FIG. 4 shows an initial structure 45 on which a number of devices 11 are formed.

[0069] Structure 45 comprises, from bottom to top in the orientation of FIG. 4, substrate 27, layer 19, active layer 25, and layer 21.

[0070] The substrate 27 corresponds to a circular semiconductor wafer, for example, preferably having a diameter of the order of 150 mm, 200 nm, or 300 nm. The layers 19, 25, 21 are all formed as full plates so as to cover substantially the entire top surface of the substrate 27.

[0071] FIG. 5 shows a structure 47 obtained by forming a first electrode 23 for each device 11 on the top surface of the structure 45 shown in FIG.

[0072] The material forming the first electrode 23 is deposited, for example, in a full plate and then etched for each device 11, leaving the first electrode 23 only in the desired area. The electrode 23 is formed, for example, by a lift-off technique. This technique involves depositing a resin layer, forming a pattern in the resin layer, and then depositing a metal layer over the entire structure, particularly the resin pattern. The resin is then dissolved in a solvent and removed, along with the metal parts covering the resin pattern. The metal deposition is carried out, for example, by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0073] FIG. 6 shows the structure 49 obtained at the end of the steps of etching and depositing an insulating layer 29 on top of the structure 47 shown in FIG.

[0074] In the step shown in FIG. 6, for each device 11, the structure 47 is etched to form openings 261, 281 along a height h1 that is equal to or greater than the sum of the thicknesses of layers 21 and 25, for example, on the order of 0.5 μm. In addition to layers 21 and 25, portions of layer 19 facing openings 261 and 281 may also be etched during this etching step. Only two openings 261 and one opening 281 are shown in FIG. 6. Opening 261 is located where a cutting operation for device 11 will be performed in a subsequent step. Opening 281 is located at the location of via 28.

[0075] In the cross-sectional plane of FIG. 6, the opening 261 has a width l1 of, for example, about 50 μm, and the opening 281 has a width l2 of, for example, about 10 μm.

[0076] An insulating layer 29 is preferably deposited on the surface of the structure obtained upon completion of etching of the openings 261, 281 so as to cover the upper surface of the layer 21, the upper surface of the electrode 23, the side edges of the openings 261, 281, and the bottom of the openings 261, 281. The thickness of the layer 29 is, for example, about 1 μm.

[0077] Next, insulating layer 29 is etched, for example by wet or dry etching, to expose a portion of electrode 23 and a portion of layer 19 for each device 11. This etching exposes layer 19 in opening 281 over a width l3 of, for example, about 5 μm in the cross-sectional plane of FIG.

[0078] Figure 7 shows the structure 50 obtained at the end of the step of depositing a conductive layer 51 on top of the structure 49 shown in Figure 6 to form the conductive sub-layer 173 and the vias 28. In this way, a wafer comprising a plurality of optoelectronic circuits 13 is obtained.

[0079] Conductive layer 51 is preferably deposited over the entire top surface of structure 49 such that conductive layer 51 covers insulating layer 29 and contacts electrode 23, and contacts semiconductor layer 19 in opening 281. Conductive layer 51 further extends in opening 261.

[0080] At the end of the step of depositing the conductive layer 51, the structure is optionally planarized by chemical mechanical polishing (CMP).

[0081] 8 shows structure 52. Structure 52 comprises, from top to bottom in the orientation of FIG. 8, substrate 53 and sublayer 175.

[0082] The substrate 53 preferably comprises a plurality of MOS circuits 33 and an area 55 that is free of any electronic components.

[0083] Substrate 53 is, for example, a semiconductor wafer with electronic components formed thereon and therein. Substrate 53 preferably has a diameter on the order of 100 mm, 200 mm, or 300 mm. MOS circuitry 33 forms the bottom portion of substrate 53 in the orientation of FIG. 8, and region 55 is the top portion of substrate 53 in the orientation of FIG. 8.

[0084] Sublayer 175 has a thickness of, for example, greater than 500 nm.

[0085] Optionally, in order to planarize the underside of the structure 52, and more precisely the underside of the sub-layer 175, the latter may be subjected to chemical mechanical polishing CMP.

[0086] FIG. 9 shows the structure 57 obtained at the end of the assembly steps of the structure 50 shown in FIG. 7 and the structure 52 shown in FIG.

[0087] Structure 52 is transferred onto the upper surface of structure 50. More precisely, lower surface 175i of sublayer 175 of structure 52 is transferred onto upper surface 173s of sublayer 173 of structure 50. The step of transferring structure 52 onto structure 50 preferably includes a substep of aligning MOS circuitry 33 so that it is aligned with opening 261.

[0088] According to an embodiment, the bonding of sublayer 173 and sublayer 175 is performed by a non-hybrid conductive bond, i.e., the surfaces of the contacting sublayers are planar, continuous, and made of a single material. The materials forming the two sublayers are the same. Thus, layers 173 and 175 are bonded to each other without any bonding material.

[0089] FIG. 10 shows the structure 59 obtained at the end of the thinning step of the structure 57 shown in FIG.

[0090] Thinning of structure 57 shown in FIG. 9 is performed from the top surface to remove region 55 of substrate 53, leaving only MOS circuitry 33 in substrate 53.

[0091] Figure 11 shows the structure 61 obtained at the end of the step of forming grooves 63 in the structure 59 shown in Figure 10. In Figure 11, a single groove 63 is shown.

[0092] Preferably, trench 63 extends from the top surface of structure 61 through MOS circuitry 33, sublayer 175, and sublayer 173 to expose the top surface of insulating layer 29.

[0093] Groove 63 is preferably formed by two successive dry or wet etches, one allowing etching through different layers of MOS circuitry 33 and the other allowing etching through sublayers 173 and 175. Insulating layer 29 can act as an etch stop layer during the formation of groove 63.

[0094] Preferably, a single groove 63 is formed by device 11, i.e., each opening 261 surrounds a single groove 63. Each groove 63 is intended to become an insulating groove 391 as shown in Figures 1A, 1B, and 2. Thus, all grooves 63 have the same shape as insulating groove 391.

[0095] The groove 63 preferably has a width 14 of about 5 μm in the cross-sectional plane of FIG.

[0096] FIG. 12 shows the structure 65 obtained at the end of the step of forming insulating structures 39 on the top surface of structure 61 and in trenches 63 .

[0097] The insulating structure 39, comprising the insulating layer 393 and the insulating trench 391, is preferably formed by successive deposition of two layers 67 and 69. The layer 67 is an insulating layer and is deposited, for example, on the top surface of the structure 61 shown in Figure 11 so that the layer 67 covers the top surface of the MOS circuit 33 and the sides and bottom of the opening 63. The layer 67 is preferably conformal and is deposited by a vapor deposition technique.

[0098] Layer 69 is preferably deposited to completely cover layer 67. For example, layer 69 fills trench 391. Layer 69 may be an insulating layer or a layer of fill material, such as polysilicon.

[0099] Figure 13 shows, for each device 11, a structure 71 obtained at the end of the steps of forming a stack of insulating layers 37, conductive tracks 35, and conductive vias 36 on top of and within the structure 65 shown in Figure 12. Figure 13 shows very schematically the electronic connections of the tracks 35 to one or more metallizations of the MOS circuitry 33, schematized in Figure 13 by pads 32 and vias 36. Figure 14 is an enlarged view of a portion 73 of the structure 71.

[0100] According to an embodiment, the pads 32 correspond to tracks of one of the levels of metallization of the MOS circuit 33, preferably of the first level. To reach the tracks 32, each via 36 traverses, for example, layer 37 and a first portion 331 of the MOS circuit 33.

[0101] The formation of the vias 36 preferably includes an etching step that allows the portion 331 of the MOS circuit 33 to be etched over a thickness in the range of 3 μm to 5 μm. The vias 36 preferably each have a width l5 of more than 6 μm. At the end of the etching step, the deposition of an insulating layer 81, for example of silicon dioxide, is carried out, for example by plasma-enhanced chemical vapor deposition (PECVD). The layer 81 preferably has a thickness of the order of 0.5 μm. At the end of the deposition step of the layer 81, the latter is etched so as to expose a part of the upper surface of the pad 32 (or of the pad 31, if the MOS circuit 33 does not comprise a transistor on one side of the insulating trench 391) at the bottom of the opening formed in the MOS circuit 33. The etching of the layer 81 makes it possible to expose the pad 32 along a length l6 of more than 3 μm. After the etching step of the layer 81, a metal layer 83 is deposited, for example made of aluminum, tungsten, copper, or a combination or alloy of these two materials. The layer 83 is preferably deposited by physical vapor deposition. Layer 83 therefore covers layer 81 and contacts pad 32. Layer 83 preferably has a thickness of the order of 1 μm. Layer 83 is then etched away, leaving only enough to form vias 36 and, optionally, conductive tracks 35, as shown in FIG.

[0102] FIG. 15 shows the structure 85 obtained at the end of the step of forming the connectors 41 on top of the structure 71 shown in FIG.

[0103] Connectors 41 are formed in contact with tracks 35. Preferably, for each device, at least one connector 41 is bonded to an electrode 23 and at least one connector 41 is bonded to layer 19.

[0104] FIG. 16 shows a number of devices 11 obtained at the end of the cutting step of the structure 85 shown in FIG.

[0105] The structure 85 shown in FIG. 15 is sawed to form grooves 87 with a blade having a thickness of, for example, about 40 μm.

[0106] The grooves 87 are through and allow the structure 85 to be cut into unit devices 11. For example, the grooves 87 extend through the logic circuitry 15 and the optoelectronic circuitry 13 at the openings 261. Before the sawing step of the structure 85, a step of thinning the substrate 27 over a thickness of the order of 300 μm may be carried out.

[0107] 17 and 18 are partial schematic cross-sectional views of structures obtained at steps of another embodiment of a method for manufacturing a variant of the optoelectronic device 11 shown in FIG. 1A.

[0108] More specifically, Figure 17 shows a structure 89 obtained at the end of the step of forming grooves 91 in the structure 61 shown in Figure 11. Grooves 91 may be formed at the same time as grooves 63.

[0109] Trench 91 preferably extends from the top surface of structure 89 into structure 89. Trench 91 preferably extends through MOS circuitry 33, sublayer 175, and sublayer 173, exposing layer 29 at opening 261. Trench 91 preferably has the same dimensions and shape in top view as opening 261. In other words, in this step, the layer below layer 29 is removed vertically along opening 261.

[0110] FIG. 18 shows the resulting structure 93 at the end of the steps of depositing an insulating layer 95 and forming a conductive region 97 on the top surface of the structure 93 .

[0111] The insulating layer 95 is preferably a silicon dioxide layer. The insulating layer 95 is preferably deposited by PECVD to a thickness of the order of 1 μm. Openings 99 are then etched into the insulating layer 95. The structure 93 preferably includes at least one opening 99 on each side of the trench 63. For example, the openings 99 each have a width 17 of greater than 3 μm.

[0112] The metal region 97 is preferably made of aluminum, copper, or a combination or alloy of these two materials. The metal region 97 may have a single layer structure or a multi-layer structure. The region 97 is preferably formed to extend in the opening 99. The region 97 is preferably formed over a width 18 of greater than 10 μm.

[0113] Region 97 is preferably connected to metal tracks of MOS circuitry 33 as well, for example in a manner similar to that described above with reference to FIG.

[0114] At the end of this step, a connector (not shown in FIG. 18) similar to connector 41 shown in FIG. 15 will be formed within and contacting region 97.

[0115] An advantage of the above embodiments and implementations is that the logic circuitry 15 and the optoelectronic circuitry 13 can be bonded at relatively low temperatures (ie, below 250°C), limiting the risk of damage to the materials forming the optoelectronic circuitry.

[0116] Another advantage of the above embodiments and implementations is that the reliability of the bond between the logic circuit 15 and the optoelectronic circuit 13 can be increased compared to hybrid bonds based on contact pads, for example.

[0117] Furthermore, a further advantage of the above-described embodiments and implementations is that the light-emitting diode substrate and the control circuit substrate can be assembled with less constraints on positioning accuracy than hybrid bonding.

[0118] Yet another advantage of the above embodiments and implementations is that there are no restrictions on the electrical connection between the circuit 15 and the circuit 13, compared to document US10468452.

[0119] Yet another advantage of the above embodiments and implementations is that the useful surface area of ​​LEDs formed on the same growth surface can be maximized.

[0120] A further advantage of the above embodiments and implementations is that the risk of damaging the substrate 27 can be limited, given that the insulating grooves 391 do not extend all the way to the substrate 27 .

[0121] An advantage of the above embodiments and implementations is that they are compatible with regular component production lines for microelectronics.

[0122] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations are also contemplated. In particular, in the above-described embodiment, molecular bonding between sublayer 173 and sublayer 175 can be performed, the planarity of surface 13s of sublayer 173 can be achieved by an optional planarization step performed after deposition of sublayer 173, and the planarity of surface 15i of sublayer 175 can be achieved by an optional planarization step performed after deposition of sublayer 175. Alternatively, the planarity of surface 13s of sublayer 173 can be achieved as follows: before forming sublayer 173, an electrically insulating planarization layer, e.g., oxide, is deposited on the underlying structure, vias are formed across this insulating planarization layer, and sublayer 173 is deposited on the planarization layer to contact the vias, so that sublayer 173 directly has the desired planarization characteristics. Formation of the insulating planarization layer can include deposition of at least one insulating layer followed by a planarization step, e.g., by CMP. Similarly, the planarity of surface 15i of sublayer 175 may be obtained as follows: before sublayer 175 is formed, an electrically insulating planarizing layer, e.g., oxide, is deposited on the underlying structure, vias are formed across this insulating planarizing layer, and then sublayer 175 is deposited on the planarizing layer and contacts the vias, so that sublayer 175 directly has the desired planarization properties.

[0123] Finally, practical implementation of the above embodiments and variations is within the capabilities of those skilled in the art based on the functional representations provided herein.

[0124] This patent application claims priority from French Patent Application No. 20 / 10001, which is incorporated herein by reference.

Claims

1. 1. An optoelectronic device comprising: a stack of a first circuit and a second circuit; the first circuit comprises at least one inorganic light emitting diode emitting light through a first surface of the first circuit and comprising first and second electrodes; the second circuit is for controlling the light emitting diode, is disposed on a second surface opposite the first surface of the first circuit, and includes first and second conductive pads; a conductive layer comprising a stack of a first conductive sub-layer of the first circuit and a second conductive sub-layer of the second circuit, the conductive layer being located at an interface between the first circuit and the second circuit, the conductive layer being divided into a first portion and a second portion in a direction perpendicular to a stacking direction of the first circuit and the second circuit; the first electrode is electrically coupled to the first conductive pad through the first portion of the conductive layer, and the second electrode is electrically coupled to the second conductive pad through the second portion of the conductive layer; the first and second conductive portions of the conductive layer being separated by an electrically insulating groove; Optoelectronic devices.

2. at least two connectors located on the second circuit opposite the first circuit for electrically coupling the device to an external object; The device of claim 1 .

3. the first and second conductive pads are separated by the electrically insulating groove; 3. A device according to claim 1 or 2.

4. the second circuit comprises a metal oxide gate field effect transistor and has two portions electrically separated by the electrical isolation trench; A device according to any one of claims 1 to 3.

5. the two portions of the second circuit being electrically coupled by connections made by conductive tracks located on the opposite side of the metal oxide gate field effect transistor from the first circuit; The device of claim 4.

6. the electrically insulating groove has a closed shape in a plane parallel to the second surface; A device according to any one of claims 1 to 5.

7. the electrically insulating groove has an open shape in a plane parallel to the second surface, the two free ends of which emerge on one or more side surfaces of the device; A device according to any one of claims 1 to 5.

8. the first circuit includes a substrate on the first surface side; A device according to any one of claims 1 to 7.

9. The substrate is made of sapphire or glass. The device of claim 8.

10. The conductive layer is made of a metal or a conductive polymer. A device according to any one of claims 1 to 9.

11. The light emitting diode is wire-shaped or pyramidal-shaped. A device according to any one of claims 1 to 10.

12. The first conductive sublayer covers the entire first electrode. A device according to any one of claims 1 to 11.

13. A structure comprising a plurality of optoelectronic devices according to any one of claims 1 to 12.

14. A method for manufacturing an optoelectronic device according to any one of claims 1 to 12, comprising: a) combining a first wafer comprising a plurality of the first circuits with a second wafer comprising a plurality of the second circuits; method.

15. Step a) is performed by contacting the first and second sub-layers of the conductive layer in the absence of a bonding material; 15. The method of claim 14.

16. In step b) before step a), each first circuit is partially etched to form a first cavity at the position of the second electrode; 16. The method of claim 14 or 15.

17. In step b') before step a), each first circuit is partially etched to form a second cavity capable of defining an edge of the light-emitting diode; The method according to any one of claims 14 to 16.

18. Between step a) and step b) or step b'), step c) is included of covering each light-emitting diode on the second surface side of the first circuit with a dielectric layer having openings at the level of the first and second electrodes, 18. The method of claim 16 or 17.

19. between step c) and step a), covering each light emitting diode on the second surface side of the first circuit with the first conductive sub-layer; 20. The method of claim 18.

20. before step a), covering each second circuit with the second conductive sub-layer; 20. The method of claim 19.

21. Step a) is performed by non-hybrid bonding of the first conductive sub-layer and the second conductive sub-layer; 21. The method of claim 20.

22. Step a) is followed by step d) for each optoelectronic device, etching a trench in the second wafer through the conductive layer down to the dielectric layer; The method according to any one of claims 18 to 21.

23. Step d) is followed by a step of filling said grooves with an insulating material.

23. The method of claim 22.

Images