SiC semiconductor device

Abstract

This SiC semiconductor device comprises: a SiC chip that includes a first surface, a second surface recessed outside the first surface to a first depth in the thickness direction, and a connection surface connecting the first surface and the second surface, and that has a main surface the plateau of which is partitioned by the first surface, the second surface, and the connection surface; a transistor structure that includes a trench gate structure having a second depth less than the first depth, and a trench source structure having a third depth exceeding the second depth and adjacent to the trench gate structure in one direction, and that is formed in the inner portion of the first surface; and a dummy structure that includes a plurality of dummy trench source structures each having the third depth and adjacent to each other in one direction, and is formed on the peripheral edge of the first surface.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-131043 filed with the Japan Patent Office on July 31, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a SiC semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a trench gate structure formed in the semiconductor substrate, and a trench source structure formed in the semiconductor substrate adjacent to the trench gate structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2017 / 0040423 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a SiC semiconductor device that can improve reliability. [Means for solving the problem]

[0005] One embodiment of the present invention provides a SiC semiconductor device including: an SiC chip having a main surface including a first surface, a second surface recessed by a first depth in the thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, including a trench gate structure having a second depth less than the first depth and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; and a dummy structure formed in a peripheral portion of the first surface, including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction.

[0006] One embodiment of the present invention provides a SiC semiconductor device including: an SiC chip having a main surface including a first surface, a second surface recessed by a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, including a trench gate structure having a second depth less than the first depth and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; and a dummy structure formed in a peripheral portion of the first surface, including a dummy trench gate structure having the second depth and a dummy trench source structure having the third depth and adjacent to the dummy trench gate structure in the one direction.

[0007] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a SiC semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, omitting the internal structure of the SiC chip. [Figure 3] FIG. 3 is a plan view showing the first main surface of the SiC chip shown in FIG. 1, with the internal structure of the SiC chip omitted. [Figure 4] FIG. 4 is a simplified plan view showing the structure in which the first main surface shown in FIG. 3 is built into an SiC chip. [Figure 5] FIG. 5 is an enlarged plan view of a main part of the first main surface shown in FIG. [Figure 6] FIG. 6 is an enlarged plan view of the end portion of the transistor region shown in FIG. [Figure 7] FIG. 7 is an enlarged plan view of the inner part of the transistor region shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. [Figure 13] FIG. 13 is an enlarged plan view of a corner of the first peripheral region shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. [Figure 16] FIG. 16 is an enlarged plan view of the end portion of the first peripheral region shown in FIG. [Figure 17] FIG. 17 is an enlarged plan view of the inner part of the first peripheral region shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. [Figure 20]FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. [Figure 23] 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. [Figure 25] 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. [Figure 26] 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. [Figure 27] FIG. 27 is a plan view for explaining the structure of the principal surface electrodes. [Figure 28] FIG. 28 is a plan view illustrating the structure of the second inorganic insulating film. [Figure 29A] FIG. 29A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 29B] FIG. 29B is a cross-sectional view showing a step subsequent to that of FIG. 29A. [Figure 29C] FIG. 29C is a cross-sectional view showing a step subsequent to FIG. 29B. [Figure 29D] FIG. 29D is a cross-sectional view showing a step subsequent to FIG. 29C. [Figure 29E] FIG. 29E is a cross-sectional view showing a step subsequent to FIG. 29D. [Figure 29F] FIG. 29F is a cross-sectional view showing a step subsequent to FIG. 29E. [Figure 29G] FIG. 29G is a cross-sectional view showing a step subsequent to FIG. 29F. [Figure 29H] FIG. 29H is a cross-sectional view showing a step subsequent to FIG. 29G. [Figure 29I] FIG. 29I is a cross-sectional view showing a step subsequent to FIG. 29H. [Figure 29J] FIG. 29J is a cross-sectional view showing a step subsequent to FIG. 29I. [Figure 29K] FIG. 29K is a cross-sectional view showing a step subsequent to FIG. 29J. [Figure 29L] FIG. 29L is a cross-sectional view showing a step subsequent to FIG. 29K. [Figure 29M] FIG. 29M is a cross-sectional view showing a step subsequent to FIG. 29L. [Figure 29N] FIG. 29N is a cross-sectional view showing a step subsequent to FIG. 29M. [Figure 29O] FIG. 29O is a cross-sectional view showing a step subsequent to FIG. 29N. [Figure 29P] FIG. 29P is a cross-sectional view showing a step subsequent to that shown in FIG. 29O. [Figure 29Q] FIG. 29Q is a cross-sectional view showing a step subsequent to FIG. 29P. [Figure 29R] FIG. 29R is a cross-sectional view showing a step subsequent to FIG. 29Q. [Figure 29S] FIG. 29S is a cross-sectional view showing a step subsequent to FIG. 29R. [Figure 29T] FIG. 29T is a cross-sectional view showing a step subsequent to FIG. 29S. [Figure 29U] FIG. 29U is a cross-sectional view showing a step subsequent to FIG. 29T. [Figure 29V] FIG. 29V is a cross-sectional view showing a step subsequent to FIG. 29U. [Figure 30] FIG. 30 corresponds to FIG. 5 and is a plan view showing a SiC semiconductor device according to a first reference preferred embodiment. [Figure 31A] FIG. 31A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 31B] FIG. 31B is a cross-sectional view showing a step subsequent to that shown in FIG. 31A. [Figure 31C] FIG. 31C is a cross-sectional view showing a step subsequent to FIG. 31B. [Figure 31D] FIG. 31D is a cross-sectional view showing a step subsequent to FIG. 31C. [Figure 32]FIG. 32 corresponds to FIG. 6 and is a plan view showing a SiC semiconductor device according to a second reference preferred embodiment. [Figure 33] 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. [Figure 34] FIG. 34 corresponds to FIG. 6 and is a plan view showing the SiC semiconductor device according to the second embodiment of the present invention. [Figure 35] FIG. 35 is a cross-sectional view taken along the line XXXV-XXXV shown in FIG. [Figure 36] 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in FIG. [Figure 37] FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in FIG. [Figure 38] FIG. 38 corresponds to FIG. 16 and is a plan view showing the SiC semiconductor device shown in FIG. [Figure 39] FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in FIG. [Figure 40] FIG. 40 is a cross-sectional view taken along the line XL-XL shown in FIG. [Figure 41] FIG. 41 is a cross-sectional view taken along line XLI-XLI shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Fig. 1 is a plan view showing a SiC semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, omitting the internal structure of a SiC chip 2. Fig. 3 is a plan view showing a first main surface 3 of the SiC chip 2 shown in Fig. 1, omitting the internal structure of the SiC chip 2.

[0010] 1 to 3, in this embodiment, the SiC semiconductor device 1 is an electronic component including a SiC chip 2 made of a hexagonal SiC (silicon carbide) single crystal. In addition, in this embodiment, the SiC semiconductor device 1 is a semiconductor switching device including a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor). The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the SiC chip 2 is made of a 4H-SiC single crystal, but other polytypes are not excluded.

[0011] The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 is a device surface on which functional devices are formed. The second main surface 4 is a non-device surface on which no functional devices are formed. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from their normal direction Z (hereinafter simply referred to as "planar view"). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a planar view.

[0012] The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The c-plane includes the silicon plane ((0001) plane) and the carbon plane ((000-1) plane) of the SiC single crystal. Preferably, the first main surface 3 faces the silicon plane, and the second main surface 4 faces the carbon plane. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction relative to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not greater than 10°. The off-angle is preferably not greater than 5°. It is particularly preferable that the off-angle be 2° or greater and 4.5° or less.

[0013] The second main surface 4 may be a rough surface having either or both of grinding marks and annealing marks (specifically, laser irradiation marks). The annealing marks may include amorphous SiC and / or SiC (specifically, Si) silicided (alloyed) with a metal. The second main surface 4 is preferably an ohmic surface having at least annealing marks.

[0014] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal. That is, the first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal, and the third side surface 5C and the fourth side surface 5D are formed by the m-plane of the SiC single crystal. The first to fourth side surfaces 5A to 5D form the periphery of the first main surface 3 and the periphery of the second main surface 4, respectively.

[0015] The first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks formed by cutting with a dicing blade, or may be cleaved surfaces having modified layers formed by laser light irradiation. Specifically, the modified layers are regions in which part of the crystal structure of the SiC chip 2 has been modified to have different properties. That is, the modified layers are regions in which the density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the SiC chip 2. The modified layers may include at least one layer selected from the group consisting of an amorphous layer, a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer.

[0016] When the first to fourth side surfaces 5A to 5D are cleavage planes, the first side surface 5A and the second side surface 5B may form inclined surfaces having an inclination angle due to the off-angle. The inclination angle due to the off-angle is an angle with respect to the normal direction Z when the normal direction Z is set to 0°. The first side surface 5A and the second side surface 5B may form inclined surfaces extending along the c-axis direction (0001 direction) of the SiC single crystal with respect to the normal direction Z.

[0017] The tilt angle due to the off angle is approximately equal to the off angle. The tilt angle due to the off angle may be greater than 0° and less than 10° (preferably greater than or equal to 2° and less than or equal to 4.5°). The third side surface 5C and the fourth side surface 5D extend in the off direction (a-axis direction) and therefore do not have a tilt angle due to the off angle. The third side surface 5C and the fourth side surface 5D extend planarly in the second direction Y (a-axis direction) and the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed approximately perpendicular to the first main surface 3 and the second main surface 4.

[0018] The first main surface 3 has an active surface 6, an outer surface 7, and first to fourth connecting surfaces 8A to 8D. The active surface 6, the outer surface 7, and the first to fourth connecting surfaces 8A to 8D define an active mesa 9 on the first main surface 3. The active surface 6 may be referred to as a first surface, the outer surface 7 may be referred to as a second surface, and the active mesa 9 may be referred to as a plateau.

[0019] The active surface 6 is a surface on which a trench insulating gate type MISFET is formed. The active surface 6 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 6 has a flat surface extending in the first direction X and the second direction Y. In plan view, the active surface 6 is formed in a quadrangular shape having four sides parallel to the periphery of the first main surface 3. In this embodiment, the corners of the active surface 6 are chamfered (specifically, R-chamfered) in a curved shape toward the outer side surface 7. Therefore, in this embodiment, the active surface 6 is formed in a quadrangular shape with four curved corners in plan view.

[0020] The outer surface 7 is located outside the active surface 6 and is recessed from the active surface 6 in the thickness direction of the SiC chip 2 (toward the second main surface 4) by a first depth D1. In other words, the outer surface 7 is located on the second main surface 4 side of the active surface 6. The outer surface 7 is formed in a band shape extending along the active surface 6 in a plan view. Specifically, the outer surface 7 is formed in a ring shape (specifically, a square ring) surrounding the active surface 6 in a plan view.

[0021] The outer surface 7 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 6. The outer surface 7 communicates with the first to fourth side surfaces 5A to 5D. The first depth D1 of the outer surface 7 may be 0.5 μm or more and 10 μm or less. The first depth D1 is preferably 5 μm or less. It is particularly preferable that the first depth D1 be 2.5 μm or less.

[0022] The first to fourth connecting surfaces 8A to 8D extend in the normal direction Z and connect the active surface 6 and the outer surface 7. The first connecting surface 8A is located on the first side surface 5A side, the second connecting surface 8B is located on the second side surface 5B side, the third connecting surface 8C is located on the third side surface 5C side, and the fourth connecting surface 8D is located on the fourth side surface 5D side. The first connecting surface 8A and the second connecting surface 8B extend in the first direction X and face the second direction Y. The third connecting surface 8C and the fourth connecting surface 8D extend in the second direction Y and face the first direction X. The first connecting surface 8A and the second connecting surface 8B face the a-plane of the SiC single crystal, and the third connecting surface 8C and the fourth connecting surface 8D face the m-plane of the SiC single crystal.

[0023] The first to fourth connecting surfaces 8A to 8D may be formed substantially perpendicular to the active surface 6 and the outer surface 7. In this case, square pillar-shaped active plateaus 9 are defined on the first main surface 3. The first to fourth connecting surfaces 8A to 8D may be inclined obliquely downward from the active surface 6 toward the outer surface 7. In this case, square pyramidal-shaped active plateaus 9 are defined on the first main surface 3. The inclination angle of the first to fourth connecting surfaces 8A to 8D may be 90° or more and 135° or less. The inclination angle of the first to fourth connecting surfaces 8A to 8D is the angle formed by the first to fourth connecting surfaces 8A to 8D and the active surface 6 within the SiC chip 2. The inclination angle of the first to fourth connecting surfaces 8A to 8D is preferably 95° or less.

[0024] The SiC semiconductor device 1 includes an n-type (first conductivity type) first semiconductor region 10 formed in a surface layer portion of the second main surface 4 of the SiC chip 2. The first semiconductor region 10 forms the drain of the MISFET. The first semiconductor region 10 may also be referred to as a drain region. The first semiconductor region 10 has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the first semiconductor region 10 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0025] The first semiconductor region 10 is formed in a surface layer portion of the second main surface 4 at a distance from the outer surface 7 toward the second main surface 4. The first semiconductor region 10 is formed over the entire surface layer portion of the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In other words, the first semiconductor region 10 has parts of the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0026] The thickness of the first semiconductor region 10 may be 5 μm or more and 300 μm or less. The thickness of the first semiconductor region 10 is typically 50 μm or more and 250 μm or less. The thickness of the first semiconductor region 10 is adjusted by grinding the second main surface 4. In this embodiment, the first semiconductor region 10 is formed of an n-type semiconductor substrate (SiC substrate).

[0027] The SiC semiconductor device 1 includes an n-type second semiconductor region 11 formed in a surface layer portion of the first main surface 3 of the SiC chip 2. The second semiconductor region 11 is electrically connected to the first semiconductor region 10, and forms the drain of the MISFET together with the first semiconductor region 10. The second semiconductor region 11 may also be referred to as a drift region. The second semiconductor region 11 has an n-type impurity concentration that is less than the n-type impurity concentration of the first semiconductor region 10. The n-type impurity concentration of the second semiconductor region 11 is 1×10 15 cm -3 More than 1×10 18 cm -3 It may be the following:

[0028] The second semiconductor region 11 is formed over the entire surface portion of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. Specifically, the second semiconductor region 11 is exposed from the active surface 6, the outer side surface 7, and the first to fourth connecting surfaces 8A to 8D. The second semiconductor region 11 has parts of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The thickness of the second semiconductor region 11 may be 5 μm or more and 20 μm or less. The thickness of the second semiconductor region 11 is measured based on the active surface 6. In this embodiment, the second semiconductor region 11 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0029] The second semiconductor region 11 preferably has a concentration gradient in which the n-type impurity concentration increases (specifically, gradually increases) from the first semiconductor region 10 side toward the first main surface 3. That is, the second semiconductor region 11 preferably has a first concentration region 12 (low concentration region) with a relatively low concentration located on the first semiconductor region 10 side, and a second concentration region 13 (high concentration region) located on the first main surface 3 side and with a higher concentration than the first concentration region 12.

[0030] The first concentration region 12 is located on the first semiconductor region 10 side of the outer surface 7, and is exposed from the first to fourth side surfaces 5A to 5D. The second concentration region 13 is located on the first main surface 3 side of the first concentration region 12, and is exposed from the active surface 6, the outer surface 7, and the first to fourth connecting surfaces 8A to 8D. The n-type impurity concentration of the first concentration region 12 is 1×10 15cm -3 More than 1×10 17 cm -3 The n-type impurity concentration of the second concentration region 13 may be 1×10 16 cm -3 More than 1×10 18 cm -3 It may be the following:

[0031] The SiC semiconductor device 1 includes an n-type third semiconductor region 14 (concentration transition region) interposed between the first semiconductor region 10 and the second semiconductor region 11 in the SiC chip 2. The third semiconductor region 14 is electrically connected to the first semiconductor region 10 and the second semiconductor region 11, and forms the drain of the MISFET together with the first semiconductor region 10 and the second semiconductor region 11. The third semiconductor region 14 may also be referred to as a buffer region. The third semiconductor region 14 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration of the first semiconductor region 10 to the n-type impurity concentration of the second semiconductor region 11.

[0032] The third semiconductor region 14 is interposed over the entire area between the first semiconductor region 10 and the second semiconductor region 11, and is exposed from the first to fourth side surfaces 5A to 5D. That is, the third semiconductor region 14 has parts of the first to fourth side surfaces 5A to 5D. The thickness of the third semiconductor region 14 may be 1 μm or more and 10 μm or less. In this embodiment, the third semiconductor region 14 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0033] Fig. 4 is a simplified plan view showing the structure of the first main surface 3 shown in Fig. 3 built into the SiC chip 2. Fig. 5 is an enlarged plan view of a main part of the first main surface 3 shown in Fig. 4.

[0034] 4 and 5, the SiC semiconductor device 1 includes a transistor region 20 defined on the active surface 6. The transistor region 20 may also be referred to as an active region. In this embodiment, only one transistor region 20 is defined on the active surface 6. That is, in this embodiment, the SiC semiconductor device 1 is a discrete device including a single transistor region 20. In this embodiment, the transistor region 20 is defined in the center of the active surface 6, spaced inward from the first connection surface 8A and the second connection surface 8B. The transistor region 20 is defined in a rectangular shape having four sides parallel to the first to fourth connection surfaces 8A to 8D.

[0035] The SiC semiconductor device 1 includes a plurality of peripheral regions 21, 22 set in a region outside the transistor region 20 on the active surface 6. The plurality of peripheral regions 21, 22 specifically include a first peripheral region 21 and a second peripheral region 22. The first peripheral region 21 is set in a strip shape extending in the first direction X between the third connecting surface 8C and the fourth connecting surface 8D in the region between the first connecting surface 8A and the transistor region 20. The first peripheral region 21 faces the transistor region 20 in the second direction Y. The second peripheral region 22 is set in a strip shape extending in the first direction X between the third connecting surface 8C and the fourth connecting surface 8D in the region between the second connecting surface 8B and the transistor region 20. The second peripheral region 22 faces the first peripheral region 21 in the second direction Y, with the transistor region 20 sandwiched between them.

[0036] 6 is an enlarged plan view of an end portion of the transistor region 20 shown in FIG. 5. FIG. 7 is an enlarged plan view of an inner portion of the transistor region 20 shown in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 6. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 6. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 7.

[0037] 6 to 12, SiC semiconductor device 1 includes a p-type (second conductivity type) body region 23 formed in a surface layer portion of active surface 6. Body region 23 forms a part of the body diode of the MISFET. The p-type impurity concentration of body region 23 is 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 23 may be formed in the surface layer portion of the second semiconductor region 11 over the entire active surface 6. More specifically, the body region 23 is formed in the surface layer portion of the second concentration region 13, and faces the first semiconductor region 10 (third semiconductor region 14) with a part of the first concentration region 12 sandwiched therebetween.

[0038] The SiC semiconductor device 1 includes an n-type source region 24 formed in a surface layer portion of the body region 23 on the active surface 6. The source region 24 forms the source of the MISFET. The source region 24 has an n-type impurity concentration that exceeds the n-type impurity concentration of the second semiconductor region 11 (second concentration region 13). The n-type impurity concentration of the source region 24 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0039] In this embodiment, the source region 24 is formed in the surface layer portion of the body region 23 over the entire active surface 6. The source region 24 is formed at an interval from the bottom of the body region 23 toward the active surface 6. The source region 24 forms a channel of the MISFET together with the second semiconductor region 11 (second concentration region 13) within the body region 23. The source region 24 does not necessarily have to be formed over the entire active surface 6, and may be formed only in a region of the active surface 6 where a channel is to be formed (for example, the transistor region 20).

[0040] The SiC semiconductor device 1 includes a transistor structure 30 formed on the active surface 6 in the transistor region 20 (the inner part of the active surface 6). The transistor structure 30 includes a plurality of trench gate structures 31 formed on the active surface 6. The plurality of trench gate structures 31 form the gate of the MISFET. A gate potential is applied to the plurality of trench gate structures 31. The plurality of trench gate structures 31 control the on / off of the channel in the body region 23.

[0041] The plurality of trench gate structures 31 are formed in the inner part of the active surface 6 at intervals from the first to fourth connection surfaces 8A to 8D in a plan view. The plurality of trench gate structures 31 are each formed in a strip shape (rectangular shape) extending in the first direction X and are formed at intervals in the second direction Y. The plurality of trench gate structures 31 are formed in a stripe shape extending in the first direction X in a plan view. Preferably, the plurality of trench gate structures 31 cross a line passing through the central part of the active surface 6 in the second direction Y in the first direction X in a plan view.

[0042] The plurality of trench gate structures 31 each have a first width W1. The first width W1 is the width in a direction orthogonal to the direction in which each trench gate structure 31 extends (that is, the second direction Y). The first width W1 may be 0.1 μm or more and 3 μm or less. Preferably, the first width W1 is 0.5 μm or more and 1.5 μm or less.

[0043] The plurality of trench gate structures 31 are arranged at a first interval P1 in the second direction Y. The first interval P1 is the distance between two adjacent trench gate structures 31 in the second direction Y. Preferably, the first interval P1 exceeds the first width W1 (W1 < P1). The first interval P1 may be 0.4 μm or more and 5 μm or less. Preferably, the first interval P1 is 0.8 μm or more and 3 μm or less.

[0044] Each trench gate structure 31 has a second depth D2. The second depth D2 is less than the first depth D1 of the outer surface 7 (D2 < D1). The second depth D2 may be 0.1 μm or more and 3 μm or less. The second depth D2 is preferably 0.5 μm or more and 2 μm or less. The aspect ratio D2 / W1 of each trench gate structure 31 is preferably 1 or more and 5 or less. The aspect ratio D2 / W1 is the ratio of the second depth D2 to the first width W1. The aspect ratio D2 / W1 is particularly preferably 1.5 or more.

[0045] Each trench gate structure 31 includes side walls and a bottom wall. The portion forming the long side among the side walls of each trench gate structure 31 is formed by the a-plane of the SiC single crystal. The portion forming the short side among the side walls of each trench gate structure 31 is formed by the m-plane of the SiC single crystal. The bottom wall of each trench gate structure 31 is formed by the c-plane of the SiC single crystal.

[0046] Each trench gate structure 31 may be formed in a vertical shape having a substantially constant opening width. Each trench gate structure 31 may be formed in a tapered shape having an opening width that narrows toward the bottom wall. The bottom wall of each trench gate structure 31 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each trench gate structure 31 may have a flat surface parallel to the active surface 6.

[0047] Each trench gate structure 31 is formed on the active surface 6 so as to reach the second semiconductor region 11 across the body region 23 and the source region 24. Specifically, each trench gate structure 31 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6 side, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In this form, each trench gate structure 31 is formed in the second concentration region 13 and faces the first concentration region 12 across a part of the second concentration region 13. The side walls of each trench gate structure 31 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each trench gate structure 31 is in contact with the second semiconductor region 11.

[0048] Each of the multiple trench gate structures 31 includes a gate trench 32, a gate insulating film 33, and a gate electrode 34. Below, a description will be given of one trench gate structure 31. The gate trench 32 forms the sidewalls and bottom wall of the trench gate structure 31. The sidewalls and bottom wall form the wall surfaces (inner wall and outer wall) of the gate trench 32.

[0049] The opening edge of the gate trench 32 slopes obliquely downward from the active surface 6 toward the gate trench 32. The opening edge is a connection portion between the active surface 6 and the sidewall of the gate trench 32. In this embodiment, the opening edge is formed in a curved shape recessed toward the SiC chip 2. The opening edge may also be formed in a curved shape directed toward the inside of the gate trench 32.

[0050] The gate insulating film 33 is formed in the form of a film on the inner wall of the gate trench 32, and defines a recess space within the gate trench 32. The gate insulating film 33 covers the second semiconductor region 11, the body region 23, and the source region 24 on the inner wall of the gate trench 32. The gate insulating film 33 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 33 has a single-layer structure made of a silicon oxide film.

[0051] The gate insulating film 33 includes a first portion 33a, a second portion 33b, and a third portion 33c. The first portion 33a covers the sidewall of the gate trench 32. The second portion 33b covers the bottom wall of the gate trench 32. The third portion 33c covers the opening edge portion. In this embodiment, the third portion 33c bulges in a curved shape toward the inside of the gate trench 32 at the opening edge portion.

[0052] The thickness of the first portion 33a may be 10 nm or more and 100 nm or less. The second portion 33b may have a thickness greater than the thickness of the first portion 33a. The thickness of the second portion 33b may be 50 nm or more and 200 nm or less. The third portion 33c has a thickness greater than the thickness of the first portion 33a. The thickness of the third portion 33c may be 50 nm or more and 200 nm or less. Of course, the gate insulating film 33 may have a uniform thickness.

[0053] The gate electrode 34 is buried in the gate trench 32 with the gate insulating film 33 sandwiched therebetween. The gate electrode 34 faces the second semiconductor region 11, the body region 23, and the source region 24 with the gate insulating film 33 sandwiched therebetween. The gate electrode 34 has an electrode surface exposed from the gate trench 32. The electrode surface of the gate electrode 34 is formed in a curved shape recessed toward the bottom wall of the gate trench 32, and narrowed by the third portion 33c of the gate insulating film 33.

[0054] A gate potential is applied to the gate electrode 34. The gate electrode 34 controls the on / off of a channel in the body region 23 via the gate insulating film 33. The gate electrode 34 is preferably made of conductive polysilicon. The gate electrode 34 may include n-type polysilicon doped with n-type impurities and / or p-type polysilicon doped with p-type impurities.

[0055] The transistor structure 30 includes a plurality of first trench source structures 41 formed in the active surface 6. A source potential is applied to the plurality of first trench source structures 41. The source potential may be a reference potential that serves as an operating reference for the MISFET. The plurality of first trench source structures 41 are respectively formed in the active surface 6 so as to be adjacent to the plurality of trench gate structures 31 in the second direction Y. Specifically, the plurality of first trench source structures 41 are respectively formed in regions between two adjacent trench gate structures 31 in the active surface 6 at intervals from each trench gate structure 31.

[0056] The multiple first trench source structures 41 are each formed in a band shape extending in the first direction X in a plan view, and are formed at intervals in the second direction Y so as to sandwich one trench gate structure 31. The multiple first trench source structures 41 are formed in a stripe shape extending in the first direction X in a plan view.

[0057] The multiple first trench source structures 41 preferably cross in the first direction X a line that passes through the center of the active surface 6 in the second direction Y in a plan view. In this embodiment, each first trench source structure 41 has a length in the first direction X that exceeds the length of each trench gate structure 31. The multiple first trench source structures 41 cross the end of each trench gate structure 31 in the first direction X from the second direction Y side in a plan view.

[0058] The plurality of first trench source structures 41 each include a portion facing in the second direction Y in a region between the periphery of the active surface 6 (the third connection surface 8C and the fourth connection surface 8D) and the ends of each trench gate structure 31 in a plan view. The plurality of first trench source structures 41 are exposed from at least one of the third connection surface 8C and the fourth connection surface 8D. In this form, the plurality of first trench source structures 41 are exposed from both the third connection surface 8C and the fourth connection surface 8D. That is, the plurality of first trench source structures 41 penetrate the third connection surface 8C and the fourth connection surface 8D.

[0059] The plurality of first trench source structures 41 each have a second width W2. The second width W2 is the width in a direction orthogonal to the direction in which each first trench source structure 41 extends (that is, the second direction Y). The second width W2 may be 0.1 μm or more and 3 μm or less. Preferably, the second width W2 is 0.5 μm or more and 1.5 μm or less. The second width W2 may exceed the first width W1 (W1 < W2), or may be less than or equal to the first width W1 (W1 ≧ W2). In this form, the second width W2 is approximately equal to the first width W1 (W1 ≒ W2). Preferably, the second width W2 has a value within the range of ±10% of the value of the first width W1.

[0060] Each first trench source structure 41 has a third depth D3. The third depth D3 exceeds the second depth D2 (D2 < D3) of the trench gate structure 31. Preferably, the third depth D3 is 1.5 times or more and 3 times or less the second depth D2. In this form, the third depth D3 is approximately equal to the first depth D1 of the outer surface 7 (D1 ≒ D3). That is, each first trench source structure 41 communicates with the outer surface 7, the third connection surface 8C, and the fourth connection surface 8D. Preferably, the third depth D3 has a value within the range of ±10% of the value of the first depth D1.

[0061] The third depth D3 may be 0.5 μm or more and 10 μm or less. The third depth D3 is preferably 5 μm or less. The third depth D3 is particularly preferably 2.5 μm or less. The aspect ratio D3 / W2 of each first trench source structure 41 is preferably 1 or more and 5 or less. The aspect ratio D3 / W2 is the ratio of the third depth D3 to the second width W2. The aspect ratio D3 / W2 is particularly preferably 2 or more.

[0062] The plurality of first trench source structures 41 are arranged at a second interval P2 in the second direction Y from the plurality of trench gate structures 31. The second interval P2 is the distance between one trench gate structure 31 and one first trench source structure 41 adjacent in the second direction Y. The second interval P2 is preferably 1 / 4 or more and 1 / 2 or less of the first interval P1 (1 / 4×P1≦P2≦1 / 2×P1).

[0063] The second interval P2 may be 0.1 μm or more and 2.5 μm or less. The second interval P2 is preferably 0.5 μm or more and 1.5 μm or less. The second interval P2 is preferably less than the first width W1 of the trench gate structure 31 (P2<W1). The second interval P2 is preferably less than the second width W2 of the first trench source structure 41 (P2<W2). Of course, the second interval P2 may be equal to or greater than the first width W1 and the second width W2.

[0064] Each first trench source structure 41 includes side walls and a bottom wall. The side walls of each first trench source structure 41 are formed by the a-plane of a SiC single crystal. The side walls of each first trench source structure 41 communicate with the third connection surface 8C and the fourth connection surface 8D. The bottom wall of each first trench source structure 41 is formed by the c-plane of a SiC single crystal. The bottom wall of each first trench source structure 41 communicates with the outer surface 7.

[0065] Each first trench source structure 41 may be formed in a vertical shape with a substantially constant opening width. Each first trench source structure 41 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of each first trench source structure 41 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each first trench source structure 41 may have a flat surface parallel to the active surface 6.

[0066] Each first trench source structure 41 is formed in the active surface 6 to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, each first trench source structure 41 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) with a portion of the second semiconductor region 11 in between. In this embodiment, each first trench source structure 41 is formed in the second concentration region 13, and faces the first concentration region 12 with a portion of the second concentration region 13 in between.

[0067] The sidewalls of each first trench source structure 41 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each first trench source structure 41 is in contact with the second semiconductor region 11. In this embodiment, each first trench source structure 41 is formed deeper than each trench gate structure 31. That is, the bottom wall of each first trench source structure 41 is located closer to the bottom of the second semiconductor region 11 (second concentration region 13) than the bottom wall of each trench gate structure 31.

[0068] Each of the multiple first trench source structures 41 includes a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42, source insulating film 43, and source electrode 44 of each first trench source structure 41 may be referred to as a "first source trench," a "first source insulating film," and a "first source electrode." Below, one first trench source structure 41 will be described.

[0069] The source trench 42 forms the sidewalls and bottom wall of the first trench source structure 41. The sidewalls and bottom wall form the wall surfaces (inner wall and outer wall) of the source trench 42. The opening edge portion of the source trench 42 slopes obliquely downward from the active surface 6 toward the source trench 42. The opening edge portion is the connection portion between the active surface 6 and the sidewall of the source trench 42. In this embodiment, the opening edge portion is formed in a curved shape recessed toward the SiC chip 2. The opening edge portion may also be formed in a curved shape directed inward of the source trench 42.

[0070] The source insulating film 43 is formed in the form of a film on the inner wall of the source trench 42, and defines a recess space within the source trench 42. The source insulating film 43 covers the second semiconductor region 11, the body region 23, and the source region 24 on the inner wall of the source trench 42. The source insulating film 43 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the source insulating film 43 has a single-layer structure made of a silicon oxide film.

[0071] The source insulating film 43 includes a first portion 43a, a second portion 43b, and a third portion 43c. The first portion 43a covers the sidewall of the source trench 42. Specifically, the first portion 43a covers the sidewall of the source trench 42 at a distance from the opening end of the source trench 42 toward the bottom wall in an arbitrary region of the source trench 42 (specifically, a region where a contact region 70, described later, is formed), and exposes a surface portion of the first main surface 3 from the sidewall of the source trench 42.

[0072] The first portion 43a covers the entire sidewall of the source trench 42 on the peripheral edge side of the active surface 6. The second portion 43b covers the bottom wall of the source trench 42. The third portion 43c covers the opening edge of the source trench 42 outside the region where the first portion 43a is formed. In this embodiment, the third portion 43c bulges in a curved shape toward the inside of the source trench 42 at the opening edge.

[0073] The thickness of the first portion 43a may be not less than 10 nm and not more than 100 nm. The second portion 43b may have a thickness greater than the thickness of the first portion 43a. The thickness of the second portion 43b may be not less than 50 nm and not more than 200 nm. The third portion 43c has a thickness greater than the thickness of the first portion 43a. The thickness of the third portion 43c may be not less than 50 nm and not more than 200 nm. Of course, the source insulating film 43 may have a uniform thickness.

[0074] The source electrode 44 is buried in the source trench 42 with the source insulating film 43 sandwiched therebetween. The source electrode 44 faces the second semiconductor region 11, the body region 23, and the source region 24 with the source insulating film 43 sandwiched therebetween. The source electrode 44 has an upper end exposed from the source insulating film 43 in a portion where the first portion 43a of the source insulating film 43 is formed. The upper end of the source electrode 44 defines a recess recessed in the thickness direction of the SiC chip 2 between the source trench 42 and the source insulating film 43.

[0075] The source electrode 44 has an electrode surface exposed from the source trench 42. The electrode surface of the source electrode 44 is formed in a curved shape recessed toward the bottom wall of the source trench 42. The electrode surface of the source electrode 44 is narrowed by the third portion 43c of the insulating film on the peripheral edge side of the active surface 6.

[0076] A source potential is applied to the source electrode 44. The source electrode 44 is preferably made of conductive polysilicon. The source electrode 44 may include n-type polysilicon doped with n-type impurities and / or p-type polysilicon doped with p-type impurities. The source electrode 44 preferably includes the same conductive material as the gate electrode 34.

[0077] The transistor structure 30 includes a plurality of second trench source structures 51. The second trench source structures 51 may also be referred to as intermediate trench source structures. A source potential is applied to the second trench source structures 51.

[0078] The plurality of second trench source structures 51 are respectively formed on the periphery of the active surface 6 and in regions between the plurality of trench gate structures 31. Specifically, the plurality of second trench source structures 51 are respectively formed in regions on the active surface 6 between the third connection surface 8C and the plurality of trench gate structures 31 and in regions on the active surface 6 between the fourth connection surface 8D and the plurality of trench gate structures 31. The plurality of second trench source structures 51 are respectively formed in regions on the active surface 6 between two adjacent first trench source structures 41 at intervals from the trench gate structure 31 and the two first trench source structures 41.

[0079] Specifically, the multiple second trench source structures 51 are arranged at intervals in the second direction Y with one first trench source structure 41 sandwiched between them, and each face the multiple trench gate structures 31 in a one-to-one correspondence in the first direction X. That is, each second trench source structure 51 faces the trench gate structure 31 in the first direction X and faces the second trench source structure 51 in the second direction Y.

[0080] The second trench source structures 51 are arranged in an area on the third connection surface 8C side and an area on the fourth connection surface 8D side so as to sandwich a corresponding trench gate structure 31 from both sides in the first direction X. The second trench source structures 51 are each formed in a band shape extending in the first direction X in a plan view. The second trench source structures 51 are formed in a stripe shape extending in the first direction X in a plan view.

[0081] The plurality of second trench source structures 51 located on the side of the third connection surface 8C are exposed from the third connection surface 8C, and the plurality of second trench source structures 51 located on the side of the fourth connection surface 8D are exposed from the fourth connection surface 8D. That is, the plurality of second trench source structures 51 are formed so as to penetrate either one of the third connection surface 8C and the fourth connection surface 8D according to the arrangement.

[0082] The plurality of second trench source structures 51 have a length less than the length of the plurality of trench gate structures 31 in the first direction X. Looking at one trench gate structure 31 and two second trench source structures 51 arranged in the first direction X, the total length of the two second trench source structures 51 is less than the length of one trench gate structure 31. Such a structure is effective in securing the channel length.

[0083] Similar to the first trench source structure 41, the plurality of second trench source structures 51 each have a second width W2 and a third depth D3 (aspect ratio D3 / W2). Also, similar to the first trench source structure 41, the plurality of second trench source structures 51 are arranged at a second interval P2 in the second direction Y.

[0084] The plurality of second trench source structures 51 are arranged at a third interval P3 from the plurality of trench gate structures 31 in the first direction X. The third interval P3 is the distance between one trench gate structure 31 and one second trench source structure 51 adjacent in the first direction X. The third interval P3 is preferably not less than one-fourth and not more than the first interval P1 of the plurality of trench gate structures 31 (1 / 4×P1≦P3<P1). The third interval P3 is preferably not more than one-half of the first interval P1 (P3≦1 / 2×P1).

[0085] The third spacing P3 may be 0.1 μm or more and 2.5 μm or less. The third spacing P3 is preferably 0.5 μm or more and 1.5 μm or less. The third spacing P3 is preferably approximately equal to the second spacing P2 between the trench gate structure 31 and the first trench source structure 41 (P2≈P3). The third spacing P3 preferably has a value within a range of ±10% of the value of the second spacing P2.

[0086] Each second trench source structure 51 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each second trench source structure 51 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each second trench source structure 51 are formed by the m-plane of the SiC single crystal. The sidewalls of each second trench source structure 51 communicate with either the third connection surface 8C or the fourth connection surface 8D. The bottom wall of each second trench source structure 51 is formed by the c-plane of the SiC single crystal. The bottom wall of each second trench source structure 51 communicates with the outer surface 7.

[0087] Each second trench source structure 51 may be formed in a vertical shape with a substantially constant opening width. Each second trench source structure 51 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of each second trench source structure 51 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each second trench source structure 51 may have a flat surface parallel to the active surface 6.

[0088] Each second trench source structure 51 is formed in the active surface 6 to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, each second trench source structure 51 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) with a portion of the second semiconductor region 11 in between. In this embodiment, each second trench source structure 51 is formed in the second concentration region 13, and faces the first concentration region 12 with a portion of the second concentration region 13 in between.

[0089] The sidewalls of each second trench source structure 51 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each second trench source structure 51 is in contact with the second semiconductor region 11. In this embodiment, each second trench source structure 51 is formed deeper than each trench gate structure 31. That is, the bottom wall of each second trench source structure 51 is located closer to the bottom of the second semiconductor region 11 (second concentration region 13) than the bottom wall of each trench gate structure 31.

[0090] Similar to the first trench source structure 41, the multiple second trench source structures 51 each include a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42, source insulating film 43, and source electrode 44 of each second trench source structure 51 may also be referred to as a "second source trench," a "second source insulating film," and a "second source electrode."

[0091] In each second trench source structure 51, the third portion 43c of the source insulating film 43 is formed over the entire opening edge of the source trench 42. The descriptions of the source trench 42, source insulating film 43, and source electrode 44 of the first trench source structure 41 also apply to the source trench 42, source insulating film 43, and source electrode 44 of the second trench source structure 51, respectively.

[0092] Fig. 13 is an enlarged plan view of a corner of the first peripheral region 21 shown in Fig. 5. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 13. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 13. Fig. 16 is an enlarged plan view of an end portion of the first peripheral region 21 shown in Fig. 5. Fig. 17 is an enlarged plan view of an inner portion of the first peripheral region 21 shown in Fig. 5. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig. 16.

[0093] FIG. 19 is a cross-sectional view taken along the XIX-XIX line shown in FIG. 16. FIG. 20 is a cross-sectional view taken along the XX-XX line shown in FIG. 16. FIG. 21 is a cross-sectional view taken along the XXI-XXI line shown in FIG. 17. Since the structure on the side of the second peripheral region 22 (the side of the second connection surface 8B) is the same as the structure on the side of the first peripheral region 21 (the side of the first connection surface 8A), the structure on the side of the first peripheral region 21 (the side of the first connection surface 8A) will be described below as an example.

[0094] Referring to FIGS. 5 and 13 to 21, the SiC semiconductor device 1 includes a dummy structure 60 formed in the first peripheral region 21 (the peripheral portion of the active surface 6) on the active surface 6. The dummy structure 60 is a region that does not operate as a MISFET and may be referred to as a dummy transistor structure. In this form, the dummy structure 60 includes a first dummy structure 60A and a second dummy structure 60B.

[0095] The first dummy structure 60A is formed in the first peripheral region 21 in a region between the periphery of the active surface 6 (the first connection surface 8A) and the transistor structure 30. The first dummy structure 60A is formed at the outermost edge of the active surface 6 (the region close to the first connection surface 8A) in the first peripheral region 21. The second dummy structure 60B is formed in the first peripheral region 21 in a region between the transistor structure 30 and the first dummy structure 60A.

[0096] The first dummy structure 60A has a first dummy width WD1 in the second direction Y. The second dummy structure 60B has a second dummy width WD2 in the second direction Y. The second dummy width WD2 is arbitrary, but it is preferably greater than the first dummy width WD1 (WD1 < WD2). The second dummy width WD2 is preferably not more than 5 times the first dummy width WD1 (WD2 < 5×WD1). Particularly preferably, the second dummy width WD2 is not more than 3 times the first dummy width WD1 (WD2 < 3×WD1).

[0097] The dummy structure 60 may include at least one of the first dummy structure 60A and the second dummy structure 60B, and does not necessarily include both the first dummy structure 60A and the second dummy structure 60B. The dummy structure 60 may have a single dummy structure consisting of either the first dummy structure 60A or the second dummy structure 60B. It is preferable that the dummy structure 60 include at least the first dummy structure 60A. It is most preferable that the dummy structure 60 include both the first dummy structure 60A and the second dummy structure 60B.

[0098] The first dummy structure 60A includes at least one first dummy trench source structure 61 formed on the active surface 6. In this embodiment, the first dummy structure 60A includes a plurality of first dummy trench source structures 61. The number of first dummy trench source structures 61 is arbitrary, but is preferably 10 to 50. The first dummy width WD1 is adjusted by the number of first dummy trench source structures 61. It is particularly preferable that the number of first dummy trench source structures 61 be 25 or less. In this case, a reduction in the area of ​​the transistor region 20 due to the first peripheral region 21 can be suppressed.

[0099] A source potential is applied to the first dummy trench source structures 61. The first dummy trench source structures 61 are each formed in a strip shape extending in a first direction X in a plan view, and are continuously arranged adjacent to each other at intervals in a second direction Y. The first dummy trench source structures 61 are formed in a strip shape extending in the first direction X in a plan view.

[0100] The multiple first dummy trench source structures 61 preferably cross in the first direction X a line that passes through the center of the active surface 6 in the second direction Y in a plan view. In this embodiment, each first dummy trench source structure 61 has a length in the first direction X that exceeds the length of each trench gate structure 31. The multiple first dummy trench source structures 61 cross the end of each trench gate structure 31 in the first direction X from the second direction Y side in a plan view.

[0101] The multiple first dummy trench source structures 61 each include a portion facing the second direction Y in a region between the periphery of the active surface 6 (the third connection surface 8C and the fourth connection surface 8D) and the end of each trench gate structure 31 in a plan view. The multiple first dummy trench source structures 61 face the multiple trench gate structures 31, the multiple first trench source structures 41, and the multiple second trench source structures 51 in the second direction Y.

[0102] The plurality of first dummy trench source structures 61 are each exposed from at least one of the third connection surface 8C and the fourth connection surface 8D. In this embodiment, the plurality of first dummy trench source structures 61 are each exposed from both the third connection surface 8C and the fourth connection surface 8D. In other words, the plurality of first dummy trench source structures 61, like the first trench source structures 41, penetrate the third connection surface 8C and the fourth connection surface 8D.

[0103] Each of the plurality of first dummy trench source structures 61 has a second width W2 and a third depth D3 (aspect ratio D3 / W2), similar to the first trench source structure 41. That is, each of the first dummy trench source structures 61 communicates with the outer side surface 7, the third connecting surface 8C, and the fourth connecting surface 8D.

[0104] The plurality of first dummy trench source structures 61 are arranged at a fourth interval P4 from each other in the second direction Y. The fourth interval P4 is the distance between two first dummy trench source structures 61 adjacent to each other in the second direction Y. The fourth interval P4 is preferably not less than one-fourth and not more than one-half of the first interval P1 (1 / 4×P1≦P4≦1 / 2×P1).

[0105] The fourth interval P4 may be not less than 0.1 μm and not more than 2.5 μm. The fourth interval P4 is preferably not less than 0.5 μm and not more than 1.5 μm. The fourth interval P4 is preferably less than the first width W1 of the trench gate structure 31 (P4<W1). The fourth interval P4 is preferably less than the second width W2 of the first dummy trench source structure 61 (P4<W2). Of course, the fourth interval P4 may be not less than the first width W1 and the second width W2.

[0106] The fourth interval P4 is preferably approximately equal to the second interval P2 between the trench gate structure 31 and the first trench source structure 41 (P2≒P4). The fourth interval P4 preferably has a value within a range of ±10% of the value of the second interval P2. The fourth interval P4 is preferably approximately equal to the third interval P3 between the trench gate structure 31 and the second trench source structure 51 (P3≒P4). The fourth interval P4 preferably has a value within a range of ±10% of the value of the third interval P3.

[0107] Each first dummy trench source structure 61 includes a side wall and a bottom wall. The side wall of each first dummy trench source structure 61 is formed by the a-plane of the SiC single crystal. The side wall of each first dummy trench source structure 61 communicates with the third connection surface 8C and the fourth connection surface 8D. The bottom wall of each first dummy trench source structure 61 is formed by the c-plane of the SiC single crystal. The bottom wall of each first dummy trench source structure 61 communicates with the outer surface 7.

[0108] Each first dummy trench source structure 61 may be formed in a vertical shape with a substantially constant opening width. Each first dummy trench source structure 61 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of each first dummy trench source structure 61 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each first dummy trench source structure 61 may have a flat surface parallel to the active surface 6.

[0109] Each first dummy trench source structure 61 is formed in the active surface 6 to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, each first dummy trench source structure 61 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) with a portion of the second semiconductor region 11 in between. In this embodiment, each first dummy trench source structure 61 is formed in the second concentration region 13, and faces the first concentration region 12 with a portion of the second concentration region 13 in between.

[0110] The sidewalls of each first dummy trench source structure 61 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each first dummy trench source structure 61 is in contact with the second semiconductor region 11. In this embodiment, each first dummy trench source structure 61 is formed deeper than each trench gate structure 31. That is, the bottom wall of each first dummy trench source structure 61 is located closer to the bottom of the second semiconductor region 11 (second concentration region 13) than the bottom wall of each trench gate structure 31.

[0111] Similar to the first trench source structure 41, each of the multiple first dummy trench source structures 61 includes a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42, the source insulating film 43, and the source electrode 44 of each first dummy trench source structure 61 may be referred to as a "first dummy source trench," a "first dummy source insulating film," and a "first dummy source electrode."

[0112] In each first dummy trench source structure 61, the third portion 43c of the source insulating film 43 is formed over the entire opening edge of the source trench 42. The descriptions of the source trench 42, source insulating film 43, and source electrode 44 of the first trench source structure 41 also apply to the descriptions of the source trench 42, source insulating film 43, and source electrode 44 of the first dummy trench source structure 61, respectively.

[0113] The second dummy structure 60B includes at least one dummy trench gate structure 62 formed in the active surface 6, and at least one second dummy trench source structure 63 formed in the active surface 6 adjacent to the dummy trench gate structure 62. In this embodiment, the second dummy structure 60B includes a plurality of dummy trench gate structures 62 and a plurality of second dummy trench source structures 63.

[0114] The multiple dummy trench gate structures 62 and the multiple second dummy trench source structures 63 are alternately arranged at intervals in the second direction Y, with two dummy trench gate structures 62 as the start and end points of the arrangement. That is, in this embodiment, the second dummy structure 60B is defined by a group of trench structures with two dummy trench gate structures 62 as the start and end points of the arrangement. The second dummy structure 60B is formed at a second interval P2 from the first trench source structure 41 of the transistor structure 30, and at a fourth interval P4 (second interval P2) from the first dummy trench source structure 61 of the first dummy structure 60A.

[0115] The number of dummy trench gate structures 62 is arbitrary, but is preferably less than the number of trench gate structures 31. The number of dummy trench gate structures 62 may be 10 or more and 50 or less. The number of dummy trench gate structures 62 is preferably 25 or less. The number of second dummy trench source structures 63 is arbitrary, but is preferably less than the number of first trench source structures 41. The number of second dummy trench source structures 63 may be 10 or more and 50 or less. The number of second dummy trench source structures 63 is preferably 25 or less.

[0116] The total number of the dummy trench gate structures 62 and the second dummy trench source structures 63 preferably exceeds the total number of the first dummy trench source structures 61 of the first dummy structure 60A. The total number of the dummy trench gate structures 62 and the second dummy trench source structures 63 is preferably 50 or less. In this case, a reduction in the area of ​​the transistor region 20 due to the first peripheral region 21 can be suppressed.

[0117] Unlike the trench gate structure 31, the multiple dummy trench gate structures 62 do not form gates of the MISFET. A source potential is applied to the multiple dummy trench gate structures 62. Therefore, the formation of channels due to the multiple dummy trench gate structures 62 is suppressed. The multiple dummy trench gate structures 62 are each formed in a band shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The multiple dummy trench gate structures 62 are formed in a stripe shape extending in the first direction X in a plan view.

[0118] The multiple dummy trench gate structures 62 preferably cross in the first direction X a line that passes through the center of the active surface 6 in the second direction Y in plan view. In this embodiment, each dummy trench gate structure 62 has a length in the first direction X that exceeds the length of each trench gate structure 31. The multiple dummy trench gate structures 62 cross the end of each trench gate structure 31 in the first direction X from the second direction Y side in plan view.

[0119] The multiple dummy trench gate structures 62 include portions facing in the second direction Y in a region between the periphery of the active surface 6 (the third connection surface 8C and the fourth connection surface 8D) and the ends of each trench gate structure 31 in a plan view. The multiple dummy trench gate structures 62 face the multiple trench gate structures 31, the multiple first trench source structures 41, the multiple second trench source structures 51, and the multiple first dummy trench source structures 61 in the second direction Y.

[0120] The plurality of dummy trench gate structures 62 are exposed from at least one of the third connection surface 8C and the fourth connection surface 8D. In this embodiment, the plurality of dummy trench gate structures 62 are exposed from both the third connection surface 8C and the fourth connection surface 8D. That is, like the first trench source structure 41, the plurality of dummy trench gate structures 62 penetrate the third connection surface 8C and the fourth connection surface 8D.

[0121] Similar to the trench gate structures 31, each of the dummy trench gate structures 62 has a first width W1 and a second depth D2 (aspect ratio D2 / W1). That is, each dummy trench gate structure 62 communicates with the third connecting surface 8C and the fourth connecting surface 8D at intervals from the outer surface 7 toward the active surface 6. Similarly to the trench gate structures 31, the dummy trench gate structures 62 are arranged at first intervals P1 in the second direction Y.

[0122] Each dummy trench gate structure 62 includes a sidewall and a bottom wall. The sidewall of each dummy trench gate structure 62 is formed by the a-plane of the SiC single crystal. The sidewall of each dummy trench gate structure 62 is connected to the third connection surface 8C and the fourth connection surface 8D. The bottom wall of each dummy trench gate structure 62 is formed by the c-plane of the SiC single crystal. The bottom wall of each dummy trench gate structure 62 is connected to the third connection surface 8C and the fourth connection surface 8D.

[0123] Each dummy trench gate structure 62 may be formed in a vertical shape with a substantially constant opening width. Each dummy trench gate structure 62 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of each dummy trench gate structure 62 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each dummy trench gate structure 62 may have a flat surface parallel to the active surface 6.

[0124] Each dummy trench gate structure 62 is formed in the active surface 6 so as to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, each dummy trench gate structure 62 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) with a part of the second semiconductor region 11 in between.

[0125] In this embodiment, each dummy trench gate structure 62 is formed in the second concentration region 13 and faces the first concentration region 12 across a part of the second concentration region 13. The sidewalls of each dummy trench gate structure 62 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each dummy trench gate structure 62 is in contact with the second semiconductor region 11.

[0126] Similar to the trench gate structure 31, the multiple dummy trench gate structures 62 each include a gate trench 32, a gate insulating film 33, and a gate electrode 34. The gate trench 32, gate insulating film 33, and gate electrode 34 of each dummy trench gate structure 62 may be referred to as a "dummy gate trench," a "dummy gate insulating film," and a "dummy gate electrode." The descriptions of the gate trench 32, gate insulating film 33, and gate electrode 34 of the dummy trench gate structure 62 also apply to the descriptions of the gate trench 32, gate insulating film 33, and gate electrode 34 of the trench gate structure 31, respectively.

[0127] A source potential is applied to the plurality of second dummy trench source structures 63. The plurality of second dummy trench source structures 63 are each formed in the active surface 6 so as to be adjacent to the plurality of dummy trench gate structures 62 in the second direction Y. Specifically, the plurality of second dummy trench source structures 63 are each formed in a region between two adjacent dummy trench gate structures 62 in the active surface 6 at an interval from each dummy trench gate structure 62.

[0128] More specifically, the second dummy trench source structures 63 are each formed in a strip shape extending in the first direction X in a plan view, and are formed at intervals in the second direction Y so as to sandwich one dummy trench gate structure 62 therebetween. The second dummy trench source structures 63 are formed in a stripe shape extending in the first direction X in a plan view. It is preferable that the second dummy trench source structures 63 cross in the first direction X a line that passes through the center of the active surface 6 in the second direction Y in a plan view.

[0129] In this embodiment, the plurality of second dummy trench source structures 63 have a length in the first direction X that exceeds the length of the plurality of trench gate structures 31. In a plan view, the plurality of second dummy trench source structures 63 cross the ends of the plurality of trench gate structures 31 from the second direction Y side in the first direction X. In a plan view, the plurality of second dummy trench source structures 63 include portions facing the second direction Y in regions between the periphery of the active surface 6 (the third connection surface 8C and the fourth connection surface 8D) and the ends of each dummy trench gate structure 62. The second dummy trench source structure 63 faces the plurality of trench gate structures 31, the plurality of first trench source structures 41, the plurality of second trench source structures 51, the plurality of first dummy trench source structures 61, and the plurality of dummy trench gate structures 62 in the second direction Y.

[0130] The second dummy trench source structures 63 are exposed from at least one of the third connection surface 8C and the fourth connection surface 8D. In this embodiment, the second dummy trench source structures 63 are exposed from both the third connection surface 8C and the fourth connection surface 8D. In other words, the second dummy trench source structures 63 penetrate the third connection surface 8C and the fourth connection surface 8D.

[0131] Similar to the first trench source structure 41, each of the second dummy trench source structures 63 has a second width W2 and a third depth D3 (aspect ratio D3 / W2). That is, similar to the first trench source structure 41, each second dummy trench source structure 63 communicates with the outer side surface 7, the third connecting surface 8C, and the fourth connecting surface 8D. Similarly to the first trench source structure 41, the second dummy trench source structures 63 are arranged at second intervals P2 in the second direction Y.

[0132] Each second dummy trench source structure 63 includes a sidewall and a bottom wall. The sidewall of each second dummy trench source structure 63 is formed by the a-plane of the SiC single crystal. The sidewall of each second dummy trench source structure 63 is connected to the third connection surface 8C and the fourth connection surface 8D. The bottom wall of each second dummy trench source structure 63 is formed by the c-plane of the SiC single crystal. The bottom wall of each second dummy trench source structure 63 is connected to the outer surface 7.

[0133] Each second dummy trench source structure 63 may be formed in a vertical shape with a substantially constant opening width. Each second dummy trench source structure 63 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of each second dummy trench source structure 63 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each second dummy trench source structure 63 may have a flat surface parallel to the active surface 6.

[0134] Each second dummy trench source structure 63 is formed in the active surface 6 to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, each second dummy trench source structure 63 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) with a portion of the second semiconductor region 11 in between. In this embodiment, each second dummy trench source structure 63 is formed in the second concentration region 13, and faces the first concentration region 12 with a portion of the second concentration region 13 in between.

[0135] The sidewalls of each second dummy trench source structure 63 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each second dummy trench source structure 63 is in contact with the second semiconductor region 11. In this embodiment, each second dummy trench source structure 63 is formed deeper than each dummy trench gate structure 62. That is, the bottom wall of each second dummy trench source structure 63 is located closer to the bottom of the second semiconductor region 11 (second concentration region 13) than the bottom wall of each dummy trench gate structure 62.

[0136] Similar to the first trench source structure 41, each of the plurality of second dummy trench source structures 63 includes a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42, the source insulating film 43, and the source electrode 44 of each second dummy trench source structure 63 may be referred to as a "second dummy source trench," a "second dummy source insulating film," and a "second dummy source electrode."

[0137] In each second dummy trench source structure 63, the third portion 43c of the source insulating film 43 is formed over the entire opening edge of the source trench 42. The descriptions of the source trench 42, source insulating film 43, and source electrode 44 of the first trench source structure 41 also apply to the source trench 42, source insulating film 43, and source electrode 44 of the second dummy trench source structure 63.

[0138] 6 to 12 again, the SiC semiconductor device 1 includes a plurality of p-type contact regions 70 (a plurality of contact regions) formed in a surface layer portion of the active surface 6 of the transistor region 20. The plurality of contact regions 70 (the contact regions) are formed in regions along the plurality of first trench source structures 41, respectively, but are not formed in regions along the plurality of second trench source structures 51. The plurality of contact regions 70 each have a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of the plurality of contact regions 70 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0139] The plurality of contact regions 70 are formed in a one-to-many correspondence with the respective first trench source structures 41 in a plan view. The plurality of contact regions 70 are formed at intervals along the respective first trench source structures 41 in a plan view, and partially expose the respective first trench source structures 41. In this embodiment, the plurality of contact regions 70 are each formed in a strip shape extending in the first direction X in a plan view. It is preferable that each of the plurality of contact regions 70 has a length that exceeds the distance between two adjacent contact regions 70 in the first direction X.

[0140] The plurality of contact regions 70 covering one first trench source structure 41 face the plurality of contact regions 70 covering another adjacent first trench source structure 41 in a one-to-one correspondence in the second direction Y. That is, in this embodiment, the plurality of contact regions 70 are arranged in a matrix with intervals between them in the first direction X and the second direction Y as a whole in a plan view.

[0141] The contact regions 70 covering one first trench source structure 41 may be arranged offset by a half pitch in the first direction X with respect to the contact regions 70 covering another adjacent first trench source structure 41. In other words, the contact regions 70 may be arranged in a staggered pattern as a whole in the first direction X and the second direction Y with intervals in between in a plan view.

[0142] In this embodiment, the multiple contact regions 70 are formed at intervals from the periphery of the active surface 6 (the third connection surface 8C and the fourth connection surface 8D) in plan view to the inner portions of the multiple first trench source structures 41. Specifically, the multiple contact regions 70 are formed in the inner portions of the active surface 6 so that the distance between the end of the first trench source structure 41 and the outermost contact region 70 is greater than the distance between two contact regions 70 adjacent to each other in the first direction X.

[0143] In this embodiment, the contact regions 70 are not formed in the first trench source structures 41 at portions thereof facing the second trench source structures 51. In addition, the contact regions 70 are not formed in the first trench source structures 41 at portions thereof facing the ends of the trench gate structures 31.

[0144] The plurality of contact regions 70 are exposed from the active surface 6. The plurality of contact regions 70 are formed at intervals from the trench gate structure 31 toward the first trench source structure 41. Each contact region 70 is formed at intervals from the bottom of the second semiconductor region 11 (second concentration region 13) toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a portion of the second semiconductor region 11. Each contact region 70 covers the sidewalls and bottom wall of each first trench source structure 41 in the second semiconductor region 11 (second concentration region 13). The plurality of contact regions 70 are electrically connected to the body region 23 on the sidewalls of each first trench source structure 41.

[0145] The SiC semiconductor device 1 includes a plurality of p-type well regions 71 formed in a surface layer portion of the active surface 6 of the transistor region 20. The plurality of well regions 71 are formed in regions along the plurality of first trench source structures 41, respectively. The plurality of well regions 71 each have a p-type impurity concentration less than the p-type impurity concentration of each contact region 70. The p-type impurity concentration of the plurality of well regions 71 preferably exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of the plurality of well regions 71 is 1×10 16 cm -3 More than 1×10 18 cm -3 It may be the following:

[0146] The multiple well regions 71 are formed in one-to-one correspondence with the multiple first trench source structures 41. Each well region 71 is formed in a strip shape extending along the corresponding first trench source structure 41 in plan view, and is exposed from the third connection surface 8C and the fourth connection surface 8D. Each well region 71 is formed at an interval on the first trench source structure 41 side from the trench gate structure 31, exposing the trench gate structure 31.

[0147] Each well region 71 covers the sidewalls and bottom wall of each first trench source structure 41. Each well region 71 covers each first trench source structure 41 with multiple contact regions 70 sandwiched between them. That is, each well region 71 includes a portion that directly covers each first trench source structure 41 with multiple contact regions 70 sandwiched between them, and a portion that covers each first trench source structure 41 with multiple contact regions 70 sandwiched between them. Each well region 71 is electrically connected to the body region 23 on the sidewall of each first trench source structure 41.

[0148] The thickness of the portion of each well region 71 covering the bottom wall of each first trench source structure 41 preferably exceeds the thickness of the portion of each well region 71 covering the side wall of each first trench source structure 41. The thickness of the portion of each well region 71 covering the side wall of each first trench source structure 41 is the thickness in the normal direction to the side wall of each first trench source structure 41. The thickness of the portion of each well region 71 covering the bottom wall of each first trench source structure 41 is the thickness in the normal direction to the bottom wall of each first trench source structure 41.

[0149] In this embodiment, the multiple well regions 71 are also formed in regions along the multiple second trench source structures 51. The multiple well regions 71 are formed in a one-to-one correspondence with the multiple second trench source structures 51. Each well region 71 is formed in a strip shape extending along the corresponding second trench source structure 51 in plan view. Each well region 71 along each second trench source structure 51 on the third connection surface 8C side is exposed from the third connection surface 8C. Each well region 71 along each second trench source structure 51 on the fourth connection surface 8D side is exposed from the fourth connection surface 8D.

[0150] Each well region 71 is formed at a distance from the trench gate structure 31 toward the second trench source structure 51, exposing the trench gate structure 31. Each well region 71 covers the sidewalls and bottom wall of each second trench source structure 51. Each well region 71 directly covers each second trench source structure 51. Each well region 71 is electrically connected to the body region 23 on the sidewall of each second trench source structure 51.

[0151] The thickness of the portion of each well region 71 covering the bottom wall of each second trench source structure 51 preferably exceeds the thickness of the portion of each well region 71 covering the side wall of each second trench source structure 51. The thickness of the portion of each well region 71 covering the side wall of each second trench source structure 51 is the thickness in the normal direction to the side wall of each second trench source structure 51. The thickness of the portion of each well region 71 covering the bottom wall of each second trench source structure 51 is the thickness in the normal direction to the bottom wall of each second trench source structure 51.

[0152] Each well region 71 is formed at an interval from the bottom of the second semiconductor region 11 (second concentration region 13) toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In other words, each well region 71 is electrically connected to the second semiconductor region 11 (second concentration region 13).

[0153] The bottoms of the multiple well regions 71 are preferably formed at a substantially constant depth relative to the bottom walls of the multiple first trench source structures 41 and the multiple second trench source structures 51. The multiple well regions 71 form pn junctions with the second semiconductor region 11 (second concentration region 13) and expand the depletion layer in the width and depth directions of the SiC chip 2. The multiple well regions 71 bring the trench insulated gate MISFET closer to a pn junction diode structure and alleviate the electric field within the SiC chip 2.

[0154] The multiple well regions 71 are preferably formed so that a depletion layer overlaps the bottom wall of the trench gate structure 31. The second concentration regions 13 interposed between the multiple well regions 71 reduce JFET (Junction Field Effect Transistor) resistance. The second concentration regions 13 located below the multiple well regions 71 reduce current spreading resistance. In such a structure, the first concentration regions 12 increase the breakdown voltage of the SiC chip 2.

[0155] The SiC semiconductor device 1 includes a plurality of p-type gate well regions 72 (a plurality of gate well regions) formed in regions along the plurality of trench gate structures 31 in the surface layer portion of the active surface 6. The plurality of gate well regions 72 have a p-type impurity concentration lower than the p-type impurity concentration of the plurality of contact regions 70. The p-type impurity concentration of each gate well region 72 preferably exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of each gate well region 72 is 1×10 16 cm -3 More than 1×10 18 cm -3 The p-type impurity concentration of each gate well region 72 is preferably approximately equal to the p-type impurity concentration of each well region 71.

[0156] The multiple gate well regions 72 are formed in a one-to-one correspondence with the multiple trench gate structures 31. Each gate well region 72 is formed in a strip shape extending along each trench gate structure 31 in a plan view. Each gate well region 72 is formed at an interval from the first trench source structure 41 toward the trench gate structure 31. Each gate well region 72 covers the sidewalls and bottom wall of each trench gate structure 31. Each gate well region 72 is electrically connected to the body region 23 on the sidewall of each trench gate structure 31.

[0157] Each gate well region 72 is formed at an interval from the bottom of the second semiconductor region 11 (second concentration region 13) toward the first main surface 3, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In this embodiment, each gate well region 72 is formed in the second concentration region 13, and faces the first concentration region 12 across a part of the second concentration region 13.

[0158] The thickness of the portion of each gate well region 72 covering the bottom wall of each trench gate structure 31 preferably exceeds the thickness of the portion of each gate well region 72 covering the side wall of each trench gate structure 31. The thickness of the portion of each gate well region 72 covering the side wall of each trench gate structure 31 is the thickness in the normal direction to the side wall of each trench gate structure 31. The thickness of the portion of each gate well region 72 covering the bottom wall of each trench gate structure 31 is the thickness in the normal direction to the bottom wall of each trench gate structure 31.

[0159] The bottoms of the multiple gate well regions 72 are located closer to the bottom wall of the trench gate structure 31 than the bottoms of the multiple well regions 71. The bottoms of the multiple gate well regions 72 are preferably formed at a substantially constant depth relative to the bottom walls of the multiple trench gate structures 31. The multiple gate well regions 72 form pn junctions with the second semiconductor region 11 (second concentration region 13) and expand the depletion layer in the width and depth directions of the SiC chip 2. The multiple gate well regions 72 bring the trench insulated gate MISFET closer to a pn junction diode structure and reduce the electric field within the SiC chip 2.

[0160] 13 to 21 again, SiC semiconductor device 1 includes a plurality of p-type dummy contact regions 73 formed in a surface layer portion of active surface 6 of first peripheral region 21. The plurality of dummy contact regions 73 are formed in regions along the plurality of second dummy trench source structures 63 of second dummy structure 60B, respectively, but are not formed in regions along the plurality of first dummy trench source structures 61 of first dummy structure 60A.

[0161] The plurality of dummy contact regions 73 each have a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of the plurality of dummy contact regions 73 is 1×10 18 cm -3 More than 1×10 21 cm -3The p-type impurity concentration of the plurality of dummy contact regions 73 preferably exceeds the p-type impurity concentration of the plurality of well regions 71. The p-type impurity concentration of the plurality of dummy contact regions 73 preferably is approximately equal to the p-type impurity concentration of the plurality of contact regions 70.

[0162] The multiple dummy contact regions 73 are formed in a one-to-many correspondence with each second dummy trench source structure 63 in a plan view. The multiple dummy contact regions 73 are formed at intervals along each second dummy trench source structure 63 in a plan view, partially exposing each second dummy trench source structure 63. In this embodiment, the multiple dummy contact regions 73 are each formed in a strip shape extending in the first direction X in a plan view. It is preferable that the multiple dummy contact regions 73 have a length that exceeds the distance between two adjacent dummy contact regions 73 in the first direction X.

[0163] The multiple dummy contact regions 73 covering one second dummy trench source structure 63 face the multiple dummy contact regions 73 covering another nearby second dummy trench source structure 63 in a one-to-one correspondence in the second direction Y. That is, in this embodiment, the multiple dummy contact regions 73 are arranged in a matrix form as a whole at intervals in the first direction X and the second direction Y in plan view. In this embodiment, the multiple dummy contact regions 73 face the multiple contact regions 70 in the second direction Y in plan view.

[0164] The multiple dummy contact regions 73 covering one second dummy trench source structure 63 may be arranged offset by a half pitch in the first direction X with respect to the multiple dummy contact regions 73 covering another adjacent second dummy trench source structure 63. In other words, the multiple dummy contact regions 73 may be arranged in a staggered pattern overall in plan view with intervals in the first direction X and the second direction Y. In this case, the multiple dummy contact regions 73 may face the multiple contact regions 70 in the second direction Y in plan view.

[0165] In this embodiment, the multiple dummy contact regions 73 are formed at intervals from the periphery (third connection surface 8C and fourth connection surface 8D) of the active surface 6 to the inner portions of the multiple second dummy trench source structures 63 in plan view. Specifically, the multiple dummy contact regions 73 are formed in the inner portions of the active surface 6 so that the distance between the end of the second dummy trench source structure 63 and the outermost dummy contact region 73 is greater than the distance between two dummy contact regions 73 adjacent to each other in the first direction X.

[0166] In this embodiment, the dummy contact regions 73 are not formed in portions of the second dummy trench source structures 63 that face the second trench source structures 51. Furthermore, the dummy contact regions 73 are not formed in portions of the second dummy trench source structures 63 that face the ends of the trench gate structures 31. In other words, the dummy contact regions 73 are formed along the second dummy trench source structures 63 in the same manner as the contact regions 70.

[0167] The plurality of dummy contact regions 73 are exposed from the active surface 6. The plurality of dummy contact regions 73 are formed at intervals from the dummy trench gate structure 62 toward the second dummy trench source structure 63. Each dummy contact region 73 is formed at intervals from the bottom of the second semiconductor region 11 (second concentration region 13) toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. Each dummy contact region 73 covers the sidewalls and bottom wall of each second dummy trench source structure 63 in the second semiconductor region 11 (second concentration region 13). The plurality of dummy contact regions 73 are electrically connected to the body region 23 on the sidewalls of each second dummy trench source structure 63.

[0168] The SiC semiconductor device 1 includes a plurality of p-type dummy well regions 74 (a plurality of dummy well regions) formed in a surface layer portion of the active surface 6 of the first peripheral region 21. The plurality of dummy well regions 74 (the dummy well regions) each have a p-type impurity concentration less than the p-type impurity concentration of the plurality of dummy contact regions 73. The p-type impurity concentration of the plurality of dummy well regions 74 preferably exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of the plurality of dummy well regions 74 is 1×10 16 cm -3 More than 1×10 18 cm -3 The p-type impurity concentration of the plurality of dummy well regions 74 is preferably approximately equal to the p-type impurity concentration of the plurality of well regions 71.

[0169] The multiple dummy well regions 74 are formed in the first dummy structure 60A in regions along the multiple first dummy trench source structures 61. The multiple dummy well regions 74 are formed in a one-to-one correspondence with the multiple first dummy trench source structures 61. Specifically, each dummy well region 74 covers a corresponding first dummy trench source structure 61 at a distance from the adjacent first dummy trench source structure 61.

[0170] Each dummy well region 74 is formed in a strip shape extending along each first dummy trench source structure 61 in a plan view and is exposed from the third connection surface 8C and the fourth connection surface 8D. Each dummy well region 74 covers the sidewalls and bottom wall of each first dummy trench source structure 61. Each dummy well region 74 directly covers each first dummy trench source structure 61. Each dummy well region 74 is electrically connected to the body region 23 on the sidewall of each first dummy trench source structure 61.

[0171] The thickness of the portion of each dummy well region 74 covering the bottom wall of each first dummy trench source structure 61 preferably exceeds the thickness of the portion of each dummy well region 74 covering the sidewall of each first dummy trench source structure 61. The thickness of the portion of each dummy well region 74 covering the sidewall of each first dummy trench source structure 61 is the thickness in the normal direction to the sidewall of each first dummy trench source structure 61. The thickness of the portion of each dummy well region 74 covering the bottom wall of each first dummy trench source structure 61 is the thickness in the normal direction to the bottom wall of each first dummy trench source structure 61.

[0172] In this embodiment, the multiple dummy well regions 74 are also formed in the second dummy structure 60B in regions along the multiple second dummy trench source structures 63. The multiple dummy well regions 74 are formed in a one-to-one correspondence with the multiple second dummy trench source structures 63. Each dummy well region 74 covers the corresponding second dummy trench source structure 63 at a distance from the dummy trench gate structure 62 toward the second dummy trench source structure 63.

[0173] Each dummy well region 74 is formed in a strip shape extending along each second dummy trench source structure 63 in a plan view, and is exposed from the third connection surface 8C and the fourth connection surface 8D. Each dummy well region 74 covers the sidewalls and bottom wall of each second dummy trench source structure 63. Each dummy well region 74 covers each second dummy trench source structure 63 with multiple dummy contact regions 73 sandwiched between them.

[0174] That is, each dummy well region 74 includes a portion that directly covers each second dummy trench source structure 63 with the multiple dummy contact regions 73 sandwiched therebetween, and a portion that covers each second dummy trench source structure 63 with the multiple dummy contact regions 73 sandwiched therebetween. Each dummy well region 74 is electrically connected to the body region 23 at the sidewall of each second dummy trench source structure 63.

[0175] The thickness of the portion of each dummy well region 74 covering the bottom wall of each second dummy trench source structure 63 preferably exceeds the thickness of the portion of each dummy well region 74 covering the sidewall of each second dummy trench source structure 63. The thickness of the portion of each dummy well region 74 covering the sidewall of each second dummy trench source structure 63 is the thickness in the normal direction to the sidewall of each second dummy trench source structure 63. The thickness of the portion of each dummy well region 74 covering the bottom wall of each second dummy trench source structure 63 is the thickness in the normal direction to the bottom wall of each second dummy trench source structure 63.

[0176] Each dummy well region 74 is formed at an interval from the bottom of the second semiconductor region 11 (second concentration region 13) toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In other words, each dummy well region 74 is electrically connected to the second semiconductor region 11 (second concentration region 13). The bottoms of the multiple dummy well regions 74 are preferably formed at a substantially constant depth relative to the bottom walls of the multiple first dummy trench source structures 61 and the multiple second dummy trench source structures 63.

[0177] The bottoms of the multiple dummy well regions 74 are preferably formed at approximately the same depth as the bottoms of the multiple well regions 71. The multiple dummy well regions 74 form pn junctions with the second semiconductor region 11 (second concentration region 13) and expand the depletion layer in the width and depth directions of the SiC chip 2. The multiple dummy well regions 74 bring the trench insulated gate type MISFET closer to a pn junction diode structure and relieve the electric field within the SiC chip 2. The multiple dummy well regions 74 are preferably formed so that the depletion layer overlaps the bottom wall of the dummy trench gate structure 62.

[0178] The SiC semiconductor device 1 includes a plurality of p-type dummy gate well regions 75 formed in regions along the plurality of dummy trench gate structures 62 in the surface layer portion of the active surface 6. The plurality of dummy gate well regions 75 have a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of each dummy gate well region 75 is preferably lower than the p-type impurity concentration of the plurality of dummy contact regions 73. The p-type impurity concentration of each dummy gate well region 75 is 1×10 16 cm -3 More than 1×10 18 cm -3 The p-type impurity concentration of each dummy gate well region 75 is preferably approximately equal to the p-type impurity concentration of each gate well region 72.

[0179] The multiple dummy gate well regions 75 are formed in a one-to-one correspondence with the multiple dummy trench gate structures 62. Each dummy gate well region 75 is formed in a strip shape extending along each dummy trench gate structure 62 in a plan view. Each dummy gate well region 75 is formed at an interval from the second dummy trench source structure 63 toward the dummy trench gate structure 62. Each dummy gate well region 75 covers the sidewalls and bottom wall of each dummy trench gate structure 62. Each dummy gate well region 75 is electrically connected to the body region 23 on the sidewall of each dummy trench gate structure 62.

[0180] Each dummy gate well region 75 is formed at an interval from the bottom of the second semiconductor region 11 (second concentration region 13) toward the first main surface 3, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In this embodiment, each dummy gate well region 75 is formed in the second concentration region 13, and faces the first concentration region 12 across a part of the second concentration region 13.

[0181] The thickness of the portion of each dummy gate well region 75 covering the bottom wall of each dummy trench gate structure 62 preferably exceeds the thickness of the portion of each dummy gate well region 75 covering the sidewall of each dummy trench gate structure 62. The thickness of the portion of each dummy gate well region 75 covering the sidewall of each dummy trench gate structure 62 is the thickness in the normal direction to the sidewall of each dummy trench gate structure 62. The thickness of the portion of each dummy gate well region 75 covering the bottom wall of each dummy trench gate structure 62 is the thickness in the normal direction to the bottom wall of each dummy trench gate structure 62.

[0182] The bottoms of the plurality of dummy gate well regions 75 are located closer to the bottom wall of the dummy trench gate structure 62 than the bottoms of the plurality of dummy well regions 74. The bottoms of the plurality of dummy gate well regions 75 are preferably formed at a substantially constant depth from the bottom walls of the plurality of dummy trench gate structures 62. The bottoms of the plurality of dummy gate well regions 75 are preferably formed at a depth substantially equal to the depth of the bottoms of the plurality of gate well regions 72.

[0183] The multiple dummy gate well regions 75 form pn junctions with the second semiconductor region 11 (second concentration region 13) and expand the depletion layer in the width and depth directions of the SiC chip 2. The multiple dummy gate well regions 75 bring the trench insulated gate type MISFET closer to a pn junction diode structure and reduce the electric field in the SiC chip 2.

[0184] Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 1. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 1. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 1. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 1. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 1. Fig. 27 is a plan view illustrating the structure of the first principal surface electrode 120. Fig. 28 is a plan view illustrating the structure of the second inorganic insulating film 150.

[0185] The SiC semiconductor device 1 includes a p-type outer contact region 80 formed in the surface layer portion of the outer surface 7. The outer contact region 80 has a size of 1×10 18 cm -3 More than 1×10 21 cm -3 The outer contact region 80 may have the following p-type impurity concentration: The outer contact region 80 has a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 23. The p-type impurity concentration of the outer contact region 80 is preferably approximately equal to the p-type impurity concentration of the contact region 70 (dummy contact region 73).

[0186] The outer contact region 80 is formed in a region between the periphery of the active surface 6 and the periphery of the outer surface 7, spaced apart from the periphery of the active surface 6 (first to fourth connection surfaces 8A to 8D) and the periphery of the outer surface 7 (first to fourth side surfaces 5A to 5D) in a plan view. The outer contact region 80 extends in a strip shape along the active surface 6 (first to fourth connection surfaces 8A to 8D) in a plan view. In this embodiment, the outer contact region 80 is formed in a ring shape surrounding the active surface 6 in a plan view. Specifically, the outer contact region 80 is formed in a quadrangular ring shape having four sides parallel to the active surface 6 in a plan view.

[0187] The outer contact region 80 is formed at a distance from the bottom of the second semiconductor region 11 to the outer side surface 7. Specifically, the outer contact region 80 is formed at a distance from the bottom of the second concentration region 13 to the outer side surface 7. The entire outer contact region 80 is located on the bottom side of the second semiconductor region 11 with respect to the bottom walls of the plurality of trench gate structures 31 and the bottom walls of the plurality of dummy trench gate structures 62. The bottom of the outer contact region 80 is located on the bottom side of the second semiconductor region 11 with respect to the bottom walls of the plurality of first trench source structures 41, the bottom walls of the plurality of second trench source structures 51, the bottom walls of the plurality of first dummy trench source structures 61, and the bottom walls of the plurality of second dummy trench source structures 63.

[0188] The bottom of the outer contact region 80 is preferably formed at a depth position substantially equal to that of the bottoms of the plurality of contact regions 70 and the plurality of dummy contact regions 73. The outer contact region 80 forms a pn junction with the second semiconductor region 11 (specifically, the second concentration region 13). This forms a pn junction diode with the outer contact region 80 as the anode and the second semiconductor region 11 as the cathode. The outer contact region 80 may also be referred to as an anode region.

[0189] The SiC semiconductor device 1 includes a p-type outer well region 81 formed in the surface layer portion of the outer side surface 7. The p-type impurity concentration of the outer well region 81 is 1×10 16 cm -3 More than 1×10 18 cm -3 or less. The outer well region 81 has a p-type impurity concentration that is lower than the p-type impurity concentration of the outer contact region 80. The p-type impurity concentration of the outer well region 81 is preferably approximately equal to the p-type impurity concentration of the well region 71 (dummy well region 74). The p-type impurity concentration of the outer well region 81 is preferably approximately equal to the p-type impurity concentration of the gate well region 72 (dummy gate well region 75).

[0190] The outer well region 81 is formed in a region between the periphery of the active surface 6 (first to fourth connection surfaces 8A to 8D) and the outer contact region 80 in a plan view. The outer well region 81 extends in a strip shape along the active surface 6 (first to fourth connection surfaces 8A to 8D) in a plan view. In this embodiment, the outer well region 81 is formed in a ring shape (a quadrangular ring in this embodiment) surrounding the active surface 6 (first to fourth connection surfaces 8A to 8D) in a plan view.

[0191] In this embodiment, the outer well region 81 is formed over the entire region between the first to fourth connection surfaces 8A to 8D and the outer contact region 80. The outer well region 81 further extends from the outer side surface 7 toward the first to fourth connection surfaces 8A to 8D, and covers the first to fourth connection surfaces 8A to 8D within the SiC chip 2. The outer well region 81 is electrically connected to the well region 71, the dummy well region 74, and the dummy gate well region 75 in the surface layer portions of the first to fourth connection surfaces 8A to 8D. The portions of the outer well region 81 that cover the first to fourth connection surfaces 8A to 8D may be considered to be an integral well region that integrally includes the well region 71, the dummy well region 74, and the dummy gate well region 75.

[0192] The outer well region 81 is continuous with the well region 71 at a portion where the bottom wall of the first trench source structure 41 communicates with the outer surface 7. That is, the outer well region 81 is continuously extended in the planar direction from a portion of the well region 71 that covers the bottom wall of the first trench source structure 41 toward the outer surface 7. The outer well region 81 is continuous with the well region 71 at a portion where the bottom wall of the second trench source structure 51 communicates with the outer surface 7. That is, the outer well region 81 is continuously extended in the planar direction from a portion of the well region 71 that covers the bottom wall of the second trench source structure 51 toward the outer surface 7.

[0193] The outer well region 81 is continuous with the dummy well region 74 at a portion where the bottom wall of the first dummy trench source structure 61 communicates with the outer surface 7. That is, the outer well region 81 is continuously extended in the surface direction from a portion of the dummy well region 74 that covers the bottom wall of the first dummy trench source structure 61 toward the outer surface 7. The outer well region 81 is continuous with the dummy well region 74 at a portion where the bottom wall of the second dummy trench source structure 63 communicates with the outer surface 7. That is, the outer well region 81 is continuously extended in the surface direction from a portion of the dummy well region 74 that covers the bottom wall of the second dummy trench source structure 63 toward the outer surface 7.

[0194] The outer well region 81 is formed at a distance from the bottom of the second semiconductor region 11 to the outer surface 7. Specifically, the outer well region 81 is formed at a distance from the bottom of the second concentration region 13 to the outer surface 7. The entire outer well region 81 is located on the bottom side of the second semiconductor region 11 with respect to the bottom walls of the plurality of trench gate structures 31 and the bottom walls of the plurality of dummy trench gate structures 62.

[0195] The outer well region 81 is electrically connected to the outer contact region 80 at the outer side surface 7. The outer well region 81 is formed deeper than the outer contact region 80. The bottom of the outer well region 81 is located closer to the bottom of the second semiconductor region 11 than the bottom walls of the plurality of first trench source structures 41, the bottom walls of the plurality of second trench source structures 51, the bottom walls of the plurality of first dummy trench source structures 61, and the bottom walls of the plurality of second dummy trench source structures 63. The bottom of the outer well region 81 is preferably formed at a depth substantially equal to the bottoms of the well region 71 and the dummy well region 74.

[0196] The outer well region 81 forms a pn junction with the second semiconductor region 11 (specifically, the second concentration region 13) together with the outer contact region 80. The outer well region 81 also forms a pn junction with the second semiconductor region 11 in portions along the first to fourth connection surfaces 8A to 8D. That is, pn junctions are formed in the SiC chip 2 in portions along the first to fourth connection surfaces 8A to 8D.

[0197] The SiC semiconductor device 1 includes at least one (preferably two or more and twenty or less) p-type field region 82A-82E formed in a surface layer portion of the outer surface 7 in a region between the outer contact region 80 and the periphery of the outer surface 7 (first to fourth side surfaces 5A-5D). In this embodiment, the SiC semiconductor device 1 includes five field regions 82A-82E. The five field regions 82A-82E include a first field region 82A, a second field region 82B, a third field region 82C, a fourth field region 82D, and a fifth field region 82E. The first to fifth field regions 82A-82E are formed at intervals in this order from the outer contact region 80 side toward the periphery of the outer surface 7.

[0198] The field regions 82A to 82E relax the electric field at the outer surface 7. The number, width, depth, p-type impurity concentration, etc. of the field regions 82A to 82E can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentration of the field regions 82A to 82E is 1×10 15 cm -3 More than 1×10 18 cm -3 It may be the following:

[0199] Each of the field regions 82A-82E is formed in a strip shape extending along the active surface 6 in a plan view. Each of the field regions 82A-82E is formed in a ring shape surrounding the active surface 6 in a plan view. Specifically, each of the field regions 82A-82E is formed in a quadrangular ring shape having four sides parallel to the active surface 6 (first to fourth connecting surfaces 8A-8D) in a plan view. Each of the field regions 82A-82E may be referred to as an FLR (Field Limiting Ring) region.

[0200] In this embodiment, the innermost first field region 82A is connected to the outer contact region 80. The innermost first field region 82A, together with the outer contact region 80, forms a pn junction with the second semiconductor region 11 (specifically, the second concentration region 13). On the other hand, the second to fifth field regions 82B to 82E are formed in an electrically floating state at intervals from the outer contact region 80. Each of the field regions 82A to 82E is formed deeper than the outer contact region 80. Each of the field regions 82A to 82E is formed at an interval from the bottom of the second semiconductor region 11 to the outer side surface 7. Specifically, each of the field regions 82A to 82E is formed at an interval from the bottom of the second concentration region 13 to the outer side surface 7.

[0201] The entirety of each of the field regions 82A-82E is located on the bottom side of the second semiconductor region 11 relative to the bottom walls of the plurality of trench gate structures 31 and the plurality of dummy trench gate structures 62. The bottom of each of the field regions 82A-82E is located on the bottom side of the second semiconductor region 11 relative to the bottom walls of the plurality of first trench source structures 41, the bottom walls of the plurality of second trench source structures 51, the bottom walls of the plurality of first dummy trench source structures 61, and the bottom walls of the plurality of second dummy trench source structures 63.

[0202] 6 to 21, the SiC semiconductor device 1 includes a main surface insulating film 90 covering the first main surface 3. The main surface insulating film 90 specifically covers the active surface 6, the outer side surface 7, and the first to fourth connecting surfaces 8A to 8D in the form of a film. The main surface insulating film 90 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 90 has a single-layer structure made of a silicon oxide film. The main surface insulating film 90 specifically includes a silicon oxide film made of an oxide of the SiC chip 2. The thickness of the main surface insulating film 90 may be 50 nm or more and 500 nm or less.

[0203] The main surface insulating film 90 covers the active surface 6 so as to be continuous with the gate insulating film 33 of the multiple trench gate structures 31, the source insulating film 43 of the multiple first trench source structures 41, the source insulating film 43 of the multiple second trench source structures 51, the source insulating film 43 of the multiple first dummy trench source structures 61, the gate insulating film 33 of the multiple dummy trench gate structures 62, and the source insulating film 43 of the multiple second dummy trench source structures 63.

[0204] In other words, the main surface insulating film 90 exposes the gate electrodes 34 of the multiple trench gate structures 31, the source electrodes 44 of the multiple first trench source structures 41, the source electrodes 44 of the multiple second trench source structures 51, the source electrodes 44 of the multiple first dummy trench source structures 61, the gate electrodes 34 of the multiple dummy trench gate structures 62, and the source electrodes 44 of the multiple second dummy trench source structures 63 on the active surface 6.

[0205] The main surface insulating film 90 covers the first to fourth connection surfaces 8A to 8D so as to be continuous with the gate insulating film 33 of the multiple trench gate structures 31, the source insulating film 43 of the multiple first trench source structures 41, the source insulating film 43 of the multiple second trench source structures 51, the source insulating film 43 of the multiple first dummy trench source structures 61, the gate insulating film 33 of the multiple dummy trench gate structures 62, and the source insulating film 43 of the multiple second dummy trench source structures 63.

[0206] That is, the main surface insulating film 90 exposes, at the first to fourth connecting surfaces 8A to 8D, the gate electrodes 34 of the plurality of trench gate structures 31, the source electrodes 44 of the plurality of first trench source structures 41, the source electrodes 44 of the plurality of second trench source structures 51, the source electrodes 44 of the plurality of first dummy trench source structures 61, the gate electrodes 34 of the plurality of dummy trench gate structures 62, and the source electrodes 44 of the plurality of second dummy trench source structures 63. The main surface insulating film 90 is formed at a distance inward from the periphery of the outer surface 7 (first to fourth side surfaces 5A to 5D), and has a peripheral end wall that exposes the periphery of the outer surface 7.

[0207] 6 and 8, the SiC semiconductor device 1 includes a plurality of gate contact electrodes 91 covering the gate electrode 34 of the trench gate structure 31 above the first main surface 3 (specifically, the active surface 6) in the transistor region 20. In FIG. 6, the plurality of gate contact electrodes 91 are indicated by thick dashed lines. In this embodiment, the plurality of gate contact electrodes 91 are not formed in the first peripheral region 21 or the second peripheral region 22. That is, the plurality of gate contact electrodes 91 are not formed on the gate electrode 34 of the dummy trench gate structure 62.

[0208] The multiple gate contact electrodes 91 cover the multiple trench gate structures 31, respectively, and are electrically connected to the corresponding gate electrodes 34. Specifically, the multiple gate contact electrodes 91 are formed on both ends of the multiple trench gate structures 31, respectively, with a gap between them from the inner parts of the multiple trench gate structures 31. In other words, the multiple gate contact electrodes 91 are electrically connected to the corresponding gate electrodes 34 in regions close to both ends of the trench gate structures 31 relative to the inner parts of the trench gate structures 31.

[0209] The plurality of gate contact electrodes 91 are respectively extended from above the plurality of trench gate structures 31 onto the main surface insulating film 90. The plurality of gate contact electrodes 91 are respectively formed at intervals in the second direction Y from the plurality of first trench source structures 41 in plan view. The plurality of gate contact electrodes 91 are respectively formed at intervals in the first direction X from the plurality of second trench source structures 51 in plan view.

[0210] The plurality of gate contact electrodes 91 are arranged alternately with the plurality of first trench source structures 41 in the second direction Y in a manner of sandwiching one first trench source structure 41 in a plan view. The plurality of gate contact electrodes 91 are each formed in a strip shape extending in the first direction X in this form. The plurality of gate contact electrodes 91 are formed in a stripe shape extending in the first direction X in a plan view. The plurality of gate contact electrodes 91 do not face the plurality of second trench source structures 51 in the second direction Y in a plan view.

[0211] The plurality of gate contact electrodes 91 have an electrode width WE (W1 < WE) that exceeds the first width W1 of the trench gate structure 31 with respect to the first direction X. The electrode width WE is the width in the direction (second direction Y) orthogonal to the direction (first direction X) in which the gate contact electrode 91 extends. The plurality of gate contact electrodes 91 have a length less than the length of the trench gate structure 31 with respect to the second direction Y.

[0212] The plurality of gate contact electrodes 91 each have an electrode surface 91a extending along the active surface 6. In this form, the plurality of gate contact electrodes 91 are formed in a tapered shape (frustum of a square pyramid shape) in which the electrode width WE narrows from the active surface 6 toward the electrode surface 91a. The electrode surface 91a is preferably formed wider than the electrode surface of the gate electrode 34 with respect to the second direction Y. That is, the electrode surface 91a preferably includes a portion facing the gate electrode 34 in the normal direction Z and a portion facing the region outside the trench gate structure 31 (that is, the main surface insulating film 90) in the normal direction Z.

[0213] Each gate contact electrode 91 is preferably made of conductive polysilicon. Each gate contact electrode 91 may include n-type polysilicon doped with n-type impurities and / or p-type polysilicon doped with p-type impurities. Each gate contact electrode 91 is preferably made of the same conductive material as each gate electrode 34. In this embodiment, each gate contact electrode 91 is made of an extension portion extending from each gate electrode 34 above the active surface 6. In other words, the multiple gate contact electrodes 91 are extended from the gate electrode 34 onto the main surface insulating film 90 via the third portion 33c of the gate insulating film 33.

[0214] 5 to 21, the SiC semiconductor device 1 includes a sidewall wiring 100 formed above the outer side surface 7 so as to cover at least one of the first to fourth connection surfaces 8A to 8D. The sidewall wiring 100 is formed as a sidewall structure (step reduction structure) that reduces the step formed between the active surface 6 and the outer side surface 7. Specifically, the sidewall wiring 100 is formed on the main surface insulating film 90.

[0215] The sidewall wiring 100 preferably covers at least one of the third connecting surface 8C and the fourth connecting surface 8D. In this embodiment, the sidewall wiring 100 is formed in a strip shape extending along the first to fourth connecting surfaces 8A to 8D in a plan view. Specifically, the sidewall wiring 100 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 6 in a plan view, and covers the entire areas of the first to fourth connecting surfaces 8A to 8D.

[0216] That is, on the first connecting surface 8A side and the second connecting surface 8B side, the sidewall wiring 100 extends in a direction (first direction X) along the trench gate structure 31, the first trench source structure 41, the second trench source structure 51, the first dummy trench source structure 61, the dummy trench gate structure 62, and the second dummy trench source structure 63. On the third connecting surface 8C side and the fourth connecting surface 8D side, the sidewall wiring 100 extends in a direction (second direction Y) intersecting the trench gate structure 31, the first trench source structure 41, the second trench source structure 51, the first dummy trench source structure 61, the dummy trench gate structure 62, and the second dummy trench source structure 63.

[0217] The portions of the sidewall wiring 100 that cover the four corners of the active surface 6 (corners of the first to fourth connecting surfaces 8A to 8D) are curved toward the outer surface 7. Therefore, in this embodiment, the sidewall wiring 100 is formed in a quadrangular ring shape with curved corners as a whole in a plan view.

[0218] The sidewall wiring 100 includes a portion extending in a film-like manner along the outer surface 7 and portions extending in a film-like manner along the first to fourth connecting surfaces 8A to 8D. The portion of the sidewall wiring 100 located on the outer surface 7 may cover the outer surface 7 in a region on the outer surface 7 side relative to the active surface 6. The portion of the sidewall wiring 100 located on the outer surface 7 may have a thickness less than the thickness (first depth D1) of the active plateau 9.

[0219] The portions of the sidewall wiring 100 located on the first to fourth connecting faces 8A to 8D are formed in the form of a film along the first to fourth connecting faces 8A to 8D. The portions of the sidewall wiring 100 located on the first to fourth connecting faces 8A to 8D may have outer surfaces that slope obliquely downward from the active surface 6 toward the outer surface 7. In this case, the outer surfaces of the sidewall wiring 100 may be formed in a curved shape that protrudes in a direction away from the first to fourth connecting faces 8A to 8D, or may be formed in a curved shape that is recessed toward the first to fourth connecting faces 8A to 8D.

[0220] The sidewall wiring 100 faces a part of the outer well region 81 on the outer side surface 7, with the main surface insulating film 90 sandwiched therebetween. The sidewall wiring 100 also faces the outer contact region 80 on the outer side surface 7, with the main surface insulating film 90 sandwiched therebetween. In this embodiment, the sidewall wiring 100 is formed at an interval toward the active surface 6 from the field regions 82A-82E in plan view, and does not face the field regions 82A-82E with the main surface insulating film 90 sandwiched therebetween.

[0221] The sidewall wiring 100 faces the SiC chip 2 on the first to fourth connection surfaces 8A to 8D, with the main surface insulating film 90 sandwiched therebetween. That is, the sidewall wiring 100 faces the pn junctions (the pn junctions of the outer well region 81 and the second semiconductor region 11) along the first to fourth connection surfaces 8A to 8D, with the main surface insulating film 90 sandwiched therebetween, on the first to fourth connection surfaces 8A to 8D.

[0222] The sidewall wiring 100 further covers, on the first to fourth connecting surfaces 8A to 8D, exposed portions of the first trench source structure 41, the second trench source structure 51, the first dummy trench source structure 61, the dummy trench gate structure 62, and the second dummy trench source structure 63. As a result, the sidewall wiring 100 is electrically connected to the first trench source structure 41, the second trench source structure 51, the first dummy trench source structure 61, the dummy trench gate structure 62, and the second dummy trench source structure 63 on the first to fourth connecting surfaces 8A to 8D.

[0223] Specifically, the sidewall wiring 100 is electrically connected on the first to fourth connecting surfaces 8A to 8D to the source electrode 44 of the first trench source structure 41, the source electrode 44 of the second trench source structure 51, the source electrode 44 of the first dummy trench source structure 61, the gate electrode 34 of the dummy trench gate structure 62, and the source electrode 44 of the second dummy trench source structure 63. In other words, the sidewall wiring 100 is formed on the outer surface 7 as wiring for applying a source potential.

[0224] In this embodiment, the sidewall wiring 100 is integrally formed on the first to fourth connection surfaces 8A to 8D with the source electrode 44 of the first trench source structure 41, the source electrode 44 of the second trench source structure 51, the source electrode 44 of the first dummy trench source structure 61, the gate electrode 34 of the dummy trench gate structure 62, and the source electrode 44 of the second dummy trench source structure 63.

[0225] The sidewall wiring 100 has overlapping portions 101 that extend from at least one of the first to fourth connecting surfaces 8A to 8D onto the edge of the active surface 6. The overlapping portions 101 are formed in a strip shape that extends along the edge of the active surface 6 in a plan view. In this embodiment, the overlapping portions 101 extend from all of the first to fourth connecting surfaces 8A to 8D onto the edge of the active surface 6. In other words, the overlapping portions 101 extend along the edge of the active surface 6 in a plan view and are formed in a ring shape that surrounds the inner part of the active surface 6.

[0226] The overlap portion 101 includes a pair of first overlap portions 101A and a pair of second overlap portions 101B. The pair of first overlap portions 101A are portions of the overlap portion 101 that extend along the first connecting surface 8A and the second connecting surface 8B. The pair of second overlap portions 101B are portions of the overlap portion 101 that extend along the third connecting surface 8C and the fourth connecting surface 8D. The pair of first overlap portions 101A have the same structure, and the pair of second overlap portions 101B have the same structure. The structures of the first overlap portion 101A on the first connecting surface 8A side and the second overlap portion 101B on the third connecting surface 8C side will be described below.

[0227] The first overlapping portion 101A faces the active surface 6 with the main surface insulating film 90 interposed therebetween, and covers at least one of the outermost first dummy trench source structures 61. In this embodiment, the first overlapping portion 101A covers the entire area of ​​one of the outermost first dummy trench source structures 61. The first overlapping portion 101A is electrically connected to the source electrode 44 of the outermost first dummy trench source structure 61 on the active surface 6.

[0228] Specifically, the first overlapping portion 101A is formed integrally with the source electrode 44 of the outermost first dummy trench source structure 61 on the active surface 6. The first overlapping portion 101A may cover a plurality of first dummy trench source structures 61. In this case, it is preferable that the number of first dummy trench source structures 61 covered by the first overlapping portion 101A is less than the number of first dummy trench source structures 61 exposed from the first overlapping portion 101A.

[0229] The second overlap portion 101B faces the active surface 6 with the main surface insulating film 90 interposed therebetween, and covers the ends of the first trench source structure 41, the ends of the second trench source structure 51, the ends of the first dummy trench source structure 61, the ends of the dummy trench gate structure 62, and the ends of the second dummy trench source structure 63. The second overlap portion 101B is electrically connected to the source electrode 44 of the first trench source structure 41, the source electrode 44 of the second trench source structure 51, the source electrode 44 of the first dummy trench source structure 61, the gate electrode 34 of the dummy trench gate structure 62, and the source electrode 44 of the second dummy trench source structure 63 on the active surface 6.

[0230] Specifically, the second overlap portion 101B is integrally formed with the source electrode 44 of the first trench source structure 41, the source electrode 44 of the second trench source structure 51, the source electrode 44 of the first dummy trench source structure 61, the gate electrode 34 of the dummy trench gate structure 62, and the source electrode 44 of the second dummy trench source structure 63 on the active surface 6.

[0231] The overlap portion 101 has an overlap width WO. The overlap width WO is the width in a direction orthogonal to the direction in which the overlap portion 101 extends, with reference to the first to fourth connection surfaces 8A to 8D. It is preferable that the overlap width WO is less than the first depth D1 of the outer surface 7 (WO < D1). It is preferable that the overlap width WO is less than the third depth of the first trench source structure 41 (WO < D3). The overlap width WO may be greater than or equal to the second depth D2 of the trench gate structure 31 (WO ≥ D2), or may be less than the second depth D2 (WO < D2).

[0232] The sidewall wiring 100 is preferably made of conductive polysilicon. The sidewall wiring 100 may include n-type polysilicon doped with n-type impurities and / or p-type polysilicon doped with p-type impurities. The sidewall wiring 100 is preferably made of the same conductive material as the gate electrode 34. Furthermore, the sidewall wiring 100 is preferably made of the same conductive material as the source electrode 44.

[0233] The SiC semiconductor device 1 includes a first inorganic insulating film 110 formed on the main surface insulating film 90. The first inorganic insulating film 110 may also be referred to as an "interlayer insulating film," "intermediate insulating film," "upper insulating film," or "covered object." The first inorganic insulating film 110 may have a layered structure including multiple insulating films, or a single-layer structure consisting of a single insulating film. The first inorganic insulating film 110 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first inorganic insulating film 110 may have a layered structure including multiple silicon oxide films, a layered structure including multiple silicon nitride films, or a layered structure including multiple silicon oxynitride films.

[0234] The first inorganic insulating film 110 may have a layered structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are layered in any order. The first inorganic insulating film 110 may have a single-layer structure made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this form, the first inorganic insulating film 110 has a layered structure in which multiple silicon oxide films are layered.

[0235] Specifically, the first inorganic insulating film 110 has a laminated structure including an NSG (nondoped silicate glass) film and a PSG (phosphor silicate glass) film laminated in this order from the main surface insulating film 90 side. The NSG film is made of a silicon oxide film with no added impurities. The PSG film is made of a silicon oxide film with added phosphorus. The thickness of the NSG film may be 10 nm or more and 300 nm or less. The thickness of the PSG film may be 50 nm or more and 500 nm or less. The thickness of the first inorganic insulating film 110 preferably exceeds the thickness of the main surface insulating film 90.

[0236] The first inorganic insulating film 110 covers the transistor region 20, the first peripheral region 21, and the second peripheral region 22 on the active surface 6 in the form of a film. The first inorganic insulating film 110 selectively covers the plurality of trench gate structures 31, the plurality of first trench source structures 41, and the plurality of second trench source structures 51 in the transistor region 20. The first inorganic insulating film 110 covers the entire first dummy structure 60A and the entire second dummy structure 60B in the first peripheral region 21 and the second peripheral region 22. In other words, the first inorganic insulating film 110 collectively covers the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63.

[0237] The first inorganic insulating film 110 covers the sidewall wiring 100 in the region between the active surface 6 and the outer surface 7, and is extended from above the active surface 6 across the first to fourth connecting surfaces 8A to 8D onto the outer surface 7. The first inorganic insulating film 110 covers the sidewall wiring 100 in the form of a film. The first inorganic insulating film 110 covers the main surface insulating film 90 in the form of a film on the outer surface 7. The first inorganic insulating film 110 is formed at a distance inward from the periphery of the outer surface 7 (the first to fourth side surfaces 5A to 5D), and has a peripheral end wall that exposes the peripheral portion of the outer surface 7. The peripheral end wall of the first inorganic insulating film 110, together with the peripheral end wall of the main surface insulating film 90, defines a notched opening 111 that exposes the peripheral portion of the outer surface 7.

[0238] 6 and 14, the first inorganic insulating film 110 has a plurality of gate openings 112 on the active surface 6 side. The plurality of gate openings 112 are formed on the transistor region 20 side, and expose both ends of the plurality of trench gate structures 31. The plurality of gate openings 112 are not formed on the first peripheral region 21 side and the second peripheral region 22 side, and do not expose the plurality of dummy trench gate structures 62.

[0239] In this embodiment, the plurality of gate openings 112 expose the plurality of gate contact electrodes 91 in a one-to-one correspondence, respectively. Of course, the plurality of gate openings 112 may each expose one gate contact electrode 91 in a one-to-many correspondence. In this embodiment, the plurality of gate openings 112 expose the electrode surface 91a of the corresponding gate contact electrode 91 at intervals from the periphery of the corresponding gate contact electrode 91 in plan view.

[0240] That is, each of the multiple gate openings 112 exposes only the electrode surface 91a of the corresponding gate contact electrode 91. In this embodiment, the multiple gate openings 112 are each formed in a strip shape extending in the direction in which the gate contact electrode 91 extends (first direction X). The multiple gate openings 112 are formed in a stripe shape as a whole in a plan view. The planar shape of the multiple gate openings 112 is arbitrary, and they may be formed in a circular shape.

[0241] 11, the first inorganic insulating film 110 has a plurality of source openings 113 on the active surface 6 side. The plurality of source openings 113 are formed on the transistor region 20 side and expose the plurality of first trench source structures 41, respectively. The plurality of source openings 113 do not expose the plurality of second trench source structures 51. In other words, the plurality of second trench source structures 51 are covered by the first inorganic insulating film 110. Furthermore, the plurality of source openings 113 are not formed on the first peripheral region 21 side and the second peripheral region 22 side and do not expose the plurality of first dummy trench source structures 61 and the plurality of second dummy trench source structures 63.

[0242] In this embodiment, the source openings 113 are formed in one-to-one correspondence with the contact regions 70, respectively, and expose the corresponding first trench source structures 41 from multiple locations. That is, the source openings 113 are arranged in a matrix or staggered pattern at intervals in the first direction X and the second direction Y in plan view, according to the arrangement of the contact regions 70.

[0243] In this embodiment, the source openings 113 are each formed in a strip shape extending in the first direction X to correspond to the planar shapes of the contact regions 70. The planar shape of the source openings 113 is arbitrary and may be formed in a circular shape. Each of the source openings 113 exposes the corresponding source region 24 and the corresponding contact region 70 in addition to the source electrode 44 of the corresponding first trench source structure 41. Of course, the source openings 113 may also expose the corresponding first trench source structures 41 in a one-to-one correspondence. In this case, the first trench source structures 41 are preferably formed in a strip shape extending along the corresponding first trench source structures 41.

[0244] 10, 13, and 14, the first inorganic insulating film 110 has at least one sidewall opening 114 on the outer surface 7 side. In this embodiment, the first inorganic insulating film 110 has one sidewall opening 114. The sidewall opening 114 is formed in a strip shape extending along the sidewall wiring 100 in a plan view. In this embodiment, the sidewall opening 114 is formed in a ring shape (specifically, a quadrangular ring) extending along the sidewall wiring 100 in a plan view. The sidewall opening 114 exposes the entire periphery of the portion of the sidewall wiring 100 that covers the outer surface 7. In this embodiment, the sidewall opening 114 also exposes the entire periphery of the outer contact region 80.

[0245] 22 to 28, the SiC semiconductor device 1 includes a first principal surface electrode 120 formed on a first inorganic insulating film 110. In this embodiment, the first principal surface electrode 120 is disposed only on the active surface 6, and is not disposed on the outer surface 7. The first principal surface electrode 120 includes a gate principal surface electrode 121. The gate principal surface electrode 121 may also be referred to as a gate pad electrode. The gate principal surface electrode 121 is electrically connected to the plurality of trench gate structures 31 (gate electrodes 34) and applies an externally input gate potential (gate signal) to the plurality of trench gate structures 31 (gate electrodes 34).

[0246] The gate principal surface electrode 121 is arranged on the peripheral edge of the active surface 6 at intervals from the first to fourth connection surfaces 8A to 8D in a plan view. In this embodiment, the gate principal surface electrode 121 is arranged in a region facing the center of the first connection surface 8A on the peripheral edge of the active surface 6. The gate principal surface electrode 121 is arranged at an interval inward of the active surface 6 from at least the outermost first dummy trench source structure 61 (sidewall wiring 100). The gate principal surface electrode 121 is formed in a quadrangle shape having four sides parallel to the active surface 6 in a plan view.

[0247] The gate principal surface electrode 121 faces a part of the first peripheral region 21 (a part of the first dummy structure 60A) with the first inorganic insulating film 110 interposed therebetween. The gate principal surface electrode 121 preferably faces at least one first dummy trench source structure 61 with the first inorganic insulating film 110 interposed therebetween. In this embodiment, the gate principal surface electrode 121 crosses the multiple first dummy trench source structures 61. The gate principal surface electrode 121 is electrically isolated from the multiple first dummy trench source structures 61 by the first inorganic insulating film 110.

[0248] The gate principal surface electrode 121 extends from the first dummy structure 60A side to the second dummy structure 60B side and faces a part of the second dummy structure 60B across the first inorganic insulating film 110. The gate principal surface electrode 121 faces either or both of the dummy trench gate structure 62 and the second dummy trench source structure 63 across the first inorganic insulating film 110. In this embodiment, the gate principal surface electrode 121 crosses all of the multiple dummy trench gate structures 62 and the multiple second dummy trench source structures 63. The gate principal surface electrode 121 is electrically isolated from the multiple dummy trench gate structures 62 and the multiple second dummy trench source structures 63 by the first inorganic insulating film 110.

[0249] The gate principal surface electrode 121 extends from the first peripheral region 21 side to the transistor region 20 side and faces a part of the transistor structure 30 across the first inorganic insulating film 110. The gate principal surface electrode 121 faces either one or both of the trench gate structure 31 and the first trench source structure 41. In this embodiment, the gate principal surface electrode 121 crosses the plurality of trench gate structures 31 and the plurality of first trench source structures 41. The gate principal surface electrode 121 is electrically isolated from the plurality of trench gate structures 31 and the plurality of first trench source structures 41 by the first inorganic insulating film 110. The gate principal surface electrode 121 is disposed at a distance from the plurality of second trench source structures 51 and is also electrically isolated from the plurality of second trench source structures 51.

[0250] The gate principal surface electrode 121 has a gate electrode sidewall 121a (electrode sidewall) located on the first inorganic insulating film 110. The gate electrode sidewall 121a is formed in a tapered shape that slopes obliquely downward from the principal surface of the gate principal surface electrode 121. The gate electrode sidewall 121a may be formed in a curved tapered shape that curves toward the first inorganic insulating film 110.

[0251] The first principal surface electrode 120 includes a source principal surface electrode 122. The source principal surface electrode 122 is disposed on the active surface 6 at a distance from the gate principal surface electrode 121. The source principal surface electrode 122 may also be referred to as a source pad electrode. The source principal surface electrode 122 is electrically connected to the plurality of first trench source structures 41 (source electrodes 44) and applies an externally input source potential to the plurality of first trench source structures 41 (source electrodes 44).

[0252] The source principal surface electrode 122 is formed on the active surface 6 at intervals from the first to fourth connection surfaces 8A to 8D in a plan view. In this embodiment, the source principal surface electrode 122 is formed in a quadrangular shape having four sides parallel to the active surface 6 (first to fourth connection surfaces 8A to 8D) in a plan view. Specifically, the source principal surface electrode 122 is formed in a polygonal shape having a recess recessed inward of the active surface 6 on a side along the first connection surface 8A in a plan view so as to match with the gate principal surface electrode 121.

[0253] The source principal surface electrode 122 has a planar area larger than that of the gate principal surface electrode 121. The source principal surface electrode 122 is arranged at a distance inward from at least the outermost first dummy trench source structure 61 (sidewall wiring 100) on the active surface 6. In this embodiment, the source principal surface electrode 122 is arranged at a distance inward from the first dummy structure 60A on the active surface 6 in plan view.

[0254] The source principal surface electrode 122 includes a body portion 123, a first lead portion 124, a second lead portion 125, and a third lead portion 126. The body portion 123 is disposed on the transistor region 20 and faces the gate principal surface electrode 121 in the second direction Y. In this embodiment, the body portion 123 faces all of the trench gate structures 31 and all of the first trench source structures 41. The body portion 123 extends from above the first inorganic insulating film 110 into the source openings 113 and is electrically connected to the source regions 24, the source electrodes 44, and the contact regions 70. As a result, a source potential applied to the source principal surface electrode 122 is applied to the source electrodes 44, the source regions 24, and the contact regions 70.

[0255] The first drawn-out portion 124 is drawn out from above the transistor region 20 onto one side (the third connection surface 8C side) of the first peripheral region 21, and faces the gate main surface electrode 121 in the first direction X. The second drawn-out portion 125 is drawn out from above the transistor region 20 onto the other side (the fourth connection surface 8D side) of the first peripheral region 21, and faces the first drawn-out portion 124 in the first direction X across the gate main surface electrode 121.

[0256] The first and second lead portions 124-125 each face a part of the second dummy structure 60B across the first inorganic insulating film 110. The first and second lead portions 124-125 each face either one or both of the dummy trench gate structure 62 and the second dummy trench source structure 63. In this embodiment, the first and second lead portions 124-125 each face both the dummy trench gate structure 62 and the second dummy trench source structure 63.

[0257] The first and second lead portions 124-125 may face the plurality of dummy trench gate structures 62 and the plurality of second dummy trench source structures 63, respectively. The first and second lead portions 124-125 are electrically isolated from the plurality of dummy trench gate structures 62 and the plurality of second dummy trench source structures 63 by the first inorganic insulating film 110.

[0258] In this embodiment, the first and second lead portions 124-125 are arranged at intervals from the first dummy structure 60A side to the second dummy structure 60B side. Therefore, the first and second lead portions 124-125 do not face the multiple first dummy trench source structures 61 across the first inorganic insulating film 110. The first and second lead portions 124-125 are electrically isolated from the multiple first dummy trench source structures 61 by the first inorganic insulating film 110.

[0259] Of course, the first and second drawn-out portions 124-125 may be drawn out from the second dummy structure 60B side to the first dummy structure 60A side, and may each face a part of the first dummy structure 60A across the first inorganic insulating film 110. In this case, the first and second drawn-out portions 124-125 may each face at least one first dummy trench source structure 61 across the first inorganic insulating film 110.

[0260] The third drawn-out portion 126 is drawn out from above the transistor region 20 to above the second peripheral region 22, and faces a part of the second dummy structure 60B across the first inorganic insulating film 110. The third drawn-out portion 126 faces either or both of the dummy trench gate structure 62 and the second dummy trench source structure 63.

[0261] In this embodiment, the third lead portion 126 faces both the dummy trench gate structure 62 and the second dummy trench source structure 63. The third lead portion 126 may face the plurality of dummy trench gate structures 62 and the plurality of second dummy trench source structures 63. The third lead portion 126 is electrically isolated from the plurality of dummy trench gate structures 62 and the plurality of second dummy trench source structures 63 by the first inorganic insulating film 110.

[0262] The third lead portions 126 are led from the second dummy structure 60B side to the first dummy structure 60A side, and face parts of the first dummy structures 60A across the first inorganic insulating film 110. The third lead portions 126 face the plurality of (in this embodiment, all of) first dummy trench source structures 61 across the first inorganic insulating film 110. The third lead portions 126 are electrically isolated from the plurality of first dummy trench source structures 61 by the first inorganic insulating film 110.

[0263] The source principal surface electrode 122 has a source electrode sidewall 122a (electrode sidewall) located on the first inorganic insulating film 110. The source electrode sidewall 122a is formed in a tapered shape that slopes obliquely downward from the principal surface of the source principal surface electrode 122. The source electrode sidewall 122a may be formed in a curved tapered shape that curves toward the first inorganic insulating film 110.

[0264] The SiC semiconductor device 1 includes a wiring electrode 130 formed on a first inorganic insulating film 110. The wiring electrode 130 is routed to any region on the first inorganic insulating film 110, including a region covering the active surface 6 and a region covering the outer surface 7.

[0265] The wiring electrode 130 includes a gate wiring electrode 131 (gate wiring). The gate wiring electrode 131 may also be referred to as a gate finger electrode. The gate wiring electrode 131 is drawn out from the gate principal surface electrode 121 onto a portion of the first inorganic insulating film 110 that covers the active surface 6. The gate wiring electrode 131 is formed on the active surface 6, but is not formed on the outer surface 7. The gate wiring electrode 131 transmits the gate potential applied to the gate principal surface electrode 121 to other regions.

[0266] The gate wiring electrode 131 is spaced apart from the first to fourth connection surfaces 8A to 8D and the source principal surface electrode 122 and is drawn out from the gate principal surface electrode 121 to a region between the first to fourth connection surfaces 8A to 8D and the source principal surface electrode 122. The gate wiring electrode 131 is formed in a strip shape extending along the first to fourth connection surfaces 8A to 8D. Specifically, it is preferable that the gate wiring electrode 131 extends in a strip shape along at least two of the first to fourth connection surfaces 8A to 8D so as to face the source principal surface electrode 122 from a plurality of directions in a plan view.

[0267] In this embodiment, the gate wiring electrode 131 faces the source principal surface electrode 122 from four directions in a plan view. The portions of the gate wiring electrode 131 that extend along the four corners of the active surface 6 are curved toward the outer surface 7. Therefore, in this embodiment, the gate wiring electrode 131 extends in a strip shape with curved corners as a whole in a plan view. The gate wiring electrode 131 has an opening on the second connection surface 8B side. The position and size of the opening are arbitrary.

[0268] The gate wiring electrode 131 is drawn out from the gate principal surface electrode 121 onto the first peripheral region 21 and extends along the first connecting surface 8A and the third connecting surface 8C. The gate wiring electrode 131 faces a part of the first dummy structure 60A and a part of the second dummy structure 60B on the first peripheral region 21 side, with the first inorganic insulating film 110 interposed therebetween.

[0269] Specifically, the gate wiring electrode 131 faces the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63, with the first inorganic insulating film 110 sandwiched therebetween. The gate wiring electrode 131 is electrically isolated from the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63 by the first inorganic insulating film 110.

[0270] The gate wiring electrode 131 is drawn out from the first peripheral region 21 side to the transistor region 20 side, and extends along the third connection surface 8C and the fourth connection surface 8D. The gate wiring electrode 131 faces a part of the transistor structure 30 on the transistor region 20 side, with the first inorganic insulating film 110 sandwiched therebetween. In the transistor region 20, the gate wiring electrode 131 intersects (specifically, is perpendicular to) the plurality of trench gate structures 31 and the plurality of first trench source structures 41 in plan view.

[0271] That is, the gate wiring electrode 131 extends in a direction (second direction Y) that intersects (specifically, is perpendicular to) the direction (first direction X) in which the plurality of trench gate structures 31 and the plurality of first trench source structures 41 extend. In other words, the gate wiring electrode 131 extends in a direction (second direction Y) that intersects (specifically, is perpendicular to) the opposing direction (first direction X) in which the plurality of trench gate structures 31 and the plurality of second trench source structures 51 face each other.

[0272] The gate wiring electrode 131 extends across the region between the trench gate structure 31 and the second trench source structure 51 in a plan view, and intersects (specifically, perpendicular to) the ends of the trench gate structures 31, the inner portions of the first trench source structures 41, and the ends of the second trench source structures 51. The gate wiring electrode 131 enters the gate openings 112 from above the first inorganic insulating film 110, and is electrically connected to the gate contact electrodes 91. As a result, the gate potential applied to the gate principal surface electrode 121 is imparted to the trench gate structures 31 via the gate wiring electrode 131.

[0273] The gate wiring electrode 131 is drawn out from the transistor region 20 onto the second peripheral region 22 and extends along the third connecting surface 8C and the second connecting surface 8B. The gate wiring electrode 131 faces a part of the first dummy structure 60A and a part of the second dummy structure 60B on the second peripheral region 22 side, with the first inorganic insulating film 110 interposed therebetween.

[0274] Specifically, the gate wiring electrode 131 faces the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63, with the first inorganic insulating film 110 sandwiched therebetween. The gate wiring electrode 131 is electrically isolated from the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63 by the first inorganic insulating film 110.

[0275] The gate wiring electrode 131 has a gate wiring sidewall 131a (wiring sidewall) located on the first inorganic insulating film 110. The gate wiring sidewall 131a is formed in a tapered shape that slopes obliquely downward from the main surface of the gate wiring electrode 131. The gate wiring sidewall 131a may be formed in a curved tapered shape that curves toward the first inorganic insulating film 110.

[0276] The wiring electrode 130 includes a source wiring electrode 132 (source wiring). The source wiring electrode 132 may also be referred to as a source finger electrode. The source wiring electrode 132 transmits the source potential applied to the source principal surface electrode 122 to other regions. The source wiring electrode 132 passes through the open portion of the gate wiring electrode 131 from the source principal surface electrode 122 and is drawn out onto a portion of the first inorganic insulating film 110 that covers the sidewall wiring 100. The source wiring electrode 132 is formed in a strip shape extending along the sidewall wiring 100 at a distance from the gate wiring electrode 131 in a plan view.

[0277] The source wiring electrode 132 is formed in a strip shape extending along the first to fourth connecting faces 8A to 8D. Specifically, the source wiring electrode 132 preferably extends in a strip shape along at least two of the first to fourth connecting faces 8A to 8D so as to face the source main surface electrode 122 from a plurality of directions in a plan view. In this embodiment, the source wiring electrode 132 is formed in a ring shape (specifically, a quadrangular ring) extending along the sidewall wiring 100 so as to face the source main surface electrode 122 from four directions in a plan view. In other words, the source wiring electrode 132 collectively surrounds the gate main surface electrode 121, the source main surface electrode 122, and the gate wiring electrode 131 in a plan view.

[0278] The portions of the source wiring electrode 132 that extend along the four corners of the active surface 6 are curved toward the outer surface 7. Therefore, in this embodiment, the source wiring electrode 132 is formed in a ring shape with the four corners curved as a whole in a plan view. In this embodiment, the source wiring electrode 132 covers the entire area of ​​the sidewall wiring 100 with the first inorganic insulating film 110 sandwiched therebetween.

[0279] The source wiring electrode 132 is further drawn out from above the sidewall wiring 100 onto a portion of the first inorganic insulating film 110 that covers the outer surface 7. Specifically, the source wiring electrode 132 is drawn out onto the outer contact region 80 and is formed in a strip shape extending along the outer contact region 80 in a plan view. In this embodiment, the source wiring electrode 132 is formed in a ring shape (specifically, a quadrangular ring) extending along the outer contact region 80 in a plan view. In other words, the source wiring electrode 132 covers the outer contact region 80 and the sidewall wiring 100 over the entire periphery.

[0280] The source wiring electrode 132 extends from above the first inorganic insulating film 110 into the sidewall opening 114 and is electrically connected to the sidewall wiring 100 and the outer contact region 80. In this embodiment, the source wiring electrode 132 is electrically connected to the sidewall wiring 100 and the outer contact region 80 over the entire periphery. As a result, the source potential applied to the source main surface electrode 122 is imparted to the sidewall wiring 100 and the outer contact region 80 via the source wiring electrode 132.

[0281] The source potential applied to the sidewall wiring 100 is applied to the plurality of first trench source structures 41, the plurality of second trench source structures 51, the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63. In other words, the source wiring electrode 132 electrically connects the plurality of first trench source structures 41 to the source principal surface electrode 122 at a position different from the source principal surface electrode 122 via the sidewall wiring 100.

[0282] Furthermore, the source wiring electrode 132 electrically connects the plurality of second trench source structures 51, the plurality of first dummy trench source structures 61, the plurality of dummy trench gate structures 62, and the plurality of second dummy trench source structures 63, which are electrically isolated from the source main surface electrode 122 on the active surface 6, to the source main surface electrode 122 from the first to fourth connection surfaces 8A to 8D via the sidewall wiring 100. In other words, the sidewall wiring 100 electrically connects any trench structure electrically isolated from the first main surface electrode 120 on the active surface 6 to the first main surface electrode 120 in a region outside the active surface 6 (the first to fourth connection surfaces 8A to 8D).

[0283] The source wiring electrode 132 has a source wiring sidewall 132a (wiring sidewall) located on the first inorganic insulating film 110. The source wiring sidewall 132a is formed in a tapered shape that slopes obliquely downward from the main surface of the source main surface electrode 122. The source wiring sidewall 132a may be formed in a curved tapered shape that curves toward the first inorganic insulating film 110.

[0284] The first principal surface electrode 120 and the wiring electrode 130 each have a laminated structure including a first electrode film 141 and a second electrode film 142 laminated in this order from the first inorganic insulating film 110 side. The first electrode film 141 is formed in a film shape along the first inorganic insulating film 110. The first electrode film 141 is made of a metal barrier film. In this embodiment, the first electrode film 141 is made of a Ti-based metal film.

[0285] The first electrode film 141 includes at least one of a titanium film and a titanium nitride film. The first electrode film 141 may have a single-layer structure made of a titanium film or a titanium nitride film. In this embodiment, the first electrode film 141 has a multilayer structure including a titanium film and a titanium nitride film stacked in this order from the first main surface 3 side. The thickness of the first electrode film 141 may be 10 nm or more and 500 nm or less.

[0286] The second electrode film 142 is formed in a film shape along the first electrode film 141. The first electrode film 141 is made of a Cu-based metal film or an Al-based metal film. The first electrode film 141 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the first electrode film 141 has a single-layer structure made of an AlCu alloy film. The thickness of the second electrode film 142 may be 0.5 μm or more and 10 μm or less. The thickness of the second electrode film 142 is preferably 2.5 μm or more and 7.5 μm or less.

[0287] The SiC semiconductor device 1 includes a second inorganic insulating film 150. The second inorganic insulating film 150 is made of an inorganic insulator having a relatively high density and has a barrier property (shielding property) against moisture (humidity). For example, the oxide (aluminum oxide in this embodiment) of the first principal surface electrode 120 deteriorates the electrical characteristics of the first principal surface electrode 120. Furthermore, the oxide of the first principal surface electrode 120 is one factor that causes partial peeling or cracking of the first principal surface electrode 120 or other structures due to thermal expansion.

[0288] The second inorganic insulating film 150 covers either or both of the first inorganic insulating film 110 and the first principal surface electrode 120 to block moisture (humidity) from the outside and protect the SiC chip 2 and the first principal surface electrode 120 from oxidation. The second inorganic insulating film 150 may also be called a passivation film.

[0289] The second inorganic insulating film 150 may have a layered structure including multiple insulating films, or may have a single-layer structure consisting of a single insulating film. The second inorganic insulating film 150 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second inorganic insulating film 150 may have a layered structure including multiple silicon oxide films, a layered structure including multiple silicon nitride films, or a layered structure including multiple silicon oxynitride films.

[0290] The second inorganic insulating film 150 may have a layered structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are layered in any order. The second inorganic insulating film 150 may have a single-layer structure made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this embodiment, the second inorganic insulating film 150 has a single-layer structure made of a silicon nitride film. In other words, the second inorganic insulating film 150 is made of an insulator different from that of the first inorganic insulating film 110.

[0291] The thickness of the second inorganic insulating film 150 is preferably less than the thickness of the first inorganic insulating film 110. The thickness of the second inorganic insulating film 150 may be equal to or greater than the thickness of the first inorganic insulating film 110. The thickness of the second inorganic insulating film 150 is preferably greater than the thickness of the first electrode film 141. The thickness of the second inorganic insulating film 150 is preferably equal to or less than the thickness of the second electrode film 142. It is particularly preferable that the thickness of the second inorganic insulating film 150 is less than the thickness of the second electrode film 142. The thickness of the second inorganic insulating film 150 may be equal to or greater than 0.05 μm and equal to or less than 5 μm. The thickness of the second inorganic insulating film 150 is preferably equal to or greater than 0.1 μm and equal to or less than 2 μm.

[0292] 23, in this embodiment, the second inorganic insulating film 150 includes a plurality of inner covering portions 151 (electrode covering portions), outer covering portions 152 (insulating covering portions), and removed portions 153. The plurality of inner covering portions 151 respectively cover the first principal surface electrodes 120 so as to expose the electrode sidewalls of the first principal surface electrodes 120. Specifically, the plurality of inner covering portions 151 include an inner gate covering portion 154 that covers the gate principal surface electrode 121, and an inner source covering portion 155 that covers the source principal surface electrode 122.

[0293] The second inorganic insulating film 150 is required to have at least one of the inner-gate coating portion 154 and the inner-source coating portion 155, and does not necessarily have to simultaneously include both the inner-gate coating portion 154 and the inner-source coating portion 155. The second inorganic insulating film 150 preferably has the inner-source coating portion 155 that covers at least the source principal surface electrode 122, which has an area larger than that of the gate principal surface electrode 121.

[0294] It is particularly preferable that the second inorganic insulating film 150 has both the gate inner coating portion 154 and the source inner coating portion 155. Furthermore, it is sufficient that the second inorganic insulating film 150 has at least one of a plurality of inner coating portions 151 and outer coating portions 152, and it is not necessary that the second inorganic insulating film 150 has both a plurality of inner coating portions 151 and outer coating portions 152. It is preferable that the second inorganic insulating film 150 has at least a plurality of inner coating portions 151. It is most preferable that the second inorganic insulating film 150 has both a plurality of inner coating portions 151 and outer coating portions 152.

[0295] The inner-gate coating portion 154 of the second inorganic insulating film 150 covers the gate principal surface electrode 121 so as to expose the gate electrode sidewall 121a on the active surface 6. Specifically, the inner-gate coating portion 154 covers the gate principal surface electrode 121 at a distance from the gate electrode sidewall 121a so as to expose the peripheral portion of the gate principal surface electrode 121. The inner-gate coating portion 154 also exposes the inner portion of the gate principal surface electrode 121.

[0296] The inner-gate coating portion 154 is formed in a strip shape extending along the gate electrode sidewall 121a in plan view. In this embodiment, the inner-gate coating portion 154 is formed in a ring shape surrounding the inner portion of the gate principal surface electrode 121 in plan view. Specifically, the inner-gate coating portion 154 is formed in a ring shape (specifically, a quadrangular ring) having four sides parallel to the gate electrode sidewall 121a in plan view.

[0297] The inner-gate covering portion 154 has a first inner wall portion 154a on the inner side of the gate principal surface electrode 121 and a first outer wall portion 154b on the gate electrode sidewall 121a side. In this embodiment, the first inner wall portion 154a is formed in a quadrangular shape having four sides parallel to the gate electrode sidewall 121a in a plan view. The first inner wall portion 154a is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 150 toward the inner portion of the gate principal surface electrode 121. The first inner wall portion 154a defines a first gate opening 156 that exposes the inner portion of the gate principal surface electrode 121.

[0298] The first outer wall portion 154b is formed on the gate principal surface electrode 121 at a distance from the gate electrode sidewall 121a so as to expose the peripheral edge portion of the gate principal surface electrode 121. In this embodiment, the first outer wall portion 154b is formed in a quadrangular shape having four sides parallel to the gate electrode sidewall 121a in a plan view. The first outer wall portion 154b is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 150 toward the gate electrode sidewall 121a of the gate principal surface electrode 121.

[0299] The source inner covering portion 155 of the second inorganic insulating film 150 covers the source principal surface electrode 122 so as to expose the source electrode sidewall 122a on the active surface 6. Specifically, the source inner covering portion 155 covers the source principal surface electrode 122 at a distance from the source electrode sidewall 122a so as to expose the peripheral portion of the source principal surface electrode 122. The source inner covering portion 155 also exposes the inner portion of the source principal surface electrode 122.

[0300] The inner-source coating portion 155 is formed in a band shape extending along the source electrode sidewall 122a in plan view. In this embodiment, the inner-source coating portion 155 is formed in a ring shape surrounding the inner portion of the source principal surface electrode 122 in plan view. The inner-source coating portion 155 has a portion that is recessed inward of the source principal surface electrode 122 so as to follow the portion of the source electrode sidewall 122a that forms the recess in plan view. As a result, the inner-source coating portion 155 is formed in a ring shape (specifically, a polygonal ring) having sides parallel to the source electrode sidewall 122a in plan view.

[0301] The source inner covering portion 155 has a second inner wall portion 155a on the inner side of the source principal surface electrode 122 and a second outer wall portion 155b on the source electrode sidewall 122a side of the source principal surface electrode 122. In this embodiment, the second inner wall portion 155a is formed in a polygonal shape having sides parallel to the source electrode sidewall 122a in a plan view. The second inner wall portion 155a is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 150 toward the inner portion of the source principal surface electrode 122. The second inner wall portion 155a defines a first source opening 157 that exposes the inner portion of the source principal surface electrode 122.

[0302] The second outer wall portion 155b is formed on the source principal surface electrode 122 at a distance from the source electrode sidewall 122a so as to expose the peripheral edge of the source principal surface electrode 122. In this embodiment, the second outer wall portion 155b is formed in a polygonal shape having sides parallel to the source electrode sidewall 122a in a plan view. The second outer wall portion 155b is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 150 toward the source electrode sidewall 122a of the source principal surface electrode 122.

[0303] The outer coating portion 152 of the second inorganic insulating film 150 coats the first inorganic insulating film 110 at a distance from the gate principal surface electrode 121 and the source principal surface electrode 122 toward the periphery of the first main surface 3 so as to expose the gate electrode sidewall 121a and the source electrode sidewall 122a. The outer coating portion 152 is formed at a distance from the gate wiring electrode 131 toward the periphery of the first main surface 3 so as to expose the gate wiring sidewall 131a. The outer coating portion 152 is formed at a distance from the source wiring electrode 132 toward the periphery of the first main surface 3 so as to expose the source wiring sidewall 132a. The outer coating portion 152 is formed at a distance from the sidewall wiring 100 toward the periphery of the first main surface 3.

[0304] The outer covering portion 152 is formed in a strip shape extending along the active surface 6 (first to fourth connecting surfaces 8A to 8D) in a plan view. The outer covering portion 152 is formed in a ring shape surrounding the active surface 6 in a plan view. Specifically, the outer covering portion 152 is formed in a quadrangular ring shape having four sides parallel to the active surface 6 in a plan view. The outer covering portion 152 surrounds the sidewall wiring 100, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132 in a plan view.

[0305] The outer covering portion 152 faces at least one of the field regions 82A-82E across the first inorganic insulating film 110. In this embodiment, the outer covering portion 152 is formed at a distance from the innermost first field region 82A towards the peripheral edge of the first main surface 3 in plan view, and faces the second to fifth field regions 82B-82E across the first inorganic insulating film 110. Of course, the outer covering portion 152 may face all of the first to fifth field regions 82A-82E across the first inorganic insulating film 110.

[0306] In this embodiment, the outer covering portion 152 extends from above the first inorganic insulating film 110 onto the peripheral portion of the outer side surface 7 exposed from the cutout opening 111. The first inorganic insulating film 110 (outer covering portion 152) defines a dicing street 158, where the peripheral portion of the outer side surface 7 is exposed, between the first inorganic insulating film 110 and the peripheral edge of the first main surface 3. The dicing street 158 ​​is defined in the shape of a quadrangular ring extending along the peripheral edge of the first main surface 3. The width of the dicing street 158 ​​may be 5 μm or more and 25 μm or less. The width of the dicing street 158 ​​is the width in a direction perpendicular to the direction in which the dicing street 158 ​​extends.

[0307] The outer covering portion 152 has a third inner wall portion 152a on the active surface 6 side and a third outer wall portion 152b on the peripheral edge side of the first main surface 3. The third inner wall portion 152a is formed on the first inorganic insulating film 110 at a distance from the sidewall opening 114 so as to expose the first inorganic insulating film 110 on the outer side surface 7. Specifically, the third inner wall portion 152a is formed on the first inorganic insulating film 110 at a distance from the source wiring sidewall 132a of the source wiring electrode 132 so as to expose the first inorganic insulating film 110.

[0308] In this embodiment, the third inner wall portion 152a is formed in a quadrangular shape having four sides parallel to the source wiring electrode 132 (source wiring sidewall 132a) in a plan view. The third inner wall portion 152a collectively surrounds the sidewall wiring 100, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132. The third inner wall portion 152a is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 150 toward the first inorganic insulating film 110.

[0309] The third outer wall portion 152b is formed in a region between the cutout opening 111 and the periphery of the outer surface 7 in a plan view, and exposes the periphery of the outer surface 7. The third outer wall portion 152b is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 150 toward the outer surface 7. The third outer wall portion 152b defines a dicing street 158 ​​between itself and the periphery of the outer surface 7.

[0310] The removed portions 153 of the second inorganic insulating film 150 are partitioned between the gate inner covering portion 154 (first outer wall portion 154b) and the outer covering portion 152 (third inner wall portion 152a), between the source inner covering portion 155 (second outer wall portion 155b) and the outer covering portion 152 (third inner wall portion 152a), and between the gate inner covering portion 154 (first outer wall portion 154b) and the source inner covering portion 155 (second outer wall portion 155b).

[0311] In this embodiment, the removal portion 153 is formed in a strip shape extending along the first to fourth connecting surfaces 8A to 8D, the first outer wall portion 154b, and the second outer wall portion 155b in a plan view. In this embodiment, the removal portion 153 integrally includes an annular portion extending along the first outer wall portion 154b in a plan view, and an annular portion extending along the second outer wall portion 155b (the first to fourth connecting surfaces 8A to 8D).

[0312] The removed portion 153 exposes the entire periphery of the step portion (i.e., the first to fourth connection surfaces 8A to 8D) between the active surface 6 and the outer surface 7, and also exposes the entire periphery of the gate electrode sidewall 121a, the source electrode sidewall 122a, the gate wiring sidewall 131a, and the source wiring sidewall 132a. In other words, the removed portion 153 exposes the entire area of ​​the gate wiring electrode 131, the entire area of ​​the source wiring electrode 132, and the entire area of ​​the sidewall wiring 100 interposed between the gate wiring electrode 131 and the source wiring electrode 132.

[0313] In the second inorganic insulating film 150, the inner gate coating portion 154 is formed on the flat gate principal surface electrode 121, the inner source coating portion 155 is formed on the flat source principal surface electrode 122, and the outer coating portion 152 is formed on the flat first inorganic insulating film 110. Therefore, in the second inorganic insulating film 150, steps caused by the sidewall wiring 100, the gate principal surface electrode 121, the source principal surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132 are removed by the removed portion 153.

[0314] The SiC semiconductor device 1 includes an organic insulating film 160 that selectively covers the first inorganic insulating film 110, the second inorganic insulating film 150, and the first principal surface electrode 120. The organic insulating film 160 has a lower hardness than the second inorganic insulating film 150. In other words, the organic insulating film 160 has a lower elastic modulus than the second inorganic insulating film 150, and functions as a buffer (protective film) against external forces. The organic insulating film 160 protects the SiC chip 2, the first principal surface electrode 120, the second inorganic insulating film 150, etc. from external forces.

[0315] The organic insulating film 160 preferably includes a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating film 160 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this embodiment, the organic insulating film 160 includes a polyimide film.

[0316] The thickness of the organic insulating film 160 may be 1 μm or more and 50 μm or less. The thickness of the organic insulating film 160 is preferably 5 μm or more and 20 μm or less. The thickness of the organic insulating film 160 is preferably greater than the thickness of the second inorganic insulating film 150. It is particularly preferable that the thickness of the organic insulating film 160 is greater than the thickness of the first principal surface electrode 120.

[0317] The organic insulating film 160 covers the gate electrode sidewall 121a of the gate principal surface electrode 121 on the active surface 6. Specifically, the organic insulating film 160 covers the gate electrode sidewall 121a around the entire periphery of the gate principal surface electrode 121. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 on the gate electrode sidewall 121a. The organic insulating film 160 covers the edge portion of the gate principal surface electrode 121.

[0318] That is, the organic insulating film 160 extends from the gate electrode sidewall 121a toward the inner-gate coating portion 154, and covers the peripheral portion of the gate principal surface electrode 121 exposed between the gate electrode sidewall 121a and the inner-gate coating portion 154. The organic insulating film 160 further extends from the peripheral portion of the gate principal surface electrode 121 toward the top of the inner-gate coating portion 154, and covers the inner-gate coating portion 154.

[0319] The organic insulating film 160 covers the inner-gate covering portion 154 so as to expose the inner portion of the gate principal surface electrode 121. Specifically, the organic insulating film 160 covers the inner-gate covering portion 154 so as to expose the first inner wall portion 154a of the inner-gate covering portion 154. More specifically, the organic insulating film 160 covers the inner-gate covering portion 154 with a gap from the first inner wall portion 154a toward the first outer wall portion 154b, exposing the inner portion of the gate principal surface electrode 121 and the edge portion of the inner-gate covering portion 154.

[0320] The organic insulating film 160 covers the source electrode sidewall 122a of the source principal surface electrode 122 on the active surface 6. Specifically, the organic insulating film 160 covers the source electrode sidewall 122a around the entire periphery of the source principal surface electrode 122. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 on the source electrode sidewall 122a. The organic insulating film 160 covers the edge portion of the source principal surface electrode 122.

[0321] That is, the organic insulating film 160 extends from the source electrode sidewall 122a toward the inner-source covering portion 155, and covers the peripheral portion of the source principal surface electrode 122 exposed between the source electrode sidewall 122a and the inner-source covering portion 155. The organic insulating film 160 further extends from the peripheral portion of the source principal surface electrode 122 toward the top of the inner-source covering portion 155, and covers the inner-source covering portion 155.

[0322] The organic insulating film 160 covers the inner-source covering portion 155 so as to expose the inner portion of the source principal surface electrode 122. Specifically, the organic insulating film 160 covers the inner-source covering portion 155 so as to expose the second inner wall portion 155a of the inner-source covering portion 155. More specifically, the organic insulating film 160 covers the inner-source covering portion 155 with a gap from the second inner wall portion 155a toward the second outer wall portion 155b, exposing the inner portion of the source principal surface electrode 122 and the edge portion of the inner-source covering portion 155.

[0323] The organic insulating film 160 covers the gate wiring sidewall 131a of the gate wiring electrode 131 on the active surface 6. Specifically, the organic insulating film 160 covers the gate wiring sidewall 131a around the entire periphery of the gate wiring electrode 131. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 on the gate wiring sidewall 131a. The organic insulating film 160 extends from the gate wiring sidewall 131a onto the gate wiring electrode 131 and covers the entire area of ​​the gate wiring electrode 131.

[0324] The organic insulating film 160 covers the sidewall wiring 100 in the region between the active surface 6 and the outer surface 7, sandwiching the source wiring electrode 132 and the first inorganic insulating film 110. The organic insulating film 160 covers the source wiring sidewall 132a around the entire periphery of the source wiring electrode 132. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 on the source wiring sidewall 132a. The organic insulating film 160 extends from the source wiring sidewall 132a onto the source wiring electrode 132, covering the entire area of ​​the source wiring electrode 132. In other words, the organic insulating film 160 covers the entire area of ​​the sidewall wiring 100, sandwiching the source wiring electrode 132 and the first inorganic insulating film 110.

[0325] The organic insulating film 160 extends from above the source wiring electrode 132 onto the outer covering portion 152 of the second inorganic insulating film 150, and covers the outer covering portion 152. The organic insulating film 160 covers the outer covering portion 152 so as to expose the peripheral portion of the outer surface 7. Specifically, the organic insulating film 160 covers the outer covering portion 152 so as to expose the third outer wall portion 152b of the outer covering portion 152. More specifically, the organic insulating film 160 covers the outer covering portion 152 with a gap from the third outer wall portion 152b toward the third inner wall portion 152a, and exposes the peripheral portion of the outer surface 7 and the peripheral portion of the outer covering portion 152 in a plan view.

[0326] The organic insulating film 160 has a fourth inner wall portion 160a on the gate principal surface electrode 121 side. The fourth inner wall portion 160a extends along the first inner wall portion 154a (first gate opening 156) of the gate inner covering portion 154. In this embodiment, the fourth inner wall portion 160a is formed in a quadrangle shape having four sides parallel to the first inner wall portion 154a in a plan view.

[0327] Specifically, the fourth inner wall 160a is formed on the inner-gate covering portion 154 at a distance from the first inner wall 154a toward the first outer wall 154b, and exposes the inner portion of the gate principal surface electrode 121 and the edge portion of the inner-gate covering portion 154. In other words, the second gate opening 161 exposes the inner portion of the gate principal surface electrode 121 and the edge portion of the inner-gate covering portion 154. The fourth inner wall 160a defines the second gate opening 161 that exposes the inner portion of the gate principal surface electrode 121.

[0328] The fourth inner wall portion 160a (second gate opening 161) communicates with the first inner wall portion 154a (first gate opening 156) and forms one gate pad opening 162 together with the first inner wall portion 154a (first gate opening 156). The fourth inner wall portion 160a (second gate opening 161) is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 160 toward the first inner wall portion 154a. In this embodiment, the fourth inner wall portion 160a is formed in a curved tapered shape that curves toward the inner-gate covering portion 154.

[0329] The organic insulating film 160 has a fifth inner wall 160b on the source principal surface electrode 122 side. The fifth inner wall 160b extends along the second inner wall 155a (first source opening 157) of the source inner covering portion 155. In this embodiment, the fifth inner wall 160b is formed in a polygonal shape having sides parallel to the second inner wall 155a of the source inner covering portion 155 in a plan view.

[0330] Specifically, the fifth inner wall 160b is formed on the inner source covering portion 155 at a distance from the second inner wall 155a of the inner source covering portion 155 toward the second outer wall 155b, and exposes the inner portion of the source principal surface electrode 122 and the edge of the inner source covering portion 155. In other words, the second source opening 163 exposes the inner portion of the source principal surface electrode 122 and the edge of the inner source covering portion 155. The fifth inner wall 160b defines the second source opening 163, which exposes the inner portion of the source principal surface electrode 122.

[0331] The fifth inner wall portion 160b (second source opening 163) communicates with the second inner wall portion 155a (first source opening 157) of the source inner covering portion 155, and together with the second inner wall portion 155a (first source opening 157) forms one source pad opening 164. The fifth inner wall portion 160b (second source opening 163) is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 160 toward the second inner wall portion 155a. In this embodiment, the fifth inner wall portion 160b is formed in a curved tapered shape that curves toward the source inner covering portion 155.

[0332] The organic insulating film 160 has a fourth outer wall portion 160c. The fourth outer wall portion 160c is formed at a distance from the peripheral edge of the outer surface 7 (first to fourth side surfaces 5A to 5D) toward the outer covering portion 152 so as to expose the peripheral edge of the outer surface 7. Specifically, the fourth outer wall portion 160c is formed on the third outer wall portion 152b of the outer covering portion 152 so as to expose the third outer wall portion 152b.

[0333] In this embodiment, the fourth outer wall portion 160c is formed in a quadrangular shape having four sides parallel to the active surface 6 in a plan view. The fourth outer wall portion 160c is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 160 toward the third outer wall portion 152b of the outer coating portion 152. In this embodiment, the fourth outer wall portion 160c is formed in a curved tapered shape that curves toward the outer coating portion 152. The fourth outer wall portion 160c, together with the third outer wall portion 152b, defines the dicing street 158.

[0334] In this way, the organic insulating film 160 covers the edge of the gate principal surface electrode 121, the edge of the source principal surface electrode 122, the entire area of ​​the gate wiring electrode 131, and the multiple inner covering portions 151 of the second inorganic insulating film 150 on the active surface 6. The organic insulating film 160 covers the portions of the first inorganic insulating film 110 that are exposed from the gate principal surface electrode 121, the gate wiring electrode 131, the source principal surface electrode 122, and the source wiring electrode 132 on the active surface 6.

[0335] The organic insulating film 160 covers the entire area of ​​the source wiring electrode 132 (sidewall wiring 100) between the active surface 6 and the outer surface 7. The organic insulating film 160 covers the outer coating portion 152 of the second inorganic insulating film 150. On the outer surface 7, the organic insulating film 160 covers the portion of the first inorganic insulating film 110 that is exposed from the source wiring electrode 132 and the second inorganic insulating film 150.

[0336] In addition, the organic insulating film 160 is formed across the multiple inner coating portions 151 and outer coating portions 152 of the second inorganic insulating film 150, and covers the entire area of ​​the source wiring electrode 132 (sidewall wiring 100), the entire area of ​​the gate wiring electrode 131, the edge of the gate main surface electrode 121, and the edge of the source main surface electrode 122 within the removed portion 153 between the multiple inner coating portions 151 and outer coating portions 152.

[0337] That is, in the removed portion 153, the organic insulating film 160 fills in the irregularities formed by the first inorganic insulating film 110, the source wiring electrode 132 (sidewall wiring 100), the second inorganic insulating film 150, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132. The step in the organic insulating film 160 located in the removed portion 153 is reduced by the sidewall wiring 100.

[0338] The SiC semiconductor device 1 includes a second principal surface electrode 170 covering the second principal surface 4. The second principal surface electrode 170 may also be referred to as a drain electrode. The second principal surface electrode 170 covers the entire second principal surface 4 and is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first principal surface 3. The second principal surface electrode 170 is electrically connected to the first semiconductor region 10 (second principal surface 4). Specifically, the second principal surface electrode 170 forms ohmic contact with the first semiconductor region 10 (second principal surface 4).

[0339] In this embodiment, the second principal surface electrode 170 includes at least one of a Ti film, a Ni film, a Pd film, an Au film, and an Ag film. The second principal surface electrode 170 is only required to include at least a Ti film, and the presence or absence of the Ni film, the Pd film, the Au film, and the Ag film, and the order in which they are stacked, are optional. As one example, the second principal surface electrode 170 may include a Ti film, a Ni film, a Pd film, and an Au film stacked in this order from the second principal surface 4 side. As another example, the second principal surface electrode 170 may have a stacked structure including a Ti film, a Ni film, and an Au film.

[0340] 29A to 29V are cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in FIG. 1. Referring to FIG. 29A, a SiC wafer 201 (wafer / semiconductor wafer) that serves as a base for the first semiconductor region 10 is prepared. Next, a semiconductor crystal (SiC in this embodiment) is grown from one surface of the SiC wafer 201 by epitaxial growth. As a result, a third semiconductor region 14 having a predetermined n-type impurity concentration and a second semiconductor region 11 having a predetermined n-type impurity concentration are formed in this order on the SiC wafer 201. In this embodiment, the third semiconductor region 14 and the second semiconductor region 11 are each made of a SiC epitaxial layer.

[0341] Hereinafter, a wafer structure including the first semiconductor region 10 (SiC wafer 201), the third semiconductor region 14 (SiC epitaxial layer), and the second semiconductor region 11 (SiC epitaxial layer) will be referred to as a SiC epi-wafer 202. The SiC epi-wafer 202 has a first wafer main surface 203 on one side and a second wafer main surface 204 on the other side. The first wafer main surface 203 and the second wafer main surface 204 correspond to the first main surface 3 and the second main surface 4 of the SiC chip 2, respectively.

[0342] Next, a plurality of device regions 205 and cutting lines 206 that partition the plurality of device regions 205 are set on the first wafer main surface 203. The plurality of device regions 205 are set, for example, in a matrix form with gaps in the first direction X and the second direction Y in a plan view. The cutting lines 206 are set in a lattice form according to the arrangement of the plurality of device regions 205 in a plan view. In FIG. 29A, a portion of one device region 205 is shown, and the cutting lines 206 are indicated by dashed lines (the same applies to FIGS. 29B to 29V below).

[0343] 29B, p-type body regions 23 and n-type source regions 24 (not shown) are formed in the surface layer portion of the first wafer main surface 203. In this step, the body region 23 is formed throughout the surface layer portion of the first wafer main surface 203. The body region 23 is formed by introducing p-type impurities into the first wafer main surface 203. In this step, the source region 24 is formed throughout the surface layer portion of the first wafer main surface 203. The source region 24 is formed by introducing n-type impurities into the first wafer main surface 203. The source region 24 is preferably formed after the step of forming the body region 23, but may be formed before the step of forming the body region 23.

[0344] Next, referring to FIG. 29C, a hard mask 207 is formed on the first wafer main surface 203. The hard mask 207 may contain silicon oxide. The hard mask 207 may be formed by a chemical vapor deposition (CVD) method or a thermal oxidation method. In this step, the hard mask 207 is formed by a thermal oxidation method.

[0345] Next, referring to FIG. 29D , a first resist mask 208 having a predetermined pattern is formed on the hard mask 207. The first resist mask 208 exposes regions where a plurality of gate trenches 209, a plurality of source trenches 210, and the outer surface 7 will be formed, and covers the remaining regions. The plurality of gate trenches 209 include gate trenches 32 of the plurality of trench gate structures 31 and gate trenches 32 of the plurality of dummy trench gate structures 62 (the same applies below). The plurality of source trenches 210 include source trenches 42 of the plurality of first trench source structures 41, source trenches 42 of the plurality of second trench source structures 51, source trenches 42 of the plurality of first dummy trench source structures 61, and source trenches 42 of the plurality of second dummy trench source structures 63 (the same applies below).

[0346] Next, unnecessary portions of the hard mask 207 are removed by etching (e.g., dry etching) via the first resist mask 208. As a result, an exposed pattern corresponding to the plurality of gate trenches 209, the plurality of source trenches 210, and the outer surface 7 is formed in the hard mask 207. The first resist mask 208 is then removed.

[0347] 29E, unnecessary portions of the SiC epi-wafer 202 are removed by etching (e.g., dry etching) using the hard mask 207. In this step, unnecessary portions of the second semiconductor region 11 are removed. As a result, a plurality of gate trenches 209, a plurality of source trenches 210, and an outer side surface 7 are formed on the first wafer main surface 203. In addition, an active plateau 9 is formed on the first wafer main surface 203. The active plateau 9 includes an active surface 6, an outer side surface 7, and first to fourth connecting surfaces 8A to 8D.

[0348] 29F, a second resist mask 211 having a predetermined pattern is formed on the hard mask 207. The second resist mask 211 covers each of the gate trenches 209 in a manner to fill the gate trenches 209, and exposes the source trenches 210 and the outer surface 7.

[0349] That is, the second resist mask 211 exposes all of the source trenches 42 of the plurality of first dummy trench source structures 61 (i.e., the entire area of ​​the first dummy structures 60A) and all of the plurality of second dummy trench source structures 63 (i.e., parts of the second dummy structures 60B). The first dummy structures 60A and the second dummy structures 60B (particularly the first dummy structures 60A) suppress tilting of the second resist mask 211 at the peripheral portion of the active surface 6 due to a step between the active surface 6 and the outer side surface 7, and protect the transistor structure 30 from shape defects due to the tilting of the second resist mask 211.

[0350] Next, referring to FIG. 29G, unnecessary portions of the SiC epi-wafer 202 are removed by etching via the second resist mask 211. The etching is preferably anisotropic dry etching (e.g., RIE (Reactive Ion Etching)). In this step, unnecessary portions of the second semiconductor region 11 are removed. As a result, the multiple source trenches 210 and the outer side surface 7 are further dug in the thickness direction (toward the second wafer main surface 204) of the SiC epi-wafer 202. The second resist mask 211 is then removed.

[0351] 29H, the hard mask 207 is removed by an etching method, which may be a wet etching method and / or a dry etching method.

[0352] Next, referring to FIG. 29I, a third resist mask 212 having a predetermined pattern is formed on the first wafer main surface 203. The third resist mask 212 exposes regions where multiple well regions 213 are to be formed and covers other regions. The multiple well regions 213 include multiple well regions 71, multiple gate well regions 72, multiple dummy well regions 74, multiple dummy gate well regions 75, and outer well region 81. Next, p-type impurities are introduced into the surface layer portion of the first wafer main surface 203 through the third resist mask 212. As a result, multiple well regions 213 are formed in the surface layer portion of the first wafer main surface 203. The third resist mask 212 is then removed.

[0353] Next, referring to FIG. 29J, a fourth resist mask 214 having a predetermined pattern is formed on the first wafer main surface 203. The fourth resist mask 214 exposes regions where a plurality of field regions 82A-82E are to be formed, and covers the remaining regions. Next, p-type impurities are introduced into the surface layer portion of the first wafer main surface 203 through the fourth resist mask 214. As a result, a plurality of field regions 82A-82E are formed in the surface layer portion of the first wafer main surface 203. The fourth resist mask 214 is then removed.

[0354] 29K, a fifth resist mask 215 having a predetermined pattern is formed on the first wafer main surface 203. The fifth resist mask 215 exposes regions where a plurality of contact regions 216 are to be formed and covers the other regions. The plurality of contact regions 216 includes a plurality of contact regions 70, a plurality of dummy contact regions 73, and an outer contact region 80.

[0355] Specifically, the fifth resist mask 215 covers the plurality of gate trenches 209 in a manner that fills the plurality of gate trenches 209. The fifth resist mask 215 also covers the plurality of first dummy trench source structures 61 in a manner that fills the source trenches 42 of the plurality of first dummy trench source structures 61. The fifth resist mask 215 also exposes the source trenches 42 of the plurality of first trench source structures 41, the source trenches 42 of the plurality of second trench source structures 51, the source trenches 42 of the plurality of second dummy trench source structures 63, and a portion of the outer surface 7.

[0356] The fifth resist mask 215 covers all of the multiple first dummy trench source structures 61 (the entire area of ​​the first dummy structures 60A). The first dummy structures 60A and the second dummy structures 60B (particularly the second dummy structures 60B) suppress the tilt of the fifth resist mask 215 caused by a step between the active surface 6 and the outer side surface 7 at the peripheral portion of the active surface 6, and protect the transistor structure 30 from poor introduction of p-type impurities caused by the tilt of the fifth resist mask 215.

[0357] Next, p-type impurities are introduced into the surface layer portion of the first wafer main surface 203 through the fifth resist mask 215. As a result, a plurality of contact regions 216 are formed in the surface layer portion of the first wafer main surface 203. The fifth resist mask 215 is then removed.

[0358] Next, referring to FIG. 29L, a base insulating film 217 is formed to cover the first wafer main surface 203. The base insulating film 217 serves as a base for the gate insulating film 33, the source insulating film 43, and the main surface insulating film 90. The base insulating film 217 may be formed by a chemical vapor deposition (CVD) method or a thermal oxidation treatment method. In this step, the base insulating film 217 is formed by a thermal oxidation treatment method. That is, the base insulating film 217 includes an oxide film made of an oxide of the SiC epitaxial wafer 202.

[0359] In this step, the portions of the base insulating film 217 that cover the sidewalls of the gate trench 209 and the sidewalls of the source trench 210 are formed thinner than the other portions. Also, in this step, the portions of the base insulating film 217 that cover the opening edge portions of the gate trench 209 and the opening edge portions of the source trench 210 are formed thicker than the other portions.

[0360] Next, referring to FIG. 29M, a first base electrode film 218 is formed on the first wafer main surface 203. The first base electrode film 218 serves as a base for the plurality of gate electrodes 34, the plurality of source electrodes 44, the plurality of gate contact electrodes 91, and the sidewall wiring 100. The first base electrode film 218 fills the plurality of gate trenches 209 and the plurality of source trenches 210 and covers the first wafer main surface 203 (the active surface 6, the outer side surface 7, and the first to fourth connection surfaces 8A to 8D). In this step, the first base electrode film 218 includes a polysilicon film. The first base electrode film 218 may be formed by a CVD method. The CVD method is preferably an LP-CVD (Low Pressure-CVD) method.

[0361] Next, referring to FIG. 29N, a sixth resist mask 219 having a predetermined pattern is formed on the first base electrode film 218. The sixth resist mask 219 covers regions where a plurality of gate contact electrodes 91 and sidewall wirings 100 are to be formed, and leaves other regions exposed. Next, unnecessary portions of the first base electrode film 218 are removed by etching via the sixth resist mask 219. The etching method may be wet etching and / or dry etching. The unnecessary portions of the first base electrode film 218 are removed until the base insulating film 217 is exposed.

[0362] This forms a plurality of gate electrodes 34, a plurality of source electrodes 44, a plurality of gate contact electrodes 91, and sidewall wirings 100. Also formed are a plurality of trench gate structures 31, a plurality of first trench source structures 41, a plurality of second trench source structures 51, a plurality of first dummy trench source structures 61, a plurality of dummy trench gate structures 62, and a plurality of second dummy trench source structures 63. The sixth resist mask 219 is then removed.

[0363] 29O, a first inorganic insulating film 110 is formed on the first wafer main surface 203. The first inorganic insulating film 110 collectively covers the trench gate structures 31, the first trench source structures 41, the second trench source structures 51, the first dummy trench source structures 61, the dummy trench gate structures 62, the second dummy trench source structures 63, and the sidewall wirings 100 on the first wafer main surface 203. In this embodiment, the first inorganic insulating film 110 is made of a silicon oxide film. The first inorganic insulating film 110 may be formed by a CVD method.

[0364] 29P, a seventh resist mask 220 having a predetermined pattern is formed on the first inorganic insulating film 110. The seventh resist mask 220 exposes regions where the notch opening 111, the plurality of gate openings 112, the plurality of source openings 113, and the sidewall openings 114 are to be formed, and covers the other regions.

[0365] Next, unnecessary portions of the first inorganic insulating film 110 and unnecessary portions of the base insulating film 217 are removed by etching via the sixth resist mask 219. The etching may be wet etching and / or dry etching. As a result, the notch opening 111, multiple gate openings 112, multiple source openings 113, and sidewall openings 114 are formed in the first inorganic insulating film 110.

[0366] 29Q, a second base electrode film 221, which serves as a base for the first principal surface electrode 120, is formed on the first wafer principal surface 203. The second base electrode film 221 covers the entire first inorganic insulating film 110 on the first wafer principal surface 203. The second base electrode film 221 has a layered structure including a first electrode film 141 and a second electrode film 142, which are layered in this order from the first wafer principal surface 203 side.

[0367] In this embodiment, the first electrode film 141 is made of a Ti-based metal film. In this embodiment, the second electrode film 142 is made of an Al-based metal film. The first electrode film 141 and the second electrode film 142 may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method. In this embodiment, the first electrode film 141 and the second electrode film 142 are each formed by a sputtering method.

[0368] 29R, an eighth resist mask 222 having a predetermined pattern is formed on the second base electrode film 221. The eighth resist mask 222 covers regions of the second base electrode film 221 where the first main surface electrode 120 (the gate main surface electrode 121 and the source main surface electrode 122) and the wiring electrode 130 (the gate wiring electrode 131 and the source wiring electrode 132) are to be formed, and has openings that expose other regions.

[0369] Next, unnecessary portions of the second base electrode film 221 are removed by etching via the eighth resist mask 222. The etching may be wet etching and / or dry etching. This forms the first principal surface electrode 120 and the wiring electrode 130. The eighth resist mask 222 is then removed.

[0370] 29S, a second inorganic insulating film 150 is formed on the first wafer main surface 203 so as to cover the first inorganic insulating film 110 and the first main surface electrode 120. In this embodiment, the second inorganic insulating film 150 is made of a silicon nitride film. The second inorganic insulating film 150 may be formed by a CVD method.

[0371] 29T, a ninth resist mask 223 having a predetermined pattern is formed on the second inorganic insulating film 150. The ninth resist mask 223 covers portions of the second inorganic insulating film 150 that will become the multiple inner coating portions 151 and outer coating portions 152, and exposes portions of the second inorganic insulating film 150 that will become the removed portions 153 and dicing streets 158.

[0372] Next, unnecessary portions of the second inorganic insulating film 150 are removed by etching via the ninth resist mask 223. The etching may be wet etching and / or dry etching. This forms the second inorganic insulating film 150 having a plurality of inner coating portions 151, outer coating portions 152, and removed portions 153. The outer coating portions 152 of the second inorganic insulating film 150 define dicing streets 158 that expose the cutting lines 206 on the first wafer main surface 203. The ninth resist mask 223 is then removed.

[0373] 29U, an organic insulating film 160 is formed on the first wafer main surface 203 so as to cover the first main surface electrode 120, the first inorganic insulating film 110, and the second inorganic insulating film 150. The organic insulating film 160 is formed by applying a photosensitive resin onto the first wafer main surface 203. In this embodiment, the organic insulating film 160 is made of a polyimide film.

[0374] 29V, organic insulating film 160 is exposed to light in a pattern corresponding to second gate opening 161, second source opening 163, and dicing street 158, and then developed. As a result, second gate opening 161, second source opening 163, and dicing street 158 ​​are formed in organic insulating film 160.

[0375] Next, the SiC epi-wafer 202 is thinned to a desired thickness by grinding the second wafer main surface 204. The grinding process may be performed by a chemical mechanical polishing (CMP) method. As a result, grinding marks are formed on the second wafer main surface 204. The grinding process of the second wafer main surface 204 does not necessarily have to be performed, and may be omitted as necessary.

[0376] However, thinning the first semiconductor region 10 is effective in reducing the resistance value of the SiC chip 2. After the grinding process of the second wafer main surface 204, an annealing process may be performed on the second wafer main surface 204. The annealing process may be performed by a laser irradiation method. As a result, the second wafer main surface 204 (second main surface 4) becomes an ohmic surface having grinding marks and laser irradiation marks.

[0377] Next, the second principal surface electrode 170 is formed on the second wafer principal surface 204. The second principal surface electrode 170 forms ohmic contact with the second wafer principal surface 204. The second principal surface electrode 170 may include at least one of a Ti film, a Ni film, a Pd film, an Au film, and an Ag film. The Ti film, the Ni film, the Pd film, the Au film, and the Ag film may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method (in this embodiment, the sputtering method).

[0378] Next, the SiC epi-wafer 202 is cut along the cutting lines 206. The cutting process of the SiC epi-wafer 202 may include a cutting process using a dicing blade. In this case, the SiC epi-wafer 202 is cut along the cutting lines 206 defined by the dicing streets 158. The dicing blade preferably has a blade width less than the width of the dicing streets 158. The first inorganic insulating film 110, the second inorganic insulating film 150, and the organic insulating film 160 are not located on the cutting lines 206 and are therefore not cut by the dicing blade.

[0379] The cutting step of the SiC epi-wafer 202 may include a cleaving step using a laser beam irradiation method. In this case, a laser beam is irradiated from a laser beam irradiation device (not shown) onto the interior of the SiC epi-wafer 202 via the dicing streets 158. The laser beam is preferably irradiated in pulses onto the interior of the SiC epi-wafer 202 from the first wafer main surface 203 side, which does not have the second main surface electrode 170. The focusing point (focus) of the laser beam is set inside the SiC epi-wafer 202 (midway in the thickness direction), and the irradiation position of the laser beam is moved along the dicing streets 158 (specifically, the lines to cut 206).

[0380] As a result, a modified layer extending in a grid pattern along the dicing streets 158 in plan view is formed inside the SiC epi-wafer 202. The modified layer is preferably formed inside the SiC epi-wafer 202 at a distance from the first wafer main surface 203. The modified layer is preferably formed in a portion of the SiC epi-wafer 202 consisting of the first semiconductor region 10 (SiC wafer 201). It is particularly preferable that the modified layer be formed in the first semiconductor region 10 (SiC wafer 201) at a distance from the second semiconductor region 11 (SiC epitaxial layer). It is most preferable that the modified layer is not formed in the second semiconductor region 11 (SiC epitaxial layer).

[0381] After the modified layer formation step, an external force is applied to the SiC epi-wafer 202, and the SiC epi-wafer 202 is cleaved starting from the modified layer. The external force is preferably applied to the SiC epi-wafer 202 from the second wafer main surface 204 side. The second main surface electrode 170 is cleaved simultaneously with the cleavage of the SiC epi-wafer 202. The first inorganic insulating film 110, the second inorganic insulating film 150, and the organic insulating film 160 are not located on the cutting line 206, and are therefore spared from cleavage. The SiC semiconductor device 1 is manufactured through the steps including those described above.

[0382] Fig. 30 is a plan view showing a SiC semiconductor device 301 according to a first reference preferred embodiment, corresponding to Fig. 5. Referring to Fig. 30, the SiC semiconductor device 301 according to the first reference embodiment has a transistor structure 30 over the entire active surface 6, and does not have a first dummy structure 60A or a second dummy structure 60B.

[0383] That is, in the SiC semiconductor device 301, a transistor structure 30 having a plurality of trench gate structures 31, a plurality of first trench source structures 41, and a plurality of second trench source structures 51 is also formed in the peripheral portion (first peripheral region 21 and second peripheral region 22) of the active surface 6. The other structures of the SiC semiconductor device 301 according to the first reference embodiment are substantially similar to the structure of the SiC semiconductor device 1. A description of the other structures of the SiC semiconductor device 301 will be omitted.

[0384] 31A to 31D are cross-sectional views showing an example of a manufacturing method for a SiC semiconductor device 301 according to the first reference embodiment. In Fig. 31A to 31D, a cross section of a peripheral portion (first peripheral region 21) of an active surface 6 is shown.

[0385] 31A , in the method for manufacturing SiC semiconductor device 301, in the step of digging down source trenches 210 and outer surface 7, second resist mask 211 having a predetermined pattern is formed on hard mask 207 (see also FIG. 29F ). Second resist mask 211 covers each of gate trenches 209 in a manner that fills gate trenches 209, and exposes source trenches 210 and outer surface 7. In this step, the portion of second resist mask 211 that fills gate trenches 209 formed in the periphery of active surface 6 may be inclined due to a step between active surface 6 and outer surface 7.

[0386] Next, referring to FIG. 31B, unnecessary portions of the SiC epitaxial wafer 202 are removed by etching using the second resist mask 211 (see also FIG. 29G). The etching is preferably an anisotropic dry etching method (e.g., RIE). In this step, unnecessary portions of the second semiconductor region 11 are removed. As a result, the source trenches 210 and the outer side surface 7 are further dug in the thickness direction of the SiC epitaxial wafer 202 (toward the second wafer main surface 204).

[0387] 31C, second resist mask 211 is removed. At this time, removal of second resist mask 211 is insufficient at the peripheral edge of active surface 6 due to the inclination of second resist mask 211. As a result, part of second resist mask 211 remains in gate trench 209 as residue.

[0388] Next, referring to FIG. 31D, hard mask 207 is removed by etching. The etching may be wet etching and / or dry etching. At the peripheral portion of active surface 6, the inner wall of gate trench 209 is partially removed through the residue of second resist mask 211. Therefore, the portion of the inner wall of gate trench 209 exposed from the residue of second resist mask 211 is further dug down relative to the portion covered by the residue. Thereafter, SiC semiconductor device 301 is formed through steps similar to those of manufacturing SiC semiconductor device 1.

[0389] In the SiC semiconductor device 301 according to the first reference embodiment, a gate trench 32 having an inner wall with a defective shape is formed at the peripheral portion of the active surface 6. The defective gate trench 32 deteriorates the electrical characteristics of the SiC semiconductor device 301. For example, the defective gate trench 32 can be a factor in a decrease in the breakdown voltage (breakdown voltage) of the SiC semiconductor device 1 and a fluctuation in the gate threshold voltage.

[0390] Therefore, in the first embodiment, a SiC semiconductor device 1 having a SiC chip 2, a transistor structure 30, and a first dummy structure 60A (dummy structure 60) is adopted. The SiC chip 2 includes a first main surface 3. The first main surface 3 includes an active surface 6 (first surface), an outer surface 7 (second surface), and first to fourth connection surfaces 8A to 8D. The outer surface 7 is recessed at a first depth D1 in the thickness direction outside the active surface 6. The first to fourth connection surfaces 8A to 8D connect the active surface 6 and the outer surface 7. The active surface 6, the outer surface 7, and the first to fourth connection surfaces 8A to 8D define an active mesa 9 (mesa) on the first main surface 3.

[0391] The transistor structure 30 is formed in an inner portion of the active surface 6. The transistor structure 30 includes a trench gate structure 31 and a first trench source structure 41. The trench gate structure 31 has a second depth D2 (D2 < D1) less than the first depth D1. The first trench source structure 41 has a third depth D3 (D2 < D3) exceeding the second depth D2 and is adjacent to the trench gate structure 31 in one direction (second direction Y). The first dummy structure 60A is formed at a peripheral portion of the active surface 6. The first dummy structure 60A has the third depth D3 (D2 < D3) respectively and has a plurality of first dummy trench source structures 61 adjacent to each other in one direction (second direction Y).

[0392] According to this structure, the transistor structure 30 is formed in the inner portion of the active surface 6, and the first dummy structure 60A that does not function as the transistor structure 30 is formed at the peripheral portion of the active surface 6. Therefore, variations in the electrical characteristics of the transistor structure 30 due to shape defects at the peripheral portion of the active surface 6 can be suppressed. Thus, a SiC semiconductor device 1 with improved reliability can be provided.

[0393] The plurality of first dummy trench source structures 61 are specifically arranged continuously at intervals so as to be adjacent to each other. Also, the plurality of first dummy trench source structures 61 are arranged at intervals from each other without sandwiching a trench structure having a depth less than the third depth D3. A gate potential is applied to the trench gate structure 31. A source potential is applied to the first trench source structure 41. It is preferable that a source potential is applied to the first dummy trench source structure 61.

[0394] It is preferable that the plurality of first trench source structures 41 are exposed from either or both of the third connection surface 8C and the fourth connection surface 8D. It is preferable that the plurality of first dummy trench source structures 61 are exposed from either or both of the third connection surface 8C and the fourth connection surface 8D.

[0395] The trench gate structure 31 is preferably formed at a distance inward from the third connection surface 8C and the fourth connection surface 8D with respect to the active surface 6. In this case, the transistor structure 30 has a third depth D3 (D2 < D3), and preferably includes at least one second trench source structure 51 that faces the trench gate structure 31 in a direction (first direction X) orthogonal to the facing direction (second direction Y) of the trench gate structure 31 and the first trench source structure 41.

[0396] It is preferable that at least one second trench source structure 51 is formed in a region between the periphery of the active surface 6 and the trench gate structure 31. The second trench source structure 51 may be formed in a region between the third connection surface 8C and the trench gate structure 31, or may be formed in a region between the fourth connection surface 8D and the trench gate structure 31. It is preferable that the second trench source structure 51 is exposed from the third connection surface 8C or the fourth connection surface 8D.

[0397] The SiC semiconductor device 1 preferably includes a second dummy structure 60B formed in a region between the transistor structure 30 and the first dummy structure 60A at the peripheral portion of the active surface 6. The second dummy structure 60B includes a dummy trench gate structure 62 having a second depth D2 (D2 < D3), and a second dummy trench source structure 63 having a third depth D3 (D2 < D3) and adjacent to the dummy trench gate structure 62 in one direction (second direction Y).

[0398] According to this structure, a second dummy structure 60B having a similar form to the transistor structure 30 but not functioning as the transistor structure 30 is formed in a region between the transistor structure 30 and the first dummy structure 60A at the peripheral portion of the active surface 6. That is, a gradation structure in which the first dummy structure 60A, the second dummy structure 60B, and the transistor structure 30 are arranged in this order from the periphery of the active surface 6 inward is adopted for the active surface 6.

[0399] According to this structure, variations in the electrical characteristics of the transistor structure 30 due to shape defects at the peripheral portion of the active surface 6 can be appropriately suppressed. Therefore, the SiC semiconductor device 1 with improved reliability can be provided. It is preferable that a source potential is applied to the dummy trench gate structure 62. Also, it is preferable that a source potential is applied to the second dummy trench source structure 63.

[0400] The SiC semiconductor device 1 preferably includes a sidewall wiring 100 (sidewall structure) formed on the outer surface 7 so as to cover at least one of the first to fourth connection surfaces 8A to 8D. According to this structure, the step between the active surface 6 and the outer surface 7 can be alleviated.

[0401] The SiC semiconductor device 1 preferably includes a first inorganic insulating film 110 that covers the transistor structure 30 and the first dummy structure 60A on the active surface 6. The SiC semiconductor device 1 preferably includes a gate principal surface electrode 121 formed on the first inorganic insulating film 110. The SiC semiconductor device 1 preferably includes a gate wiring electrode 131 that is extended from the gate principal surface electrode 121 onto the first inorganic insulating film 110. The gate wiring electrode 131 preferably penetrates the first inorganic insulating film 110 and is electrically connected to the trench gate structure 31, and faces the first trench source structure 41 across the first inorganic insulating film 110.

[0402] The SiC semiconductor device 1 preferably includes a source principal surface electrode 122 formed on the first inorganic insulating film 110 and spaced apart from the gate principal surface electrode 121 and the gate wiring electrode 131. The source principal surface electrode 122 preferably penetrates the first inorganic insulating film 110 and is electrically connected to the first trench source structure 41, and faces the trench gate structure 31 across the first inorganic insulating film 110. The source principal surface electrode 122 is preferably formed on the first inorganic insulating film 110 and spaced apart from the first dummy structure 60A in a plan view.

[0403] The SiC semiconductor device 1 preferably includes a source wiring electrode 132 that is drawn from the source principal surface electrode 122 onto the first inorganic insulating film 110. The source wiring electrode 132 preferably penetrates the first inorganic insulating film 110 at a position different from the source principal surface electrode 122 and is electrically connected to the first trench source structure 41. The source wiring electrode 132 preferably penetrates the first inorganic insulating film 110 and is electrically connected to the first dummy trench source structure 61.

[0404] To solve the problems shown in FIGS. 31A to 31D, a SiC semiconductor device 1 including a SiC chip 2, a transistor structure 30, and a second dummy structure 60B (dummy structure 60) may be adopted. The SiC chip 2 includes a first main surface 3. The first main surface 3 includes an active surface 6 (first surface), an outer surface 7 (second surface), and first to fourth connection surfaces 8A to 8D. The outer surface 7 is recessed at a first depth D1 in the thickness direction outside the active surface 6. The first to fourth connection surfaces 8A to 8D connect the active surface 6 and the outer surface 7. The active surface 6, the outer surface 7, and the first to fourth connection surfaces 8A to 8D define an active mesa 9 (mesa) on the first main surface 3.

[0405] The transistor structure 30 is formed in an inner part of the active surface 6. The transistor structure 30 includes a trench gate structure 31 and a first trench source structure 41. The trench gate structure 31 has a second depth D2 (D2 < D1) less than the first depth D1. The first trench source structure 41 has a third depth D3 (D2 < D3) exceeding the second depth D2 and is adjacent to the trench gate structure 31 in one direction (second direction Y). The first dummy structure 60A is formed at a peripheral portion of the active surface 6. The second dummy structure 60B includes a dummy trench gate structure 62 having the second depth D2 (D2 < D1), and a second dummy trench source structure 63 having the third depth D3 (D2 < D3) and adjacent to the dummy trench gate structure 62 in one direction (second direction Y).

[0406] According to this structure, the transistor structure 30 is formed in the inner part of the active surface 6, and the second dummy structure 60B that does not function as the transistor structure 30 is formed at the peripheral portion of the active surface 6. Therefore, fluctuations in the electrical characteristics of the transistor structure 30 due to a shape defect at the peripheral portion of the active surface 6 can be suppressed. Thus, a SiC semiconductor device 1 with improved reliability can be provided.

[0407] According to the first embodiment, it is also possible to provide a SiC semiconductor device 1 having a wiring structure with flexibility in design rules in a structure having a trench structure formed in the active plateau 9. That is, the SiC semiconductor device 1 includes a SiC chip 2, a first trench source structure 41 (trench structure), and a sidewall wiring 100.

[0408] The SiC chip 2 includes a first main surface 3. The first main surface 3 includes an active surface 6 (first surface), an outer surface 7 (second surface), and first to fourth connecting surfaces 8A to 8D. The outer surface 7 is recessed in the thickness direction outside the active surface 6 to a first depth D1. The first to fourth connecting surfaces 8A to 8D connect the active surface 6 and the outer surface 7. The active surface 6, the outer surface 7, and the first to fourth connecting surfaces 8A to 8D define an active plateau 9 (plateau) on the first main surface 3.

[0409] The first trench source structure 41 is formed on the active surface 6 so as to be exposed from at least one of the first to fourth connection surfaces 8A to 8D. The sidewall wiring 100 covers at least one of the first to fourth connection surfaces 8A to 8D on the outer surface 7 so as to be electrically connected to the first trench source structure 41. This structure allows the first trench source structure 41 and the sidewall wiring 100 to be electrically connected to each other on the first to fourth connection surfaces 8A to 8D sides. Therefore, the sidewall wiring 100 can provide a SiC semiconductor device 1 having a novel wiring structure that provides flexibility in design rules.

[0410] In this structure, it is preferable that a plurality of first trench source structures 41 are formed at intervals on the active surface 6. In this case, it is preferable that the sidewall wiring 100 is electrically connected to the plurality of first trench source structures 41 at at least one of the first to fourth connection surfaces 8A to 8D.

[0411] The first trench source structure 41 preferably includes a source trench 42 formed in the active surface 6, a source insulating film 43 covering the inner wall of the source trench 42, and a source electrode 44 embedded in the source trench 42 with the source insulating film 43 sandwiched therebetween. In this case, the sidewall wiring 100 is preferably electrically connected to the source electrode 44.

[0412] The SiC semiconductor device 1 preferably includes a main surface insulating film 90 that covers the outer side surface 7 and the first to fourth connecting surfaces 8A to 8D and is continuous with the source insulating film 43. In this case, the sidewall wiring 100 is preferably formed on the main surface insulating film 90.

[0413] The SiC semiconductor device 1 preferably includes pn junctions (well regions 71 and / or outer well regions 81) formed in regions along the first to fourth connection surfaces 8A to 8D inside the SiC chip 2. In this case, the sidewall wirings 100 preferably face the pn junctions across the main surface insulating film 90 on the first to fourth connection surfaces 8A to 8D.

[0414] The sidewall wiring 100 is preferably formed integrally with the source electrode 44. The bottom wall of the source trench 42 preferably communicates with the outer side surface 7. The sidewall wiring 100 preferably includes an overlapping portion 101 that covers the peripheral edge of the active surface 6. The first trench source structure 41 preferably extends in one direction (first direction X) in plan view. In this case, the sidewall wiring 100 preferably extends in an intersecting direction (second direction Y) that intersects the one direction (first direction X) in plan view.

[0415] The SiC semiconductor device 1 preferably includes a first inorganic insulating film 110 that covers the sidewall wiring 100. According to this structure, the sidewall wiring 100 can be protected by the first inorganic insulating film 110. In this structure, the first inorganic insulating film 110 preferably covers the active surface 6 and the outer surface 7 across the sidewall wiring 100.

[0416] From another perspective, the SiC semiconductor device 1 includes a SiC chip 2, a trench gate structure 31, a first trench source structure 41, and sidewall wiring 100. The SiC chip 2 includes a first main surface 3. The first main surface 3 includes an active surface 6 (first surface), an outer surface 7 (second surface), and first to fourth connection surfaces 8A to 8D. The outer surface 7 is recessed in the thickness direction outside the active surface 6 to a first depth D1. The first to fourth connection surfaces 8A to 8D connect the active surface 6 and the outer surface 7. The active surface 6, the outer surface 7, and the first to fourth connection surfaces 8A to 8D define an active plateau 9 (plateau) on the first main surface 3.

[0417] The trench gate structure 31 is formed on the active surface 6 at a distance from the first to fourth connection surfaces 8A to 8D. The first trench source structure 41 is formed on the active surface 6 so as to be exposed from at least one of the first to fourth connection surfaces 8A to 8D. The sidewall wiring 100 covers at least one of the first to fourth connection surfaces 8A to 8D so as to be electrically connected to the first trench source structure 41, and is formed on the outer surface 7.

[0418] This structure allows electrical connection between the first trench source structure 41 and the sidewall wiring 100 on the first to fourth connection surfaces 8A to 8D sides. Therefore, the sidewall wiring 100 can provide an SiC semiconductor device 1 having a novel wiring structure that provides flexibility in design rules.

[0419] The first trench source structure 41 is preferably formed deeper than the trench gate structure 31. A plurality of trench gate structures 31 are preferably formed on the active surface 6. In this case, the plurality of first trench source structures 41 are preferably formed alternately with the plurality of trench gate structures 31 on the active surface 6. In this case, it is also preferable that the sidewall wiring 100 is electrically connected to the plurality of first trench source structures 41 and electrically isolated from the plurality of trench gate structures 31.

[0420] The SiC semiconductor device 1 preferably includes a second trench source structure 51 formed in a region of the active surface 6 between the first to fourth connection surfaces 8A to 8D and the trench gate structure 31. In this structure, the second trench source structure 51 is preferably exposed from at least one of the first to fourth connection surfaces 8A to 8D. In this structure, the sidewall wiring 100 is preferably electrically connected to the first trench source structure 41 and the second trench source structure 51.

[0421] The SiC semiconductor device 1 preferably includes a first inorganic insulating film 110 that covers the trench gate structure 31, the first trench source structure 41, and the sidewall wiring 100 on the first main surface 3. According to this structure, the trench gate structure 31, the first trench source structure 41, and the sidewall wiring 100 can be protected by the first inorganic insulating film 110.

[0422] The SiC semiconductor device 1 preferably includes a gate principal surface electrode 121 formed on the first inorganic insulating film 110. The SiC semiconductor device 1 preferably includes a gate wiring electrode 131 that is extended from the gate principal surface electrode 121 onto the first inorganic insulating film 110, penetrates the first inorganic insulating film 110, is electrically connected to the trench gate structure 31, and faces the first trench source structure 41 across the first inorganic insulating film 110.

[0423] The SiC semiconductor device 1 preferably includes a source principal surface electrode 122 formed on the first inorganic insulating film 110, electrically connected to the first trench source structure 41 through the first inorganic insulating film 110, and facing the trench gate structure 31 across the first inorganic insulating film 110. The SiC semiconductor device 1 preferably includes a source wiring electrode 132 extended from the source principal surface electrode 122 onto the first inorganic insulating film 110, penetrates the first inorganic insulating film 110, and is electrically connected to the sidewall wiring 100. The source wiring electrode 132 preferably penetrates the first inorganic insulating film 110 at a position different from that of the source principal surface electrode 122 and is electrically connected to the first trench source structure 41.

[0424] Fig. 32 corresponds to Fig. 6 and is a plan view showing a SiC semiconductor device 311 according to a second reference preferred embodiment. Fig. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in Fig. 32. In the following, structures corresponding to those described with respect to SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0425] In a SiC semiconductor device 311 according to the second reference embodiment, a plurality of first trench source structures 41 are formed inward of the active surface 6 at intervals from the first to fourth connection surfaces 8A to 8D in plan view. The plurality of first trench source structures 41 do not cross the end of each trench gate structure 31 from the second direction Y side to the first direction X in plan view. In this embodiment, the plurality of first trench source structures 41 have a length in the first direction X that is substantially equal to the length of the plurality of trench gate structures 31.

[0426] The transistor structure 30 of the SiC semiconductor device 311 includes a plurality of second trench gate structures 321 formed on the active surface 6. A gate potential is applied to the plurality of second trench gate structures 321.

[0427] The plurality of second trench gate structures 321 are formed on the active surface 6 at intervals from the first to fourth connection surfaces 8A to 8D so as to be adjacent to the plurality of first trench source structures 41 in the first direction X and adjacent to the plurality of trench gate structures 31 in the second direction Y. Specifically, the plurality of second trench gate structures 321 are formed in regions between two adjacent trench gate structures 31 on the active surface 6 at intervals from each trench gate structure 31, and are adjacent to the plurality of first trench source structures 41 in the first direction X.

[0428] The plurality of second trench gate structures 321 are each formed in a strip shape extending in the first direction X in a plan view, and are formed at intervals in the second direction Y in a manner sandwiching one trench gate structure 31. The plurality of second trench gate structures 321 are formed in a stripe shape extending in the first direction X in a plan view.

[0429] The plurality of second trench gate structures 321 each have a third width W3. The third width W3 is the width in the direction orthogonal to the direction in which each second trench gate structure 321 extends (i.e., the second direction Y). The third width W3 may be 0.1 μm or more and 3 μm or less. The third width W3 is preferably 0.5 μm or more and 1.5 μm or less. The third width W3 may exceed the first width W1 (W1 < W3), or may be equal to or less than the first width W1 (W1 ≧ W3). In this form, the third width W3 is substantially equal to the first width W1 (W1 ≒ W3). The third width W3 preferably has a value within a range of ±10% of the value of the first width W1.

[0430] Each second trench gate structure 321 has a fourth depth D4. The fourth depth D4 exceeds the second depth D2 of the trench gate structure 31 (D2 < D4). The fourth depth D4 is preferably 1.5 times or more and 3 times or less the second depth D2. In this form, the fourth depth D4 is substantially equal to the first depth D1 of the outer surface 7 (D1 ≒ D4). Also, the fourth depth D4 is substantially equal to the third depth D3 of the first trench source structure 41 (D3 ≒ D4). The fourth depth D4 preferably has a value within a range of ±10% of the value of the third depth D3.

[0431] The fourth depth D4 may be 0.5 μm or more and 10 μm or less. The fourth depth D4 is preferably 5 μm or less. The fourth depth D4 is particularly preferably 2.5 μm or less. The aspect ratio D4 / W3 of each second trench gate structure 321 is preferably 1 or more and 5 or less. The aspect ratio D4 / W3 is the ratio of the fourth depth D4 to the third width W3. The aspect ratio D4 / W3 is particularly preferably 2 or more.

[0432] The plurality of second trench gate structures 321 are arranged at a fifth interval P5 from the plurality of trench gate structures 31 in the second direction Y. The fifth interval P5 is the distance between one trench gate structure 31 and one second trench gate structure 321 adjacent in the second direction Y. The fifth interval P5 is preferably not less than one-fourth and not more than the first interval P1 of the plurality of trench gate structures 31 (1 / 4×P1≦P5<P1). The fifth interval P5 is preferably not more than one-half of the first interval P1 (P5≦1 / 2×P1).

[0433] The fifth interval P5 may be not less than 0.1 μm and not more than 2.5 μm. The fifth interval P5 is preferably not less than 0.5 μm and not more than 1.5 μm. The fifth interval P5 is preferably approximately equal to the second interval P2 between the trench gate structure 31 and the first trench source structure 41 (P2≒P5). The fifth interval P5 preferably has a value within the range of ±10% of the value of the second interval P2.

[0434] The plurality of second trench gate structures 321 are arranged at a sixth interval P6 from the plurality of first trench source structures 41 in the first direction X. The sixth interval P6 is the distance between one first trench source structure 41 and one second trench gate structure 321 adjacent in the first direction X. The sixth interval P6 is preferably not less than one-fourth and not more than the first interval P1 of the plurality of trench gate structures 31 (1 / 4×P1≦P6<P1). The sixth interval P6 is preferably not more than one-half of the first interval P1 (P6≦1 / 2×P1).

[0435] The sixth interval P6 may be not less than 0.1 μm and not more than 2.5 μm. The sixth interval P6 is preferably not less than 0.5 μm and not more than 1.5 μm. The sixth interval P6 is preferably approximately equal to the second interval P2 between the trench gate structure 31 and the first trench source structure 41 (P2≒P6). The sixth interval P6 preferably has a value within the range of ±10% of the value of the second interval P2.

[0436] Each second trench gate structure 321 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each second trench gate structure 321 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each second trench gate structure 321 are formed by the m-plane of the SiC single crystal. The bottom wall of each second trench gate structure 321 is formed by the c-plane of the SiC single crystal.

[0437] Each second trench gate structure 321 may be formed in a vertical shape with a substantially constant opening width. Each second trench gate structure 321 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of each second trench gate structure 321 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of each second trench gate structure 321 may have a flat surface parallel to the active surface 6.

[0438] Each second trench gate structure 321 is formed in the active surface 6 to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, each second trench gate structure 321 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) with a part of the second semiconductor region 11 in between. In this embodiment, each second trench gate structure 321 is formed in the second concentration region 13, and faces the first concentration region 12 with a part of the second concentration region 13 in between.

[0439] The sidewalls of each second trench gate structure 321 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each second trench gate structure 321 is in contact with the second semiconductor region 11. In this embodiment, each second trench gate structure 321 is formed deeper than each trench gate structure 31. That is, the bottom wall of each second trench gate structure 321 is located closer to the bottom of the second semiconductor region 11 (second concentration region 13) than the bottom wall of each trench gate structure 31.

[0440] Each of the multiple second trench gate structures 321 includes a second gate trench 322, a second gate insulating film 323, and a second gate electrode 324. The second gate trench 322 forms a sidewall and a bottom wall of the second trench gate structure 321. The sidewall and the bottom wall form wall surfaces (inner wall and outer wall) of the second gate trench 322.

[0441] The opening edge of the second gate trench 322 slopes obliquely downward from the active surface 6 toward the second gate trench 322. The opening edge is a connection portion between the active surface 6 and the sidewall of the second gate trench 322. In this embodiment, the opening edge is formed in a curved shape recessed toward the SiC chip 2. The opening edge may also be formed in a curved shape directed toward the inside of the second gate trench 322.

[0442] The second gate insulating film 323 is formed in the form of a film on the inner wall of the second gate trench 322, and defines a recess space within the second gate trench 322. The second gate insulating film 323 covers the second semiconductor region 11, the body region 23, and the source region 24 on the inner wall of the second gate trench 322. The second gate insulating film 323 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second gate insulating film 323 has a single-layer structure made of a silicon oxide film.

[0443] The second gate insulating film 323 includes a first portion 323a, a second portion 323b, and a third portion 323c. The first portion 323a covers the sidewall of the second gate trench 322. Specifically, on the inner side of the active surface 6, the first portion 323a covers the sidewall of the second gate trench 322 at a distance from the opening end of the second gate trench 322 toward the bottom wall, and exposes a surface portion of the first main surface 3 from the opening end of the second gate trench 322. On the peripheral side of the active surface 6, the first portion 323a covers the entire sidewall of the second gate trench 322.

[0444] The second portion 323b covers the bottom wall of the second gate trench 322. The third portion 323c is formed on the peripheral edge side of the active surface 6 at a distance from the inner portion of the active surface 6, and covers the opening edge portion of the second gate trench 322. In this form, the third portion 323c bulges in a curved shape toward the inside of the second gate trench 322 at the opening edge portion.

[0445] The thickness of the first portion 323a may be 10 nm or more and 100 nm or less. The second portion 323b may have a thickness greater than the thickness of the first portion 323a. The thickness of the second portion 323b may be 50 nm or more and 200 nm or less. The third portion 323c has a thickness greater than the thickness of the first portion 323a. The thickness of the third portion 323c may be 50 nm or more and 200 nm or less. Of course, the second gate insulating film 323 may be formed to have a uniform thickness.

[0446] The second gate electrode 324 is buried in the second gate trench 322 with the second gate insulating film 323 sandwiched therebetween. The second gate electrode 324 faces the second semiconductor region 11, the body region 23, and the source region 24 with the second gate insulating film 323 sandwiched therebetween. The second gate electrode 324 has an electrode surface exposed from the second gate trench 322. The electrode surface of the second gate electrode 324 is formed in a curved shape recessed toward the bottom wall of the second gate trench 322.

[0447] The electrode surface of the second gate electrode 324 is narrowed by the third portion 323c of the insulating film on the peripheral edge side of the active surface 6. A gate potential is applied to the second gate electrode 324. The second gate electrode 324 is preferably made of conductive polysilicon. The second gate electrode 324 may include n-type polysilicon doped with n-type impurities and / or p-type polysilicon doped with p-type impurities. The second gate electrode 324 preferably includes the same conductive material as the gate electrode 34.

[0448] As described above, in the SiC semiconductor device 311, the second trench gate structure 321 having a structure corresponding to the first trench source structure 41 is formed on the active surface 6. The second trench gate structure 321 can also be considered to be a part separated from the first trench source structure 41.

[0449] In the SiC semiconductor device 311, the plurality of second trench source structures 51 are formed at a third interval P3 in the second direction Y so as to face the plurality of trench gate structures 31 and the plurality of second trench gate structures 321 in a one-to-one correspondence in the first direction X. That is, the plurality of second trench source structures 51 sandwich one trench gate structure 31 from both sides in the first direction X. Furthermore, the plurality of second trench source structures 51 sandwich the plurality of second trench gate structures 321 from both sides in the first direction X between themselves and the plurality of first trench source structures 41. Other structures of the plurality of second trench source structures 51 are similar to those of the plurality of second trench source structures 51 in the SiC semiconductor device 1.

[0450] The contact regions 70 are not formed in regions along the second trench gate structures 321 in the surface layer portion of the first main surface 3. In this embodiment, the gate well regions 72 are formed in the trench gate structures 31 as well as in regions along the second trench gate structures 321. The gate well regions 72 are formed in a one-to-one correspondence with the second trench gate structures 321, respectively.

[0451] Each gate well region 72 is formed in a strip shape extending along the corresponding second trench gate structure 321 in a plan view. Each gate well region 72 is formed at an interval from the trench gate structure 31 and the first trench source structure 41 toward the second trench gate structure 321, exposing the trench gate structure 31 and the first trench source structure 41. Each gate well region 72 covers the entire sidewall and bottom wall of each second trench gate structure 321. Each gate well region 72 is electrically connected to the body region 23 on the sidewall of each second trench gate structure 321.

[0452] The bottom of each gate well region 72 covering each second trench gate structure 321 is located in a region on the bottom side of the second semiconductor region 11 (second concentration region 13) relative to the bottom of each gate well region 72 covering each trench gate structure 31. The bottom of each gate well region 72 covering each second trench gate structure 321 is formed at a depth approximately equal to the bottom of each well region 71 covering each first trench source structure 41.

[0453] Each gate well region 72 covering each second trench gate structure 321 is formed at an interval from the bottom of the second semiconductor region 11 (second concentration region 13) toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In other words, each gate well region 72 covering each second trench gate structure 321 is electrically connected to the second semiconductor region 11 (second concentration region 13).

[0454] The thickness of the portion of each gate well region 72 covering the bottom wall of each second trench gate structure 321 preferably exceeds the thickness of the portion of each gate well region 72 covering the sidewall of each second trench gate structure 321. The thickness of the portion of each gate well region 72 covering the sidewall of each second trench gate structure 321 is the thickness in the normal direction to the sidewall of each second trench gate structure 321. The thickness of the portion of each gate well region 72 covering the bottom wall of each second trench gate structure 321 is the thickness in the normal direction to the bottom wall of each second trench gate structure 321.

[0455] The bottoms of the plurality of gate well regions 72 are preferably formed at a substantially constant depth relative to the bottom walls of the plurality of second trench gate structures 321. The plurality of gate well regions 72 form pn junctions with the second semiconductor region 11 (second concentration region 13) and expand the depletion layer in the width and depth directions of the SiC chip 2. The plurality of gate well regions 72 bring the trench insulated gate type MISFET closer to a pn junction diode structure and alleviate the electric field within the SiC chip 2.

[0456] The SiC semiconductor device 311 includes a plurality of gate contact electrodes 91. The plurality of gate contact electrodes 91 includes a gate contact electrode 91 on the third connection surface 8C side and a gate contact electrode 91 on the fourth connection surface 8D side. The gate contact electrode 91 on the third connection surface 8C side will be described below. The gate contact electrode 91 covers the plurality of trench gate structures 31 and the plurality of second trench gate structures 321 at a distance from the plurality of first trench source structures 41 and the plurality of second trench source structures 51.

[0457] The gate contact electrode 91 is connected to the gate electrodes 34 of the plurality of trench gate structures 31 and the second gate electrodes 324 of the plurality of second trench gate structures 321. The gate contact electrode 91 is formed in a strip shape extending in the second direction Y so as to cross the ends of the plurality of trench gate structures 31 and the inner parts of the plurality of second trench gate structures 321 in a plan view.

[0458] The gate contact electrode 91 has an electrode surface 91a extending along the active surface 6. In this embodiment, the gate contact electrode 91 is formed in a tapered shape (a truncated quadrangular pyramid shape) whose width narrows from the active surface 6 toward the electrode surface 91a. The electrode surface 91a includes a portion facing the gate electrode 34 in the normal direction Z and a portion facing a region outside the trench gate structure 31 (i.e., the main surface insulating film 90) in the normal direction Z.

[0459] The gate contact electrode 91 is preferably made of conductive polysilicon. The gate contact electrode 91 may include n-type polysilicon doped with n-type impurities and / or p-type polysilicon doped with p-type impurities. The gate contact electrode 91 is preferably made of the same conductive material as each of the gate electrodes 34.

[0460] In this embodiment, each gate contact electrode 91 is composed of an extension portion that is extended from the gate electrode 34 and the second gate electrode 324 above the active surface 6. That is, the multiple gate contact electrodes 91 are extended from the gate electrode 34 onto the main surface insulating film 90 via the third portion 33c of the gate insulating film 33, and are extended from the second gate electrode 324 onto the main surface insulating film 90 via the third portion 323c of the second gate insulating film 323.

[0461] In this embodiment, the multiple gate openings 112 are formed in strip shapes extending along the multiple gate contact electrodes 91 so as to expose the multiple gate contact electrodes 91, respectively. The gate wiring electrode 131 extends into the multiple gate openings 112 from above the first inorganic insulating film 110 and is electrically connected to the multiple gate contact electrodes 91. As a result, the gate potential applied to the gate wiring electrode 131 is imparted to the multiple trench gate structures 31 and the multiple second trench gate structures 321 via the gate wiring electrode 131.

[0462] The SiC semiconductor device 311 according to the second reference embodiment includes a SiC chip 2, a trench gate structure 31, a second trench gate structure 321, a first inorganic insulating film 110, a gate principal surface electrode 121, and a gate wiring electrode 131. The trench gate structure 31 is formed on the first principal surface 3 to a second depth D2. The second trench gate structure 321 has a fourth depth D4 that exceeds the second depth D2, and is formed on the first principal surface 3 so as to be adjacent to the trench gate structure 31.

[0463] The first inorganic insulating film 110 covers the trench gate structure 31 and the second trench gate structure 321 on the first main surface 3. A gate main surface electrode 121 is formed on the first inorganic insulating film 110. The gate wiring electrode 131 is drawn from the gate main surface electrode 121 onto the first inorganic insulating film 110, penetrates the first inorganic insulating film 110, and is electrically connected to the trench gate structure 31 and the second trench gate structure 321. With this structure, a gate potential can be applied to the trench gate structure 31 while suppressing a decrease in breakdown voltage.

[0464] The SiC semiconductor device 311 according to the second reference embodiment preferably includes a gate well region 72 formed in a region along the trench gate structure 31 in the surface layer portion of the SiC chip 2. This structure makes it possible to appropriately suppress a decrease in the breakdown voltage. The SiC semiconductor device 311 preferably further includes a second gate well region 72 formed in a region along the second trench gate structure 321 in the surface layer portion of the SiC chip 2. This structure makes it possible to further appropriately suppress a decrease in the breakdown voltage.

[0465] The SiC semiconductor device 311 according to the second reference embodiment preferably further includes a gate contact electrode 91 that covers the gate electrode 34 and the second gate electrode 324 on the first main surface 3. In this case, it is preferable that the first inorganic insulating film 110 covers the gate contact electrode 91, and the gate wiring electrode 131 penetrates the first inorganic insulating film 110 and is electrically connected to the gate contact electrode 91.

[0466] According to this structure, the gate wiring electrode 131 can be electrically connected to both the gate electrode 34 and the second gate electrode 324 at the same time via the gate contact electrode 91. Furthermore, according to this structure, the alignment margin of the gate wiring electrode 131 relative to the gate electrode 34 and the second gate electrode 324 can be alleviated by the gate contact electrode 91. In other words, the gate contact electrode 91 can compensate for the positional deviation of the gate wiring electrode 131 relative to the gate electrode 34 and the second gate electrode 324.

[0467] This allows the gate wiring electrode 131 to be appropriately electrically connected to the gate electrode 34 and the second gate electrode 324. In this structure, it is preferable that the gate contact electrode 91 partially covers the gate electrode 34 and the second gate electrode 324. It is also preferable that the gate principal surface electrode 121 is formed on the first inorganic insulating film 110 at a distance from the gate contact electrode 91 in a plan view.

[0468] In the SiC semiconductor device 311 according to the second reference embodiment, a second trench gate structure 321 having a fourth depth D4 that exceeds the second depth D2 of the trench gate structure 31 is formed in a region below the gate wiring electrode 131. Therefore, due to process errors, the thickness of the second gate insulating film 323 of the second trench gate structure 321 may deviate from the thickness of the gate insulating film 33 of the trench gate structure 31. In this case, when a gate potential is applied to the second trench gate structure 321, the breakdown voltage may decrease due to electric field concentration in the second trench gate structure 321.

[0469] 1 to 28, the first embodiment employs a SiC semiconductor device 1 including a SiC chip 2, a trench gate structure 31, a first trench source structure 41, a first inorganic insulating film 110, a gate principal surface electrode 121, and a gate wiring electrode 131. The trench gate structure 31 is formed on the first principal surface 3. The first trench source structure 41 is formed on the first principal surface 3, spaced apart from the trench gate structure 31 in one direction (second direction Y).

[0470] The first inorganic insulating film 110 covers the trench gate structure 31 and the first trench source structure 41 on the first main surface 3. A gate main surface electrode 121 is formed on the first inorganic insulating film 110. The gate wiring electrode 131 is drawn from the gate main surface electrode 121 onto the first inorganic insulating film 110 so as to cross the trench gate structure 31 and the first trench source structure 41 in one direction (second direction Y), penetrates the first inorganic insulating film 110 to be electrically connected to the trench gate structure 31, and faces the first trench source structure 41 across the first inorganic insulating film 110.

[0471] This structure can avoid a decrease in breakdown voltage that occurs when the second trench gate structure 321, which is deeper than the trench gate structure 31, is formed, while the first trench source structure 41 can provide a breakdown voltage reinforcement effect in the region below the gate wiring electrode 131. Therefore, it is possible to provide a SiC semiconductor device 1 that can improve electrical characteristics.

[0472] In this structure, it is preferable that the trench gate structure 31 is formed on the first main surface 3 at the second depth D2, and the first trench source structure 41 is formed on the first main surface 3 at the third depth D3 (D2 < D3) exceeding the second depth D2. According to this structure, the withstand voltage reinforcement effect by the deep first trench source structure 41 can be obtained.

[0473] The SiC semiconductor device 1 preferably includes a source main surface electrode 122 formed on the first inorganic insulating film 110 apart from the gate main surface electrode 121 and the gate wiring electrode 131. The source main surface electrode 122 preferably penetrates the first inorganic insulating film 110 and is electrically connected to the first trench source structure 41, and preferably faces the trench gate structure 31 with the first inorganic insulating film 110 interposed therebetween.

[0474] The SiC semiconductor device 1 preferably includes a source wiring electrode 132 drawn out from the source main surface electrode 122 onto the first inorganic insulating film 110. The source wiring electrode 132 preferably penetrates the first inorganic insulating film 110 at a position different from the source main surface electrode 122 and is electrically connected to the first trench source structure 41. In this case, the source wiring electrode 132 is preferably formed at an interval from the trench gate structure 31 in a plan view.

[0475] The SiC semiconductor device 1 preferably includes a second trench source structure 51 formed on the first main surface 3 at an interval in the crossing direction (first direction X) crossing the trench gate structure 31 in one direction (second direction Y). According to this structure, the withstand voltage reinforcement effect by the second trench source structure 51 can be obtained. The second trench source structure 51 preferably faces the trench gate structure 31 in one direction (first direction X) and faces the first trench source structure 41 in the crossing direction (second direction Y).

[0476] In this case, the source principal surface electrode 122 is preferably formed on the first inorganic insulating film 110, spaced apart from the second trench source structure 51, the gate principal surface electrode 121, and the gate wiring electrode 131 in plan view. In addition, the source principal surface electrode 122 is preferably electrically connected to the first trench source structure 41 through the first inorganic insulating film 110, and faces the trench gate structure 31 across the first inorganic insulating film 110.

[0477] In this case, it is preferable that the source wiring electrode 132 is drawn from the source principal surface electrode 122 onto the first inorganic insulating film 110, penetrates the first inorganic insulating film 110, and is electrically connected to the second trench source structure 51. It is particularly preferable that the source wiring electrode 132 penetrates the first inorganic insulating film 110 at a position different from the source principal surface electrode 122, and is electrically connected to the first trench source structure 41. It is preferable that the source wiring electrode 132 is formed at a distance from the trench gate structure 31 in a plan view.

[0478] The SiC semiconductor device 1 preferably includes a source-side pn junction (well region 71) formed in a region along the first trench source structure 41 inside the SiC chip 2. This structure makes it possible to improve the breakdown voltage of the SiC semiconductor device 1 by utilizing the first trench source structure 41. In this structure, the gate wiring electrode 131 preferably faces the source-side pn junction (well region 71) on the side of the first trench source structure 41 in plan view.

[0479] The SiC semiconductor device 1 preferably includes a source-side pn junction (well region 71) formed in a region along the second trench source structure 51 inside the SiC chip 2. This structure makes it possible to improve the breakdown voltage of the SiC semiconductor device 1 by utilizing the second trench source structure 51. In this structure, the gate wiring electrode 131 preferably faces the source-side pn junction (well region 71) on the second trench source structure 51 side in plan view.

[0480] The SiC semiconductor device 1 preferably includes a gate-side pn junction (gate well region 72) formed in at least a region along an edge of the trench gate structure 31 inside the SiC chip 2. This structure makes it possible to improve the breakdown voltage of the SiC semiconductor device 1 by utilizing the trench gate structure 31. In this structure, the gate wiring electrode 131 preferably faces the gate-side pn junction (gate well region 72) in a plan view.

[0481] The SiC semiconductor device 1 preferably includes a gate contact electrode 91 that covers the gate electrode 34 on the first main surface 3. In this case, it is preferable that the first inorganic insulating film 110 covers the gate contact electrode 91, and the gate wiring electrode 131 penetrates the first inorganic insulating film 110 and is electrically connected to the gate contact electrode 91. According to this structure, the alignment margin of the gate wiring electrode 131 with respect to the gate electrode 34 can be alleviated by the gate contact electrode 91.

[0482] That is, the gate contact electrode 91 can compensate for the misalignment of the gate wiring electrode 131 with respect to the gate electrode 34. This allows the gate wiring electrode 131 to be appropriately electrically connected to the gate electrode 34. In this structure, the gate contact electrode 91 preferably partially covers the gate electrode 34. In addition, the gate principal surface electrode 121 is preferably formed on the first inorganic insulating film 110 at a distance from the gate contact electrode 91 in a plan view.

[0483] A SiC semiconductor device 1 may be employed, which includes a SiC chip 2, a trench gate structure 31, a second trench source structure 51, a first inorganic insulating film 110, a source wiring electrode 132, and a gate wiring electrode 131. The trench gate structure 31 is formed on the first main surface 3 and extends in one direction (first direction X) in a plan view. The second trench source structure 51 is formed on the first main surface 3 at a distance from the trench gate structure 31 in the one direction (first direction X) and extends in the one direction (first direction X) in a plan view.

[0484] The first inorganic insulating film 110 covers the trench gate structure 31 and the second trench source structure 51. The gate wiring electrode 131 is formed on the first inorganic insulating film 110 and penetrates the first inorganic insulating film 110 to be electrically connected to the trench gate structure 31. The source wiring electrode 132 is formed on the first inorganic insulating film 110 at a distance from the gate wiring electrode 131 and penetrates the first inorganic insulating film 110 to be electrically connected to the second trench source structure 51. With this structure, the second trench source structure 51 can provide a voltage resistance reinforcement effect below the gate wiring electrode 131.

[0485] Preferably, a plurality of trench gate structures 31 are arranged on the first main surface 3 at intervals in an intersecting direction (second direction Y) intersecting one direction (first direction X). In this case, a plurality of second trench source structures 51 are preferably arranged at intervals in the intersecting direction (second direction Y) so as to face the plurality of trench gate structures 31 in one direction (first direction X) in a one-to-one correspondence. Furthermore, in this structure, it is preferable that the source wiring electrode 132 is formed at an interval from the trench gate structure 31 in a plan view.

[0486] Fig. 34 corresponds to Fig. 6 and is a plan view showing a SiC semiconductor device 331 according to a second embodiment of the present invention. Fig. 35 is a cross-sectional view taken along line XXXV-XXXV shown in Fig. 34. Fig. 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in Fig. 34. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Fig. 34.

[0487] Hereinafter, structures corresponding to those described for the SiC semiconductor device 1 will be denoted by the same reference numerals and will not be described again. Also, since the structure on the fourth connecting surface 8D side is substantially the same as the structure on the third connecting surface 8C side, the structure on the third connecting surface 8C side will be described below as an example. The specific structure on the fourth connecting surface 8D side can be obtained by replacing "third connecting surface 8C" with "fourth connecting surface 8D" in the following description.

[0488] Referring to FIGS. 34 to 37, a plurality of second trench source structures 51 related to the SiC semiconductor device 331, in this form, include a shallow first trench portion 332 on the inner side of the active surface 6 with respect to the first direction X, and a deep second trench portion 333 on the peripheral side of the active surface 6 (the side of the third connection surface 8C). The plurality of second trench source structures 51 have a trench step portion 334 recessed from the first trench portion 332 toward the second trench portion 333 between the first trench portion 332 and the second trench portion 333. Hereinafter, one second trench source structure 51 will be described.

[0489] The first trench portion 332 is formed on the side of the trench gate structure 31 and is formed in a strip shape extending in the first direction X in a plan view. The first trench portion 332 is formed at a third interval P3 from the trench gate structure 31 in the first direction X and faces the trench gate structure 31 in the first direction X. Also, the first trench portion 332 is formed at a second interval P2 from the first trench source structure 41 in the second direction Y and faces the first trench source structure 41 in the second direction Y.

[0490] The first trench portion 332 has a first trench depth DT1. The first trench depth DT1 is less than the first depth D1 of the outer surface 7 (DT1 < D3). The first trench depth DT1 is less than the third depth D3 of the first trench source structure 41 (DT1 < D3). Preferably, the first trench depth DT1 is substantially equal to the second depth D2 of the trench gate structure 31 (DT1 ≒ D2). Preferably, the first trench depth DT1 has a value within a range of ±10% of the value of the second depth D2. The first trench portion 332 relaxes the step between the active surface 6. Also, the first trench portion 332 brings the structure on the inner side of the second trench source structure 51 closer to the trench gate structure 31.

[0491] The first trench depth DT1 may be 0.1 μm or more and 3 μm or less. The first trench depth DT1 is preferably 0.5 μm or more and 2 μm or less. The aspect ratio DT1 / W2 of the first trench portion 332 is preferably 1 or more and 5 or less. The aspect ratio DT1 / W2 is the ratio of the first trench depth DT1 to the second width W2. It is particularly preferable that the aspect ratio DT1 / W2 be 1.5 or more.

[0492] The first trench portion 332 includes side walls and a bottom wall. The side walls forming the long sides of the first trench portion 332 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of the first trench portion 332 are formed by the m-plane of the SiC single crystal. The bottom wall of the first trench portion 332 is formed by the c-plane of the SiC single crystal.

[0493] The first trench portion 332 may be formed in a vertical shape with a substantially constant opening width. The first trench portion 332 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of the first trench portion 332 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of the first trench portion 332 may have a flat surface parallel to the active surface 6.

[0494] The first trench portion 332 is formed in the active surface 6 so as to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, the first trench portion 332 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In this embodiment, the first trench portion 332 is formed in the second concentration region 13, and faces the first concentration region 12 across a part of the second concentration region 13.

[0495] The side wall of the first trench portion 332 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of the first trench portion 332 is in contact with the second semiconductor region 11. In this form, the first trench portion 332 is formed shallower than the first trench source structure 41. That is, the bottom wall of the first trench portion 332 is located on the active surface 6 side with respect to the bottom wall of the first trench source structure 41.

[0496] The second trench portion 333 is formed between the first trench portion 332 and the third connection surface 8C. The second trench portion 333 communicates with the first trench portion 332 and is formed in a strip shape extending in the first direction X so as to penetrate the third connection surface 8C. The second trench portion 333 is formed at a second interval P2 in the second direction Y from the first trench source structure 41 and faces the first trench source structure 41 in the second direction Y.

[0497] The second trench portion 333 has a second trench depth DT2 (DT1 < DT2) that exceeds the first trench depth DT1. The second trench depth DT2 exceeds the second depth D2 (D2 < DT2) of the trench gate structure 31. The second trench depth DT2 is preferably 1.5 times or more and 3 times or less the first trench depth DT1.

[0498] In this form, the second trench depth DT2 is substantially equal to the third depth D3 of the first trench source structure 41 (D3 ≒ DT2). Also, the second trench depth DT2 is substantially equal to the first depth D1 of the outer surface 7 (D1 ≒ DT2). That is, the second trench portion 333 communicates with the outer surface 7 and the third connection surface 8C. The second trench depth DT2 preferably has a value within the range of ±10% of the value of the first depth D1 (third depth D3). The second trench portion 333 alleviates the step between the first trench portion 332 and the outer surface 7.

[0499] The second trench depth DT2 may be 0.5 μm or more and 10 μm or less. The second trench depth DT2 is preferably 5 μm or less. It is particularly preferable that the second trench depth DT2 is 2.5 μm or less. The aspect ratio DT2 / W2 of the second trench portion 333 is preferably 1 or more and 5 or less. The aspect ratio DT2 / W2 is the ratio of the second trench depth DT2 to the second width W2. It is particularly preferable that the aspect ratio DT2 / W2 is 2 or more.

[0500] The second trench portion 333 includes sidewalls and a bottom wall. The sidewalls forming the long sides of the second trench portion 333 are formed by the a-plane of the SiC single crystal. The sidewalls forming the long sides of the second trench portion 333 are connected to the sidewalls of the first trench portion 332 and the third connecting surface 8C. The sidewalls forming the short sides of the second trench portion 333 are formed by the m-plane of the SiC single crystal. The sidewalls forming the short sides of the second trench portion 333 are connected to the bottom wall of the first trench portion 332. This forms a trench step portion 334 between the first trench portion 332 and the second trench portion 333. The bottom wall of the second trench portion 333 is formed by the c-plane of the SiC single crystal. The bottom wall of the second trench portion 333 is connected to the outer surface 7.

[0501] The second trench portion 333 may be formed in a vertical shape with a substantially constant opening width. The second trench portion 333 may be formed in a tapered shape with an opening width that narrows toward the bottom wall. The bottom wall of the second trench portion 333 is preferably formed in a curved shape toward the second main surface 4. Of course, the bottom wall of the second trench portion 333 may have a flat surface parallel to the active surface 6.

[0502] The second trench portion 333 is formed in the active surface 6 so as to cross the body region 23 and the source region 24 and reach the second semiconductor region 11. Specifically, the second trench portion 333 is formed at an interval from the bottom of the second semiconductor region 11 toward the active surface 6, and faces the first semiconductor region 10 (third semiconductor region 14) across a part of the second semiconductor region 11. In this embodiment, the second trench portion 333 is formed in the second concentration region 13, and faces the first concentration region 12 across a part of the second concentration region 13.

[0503] The sidewalls of the second trench portion 333 are in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of the second trench portion 333 is in contact with the second semiconductor region 11. In this embodiment, the second trench portion 333 is formed deeper than the first trench portion 332 (trench gate structure 31). That is, the bottom wall of the second trench portion 333 is located closer to the bottom of the second semiconductor region 11 (second concentration region 13) than the bottom wall of the first trench portion 332.

[0504] The proportion of the second trench portion 333 in the second trench source structure 51 (the length in the first direction X) is arbitrary. The proportion of the second trench portion 333 in the second trench source structure 51 may be equal to or greater than the proportion of the first trench portion 332 in the second trench source structure 51, or may be less than the proportion of the first trench portion 332 in the second trench source structure 51. In order to obtain a voltage-resistant structure resulting from the second trench source structure 51, it i...

Claims

1. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction, the dummy structure being formed on a peripheral portion of the first surface; The SiC semiconductor device, wherein the plurality of dummy trench source structures are exposed from the connection surface.

2. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction, the dummy structure being formed on a peripheral portion of the first surface; The SiC semiconductor device, wherein the trench source structure is exposed from the connection surface.

3. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction, the dummy structure being formed on a peripheral portion of the first surface; The trench gate structure is formed at a distance from the connection surface inwardly of the first surface.

4. The SiC semiconductor device according to claim 3 , wherein the transistor structure includes an intermediate trench source structure having the third depth and adjacent to the trench gate structure in a cross direction crossing the one direction.

5. The SiC semiconductor device according to claim 4 , wherein the intermediate trench source structure is formed in a region on the first surface between the trench gate structure and the connection surface.

6. The SiC semiconductor device according to claim 4 , wherein the intermediate trench source structure is exposed from the connection surface.

7. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure formed on a peripheral portion of the first surface, the dummy structure including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction; a dummy trench gate structure having the second depth, and a second dummy trench source structure having the third depth and adjacent to the dummy trench gate structure in the one direction, the second dummy structure being formed in a region between the transistor structure and the dummy structure at a peripheral portion of the first surface.

8. a source potential is applied to the dummy trench gate structure; The SiC semiconductor device according to claim 7 , wherein a source potential is applied to the second dummy trench source structure.

9. 9. The SiC semiconductor device according to claim 1, further comprising a sidewall structure formed on said second surface so as to cover said connection surface.

10. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure formed on a peripheral portion of the first surface, the dummy structure including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction; an insulating film covering the transistor structure and the dummy structure on the first surface; a gate electrode formed on the insulating film; a gate wiring extending from the gate principal surface electrode onto the insulating film, penetrating the insulating film and electrically connected to the trench gate structure, and facing the trench source structure across the insulating film; a source main surface electrode formed on the insulating film at a distance from the gate main surface electrode and the gate wiring, electrically connected to the trench source structure through the insulating film, and facing the trench gate structure with the insulating film interposed therebetween; The SiC semiconductor device, wherein the source principal surface electrode is formed on the insulating film and spaced apart from the dummy structure in a plan view.

11. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure formed on a peripheral portion of the first surface, the dummy structure including a plurality of dummy trench source structures each having the third depth and adjacent to each other in the one direction; an insulating film covering the transistor structure and the dummy structure on the first surface; a gate electrode formed on the insulating film; a gate wiring extending from the gate principal surface electrode onto the insulating film, penetrating the insulating film and electrically connected to the trench gate structure, and facing the trench source structure across the insulating film; a source main surface electrode formed on the insulating film at a distance from the gate main surface electrode and the gate wiring, electrically connected to the trench source structure through the insulating film, and facing the trench gate structure with the insulating film interposed therebetween; a source wiring extending from the source principal surface electrode onto the insulating film, penetrating the insulating film at a position different from the source principal surface electrode, and electrically connected to the trench source structure.

12. The SiC semiconductor device according to claim 11 , wherein the source wiring penetrates the insulating film and is electrically connected to the dummy trench source structure.

13. a SiC chip having a main surface including a first surface, a second surface recessed to a first depth in a thickness direction outside the first surface, and a connection surface connecting the first surface and the second surface, wherein a plateau is defined by the first surface, the second surface, and the connection surface; a transistor structure formed in an inner portion of the first surface, the transistor structure including: a trench gate structure having a second depth less than the first depth; and a trench source structure having a third depth greater than the second depth and adjacent to the trench gate structure in one direction; a dummy structure formed on a peripheral portion of the first surface, the dummy structure including a dummy trench gate structure having the second depth and a dummy trench source structure having the third depth and adjacent to the dummy trench gate structure in the one direction.

Images