Capacitor Structure

Abstract

To provide a capacitor structure capable of effectively increasing its electrostatic capacity.SOLUTION: Provided is a capacitor structure which includes a first capacitor element structure, a first circuit layer, and at least one second capacitor element structure. The first capacitor element structure includes a first substrate and a plurality of first capacitors. The plurality of first capacitors are located in the first substrate. The first circuit layer is located on the first capacitor element structure. The at least one second capacitor element structure is located on the first circuit layer. The second capacitor element structure includes a second substrate and a plurality of second capacitors. The plurality of second capacitors are located in the second substrate. The plurality of first capacitors and the plurality of second capacitors are connected in parallel to each other via the first circuit layer.SELECTED DRAWING: Figure 1J

Description

[Technical Field]

[0001] The present invention relates to semiconductor structures, and more particularly to capacitor structures. [Background technology]

[0002] Capacitors are semiconductor devices widely used in electronic products, but as capacitor sizes continue to shrink, how to further increase the capacitance of capacitor structures is an ongoing challenge. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a capacitor structure that can effectively increase the capacitance of the capacitor structure. [Means for solving the problem]

[0004] The present invention provides a capacitor structure including a first capacitor element structure, a first circuit layer, and at least one second capacitor element structure. The first capacitor element structure includes a first substrate and a plurality of first capacitors. The plurality of first capacitors are located within the first substrate. The first circuit layer is located on the first capacitor element structure. At least one second capacitor element structure is located on the first circuit layer. The second capacitor element structure includes a second substrate and a plurality of second capacitors. The plurality of second capacitors are located within the second substrate. The plurality of first capacitors and the plurality of second capacitors are connected in parallel via the first circuit layer. [Effects of the Invention]

[0005] Based on the above, the present invention provides a capacitor structure in which the first capacitor element structure and the second capacitor element structure are stacked, and the first capacitors in the first capacitor element structure and the second capacitors in the second capacitor element structure are connected in parallel via the first circuit layer, thereby effectively increasing the capacitance of the capacitor structure. Furthermore, the first capacitor is embedded in the first substrate, and the second capacitor is embedded in the second substrate, thereby preventing the first capacitor and the second capacitor from collapsing. Furthermore, the manufacturing process of the capacitor structure is simple, thereby effectively reducing the complexity of the manufacturing process.

[0006] In order to make the above-mentioned features and advantages of the present invention clearer and easier to understand, the following embodiments will be shown and described in detail in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1A] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1B] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1C] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1D] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1E] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1F] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1G] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1H] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1I]1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 1J] 1A-1D are cross-sectional views of a manufacturing process for a capacitor structure according to some embodiments of the present invention. [Figure 2] FIG. 2 is a schematic three-dimensional view of region R1 in FIG. 1B. DETAILED DESCRIPTION OF THE INVENTION

[0008] 1A to 1J are cross-sectional views of a manufacturing process of a capacitor structure according to some embodiments of the present invention. FIG. 2 is a three-dimensional schematic diagram of region R1 in FIG. 1B. Note that in FIG. 2, some of the components in FIG. 1B are omitted to clearly illustrate the positional relationship between the components in FIG. 2.

[0009] Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate such as a silicon substrate. Next, a plurality of openings OP1 may be formed in the substrate 100. Then, a plurality of dielectric layers 102, a plurality of electrode layers 104, a plurality of electrode layers 106, and a plurality of insulating layers 108 may be formed in the plurality of openings OP1. This allows a capacitor element structure C1 to be formed. The capacitor element structure C1 includes a substrate 100 and a plurality of capacitors 110. The plurality of capacitors 110 are located within the substrate 100. The plurality of capacitors 110 include a plurality of electrode layers 104, a plurality of electrode layers 106, and a plurality of insulating layers 108. The plurality of insulating layers 108 are located between the plurality of electrode layers 104 and the plurality of electrode layers 106. The capacitor element structure C1 may further include a plurality of dielectric layers 102. The plurality of dielectric layers 102 are located between the plurality of electrode layers 104 and the substrate 100. The material of the dielectric layer 102 is, for example, an oxide (e.g., silicon oxide). The material of the electrode layer 104 is, for example, titanium nitride (TiN) or titanium silicon nitride (TiSiN). The material of the electrode layer 106 is, for example, titanium nitride or titanium silicon nitride. The material of the insulating layer 108 is, for example, a dielectric material such as a high-dielectric-constant material.

[0010] 1B , a circuit layer 112 is formed on the capacitor element structure C1. Multiple capacitors 110 may be connected in parallel via the circuit layer 112. In some embodiments, the circuit layer 112 may include multiple interconnect structures (e.g., interconnect structure IS1 and interconnect structure IS2 in FIG. 2 ) and a dielectric layer (not shown), and the multiple interconnect structures may be located within the dielectric layer. In some embodiments, as shown in FIG. 2 , the circuit layer 112 may include an interconnect structure IS1 and an interconnect structure IS2. The interconnect structure IS1 may include a wire 114 and multiple contacts 116. The material of the interconnect structure IS1 may include a conductive material such as copper, aluminum, or tungsten. The multiple contacts 116 are electrically connected to the multiple electrode layers 104, and the multiple contacts 116 are electrically connected to the wires 114, thereby electrically connecting the multiple electrode layers 104 to each other. The interconnect structure IS2 may include a wire 118 and multiple contacts 120. The material of the interconnect structure IS2 may include a conductive material such as copper, aluminum, tungsten, etc. The contacts 120 are electrically connected to the electrode layers 106, and the contacts 120 are electrically connected to the wires 118, so that the electrode layers 106 can be electrically connected to each other. The capacitors 110 can be connected in parallel via the interconnect structure IS1 and the interconnect structure IS2.

[0011] 1C, a dielectric material layer 122 may be formed on the circuit layer 112 and the capacitor element structure C1. The material of the dielectric material layer 122 may be, for example, an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), silicon oxynitride (SiON), or silicon carbide nitride (SiCN).

[0012] 1D, a chemical mechanical polishing (CMP) process may be performed on the dielectric material layer 122 to form a dielectric layer 122a on the capacitor element structure C1 and expose the circuit layer 112. The dielectric layer 122a may be connected to the circuit layer 112.

[0013] 1E, substrate 124 can be bonded to substrate 100. In some embodiments, substrate 100 and substrate 124 can be bonded by, for example, fusion bonding. For example, substrate 100 and substrate 124 can be bonded by dielectric layer 122a and a dielectric layer (not shown) in circuit layer 112.

[0014] 1F, a thinning process may be performed on the substrate 124. In some embodiments, the thinning process may be, for example, a grinding process, a chemical-mechanical polishing process, or a combination thereof.

[0015] Referring to FIG. 1G, a plurality of openings OP2 may be formed in the substrate 124. Then, a plurality of dielectric layers 126, a plurality of electrode layers 128, a plurality of electrode layers 130, and a plurality of insulating layers 132 may be formed in the plurality of openings OP2. In this manner, a capacitor element structure C2 may be formed on the circuit layer 112. The capacitor element structure C2 includes a substrate 124 and a plurality of capacitors 134. The plurality of capacitors 134 are located in the substrate 124. The plurality of capacitors 134 include a plurality of electrode layers 128, a plurality of electrode layers 130, and a plurality of insulating layers 132. The plurality of insulating layers 132 are located between the plurality of electrode layers 128 and the plurality of electrode layers 130. The capacitor element structure C2 may further include a plurality of dielectric layers 126. The plurality of dielectric layers 126 are located between the plurality of electrode layers 128 and the substrate 124. The material of the dielectric layer 126 is, for example, an oxide (e.g., silicon oxide). The material of the electrode layer 128 is, for example, titanium nitride or titanium silicon nitride. The material of the electrode layer 130 is, for example, titanium nitride or titanium silicon nitride. The material of the insulating layer 132 is, for example, a dielectric material such as a high-dielectric-constant material.

[0016] By electrically connecting the plurality of electrode layers 128 to one another via the circuit layer 112 and electrically connecting the plurality of electrode layers 130 to one another via the circuit layer 112, it is possible to connect the plurality of capacitors 134 in parallel via the circuit layer 112. The method of electrically connecting the plurality of electrode layers 128 to one another and the method of electrically connecting the plurality of electrode layers 130 to one another can refer to the method of electrically connecting the plurality of electrode layers 104 to one another and the method of electrically connecting the plurality of electrode layers 106 to one another in FIG. 2, which will not be described again.

[0017] Furthermore, the plurality of electrode layers 104 and the plurality of electrode layers 128 can be electrically connected to each other via the circuit layer 112, and the plurality of electrode layers 106 and the plurality of electrode layers 130 can be electrically connected to each other via the circuit layer 112. For example, although not shown, the plurality of electrode layers 104 and the plurality of electrode layers 128 can be electrically connected to each other via an interconnection structure IS1, and the plurality of electrode layers 106 and the plurality of electrode layers 130 can be electrically connected to each other via an interconnection structure IS2. This allows the plurality of capacitors 110 and the plurality of capacitors 134 to be connected in parallel via the circuit layer 112.

[0018] An opening OP3 may also be formed in the substrate 124. Then, a dielectric layer 136 and a contact 138 may be formed in the opening OP3. The dielectric layer 136 is located between the contact 138 and the substrate 124. The contact 138 may be electrically connected to the circuit layer 112. The material of the dielectric layer 136 is, for example, an oxide (e.g., silicon oxide). The contact 138 may have a single-layer structure or a multi-layer structure. The material of the contact 138 is, for example, tungsten, titanium, titanium nitride, or a combination thereof.

[0019] 1H, a circuit layer 140 is formed on the capacitor element structure C2. In some embodiments, the circuit layer 140 may include multiple interconnect structures (not shown) and a dielectric layer (not shown), and the multiple interconnect structures may be located within the dielectric layer. For details regarding the circuit layer 140, please refer to the description of the circuit layer 112, and the description thereof will be omitted here.

[0020] Furthermore, a dielectric layer 142 may be formed on the capacitor element structure C2. The dielectric layer 142 can be connected to the circuit layer 140. The material of the dielectric layer 142 is, for example, an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), silicon oxynitride (SiON), or silicon carbide nitride (SiCN). Note that the method for forming the dielectric layer 142 can refer to the method for forming the dielectric layer 122a, and the description thereof will be omitted here.

[0021] 1I, the steps of forming the capacitor element structure C2, the dielectric layer 136, the contact 138, and the circuit layer 140 can be repeated at least once to form multiple capacitor element structures C2, multiple dielectric layers 136, multiple contacts 138, and multiple circuit layers 140. The multiple capacitors 134 in two adjacent capacitor element structures C2 can be connected in parallel via the circuit layer 140. The two adjacent substrates 124 in the two adjacent capacitor element structures C2 can be joined by, for example, fusion bonding. For example, the two adjacent substrates 124 in the two adjacent capacitor element structures C2 can be joined via the dielectric layer 142 and a dielectric layer (not shown) in the circuit layer 140. By the above-mentioned method, at least one capacitor element structure C2, at least one dielectric layer 136, at least one contact 138, at least one circuit layer 140, and at least one dielectric layer 142 can be formed. The number of capacitor element structures C2, the number of dielectric layers 136, the number of contacts 138, the number of circuit layers 140, and the number of dielectric layers 142 are not limited to the numbers shown in the figure. The number of capacitor element structures C2, the number of dielectric layers 136, the number of contacts 138, the number of circuit layers 140, and the number of dielectric layers 142 is within the scope of the present invention as long as there is at least one.

[0022] Referring to FIG. 1J, a dielectric layer 144 may be formed on the circuit layer 140. The material of the dielectric layer 144 may be, for example, an oxide (e.g., silicon oxide). Next, a plurality of openings OP4 may be formed in the dielectric layer 144. Then, a plurality of electrode layers 146, a plurality of electrode layers 148, and a plurality of insulating layers 150 may be formed in the plurality of openings OP4. In this manner, a capacitor element structure C3 may be formed on the circuit layer 140. The capacitor element structure C3 may include a dielectric layer 144 and a plurality of capacitors 152. The plurality of capacitors 152 are located in the dielectric layer 144. The plurality of capacitors 152 include a plurality of electrode layers 146, a plurality of electrode layers 148, and a plurality of insulating layers 150. The plurality of insulating layers 150 are located between the plurality of electrode layers 146 and the plurality of electrode layers 148. The material of the electrode layer 146 may be, for example, titanium nitride or titanium silicon nitride. The material of the electrode layer 148 may be, for example, titanium nitride or titanium silicon nitride. The material of the insulating layer 150 is, for example, a dielectric material such as a high dielectric constant material. The number of the plurality of capacitors 152 is not limited to the number shown in the figure.

[0023] The plurality of electrode layers 146 can be electrically connected to one another via the circuit layer 140, and the plurality of electrode layers 148 can be electrically connected to one another via the circuit layer 140, thereby allowing the plurality of capacitors 152 to be connected in parallel by the circuit layer 140. The method of electrically connecting the plurality of electrode layers 146 to one another and the method of electrically connecting the plurality of electrode layers 148 to one another can refer to the method of electrically connecting the plurality of electrode layers 104 to one another and the method of electrically connecting the plurality of electrode layers 106 to one another in FIG. 2, and therefore will not be described again.

[0024] Furthermore, the plurality of electrode layers 128 and the plurality of electrode layers 146 can be electrically connected to each other via the circuit layer 140, and the plurality of electrode layers 130 and the plurality of electrode layers 148 can be electrically connected to each other via the circuit layer 140. Therefore, the plurality of capacitors 134 and the plurality of capacitors 152 can be connected in parallel via the circuit layer 140.

[0025] A circuit layer 154 may then be formed over the capacitor element structure C3. In some embodiments, the circuit layer 154 may be electrically connected to the plurality of electrode layers 148. In other embodiments, the circuit layer 154 may be electrically connected to the plurality of electrode layers 150. In some embodiments, the circuit layer 140 may include a plurality of interconnect structures (not shown) and a dielectric layer (not shown), and the plurality of interconnect structures may be located within the dielectric layer.

[0026] Then, a dielectric layer 156 may be formed on the capacitor element structure C2, the capacitor element structure C3, the circuit layer 140, and the circuit layer 154. Next, an opening OP5 may be formed in the dielectric layer 156. Furthermore, a contact 158 ​​may be formed in the opening OP5. The contact 158 ​​may be electrically connected to the circuit layer 140. The contact 158 ​​may have a single-layer structure or a multi-layer structure. The material of the contact 158 ​​may be, for example, tungsten, titanium, titanium nitride, or a combination thereof.

[0027] Furthermore, a dielectric layer 160 may be formed on the dielectric layer 156. An interconnect structure IS3 may be formed in the dielectric layer 160. The interconnect structure IS3 may be electrically connected to the contact 158. An interconnect structure IS4 may be formed in the dielectric layer 160 and the dielectric layer 156. The interconnect structure IS4 may be electrically connected to the circuit layer 154. Pads 162 and 164 may be formed above the capacitor element structure C3. In this embodiment, the pads 162 and 164 may be formed on the dielectric layer 160. The pads 162 and 164 may be separated from each other. The pad 162 may be electrically connected to the interconnect structure IS3. The pad 164 may be electrically connected to the interconnect structure IS4. A protective layer 166 may be formed on the dielectric layer 160, the pad 162, and the pad 164. The protective layer 166 may expose a portion of the pad 162 and a portion of the pad 164.

[0028] 1J, the capacitor structure 10 in the above embodiment will be described. Note that the method for forming the capacitor structure 10 will be described using the above method as an example, but the present invention is not limited to this.

[0029] Referring to FIG. 1J, capacitor structure 10 includes a capacitor element structure C1, a circuit layer 112, and at least one capacitor element structure C2. In some embodiments, capacitor structure 10 may be a chiplet structure. In some embodiments, capacitor structure 10 may include a silicon capacitor structure. Capacitor element structure C1 includes a substrate 100 and a plurality of capacitors 110. The plurality of capacitors 110 is located within substrate 100. A circuit layer 112 is located on capacitor element structure C1. At least one capacitor element structure C2 is located on circuit layer 112. Capacitor element structure C2 includes a substrate 124 and a plurality of capacitors 134. The plurality of capacitors 134 is located within substrate 124. The plurality of capacitors 134 may penetrate substrate 124. The plurality of capacitors 110 and the plurality of capacitors 134 are connected in parallel via circuit layer 112, which can effectively increase the capacitance of capacitor structure 10.

[0030] The capacitor structure 10 may further include at least one circuit layer 140. The circuit layer 140 is located on the capacitor element structure C2. In this embodiment, the at least one capacitor element structure C2 may include multiple capacitor element structures C2, and the at least one circuit layer 140 may include multiple circuit layers 140. Multiple capacitor element structures C2 may be stacked on the circuit layer 112. The circuit layer 140 may be located between two adjacent capacitor element structures C2. The multiple capacitors 134 in two adjacent capacitor element structures C2 can be connected in parallel via the circuit layer 140, thereby further increasing the capacitance of the capacitor structure 10.

[0031] Capacitor structure 10 includes dielectric layer 122a and dielectric layer 142. Dielectric layer 122a is located between substrate 100 and substrate 124 of the lowermost capacitor element structure C2. Dielectric layer 142 is located between two adjacent substrates 124 in two adjacent capacitor element structures C2.

[0032] The capacitor structure 10 may further include a capacitor element structure C3. The capacitor element structure C3 is located on the circuit layer 140. The capacitor element structure C3 may include a dielectric layer 144 and a plurality of capacitors 152. The plurality of capacitors 152 are located in the dielectric layer 144. The plurality of capacitors 152 may penetrate the dielectric layer 144. The plurality of capacitors 134 and the plurality of capacitors 152 can be connected in parallel via the circuit layer 140, thereby further increasing the capacitance of the capacitor structure 10. The capacitor structure 10 may further include a circuit layer 154. The circuit layer 154 is located on the capacitor element structure C3.

[0033] The plurality of capacitors 110 includes a plurality of electrode layers 104, a plurality of electrode layers 106, and a plurality of insulating layers 108. The plurality of insulating layers 108 are located between the plurality of electrode layers 104 and the plurality of electrode layers 106. The plurality of capacitors 134 includes a plurality of electrode layers 128, a plurality of electrode layers 130, and a plurality of insulating layers 132. The plurality of insulating layers 132 are located between the plurality of electrode layers 128 and the plurality of electrode layers 130. The plurality of capacitors 152 includes a plurality of electrode layers 146, a plurality of electrode layers 148, and a plurality of insulating layers 150. The plurality of insulating layers 150 are located between the plurality of electrode layers 146 and the plurality of electrode layers 148. The capacitor element structure C1 may further include a plurality of dielectric layers 102. The plurality of dielectric layers 102 are located between the plurality of electrode layers 104 and the substrate 100. The capacitor element structure C2 may further include a dielectric layer 126. A plurality of dielectric layers 126 are located between the plurality of electrode layers 128 and the substrate 124 .

[0034] Capacitor structure 10 may further include pad 162 and pad 164. Pad 162 and pad 164 are located above capacitor element structure C3 and are spaced apart from each other. Capacitor structure 10 may further include dielectric layer 156, contact 138, contact 158, dielectric layer 136, dielectric layer 160, interconnect structure IS3, and interconnect structure IS4. Dielectric layer 156 is located on capacitor element structure C2, capacitor element structure C3, circuit layer 140, and circuit layer 154. Contact 138 and contact 158 ​​are located in substrate 124 and dielectric layer 156, respectively. Circuit layer 112, contact 138, circuit layer 140, and contact 158 ​​can be electrically connected to each other. Dielectric layer 136 is located between contact 138 and substrate 124. Dielectric layer 160 is located on dielectric layer 156. Pad 162 and pad 164 are located on dielectric layer 160. Interconnect structure IS3 is located in dielectric layer 160. Interconnect structure IS3 may be electrically connected to contact 158 ​​and pad 162. Interconnect structure IS4 is located in dielectric layer 160 and dielectric layer 156. Interconnect structure IS4 may be electrically connected to circuit layer 154 and pad 164. Capacitor structure 10 may further include a protective layer 166. Protective layer 166 is located on dielectric layer 160, pad 162, and pad 164. Protective layer 166 may expose a portion of pad 162 and a portion of pad 164.

[0035] In some embodiments, the plurality of electrode layers 104, the plurality of electrode layers 128, and the plurality of electrode layers 146 can be electrically connected to each other and to pads 162, and the plurality of electrode layers 106, the plurality of electrode layers 130, and the plurality of electrode layers 148 can be electrically connected to each other and to pads 164. In some embodiments, the plurality of electrode layers 104, the plurality of electrode layers 128, and the plurality of electrode layers 146 can be electrically connected to the circuit layer 112, the contacts 138, the circuit layer 140, the contacts 158 via interconnect structures IS3 and can be electrically connected to pads 162, and the plurality of electrode layers 106, the plurality of electrode layers 130, and the plurality of electrode layers 148 can be electrically connected to the circuit layer 112, the circuit layer 140, and the circuit layer 154 via interconnect structures IS4 and can be electrically connected to each other and to pads 164.

[0036] In other embodiments, the plurality of electrode layers 104, the plurality of electrode layers 128, and the plurality of electrode layers 146 can be electrically connected to each other and to pad 164, and the plurality of electrode layers 106, the plurality of electrode layers 130, and the plurality of electrode layers 148 can be electrically connected to each other and to pad 162. In other embodiments, the plurality of electrode layers 104, the plurality of electrode layers 128, and the plurality of electrode layers 146 can be electrically connected to the circuit layer 112, the circuit layer 140, and the circuit layer 154 via interconnect structure IS4 and to pad 164, and the plurality of electrode layers 106, the plurality of electrode layers 130, and the plurality of electrode layers 148 can be electrically connected to the circuit layer 112, the contact 138, the circuit layer 140, and the contact 158 ​​via interconnect structure IS3 and to pad 162.

[0037] The details of each component of the capacitor structure 10 (for example, materials, forming methods, etc.) have been described in detail in the above embodiment, and will not be described again here.

[0038] Based on the above-described embodiment, it can be seen that in capacitor structure 10 and its manufacturing method, capacitor element structure C1 and capacitor element structure C2 are stacked, and the plurality of capacitors 110 in capacitor element structure C1 and the plurality of capacitors 134 in capacitor element structure C2 are connected in parallel via circuit layer 112, thereby effectively increasing the capacitance of the capacitor structure. Furthermore, capacitor 110 is embedded in substrate 100, and capacitor 134 is embedded in substrate 124, which can prevent capacitors 110 and 134 from collapsing. Furthermore, the manufacturing process of capacitor structure 10 is simple, which can effectively reduce the complexity of the manufacturing process. [Industrial Applicability]

[0039] The capacitor structure provided by the present invention can be used in electronic products.

[0040] Although the present invention has been disclosed through the above embodiments, they are not intended to limit the present invention, and a person having ordinary skill in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. [Explanation of symbols]

[0041] 10: Capacitor structure 100, 124: Substrate 102, 122a, 126, 136, 142, 144, 156, 160: dielectric layers 104, 106, 128, 130, 146, 148: Electrode layer 108, 132, 150: Insulating layer 110, 134, 152: Capacitors 112, 140, 154: Circuit layer 114, 118: Wire 116, 120, 138, 158: Contact 122: Dielectric material layer 162, 164: Pad 166: Protective layer C1, C2, C3: Capacitor element structure IS1, IS2, IS3, IS4: Interconnection structures OP1, OP2, OP3, OP4, OP5: Opening R1: area

Claims

1. A first capacitor element structure, a first substrate; the first capacitor element structure comprising: a plurality of first capacitors located within the first substrate; a first circuit layer positioned on the first capacitor element structure; at least one second capacitor element structure located on the first circuit layer; at least one second circuit layer overlying the second capacitor element structure; a third capacitor element structure located on the second circuit layer; The second capacitor element structure comprises: A second substrate; a plurality of second capacitors located within the second substrate; the plurality of first capacitors and the plurality of second capacitors are connected in parallel via the first circuit layer; The third capacitor element structure comprises: a first dielectric layer; a plurality of third capacitors located within the first dielectric layer; the plurality of second capacitors and the plurality of third capacitors are connected in parallel via the second circuit layer; Capacitor structure.

2. further comprising a third circuit layer positioned on the third capacitor element structure; The capacitor structure of claim 1 .

3. the plurality of first capacitors include a plurality of first electrode layers, a plurality of second electrode layers, and a plurality of first insulating layers; the first insulating layers are located between the first electrode layers and the second electrode layers; the second capacitors include a plurality of third electrode layers, a plurality of fourth electrode layers, and a plurality of second insulating layers; the second insulating layers are located between the third electrode layers and the fourth electrode layers; the third capacitors include a plurality of fifth electrode layers, a plurality of sixth electrode layers, and a plurality of third insulating layers; the third insulating layers are located between the fifth electrode layers and the sixth electrode layers; The capacitor structure of claim 2 .

4. The first circuit layer comprises: a first interconnect structure, a first interconnect structure, wherein the first electrode layers and the third electrode layers are electrically connected to each other via the first interconnect structure; a second interconnect structure, a second interconnect structure, wherein the second electrode layers and the fourth electrode layers are electrically connected to each other via the second interconnect structure; Equipped with, The capacitor structure of claim 3 .

5. the first capacitor element structure further includes a plurality of second dielectric layers positioned between the plurality of first electrode layers and the first substrate; the second capacitor element structure further includes a plurality of third dielectric layers positioned between the plurality of third electrode layers and the second substrate; The capacitor structure of claim 3 .

6. Further comprising a first pad and a second pad, the first pad and the second pad are located above the third capacitor element structure and are spaced apart from each other; The capacitor structure of claim 3 .

7. the plurality of first electrode layers, the plurality of third electrode layers, and the plurality of fifth electrode layers are electrically connected to each other and to the first pad; the plurality of second electrode layers, the plurality of fourth electrode layers, and the plurality of sixth electrode layers are electrically connected to each other and to the second pad; The capacitor structure of claim 6.

8. a second dielectric layer, a first contact, and a second contact; the second dielectric layer is located on the second capacitor element structure, the third capacitor element structure, the second circuit layer, and the third circuit layer; the first contact and the second contact are located in the second substrate and the second dielectric layer, respectively; the first circuit layer, the first contact, the second circuit layer, and the second contact are electrically connected to one another; The capacitor structure of claim 6.

9. a third dielectric layer located on the second dielectric layer, the first pad and the second pad being located on the third dielectric layer; a first interconnect structure located within the third dielectric layer and electrically connected to the second contact and the first pad; a second interconnect structure located within the third dielectric layer and the second dielectric layer and electrically connected to the third circuit layer and the second pad; The capacitor structure of claim 8 further comprising:

10. the first electrode layers, the third electrode layers, and the fifth electrode layers are electrically connected to each other via the first circuit layer, the first contacts, and the second circuit layer, and are electrically connected to the first pads via the second contacts and the first interconnect structure; the second electrode layers, the fourth electrode layers, and the sixth electrode layers are electrically connected to each other via the first circuit layer and the second circuit layer, and are electrically connected to the second pads via the third circuit layer and the second interconnect structure; The capacitor structure of claim 9.

11. At least one of the second capacitor element structures includes a plurality of the second capacitor element structures; a plurality of the second capacitor element structures are stacked on the first circuit layer, the second circuit layer is located between two adjacent second capacitor element structures, and the plurality of second capacitors in the two adjacent second capacitor element structures are connected in parallel via the second circuit layer; The capacitor structure of claim 1 .

12. the plurality of first capacitors include a plurality of first electrode layers, a plurality of second electrode layers, and a plurality of first insulating layers; the first insulating layers are located between the first electrode layers and the second electrode layers; the second capacitors each include a third electrode layer, a fourth electrode layer, and a second insulating layer; the second insulating layers are located between the third electrode layers and the fourth electrode layers; The capacitor structure of claim 1 .

13. The first circuit layer comprises: a first interconnect structure, the first interconnect structure, wherein the first electrode layers and the third electrode layers are electrically connected to each other via the first interconnect structure; a second interconnect structure, the second interconnect structure, wherein the second electrode layers and the fourth electrode layers are electrically connected to each other via the second interconnect structure; The capacitor structure of claim 12 comprising:

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