Semiconductor device and imaging device

Abstract

This semiconductor device comprises a first capacitive element that includes a first electrode, a second electrode and a dielectric layer which is positioned between the first electrode and the second electrode, and a second capacitive element that includes a third electrode and an insulating layer which is positioned between the second electrode and the third electrode. The first capacitive element includes at least one first trench section.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and an imaging device. [Background technology]

[0002] To improve the integration density of capacitors in semiconductor integrated circuits, efforts are being made to increase the capacitance density per unit area. The capacitance C of a capacitor is expressed as C = (ε × ε × S) / t, where ε is the dielectric constant of the dielectric material, ε is the dielectric constant of a vacuum, t is the dielectric film thickness, and S is the electrode area. In other words, the capacitance density can be improved by increasing the dielectric constant ε of the dielectric material, reducing the dielectric film thickness t, increasing the surface area and electrode area S by using a three-dimensional structure (see, for example, Patent Document 1), and electrically connecting multiple capacitors in parallel (see, for example, Patent Document 2). Meanwhile, the breakdown voltage characteristics and leakage current can be improved and reduced by increasing the dielectric film thickness t, using a low-dielectric-constant material with a wide band gap, and electrically connecting multiple capacitors in series. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-145790 [Patent Document 2] US Patent Application Publication No. 2019 / 0096986 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a semiconductor device and an imaging device including a capacitive element that can exhibit excellent characteristics depending on the application. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment of the present disclosure includes a first capacitance element including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, and a second capacitance element including a third electrode and an insulating layer located between the second electrode and the third electrode, wherein the first capacitance element includes at least one first trench portion.

[0006] An imaging device according to one aspect of the present disclosure includes the semiconductor device according to the above aspect. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a semiconductor device and an imaging device including a capacitive element that can exhibit excellent characteristics depending on the application. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a circuit configuration of an imaging device according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel included in the imaging device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a pixel included in the imaging device according to the embodiment. [Figure 4A] FIG. 4A is a diagram showing a first example of electrical connection between two capacitance elements included in the imaging device according to the embodiment. [Figure 4B] FIG. 4B is a diagram showing a second example of the electrical connection between two capacitive elements included in the imaging device according to the embodiment. [Figure 5] FIG. 5 is a diagram showing a third example of the electrical connection between two capacitive elements included in the imaging device according to the embodiment. [Figure 6A] FIG. 6A is a cross-sectional view showing a first example of connection of contact vias to two capacitive elements in the imaging device according to the embodiment. [Figure 6B] FIG. 6B is a cross-sectional view showing a second example of the connection of contact vias to two capacitive elements in the imaging device according to the embodiment. [Figure 7]FIG. 7 is a cross-sectional view of a pixel included in an imaging device according to the first modification of the embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a pixel included in an imaging device according to the second modification of the embodiment. [Figure 9] FIG. 9 is a cross-sectional view of a pixel included in an imaging device according to the third modification of the embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a pixel included in an imaging device according to the fourth modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Findings that formed the basis of this disclosure) The present inventors have found that the prior art described in the "Background Art" section has the following problems.

[0010] Patent Document 1 discloses a technology that increases the capacitance density per unit area by improving the breakdown voltage of a capacitance element having a trench structure, thereby making it possible to reduce the thickness of the dielectric film. However, for example, in image sensor applications, a higher capacitance density of the capacitance element is preferable, and there is a problem that the capacitance density of the capacitance element is insufficient for purposes such as reducing the pixel size of the image sensor, increasing saturation, and improving the dynamic range.

[0011] Patent Document 2 discloses a technique for increasing the capacitance density of a capacitance element by stacking planar capacitance elements and connecting them in parallel. However, planar capacitance elements that do not have a trench structure have a problem in that they have low capacitance density.

[0012] To address these conventional problems, there is a need for a capacitive element that can be easily changed depending on the application, such as improving capacitance density and reducing leakage current. The present disclosure provides a semiconductor device and an imaging device that include a capacitive element that can exhibit excellent characteristics depending on the application.

[0013] A semiconductor device according to an embodiment of the present disclosure includes a first capacitance element including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, and a second capacitance element including a third electrode and an insulating layer located between the second electrode and the third electrode, wherein the first capacitance element includes at least one first trench portion.

[0014] This allows the two capacitive elements to exhibit excellent characteristics depending on the application by changing the electrical connection between the first electrode, the second electrode, and the third electrode. For example, by connecting a first capacitive element having a trench portion and a second capacitive element different from the first capacitive element in parallel, a semiconductor device including a capacitive element with excellent capacitance density per unit area can be provided. Furthermore, by connecting a first capacitive element having a trench portion and a second capacitive element in series, a semiconductor device including a capacitive element with excellent leakage current characteristics can be provided. In this way, a semiconductor device with high design freedom, which allows selection between series connection and parallel connection, can be provided.

[0015] Furthermore, for example, the first electrode, the second electrode, and the third electrode may be stacked in this order, and at least a portion of the first electrode, at least a portion of the second electrode, and at least a portion of the third electrode may overlap each other in a planar view.

[0016] This allows the capacitance density per unit area to be further increased.

[0017] In Patent Document 2, the stacked structure of two capacitive elements includes a first electrode formed above a substrate, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, and a third electrode formed on the second dielectric layer. The surface area of ​​the third electrode is smaller than that of the second electrode, and the surface area of ​​the second electrode is smaller than that of the first electrode. Therefore, at least one contact via wiring electrically connecting the electrode is formed on the electrode on the dielectric film functioning as a capacitive film. To form the contact via wiring, the interlayer insulating film on the electrode and the electrode are etched by dry etching. This dry etching causes etching damage to the dielectric layer directly below the electrode, which may increase leakage current and reduce the breakdown voltage characteristics of the capacitive element.

[0018] In contrast to this, the semiconductor device according to one aspect of the present disclosure may further include, for example, a first contact plug connected to the first electrode in the at least one first trench portion.

[0019] This allows contact with the first electrode from below, which prevents etching damage to the dielectric layer located between the first and second electrodes when forming a contact plug for the first electrode, thereby suppressing an increase in leakage current of the capacitance element and improving the breakdown voltage characteristics.

[0020] Also, for example, the dielectric layer may include a first non-overlapping portion that does not overlap the first electrode in a planar view, the insulating layer may include a second non-overlapping portion that does not overlap the second electrode in a planar view, and the first non-overlapping portion may be located at the same height as the second non-overlapping portion in the thickness direction of the semiconductor device.

[0021] As a result, a portion of the dielectric layer and a portion of the insulating layer are positioned at the same height in the thickness direction of the semiconductor device, so that a portion of the second electrode provided above the portion of the dielectric layer and a portion of the third electrode provided above the portion of the insulating layer can also be positioned at the same height. By making contact at these same height portions, the heights of the contacts for the second electrode and the third electrode can be aligned, thereby achieving good contact with each other.

[0022] Furthermore, for example, the first electrode may have two surfaces, and the surface of the two surfaces that is closer to the dielectric layer may be entirely covered with the dielectric layer.

[0023] This makes it possible to realize a capacitive element that effectively utilizes the entire upper surface of the first electrode, and also to prevent short circuits between the first electrode and the second electrode.

[0024] Also, for example, the second electrode may include a third non-overlapping portion that does not overlap with either the insulating layer or the third electrode in a planar view, the third electrode may include a fourth non-overlapping portion that does not overlap with either the first electrode, the dielectric layer, or the second electrode in a planar view, and the third non-overlapping portion may be located at the same height as the fourth non-overlapping portion in the thickness direction of the semiconductor device.

[0025] This allows the second electrode and the third electrode to make contact at their non-overlapping portions, so that even if etching damage occurs to the dielectric layer or the insulating layer, it is possible to suppress adverse effects on the capacitance characteristics, thereby suppressing an increase in leakage current of the capacitance element and improving the breakdown voltage characteristics.

[0026] Also, for example, a semiconductor device according to one embodiment of the present disclosure may further include a second contact plug connected to the second electrode at the third non-overlapping portion, and a third contact plug connected to the third electrode at the fourth non-overlapping portion.

[0027] This allows the second electrode and the third electrode to make contact at their non-overlapping portions, so that even if etching damage occurs to the dielectric layer or the insulating layer, it is possible to suppress adverse effects on the capacitance characteristics, thereby suppressing an increase in leakage current of the capacitance element and improving the breakdown voltage characteristics.

[0028] Furthermore, for example, the second contact plug may penetrate the third non-overlapping portion, or the third contact plug may penetrate the fourth non-overlapping portion.

[0029] This allows the other contact plug and the second or third contact plug to be formed in the same process, reducing the number of processes such as etching, making it less likely that misalignment of the mask will occur, resulting in a highly reliable semiconductor device.

[0030] Furthermore, for example, the dielectric constant of the dielectric layer may be equal to or greater than the dielectric constant of the insulating layer.

[0031] This makes it possible to increase the capacitance value of the first capacitive element, and further increase the capacitance density per unit area.

[0032] Furthermore, for example, the semiconductor device according to one aspect of the present disclosure may include an insulating cover layer that covers the second capacitive element, and the insulating layer may have a dielectric constant equal to or greater than the dielectric constant of the insulating cover layer.

[0033] This makes it possible to increase the capacitance value of the second capacitive element, and further increase the capacitance density per unit area.

[0034] Furthermore, for example, the second capacitive element may include the second electrode.

[0035] As a result, the second electrode is shared by two capacitance elements, so that the number of connection wires between the two capacitance elements can be reduced, and the occurrence of unnecessary components in the circuit, such as parasitic capacitance, can be suppressed.

[0036] Furthermore, for example, the second capacitive element may further include a fourth electrode located between the second electrode and the insulating layer.

[0037] This allows the four electrodes included in the two capacitance elements to be electrically isolated from each other, further increasing the degree of freedom in wiring layout.

[0038] Furthermore, for example, the first electrode and the third electrode may be electrically connected to each other.

[0039] This allows the first capacitive element and the second capacitive element to be connected in parallel, thereby increasing the capacitance density per unit area.

[0040] Also, for example, no potential may be supplied to the second electrode.

[0041] This allows the first capacitance element and the second capacitance element to be connected in series, thereby reducing the leakage current.

[0042] Furthermore, for example, the first electrode and the third electrode may not be electrically connected to each other.

[0043] This allows the first capacitive element and the second capacitive element to have separate functions.

[0044] Furthermore, for example, the second capacitive element may include at least one second trench portion.

[0045] This makes it possible to further increase the capacitance density per unit area. In plan view, the at least one second trench portion may overlap with the at least one first trench portion.

[0046] An imaging device according to an aspect of the present disclosure includes the semiconductor device according to the above aspect.

[0047] This allows for the realization of an imaging device including a capacitive element with a high degree of design freedom. For example, a desired function can be imparted to the capacitive element in a signal processing circuit that processes charges generated in a photoelectric conversion unit. For example, by using a capacitive element with a high capacitance density per unit area as part of a charge storage region, it is possible to improve the dynamic range, or to achieve higher pixel resolution or a more compact imaging device by reducing the pixel area. Furthermore, by using a capacitive element with reduced leakage current, it is possible to realize an imaging device that can generate high-quality images with less noise.

[0048] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0049] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0050] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0051] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0052] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0053] In this specification, the term "plan view" refers to a view from a direction perpendicular to the main surface of the semiconductor substrate.

[0054] In this specification, two layers being located in the "same layer" means that the two layers are provided in contact with the upper surface of a predetermined layer, or that the two layers are equidistant from the upper surface of the predetermined layer. In this case, if the predetermined layer is a planarization film, the two layers will have substantially the same height relative to the main surface of the semiconductor substrate.

[0055] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0056] (Embodiment) [1. Circuit configuration] FIG. 1 is a diagram illustrating an exemplary circuit configuration of an imaging device 100 according to the present embodiment. As shown in FIG. 1, the imaging device 100 includes a plurality of pixels 10 and peripheral circuits. The plurality of pixels 10 are arranged, for example, two-dimensionally to form a pixel area RA. For simplicity, FIG. 1 illustrates only four of the plurality of pixels 10, and the other pixels 10 are not illustrated. The peripheral circuits are disposed in a peripheral area outside the pixel area RA. Needless to say, the number and arrangement of the pixels 10 are not particularly limited. The pixels 10 may be arranged one-dimensionally. In this case, the imaging device 100 can be used as a line sensor.

[0057] Each of the plurality of pixels 10 is connected to a power supply wiring 22. When the imaging device 100 is in operation, a predetermined power supply voltage AVDD is supplied to each of the plurality of pixels 10 via the power supply wiring 22. An accumulation control line 17 is also connected to each of the plurality of pixels 10. As will be described in detail later, each of the plurality of pixels 10 includes a photoelectric conversion unit that photoelectrically converts incident light, and a signal detection circuit that detects a signal generated by the photoelectric conversion unit. In a typical embodiment, the accumulation control line 17 applies a predetermined voltage in common to the photoelectric conversion units of each pixel 10.

[0058] In the configuration illustrated in FIG. 1, the peripheral circuits of the imaging device 100 include a vertical scanning circuit 16, multiple load circuits 19, multiple column signal processing circuits 20, multiple inverting amplifiers 24, and a horizontal signal readout circuit 21. The load circuits 19, column signal processing circuits 20, and inverting amplifiers 24 are arranged for each column of pixels 10 arranged two-dimensionally. The vertical scanning circuit is also called a row scanning circuit. The column signal processing circuit is also called a row signal storage circuit. The horizontal signal readout circuit is also called a column scanning circuit.

[0059] An address signal line 30 and a reset signal line 26 are connected to the vertical scanning circuit 16. The vertical scanning circuit 16 selects a plurality of pixels 10 arranged in each row on a row-by-row basis by applying a predetermined voltage to the address signal line 30. By selecting a plurality of pixels 10 on a row-by-row basis, the signal voltage of the selected pixels 10 is read out and the signal charge is reset.

[0060] In the illustrated example, a feedback control line 28 and a sensitivity adjustment line 32 are further connected to the vertical scanning circuit 16. When the vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, a feedback loop is formed that negatively feeds back the output of the pixel 10. In addition, the vertical scanning circuit 16 can supply a predetermined voltage to the plurality of pixels 10 via the sensitivity adjustment line 32.

[0061] The imaging device 100 has vertical signal lines 18 provided for each column of pixels 10. A load circuit 19 is electrically connected to each vertical signal line 18. Each of the pixels 10 is electrically connected to a column signal processing circuit 20 via the corresponding vertical signal line 18.

[0062] The column signal processing circuits 20 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. A horizontal signal readout circuit 21 is electrically connected to the column signal processing circuits 20 provided corresponding to each column of the plurality of pixels 10. The horizontal signal readout circuit 21 sequentially reads out signals from the plurality of column signal processing circuits 20 to a horizontal common signal line 23.

[0063] As shown in FIG. 1 , the power supply wiring 22, the feedback line 25, and the vertical signal line 18 extend in the vertical direction in FIG. 1 , i.e., in the column direction of the pixels 10. Each of the feedback lines 25 and each of the vertical signal lines 18 provided for each column of the pixels 10 are connected to each of the pixels 10 arranged along the column direction. On the other hand, the accumulation control line 17, the reset signal line 26, the feedback control line 28, the address signal line 30, and the sensitivity adjustment line 32 extend, for example, in the row direction of the pixels 10. These signal lines are connected to each of the pixels 10 arranged along the row direction. Note that the accumulation control line 17 and the sensitivity adjustment line 32 may extend in the column direction of the pixels 10. The accumulation control line 17 and the sensitivity adjustment line 32 may also be connected to each of the pixels 10 arranged along the column direction.

[0064] In the configuration illustrated in FIG. 1 , an inverting amplifier 24 is provided corresponding to each column of pixels 10. The negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18, and a predetermined voltage Vref is supplied to the positive input terminal of the inverting amplifier 24. The voltage Vref is, for example, a positive voltage of 1 V or close to 1 V. The output terminal of the inverting amplifier 24 is connected to the pixel 10 connected to the negative input terminal of the inverting amplifier 24 via one of multiple feedback lines 25 provided corresponding to the multiple columns of pixels 10. The inverting amplifier 24 forms part of a feedback circuit that negatively feeds back the output from the pixel 10. The inverting amplifier 24 may also be referred to as a feedback amplifier.

[0065] 2 is a diagram showing an example of the circuit configuration of a pixel 10 included in the imaging device 100 according to this embodiment. In this embodiment, the multiple pixels 10 included in the imaging device 100 have the same configuration.

[0066] 2, the pixel 10 includes a photoelectric conversion unit 15 and a signal detection circuit SC. In the configuration illustrated in Fig. 2, the imaging device 100 includes a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC.

[0067] The photoelectric conversion unit 15 includes a transparent electrode 15a, a photoelectric conversion film 15b, and a pixel electrode 15c. The transparent electrode 15a of the photoelectric conversion unit 15 is connected to an accumulation control line 17. The pixel electrode 15c of the photoelectric conversion unit 15 is connected to a charge accumulation node 44. By controlling the potential of the transparent electrode 15a via the accumulation control line 17, charges of either polarity, positive charges (specifically, holes) or negative charges (specifically, electrons) generated in the photoelectric conversion film 15b by photoelectric conversion, can be collected in the pixel electrode 15c. When holes are used as signal charges, for example, the potential of the transparent electrode 15a can be set higher than that of the pixel electrode 15c. The following describes an example in which holes are used as signal charges. A voltage of, for example, about 10 V is applied to the transparent electrode 15a via the accumulation control line 17. As a result, signal charges are accumulated in the charge accumulation node 44. Note that electrons may also be used as signal charges.

[0068] The signal detection circuit SC includes a signal detection transistor 34 that amplifies and outputs a signal generated by the photoelectric conversion unit 15, and a first capacitive element 41. In the illustrated example, the signal detection circuit SC further includes a reset transistor 36, a feedback transistor 38, a second capacitive element 42 having a capacitance value smaller than that of the first capacitive element 41, and an address transistor 40. As described above, in this embodiment, each of the multiple pixels 10 has one or more capacitive elements therein. The first capacitive element 41 has a relatively large capacitance value, which can effectively reduce kTC noise, for example. Below, an example will be described in which an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as a transistor such as the signal detection transistor 34.

[0069] The gate of the signal detection transistor 34 is connected to the charge storage node 44. In other words, the gate of the signal detection transistor 34 is connected to the pixel electrode 15c. The drain of the signal detection transistor 34 is connected to the power supply line 22 as a source follower power supply, and the source is connected to the vertical signal line 18 via the address transistor 40. The signal detection transistor 34 and a load circuit 19 (see FIG. 1), which is not shown in FIG. 2, form a source follower circuit.

[0070] In the example shown in FIG. 2 , the address transistor 40 is connected between the source of the signal detection transistor 34 and the vertical signal line 18. The gate of the address transistor 40 is connected to the address signal line 30. When signal charge is accumulated in the charge storage node 44, a voltage corresponding to the amount of accumulated signal charge is applied to the gate of the signal detection transistor 34. The signal detection transistor 34 amplifies the voltage applied to this gate. When the address transistor 40 is turned on, the voltage amplified by the signal detection transistor 34 is selectively read out as a signal voltage. Note that the address transistor 40 may be connected between the drain of the signal detection transistor 34 and the power supply wiring 22. In other words, the drain of the signal detection transistor 34 may be connected to the power supply wiring 22 via the address transistor 40.

[0071] In the configuration illustrated in FIG. 2 , one of a pair of electrodes of the first capacitance element 41 is connected to a sensitivity adjustment line 32. A pad portion is connected to the sensitivity adjustment line 32, and the potential of the sensitivity adjustment line 32 is adjusted by a voltage applied to the pad portion. For example, when the imaging device 100 is in operation, the potential of the sensitivity adjustment line 32 is fixed to a constant potential such as 0 V. The sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44. The other of the pair of electrodes of the first capacitance element 41 is connected to one of the pair of electrodes of the second capacitance element 42. Hereinafter, a node including the connection point between the first capacitance element 41 and the second capacitance element 42 may be referred to as a reset drain node 46.

[0072] The other of the pair of electrodes of the second capacitance element 42 is connected to the charge storage node 44. That is, of the pair of electrodes of the second capacitance element 42, the electrode that is not connected to the reset drain node 46 is electrically connected to the pixel electrode 15c of the photoelectric conversion unit 15. In the example shown in FIG. 2, the reset transistor 36 is connected in parallel to the second capacitance element 42. The gate of the reset transistor 36 is connected to the reset signal line 26.

[0073] 2, pixel 10 includes a feedback transistor 38. As shown, one of the source and drain of feedback transistor 38 is connected to reset drain node 46. The other of the source and drain of feedback transistor 38 is connected to feedback line 25. The gate of feedback transistor 38 is connected to feedback control line 28.

[0074] [2. Pixel device structure] Next, an example of the device structure of the pixel 10 will be described with reference to FIG.

[0075] Fig. 3 is a schematic cross-sectional view of a pixel 10 included in the imaging device 100 according to the present embodiment. Note that in Fig. 3, the insulating layers included in the interlayer insulating layer 283, the transistor layer 282, and the wiring layer 284 are not shaded to indicate a cross section, in consideration of ease of viewing the drawing. The same applies to Figs. 6A to 10 described below.

[0076] The imaging device 100 according to this embodiment includes a plurality of pixels 10. Each of the plurality of pixels 10 includes a substrate 281, a transistor layer 282, an interlayer insulating layer 283, capacitance elements 201 and 202, a wiring layer 284, and a photoelectric conversion unit 15, as shown in FIG.

[0077] The photoelectric conversion section 15 includes a transparent electrode 15a, a photoelectric conversion film 15b, and a pixel electrode 15c. The photoelectric conversion film 15b is disposed between the transparent electrode 15a and the pixel electrode 15c.

[0078] The transparent electrode 15a is a film made of a metal oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), InGaZnO, InO, ZnO, AZO (Aluminum-doped Zinc Oxide), or GZO (Gallium-doped Zinc Oxide), an ultrathin metal film such as Ag, Au, or Al, or a film formed by depositing particulate or wire-shaped metal. The transparent electrode 15a is provided continuously across the plurality of pixels 10, but may also be provided separately for each pixel 10.

[0079] The photoelectric conversion film 15b is formed using a photoelectric conversion material that generates charges from incident light through photoelectric conversion. The photoelectric conversion material can be selected from organic and inorganic materials to obtain desired photoelectric conversion characteristics. For example, forming the photoelectric conversion film 15b using a material that can convert light with a wavelength of 400 nm or more and 800 nm or less into charges allows the imaging device 100 to function as a visible light sensor. Furthermore, forming the photoelectric conversion film 15b using a material that can convert light with a wavelength of 800 nm or more and 2000 nm or less into charges allows the imaging device 100 to function as a near-infrared sensor. The photoelectric conversion film 15b is provided continuously across multiple pixels 10, but may also be provided separately for each pixel 10.

[0080] The pixel electrodes 15c are films made of metal nitride such as TiN or TaN, or metal films made of Ag, Au, Al, Cu, W, Ti, Ta, etc. The pixel electrodes 15c are provided separately for each pixel 10.

[0081] The pixel electrodes 15c collect the electric charges generated by the photoelectric conversion film 15b through photoelectric conversion. A shield electrode may be formed around the pixel electrodes 15c to block the influence of the electric potential between adjacent pixel electrodes 15c.

[0082] The substrate 281 is, for example, a silicon substrate. The substrate 281 is not limited to a substrate that is entirely made of a semiconductor. For example, the substrate 281 may be an insulating substrate with a semiconductor layer provided on its surface. Here, a p-type silicon substrate is exemplified as the substrate 281.

[0083] A plurality of impurity regions are formed in the substrate 281. The impurity regions are regions in which, for example, n-type dopants are diffused. Each of the plurality of impurity regions functions as a source region or a drain region of each transistor included in the signal detection circuit SC.

[0084] A transistor layer 282 is disposed on the substrate 281. The transistor layer 282 includes a gate electrode and a gate insulating film of the transistor, contact vias connected to the gate electrode, the source region, and the drain region, respectively, and an interlayer insulating film covering the gate electrode, the gate insulating film, and the main surface of the substrate 281.

[0085] The gate electrode and the contact via are made of, for example, conductive polysilicon, but may also be made of a metal material such as Cu. The gate insulating film is formed using an insulating material such as SiO2, SiON, or SiN. The interlayer insulating film is formed using an insulating material such as TEOS (tetraethoxysilane), SiO2, SiON, or SiN. The interlayer insulating film is provided continuously across multiple pixels 10. The upper surface of the interlayer insulating film is planarized. The upper surface is the surface of the main surface of the interlayer insulating film on which the photoelectric conversion unit 15 is provided. Multiple contact vias are provided to penetrate the interlayer insulating film.

[0086] An interlayer insulating layer 283 is disposed on the transistor layer 282. The interlayer insulating layer 283 has a stacked structure of multiple insulating layers. For example, as shown in FIG. 3, the interlayer insulating layer 283 includes a lower insulating layer 283a and an upper insulating layer 283b. The lower insulating layer 283a and the upper insulating layer 283b each include one or more insulating layers. The lower insulating layer 283a is an example of a supporting insulating film that supports the capacitive elements 201 and 202. The upper insulating layer 283b is an example of a coated insulating film that covers the capacitive elements 201 and 202.

[0087] Each of the multiple insulating layers included in the interlayer insulating layer 283 is formed using an insulating material such as TEOS, SiO2, SiON, or SiN. Capacitor elements 201 and 202 are formed inside the interlayer insulating layer 283. That is, the capacitor elements 201 and 202 are each formed between the photoelectric conversion unit 15 and the substrate 281. The capacitor elements 201 and 202 are formed so as to be sandwiched between a lower insulating layer 283a and an upper insulating layer 283b. Note that the semiconductor device in the present disclosure includes, for example, the capacitor elements 201 and 202 and the interlayer insulating layer 283. The specific configurations of the capacitor elements 201 and 202 will be described later.

[0088] The wiring layer 284 includes a plurality of wirings, an interlayer insulating film covering the plurality of wirings, and via conductors connecting different wirings in the thickness direction. The pixel electrode 15c is provided on the top layer of the wiring layer 284. The wirings and via conductors are formed using a conductive material such as a metal such as Cu or conductive polysilicon. The interlayer insulating film is formed using an insulating material such as TEOS, SiO2, SiON, or SiN.

[0089] The number of wiring layers and insulating layers arranged in the wiring layer 284 is not limited to the number of layers illustrated in FIG. 3, but can be set arbitrarily.

[0090] [3. Two capacitive elements] Next, a description will be given of the specific configuration and electrical connection of the two capacitive elements 201 and 202. Note that the capacitive elements 201 and 202 correspond to, for example, the first capacitive element 41 and the second capacitive element 42 shown in FIG. 2, but are not limited to this.

[0091] [3-1.Configuration] Each of the capacitors 201 and 202 has a "metal-insulator-metal (MIM) structure" in which a dielectric or insulator is sandwiched between two electrodes formed of a conductive material such as a metal or a metal compound. The capacitor 201 is an example of a first capacitor, and includes a first electrode 220, a second electrode 230, and a dielectric layer 240. The capacitor 202 is an example of a second capacitor, and includes a second electrode 230, a third electrode 250, and an insulating layer 260.

[0092] In this embodiment, the first electrode 220, the second electrode 230, and the third electrode 250 are stacked in this order, and at least a portion of each electrode overlaps with each other in a planar view. Specifically, the first electrode 220, the dielectric layer 240, the second electrode 230, the insulating layer 260, and the third electrode 250 are stacked in this order, and at least a portion of each electrode overlaps with each other in a planar view. That is, the capacitive element 201 and the capacitive element 202 overlap with each other in a planar view.

[0093] The capacitive element 201 is a trench capacitor that includes at least one trench portion 210. The capacitive element 202 is a planar capacitor that does not include a trench portion.

[0094] The trench portion 210 is a part of the capacitive element 201, and is a portion formed in a groove or recess (i.e., a trench) formed in the interlayer insulating layer 283. Note that the trench refers to a portion where a part of the lower insulating layer 283a is removed by etching, and the shape thereof is not limited. The shape of the trench is, for example, a cylinder, a cone, a cube, a rectangular parallelepiped, etc.

[0095] A transistor layer 282 is formed on a substrate 281, a lower insulating layer 283a is formed on the transistor layer 282, and then the lower insulating layer 283a is etched to form at least one trench. A first electrode 220, a dielectric layer 240, and a second electrode 230 are formed in this order along the inner surface of the trench. Inside the trench, the first electrode 220 and the dielectric layer 240 are each formed with a substantially uniform film thickness. The second electrode 230 is formed so as to fill the trench. In other words, the capacitive element 201 extends three-dimensionally not only in a direction parallel to the major surface of the substrate 281 but also in the thickness direction of the substrate 281. This allows the capacitive element 201 to have a larger electrode area than a planar capacitor without a trench portion, thereby increasing the capacitance density per unit area.

[0096] In this embodiment, a contact via 271 formed in the transistor layer 282 is connected to the first electrode 220 of the capacitor element 201 in the trench portion 210. The contact via 271 is an example of a first contact plug. Note that a plurality of contact vias 271 may be formed in the trench portion 210 and connected to a plurality of transistors. The upper portion of the contact via 271 is exposed at the bottom of the trench. This allows contact with the first electrode 220 of the capacitor element 201.

[0097] The first electrode 220 is formed to cover a portion of the upper surface of the lower insulating layer 283a and the upper surface of the contact via 271. The first electrode 220 is formed by depositing a conductive material using a method with good film-forming properties, such as ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition), to coat the inner surface of the trench with a substantially uniform film thickness. The conductive material may be a metal nitride such as TiN or TaN, a metal film such as Ag, Au, Al, Cu, W, Ti, or Ta, or a transparent electrode such as ITO, IZO, InGaZnO, InO, ZnO, AZO, or GZO.

[0098] The first electrode 220 is patterned into a predetermined shape. A portion of the first electrode 220 is provided outside the trench. That is, the first electrode 220 includes a portion that is included in the trench portion 210 and a flat portion on the upper surface of the lower insulating layer 283a. The flat portion is provided, for example, parallel to the substrate 281.

[0099] The dielectric layer 240 is located between the first electrode 220 and the second electrode 230. For example, the dielectric layer 240 contacts the upper surface of the first electrode 220 and the lower surface of the second electrode 230. The dielectric layer 240 is patterned into a predetermined shape so as to cover the first electrode 220. For example, the dielectric layer 240 is formed by depositing a dielectric material using a method such as ALD or CVD in order to coat the upper surface of the first electrode 220 with a substantially uniform film thickness along the inner surface shape of the trench.

[0100] In the present embodiment, the dielectric layer 240 covers the entire upper surface of the first electrode 220. In other words, the first electrode 220 is completely covered by the dielectric layer 240, and no portion of the first electrode 220 protrudes from the dielectric layer 240 in plan view. The dielectric layer 240 has a non-overlapping portion 241 that does not overlap the first electrode 220 in plan view. The non-overlapping portion 241 is an example of a first non-overlapping portion, and is located on the upper surface of the lower insulating layer 283a.

[0101] In this embodiment, the dielectric constant of the dielectric layer 240 is greater than, for example, the dielectric constant of the insulating layer 260 of the capacitive element 202. For example, a so-called high-k material having a higher dielectric constant than SiO2 can be used as the dielectric material constituting the dielectric layer 240. The dielectric layer 240 can be made of a dielectric material such as SiN, SiON, AlO, Ta2O5, HfO, ZrO, or TiO. The dielectric constant of the dielectric layer 240 may be equal to the dielectric constant of the insulating layer 260. In other words, the dielectric layer 240 may be made of TEOS or SiO2.

[0102] The second electrode 230 covers the upper surface of the dielectric layer 240. The second electrode 230, together with the dielectric layer 240, is patterned into a predetermined shape by removing a portion thereof by etching so that the second electrode 230 is larger than the first electrode 220. The second electrode 230 and the dielectric layer 240 are patterned using, for example, the same mask. As a result, the shape and size of the second electrode 230 are approximately the same as the shape and size of the dielectric layer 240 in a planar view. Note that the second electrode 230 may be smaller than the dielectric layer 240. Alternatively, the second electrode 230 may be larger than the dielectric layer 240 and completely cover the dielectric layer 240.

[0103] The second electrode 230 has a non-overlapping portion 231 that does not overlap with the first electrode 220 in a planar view. The non-overlapping portion 231 is an example of a third non-overlapping portion, and does not overlap with either the insulating layer 260 or the third electrode 250 in a planar view. The non-overlapping portion 231 overlaps with the non-overlapping portion 241 of the dielectric layer 240 in a planar view.

[0104] 3, the interlayer insulating layer 283 is provided with a contact via 272 connected to the second electrode 230 at the non-overlapping portion 231. The contact via 272 is an example of a second contact plug. The contact via 272 penetrates the upper insulating layer 283b.

[0105] The second electrode 230 can be formed using the same material and film formation method as the first electrode 220. The second electrode 230 is formed so as to close the trench opening, i.e., to fill the trench. This can suppress steps in the insulating layer 260 formed on the second electrode 230. To achieve this, the second electrode 230 has, for example, a stacked structure of a first conductive film and a second conductive film. Specifically, a first conductive film having a thickness sufficient to close the trench opening is formed using a film formation method with good film coverage, such as an ALD method or a CVD method, and then a second conductive film is formed using a film formation method with poor film coverage, such as sputtering. This results in the second electrode 230 having a stacked structure. Note that the second electrode 230 may have a single-layer structure. The second electrode 230 may also be formed using a conductive material different from that of the first electrode 220.

[0106] The insulating layer 260 is located between the second electrode 230 and the third electrode 250. For example, the insulating layer 260 contacts the upper surface of the second electrode 230 and the lower surface of the third electrode 250. The insulating layer 260 is patterned into a predetermined shape so as to cover the second electrode 230. In this embodiment, the insulating layer 260 is formed in a pattern wider than the overlapping portion of at least the first electrode 220, the dielectric layer 240, and the second electrode 230 in a planar view so as not to damage the capacitive element 201 formed by the first electrode 220, the dielectric layer 240, and the second electrode 230. For example, the insulating layer 260 is provided so as to overlap at least the trench portion 210 in a planar view. The insulating layer 260 has a non-overlapping portion 261 that does not overlap the second electrode 230 in a planar view. The non-overlapping portion 261 is an example of a second non-overlapping portion and is located on the upper surface of the lower insulating layer 283a. That is, the non-overlapping portion 261 of the insulating layer 260 is located at the same height as the non-overlapping portion 241 of the dielectric layer 240 in the thickness direction.

[0107] In this embodiment, the dielectric constant of the insulating layer 260 is equal to or greater than the dielectric constant of the upper insulating layer 283b. Specifically, the insulating layer 260 is formed using a dielectric material with a high dielectric constant, such as SiN, SiON, AlO, Ta2O5, HfO, ZrO, or TiO. Alternatively, the insulating layer 260 may be formed using an insulating material with a low dielectric constant, such as TEOS or SiO2. That is, the insulating layer 260 may be formed using the same material as the dielectric layer 240 or the same material as the upper insulating layer 283b. The insulating layer 260 can be formed using a dielectric or insulating material by a sputtering method, an ALD method, a CVD method, or the like.

[0108] The third electrode 250 covers the upper surface of the insulating layer 260. The third electrode 250 and the insulating layer 260 are patterned into a predetermined shape by removing a portion thereof by etching so that the third electrode 250 is larger than the second electrode 230. The third electrode 250 and the insulating layer 260 are patterned using, for example, the same mask. As a result, the shape and size of the third electrode 250 are approximately the same as the shape and size of the insulating layer 260 in a plan view. Note that the third electrode 250 may be smaller than the insulating layer 260. Alternatively, the third electrode 250 may be larger than the insulating layer 260 and completely cover the insulating layer 260.

[0109] When the third electrode 250 comes into contact with the contact via 272 of the second electrode 230, the second electrode 230 and the third electrode 250 are electrically connected. Therefore, the third electrode 250 does not cover the second electrode 230 in the vicinity of the contact via 272 of the second electrode 230. In other words, the third electrode 250 is wider than the first electrode 220 and narrower than the second electrode 230 in a plan view in the vicinity of the contact via 272.

[0110] The third electrode 250 can be made of a metal nitride such as TiN or TaN, a metal film such as Ag, Au, Al, Cu, W, Ti, or Ta, or a transparent electrode such as ITO, IZO, InGaZnO, InO, ZnO, AZO, or GZO, similar to the first electrode 220 and the second electrode 230. The film formation method can be an ALD method, a CVD method, a sputtering method, or the like.

[0111] The third electrode 250 has a non-overlapping portion 251 that does not overlap with any of the first electrode 220, the dielectric layer 240, and the second electrode 230 in a planar view. The non-overlapping portion 251 is an example of a fourth non-overlapping portion. The non-overlapping portion 251 overlaps with the non-overlapping portion 261 of the insulating layer 260 in a planar view. The non-overlapping portion 251 is located at the same height as the non-overlapping portion 231 of the second electrode 230 in the thickness direction.

[0112] 3, the interlayer insulating layer 283 is provided with a contact via 273 connected to the third electrode 250 at the non-overlapping portion 251. The contact via 273 is an example of a third contact plug. The contact via 273 penetrates the upper insulating layer 283b.

[0113] With the above configuration, the capacitance element 201 has the trench portion 210, thereby increasing the capacitance density per unit area. Furthermore, since the capacitance element 202 is stacked on the capacitance element 201, it is possible to suppress an increase in the area occupied by the capacitance elements 201 and 202 in a plan view, while allowing the capacitance elements 201 and 202 to exhibit a desired function according to the connection relationship between them. In other words, the characteristics that the two capacitance elements 201 and 202 can exhibit can be selected by electrical connection to each electrode.

[0114] [3-2. Electrical Connections] Next, the electrical connection between the two capacitive elements 201 and 202 will be described with reference to Table 1, FIGS. 4A, 4B, and 5. FIG.

[0115] Table 1 shows examples of voltages supplied to the two capacitance elements 201 and 202 included in the image pickup device 100 according to this embodiment. Figures 4A, 4B, and 5 are diagrams showing first to third examples of electrical connections between the two capacitance elements 201 and 202 included in the image pickup device 100 according to this embodiment, respectively. [Table 1]

[0116] For example, as shown in Table 1, 0 V is applied to the first electrode 220, 3 V is applied to the third electrode 250, and the second electrode 230 is set to a floating state in which no potential is supplied. This allows the capacitance element 201 and the capacitance element 202 to be connected in series, as shown in Fig. 4A. This allows the semiconductor device including the capacitance elements 201 and 202 connected in series to be used as a capacitor with excellent leakage current characteristics.

[0117] Furthermore, as shown in Table 1, 3 V is applied to the first electrode 220, 0 V is applied to the second electrode 230, and 3 V is applied to the third electrode 250. That is, the same potential is supplied to the first electrode 220 and the third electrode 250, and they are electrically connected to each other. This allows the capacitance element 201 and the capacitance element 202 to be connected in parallel, as shown in FIG. 4B. This allows a semiconductor device including the capacitance elements 201 and 202 connected in parallel to be used as a capacitor with excellent capacitance density per unit area.

[0118] Furthermore, as shown in Table 1, 3 V is applied to the first electrode 220, 0 V is applied to the second electrode 230, and 2 V is applied to the third electrode 250. In other words, the first electrode 220 and the third electrode 250 are not electrically connected to each other. This allows the capacitive element 201 and the capacitive element 202 to be used independently as separate capacitors, as shown in FIG. 5. In this embodiment, the second electrode 230 is common to the two capacitive elements 201 and 202, so the circuit shown in FIG. 5 is essentially equivalent to the circuit shown in FIG. 4A. Even in this case, each of the capacitive elements can have its own function, as with the first capacitive element 41 and the second capacitive element 42 shown in FIG. 2.

[0119] Note that the voltage examples shown in Table 1 are merely examples, and the supplied potentials are not limited to 3 V, 2 V, or 0 V. Furthermore, when the capacitive element 201 and the capacitive element 202 are used as separate capacitors, the potentials applied to the first electrode 220 and the third electrode 250 may be different potentials or the same potential.

[0120] [3-3. Contact Via] Next, an example of electrical connection to each of the capacitive elements 201 and 202 will be described with reference to FIGS. 6A and 6B.

[0121] 6A and 6B are cross-sectional views showing first and second examples of the connection of contact vias to two capacitance elements 201 and 202 included in imaging device 100 according to this embodiment. Note that although Fig. 6A and Fig. 6B show contact vias to non-overlapping portion 231 of second electrode 230, the same applies to contact vias to non-overlapping portion 251 of third electrode 250.

[0122] 6A, a portion of the upper insulating layer 283b covering the capacitive elements 201 and 202 is removed by etching, and a metal material is deposited to form the contact via 272. At this time, by using an electrode material for the second electrode 230 that has a lower etching rate than the etching rate of the upper insulating layer 283b, or by selecting an etching gas with a high etching selectivity, the contact via 272 can be brought into contact with the second electrode 230 over a wide surface area at the bottom thereof without penetrating the second electrode 230. This reduces poor contact with the electrode.

[0123] 6A, the contact via 272 is in contact only with the top surface of the second electrode 230, but part of the contact via 272 may be embedded in the second electrode 230. This allows the contact via 272 to be in contact with the second electrode 230 not only on its bottom surface but also on part of its side surface, thereby further reducing poor contact.

[0124] Alternatively, as shown in FIG. 6B , a contact via 272A for the second electrode 230 may be formed simultaneously with the formation of a contact via 275 that reaches the transistor layer 282. The interlayer insulating layer 283 and the second electrode 230 are made of different materials, and therefore have different etching rates. Specifically, the etching rate of the interlayer insulating layer 283 is higher than the etching rate of the second electrode 230. Therefore, when the interlayer insulating layer 283 is etched until it reaches the transistor layer 282 in a portion where the second electrode 230 is not present, it does not reach the transistor layer 282 in a portion where the second electrode 230 is present. As a result, as shown in FIG. 6B , a contact via 272A that penetrates the non-overlapping portion 231 of the second electrode 230 is formed. Furthermore, by simultaneously processing the third electrode 250, a contact via that penetrates the non-overlapping portion 251 of the third electrode 250 is formed.

[0125] This allows multiple contact vias to be formed simultaneously, reducing the number of etching steps, and reducing the likelihood of misalignment of the mask, resulting in a highly reliable imaging device 100.

[0126] Note that the contact via for the second electrode 230 and the contact via for the third electrode 250 do not have to be formed at the same time. For example, one contact via may pass through the non-overlapping portions of the corresponding electrodes, while the other contact via may not pass through the non-overlapping portions of the corresponding electrodes.

[0127] [4. Modifications] Next, modified examples of the imaging device according to the embodiment will be described. The modified examples shown below differ from the embodiment in the cross-sectional structure of the pixels, but have the same circuit configuration as the embodiment. The following description will focus on the differences from the embodiment, and the description of the commonalities will be omitted or simplified.

[0128] [4-1. Variation 1] For example, although the capacitive element 202 is a planar capacitor in the embodiment, it may be a trench capacitor. Fig. 7 is a cross-sectional view of a pixel 10B included in an imaging device according to Modification 1. As shown in Fig. 7, the capacitive element 202B is a trench capacitor. The capacitive element 202B has a second electrode 230B, a third electrode 250B, and an insulating layer 260B.

[0129] The second electrode 230B and the insulating layer 260B are each formed with a substantially uniform thickness inside the trench. The third electrode 250B is formed so as to fill the trench. The second electrode 230B, the insulating layer 260B, and the third electrode 250B are each formed using the ALD method or the CVD method, which have good film-covering properties. This allows the capacitive element 202B to also have a trench portion, thereby increasing the capacitance density per unit area.

[0130] In this modification, the trench portion of the capacitive element 202B is located at a position overlapping the trench portion of the capacitive element 201 in a plan view. That is, the trench portions of the capacitive elements 201 and 202B are formed in the same trench formed in the lower insulating layer 283a, but this is not limiting. The trench portion of the capacitive element 202B may be located at a position not overlapping the trench portion of the capacitive element 201 in a plan view.

[0131] [4-2. Variation 2] Furthermore, in the embodiment, the capacitive element 201 includes one trench portion 210, but the capacitive element 201 may include two or more trench portions. Fig. 8 is a cross-sectional view of a pixel 10C included in an imaging device according to Modification 2. As shown in Fig. 8, the capacitive element 201C includes two trench portions 210 and 211.

[0132] The trench portion 211 can be formed in the same manner as the trench portion 210. There are no particular limitations on the shape, size, and number of the trench portion 211. As in the first modification, the capacitive element 202 may also include a plurality of trench portions.

[0133] [4-3. Variation 3] Furthermore, in the embodiment, the two capacitive elements 201 and 202 share the second electrode 230, but the second electrode 230 does not have to be shared. FIG. 9 is a cross-sectional view of a pixel 10D included in an imaging device according to Modification Example 3. As shown in FIG. 9, the imaging device includes an insulating layer 290 located between the capacitive element 201 and the capacitive element 202D. The capacitive element 202D also includes a fourth electrode 230D, a third electrode 250, and an insulating layer 260.

[0134] The insulating layer 290 is located between the second electrode 230 and the fourth electrode 230D. For example, the insulating layer 290 contacts the upper surface of the second electrode 230 and the lower surface of the fourth electrode 230D. The insulating layer 290 is patterned into a predetermined shape so as to cover the second electrode 230. In this embodiment, the insulating layer 290 is formed in a pattern wider than the overlapping portion of at least the first electrode 220, the dielectric layer 240, and the second electrode 230 in a planar view so as not to damage the capacitive element 201 formed by the first electrode 220, the dielectric layer 240, and the second electrode 230. For example, the insulating layer 290 is provided so as to overlap at least the trench portion 210 in a planar view. The insulating layer 290 has a non-overlapping portion 291 that does not overlap the second electrode 230 in a planar view. The non-overlapping portion 291 is located on the upper surface of the lower insulating layer 283a. That is, the non-overlapping portion 291 of the insulating layer 290 is located at the same height as the non-overlapping portion 241 of the dielectric layer 240 and the non-overlapping portion 261 of the insulating layer 260 in the thickness direction.

[0135] The fourth electrode 230D covers the upper surface of the insulating layer 290. The fourth electrode 230D is patterned into a predetermined shape together with the insulating layer 290 by removing a portion thereof by etching so that the fourth electrode 230D is larger than the second electrode 230. The fourth electrode 230D and the insulating layer 290 are patterned using, for example, the same mask. As a result, the shape and size of the fourth electrode 230D are approximately the same as those of the insulating layer 290 in a plan view. Note that the fourth electrode 230D may be smaller than the insulating layer 290. Alternatively, the fourth electrode 230D may be larger than the insulating layer 290 and may completely cover the insulating layer 290.

[0136] When the fourth electrode 230D comes into contact with the contact via 272 of the second electrode 230, the second electrode 230 and the fourth electrode 230D are electrically connected. For this reason, the fourth electrode 230D is patterned so as not to cover a portion of the second electrode 230.

[0137] The fourth electrode 230D is formed using the same material as the second electrode 230. The fourth electrode 230D can be formed by an ALD method, a CVD method, a sputtering method, or the like.

[0138] The fourth electrode 230D has a non-overlapping portion 231D that does not overlap with any of the first electrode 220, the dielectric layer 240, and the second electrode 230 in a plan view. The non-overlapping portion 231D of the fourth electrode 230D is located at the same height as the non-overlapping portion 251 of the third electrode 250 and the non-overlapping portion 231 of the second electrode 230 in the thickness direction.

[0139] 9, the interlayer insulating layer 283 is provided with a contact via 274 connected to the fourth electrode 230D at the non-overlapping portion 231D. The contact via 274 penetrates the upper insulating layer 283b. This allows different potentials to be applied independently to the second electrode 230 and the fourth electrode 230D. This makes it easy to make the two capacitive elements 201 and 202D function as separate elements.

[0140] In the cross section shown in Figure 9, the non-overlapping portion 251 of the third electrode 250 is shown as being separated from the portion that constitutes the capacitive element 202D, but in reality, it is connected to the portion that constitutes the capacitive element 202D in a portion that is not shown.

[0141] In this modification, when the capacitive element 201 and the capacitive element 202D are connected in series, for example, the second electrode 230 and the fourth electrode 230D are electrically connected, and the first electrode 220 and the third electrode 250 are not electrically connected. Alternatively, when the capacitive element 201 and the capacitive element 202D are connected in series, for example, the first electrode 220 and the third electrode 250 may be electrically connected, and the second electrode 230 and the fourth electrode 230D may not be electrically connected.

[0142] Furthermore, when the capacitive element 201 and the capacitive element 202D are connected in parallel, for example, the second electrode 230 and the fourth electrode 230D are electrically connected, and the first electrode 220 and the third electrode 250 are electrically connected. Alternatively, when the capacitive element 201 and the capacitive element 202D are connected in parallel, for example, the second electrode 230 and the third electrode 250 may be electrically connected, and the first electrode 220 and the fourth electrode 230D may be electrically connected.

[0143] Furthermore, when the capacitive element 201 and the capacitive element 202D are made to function as separate elements, for example, the first electrode 220, the second electrode 230, the third electrode 250, and the fourth electrode 230D are not electrically connected to one another. Depending on the application, the second electrode 230 and the third electrode 250 may be electrically connected, or the second electrode 230 and the fourth electrode 230D may be electrically connected.

[0144] [4-4. Variation 4] In addition, in the embodiment, the photoelectric conversion unit 15 is provided above the substrate 281, but it may be provided inside the substrate 281. In other words, the imaging device 100 may be a back-illuminated CMOS image sensor in which the photoelectric conversion unit 15E is formed on the substrate 281.

[0145] 10 is a cross-sectional view of a pixel 10E included in an imaging device according to Modification 4. As shown in FIG. 10, a photoelectric conversion unit 15E is provided in a substrate 281. The photoelectric conversion unit 15E is, for example, a photodiode. The photodiode is, for example, a pn diode having a pn junction, and is formed by an impurity region or the like formed in the substrate 281. In this modification, light is incident from the back surface of the substrate 281, i.e., the surface opposite to the surface on which the capacitive elements 201 and 202 are formed, and photoelectric conversion is performed by the photoelectric conversion unit 15E.

[0146] In this modification, instead of the capacitive elements 201 and 202, the capacitive element structures shown in each of the modifications 1 to 3 may be applied.

[0147] (Other embodiments) Although the semiconductor device or imaging device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0148] For example, the contact via 271 contacts the first electrode 220 at the bottom surface of the trench portion 210, but this is not limiting. For example, the contact via 271 may contact a flat portion of the first electrode 220. Alternatively, a wiring may be provided that covers the upper surface of the contact via 271, and an end of the wiring may contact the first electrode 220 on the side surface of the trench portion 210. In other words, the contact plug electrically connected to the trench portion 210 may include a contact via and a wiring.

[0149] Also, for example, the dielectric layer 240 may not have the non-overlapping portion 241. In this case, the non-overlapping portion 231 of the second electrode 230 is provided on the upper surface of the lower insulating layer 283a. Also, the insulating layer 260 may not have the non-overlapping portion 261. In this case, the non-overlapping portion 251 of the third electrode 250 is provided on the upper surface of the lower insulating layer 283a.

[0150] Furthermore, for example, the dielectric layer 240 may be an insulating film such as a silicon oxide film or a silicon nitride film, instead of a thin film made of a high-k material.

[0151] Furthermore, for example, the semiconductor device according to the present disclosure may be provided in a storage device having a memory array, rather than in an imaging device.

[0152] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0153] The present disclosure can be used in, for example, image sensors, digital cameras, medical cameras, robot cameras, security cameras, and vehicle-mounted cameras. [Explanation of symbols]

[0154] 10, 10B, 10C, 10D, 10E pixels 15, 15E Photoelectric conversion unit 15a transparent electrode 15b Photoelectric conversion film 15c Pixel electrode 16 Vertical scanning circuit 17 Storage control line 18 Vertical signal line 19 Load circuit 20 Column signal processing circuit 21 Horizontal signal readout circuit 22 Power wiring 23 Horizontal common signal line 24 Inverting amplifier 25 Feedback Line 26 Reset signal line 28 Feedback control line 30 Address signal line 32 Sensitivity adjustment line 34 Signal detection transistor 36 Reset transistor 38 Feedback Transistor 40 Address transistor 41 first capacitance element 42 second capacitance element 44 Charge storage node 46 Reset drain node 100 Imaging device 201, 201C, 202, 202B, 202D Capacitive elements 210, 211 Trench section 220 1st electrode 230, 230B 2nd electrode 230D 4th electrode 231, 231D, 241, 251, 261, 291 Non-overlapping part 240 dielectric layer 250, 250B 3rd electrode 260, 260B, 290 insulating layer 271, 272, 272A, 273, 274, 275 Contact vias 281 Circuit Board 282 transistor layer 283 Interlayer Insulation Layer 283a Lower insulating layer 283b Upper insulating layer 284 wiring layer FC feedback circuit RA pixel area SC signal detection circuit

Claims

1. A semiconductor device, a first capacitance element including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; a second capacitance element including a third electrode and an insulating layer located between the second electrode and the third electrode; Equipped with the first capacitive element includes at least one first trench portion; the first electrode, the second electrode, and the third electrode are stacked in this order; at least a portion of the first electrode, at least a portion of the second electrode, and at least a portion of the third electrode overlap with each other in a plan view; the dielectric layer includes a first non-overlapping portion that does not overlap the first electrode in a plan view, the insulating layer includes a second non-overlapping portion that does not overlap the second electrode in a plan view; the first non-overlapping portion is located at the same height as the second non-overlapping portion in a thickness direction of the semiconductor device. Semiconductor device.

2. further comprising a first contact plug connected to the first electrode in the at least one first trench portion. The semiconductor device according to claim 1 .

3. the first electrode has two surfaces; the surface of the two surfaces that is closer to the dielectric layer is entirely covered with the dielectric layer; 3. The semiconductor device according to claim 1.

4. A semiconductor device, a first capacitance element including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; a second capacitance element including a third electrode and an insulating layer located between the second electrode and the third electrode; Equipped with the first capacitive element includes at least one first trench portion; the first electrode, the second electrode, and the third electrode are stacked in this order; at least a portion of the first electrode, at least a portion of the second electrode, and at least a portion of the third electrode overlap with each other in a plan view; the second electrode includes a third non-overlapping portion that does not overlap with either the insulating layer or the third electrode in a plan view; the third electrode includes a fourth non-overlapping portion that does not overlap with any of the first electrode, the dielectric layer, and the second electrode in a plan view; the third non-overlapping portion is located at the same height as the fourth non-overlapping portion in the thickness direction of the semiconductor device. Semiconductor device.

5. moreover, a second contact plug connected to the second electrode in the third non-overlapping portion; a third contact plug connected to the third electrode at the fourth non-overlapping portion. The semiconductor device according to claim 4 .

6. A first capacitive element including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; a second capacitance element including a third electrode and an insulating layer located between the second electrode and the third electrode; A second contact plug; Equipped with the first capacitive element includes at least one first trench portion; the first electrode, the second electrode, and the third electrode are stacked in this order; at least a portion of the first electrode, at least a portion of the second electrode, and at least a portion of the third electrode overlap with each other in a plan view; the second electrode includes a third non-overlapping portion that does not overlap with either the insulating layer or the third electrode in a plan view; the second contact plug is connected to the second electrode at the third non-overlapping portion; the second contact plug penetrates the third non-overlapping portion. Semiconductor device.

7. The dielectric constant of the dielectric layer is equal to or greater than the dielectric constant of the insulating layer. The semiconductor device according to claim 1 .

8. further comprising an insulating film covering the second capacitance element; the dielectric constant of the insulating layer is equal to or greater than the dielectric constant of the insulating coating film; The semiconductor device according to claim 1 .

9. the second capacitive element includes the second electrode; The semiconductor device according to claim 1 .

10. the second capacitance element further includes a fourth electrode located between the second electrode and the insulating layer; The semiconductor device according to claim 1 .

11. The first electrode is electrically connected to the third electrode. The semiconductor device according to claim 1 .

12. No potential is applied to the second electrode. The semiconductor device according to claim 1 .

13. The first electrode is not electrically connected to the third electrode. The semiconductor device according to claim 1 .

14. the second capacitive element includes at least one second trench portion; The semiconductor device according to claim 1 .

15. In a plan view, the first trench portion overlaps with the second trench portion. The semiconductor device according to claim 14.

16. An imaging device comprising the semiconductor device according to claim 1 .

Images