Light-emitting device

Abstract

To protect a light emitting stacked structure during transfer process in manufacturing a light-emitting package.SOLUTION: A light emitting package 110 includes: a first LED sub-unit; a second LED sub-unit disposed on the first LED sub-unit; a third LED sub-unit disposed on the second LED sub-unit; a plurality of connection electrodes electrically connected to at least one of the first, second, and third LED sub-units, the connection electrodes having side surfaces and covering a side surface of at least one of the first, second, and third LED sub-units; a first passivation layer surrounding at least the side surfaces of the connection electrodes; an insulating layer 11p having first and second opposed surfaces, the first surface facing the LED sub-units; and a first electrode 11pc disposed on the second surface of the insulating layer and connected to at least one of the connection electrodes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Exemplary embodiments of the present invention relate to a light-emitting chip for a display and a manufacturing method thereof, and more particularly to a micro light-emitting chip with a stacked structure and a manufacturing method thereof. [Background technology]

[0002] Light-emitting diodes (LEDs), inorganic light sources, are used in a variety of technological fields, including displays, automotive lamps, and general lighting. Light-emitting diodes have advantages such as long life, low power consumption, and high response, and are rapidly becoming popular as replacements for existing light sources.

[0003] Light-emitting diodes (LEDs) have been used primarily as backlight sources for display devices, but recently microLED displays have been developed that can directly display images using light-emitting diodes.

[0004] Generally, display devices realize various colors by mixing blue, green, and red light. The display device includes pixels having sub-pixels corresponding to the blue, green, and red colors, and the color of a pixel is determined based on the color of the sub-pixel, allowing images to be displayed by combining pixels.

[0005] Because LEDs can emit a variety of colors depending on their constituent materials, display devices typically use individual LED chips emitting blue, green, and red light, arranged on a two-dimensional plane. However, if one LED chip is provided for each subpixel, the number of LED chips required to form a display device can be extremely large, for example, hundreds of thousands or even millions of chips, making the assembly process time-consuming and labor-intensive. Furthermore, because the subpixels are arranged on a two-dimensional plane, a single pixel, including the subpixels for blue, green, and red light, requires a relatively large area. Reducing the luminous area of ​​each subpixel results in a degradation of the subpixel's brightness.

[0006] Furthermore, micro LEDs typically have a very small surface area of ​​approximately 10,000 square microns or less, which presents various technical challenges. For example, an array of micro LEDs may be formed on a substrate, and the substrate may be cut to separate the micro LEDs into individual micro LED chips. The micro LED chips may then be mounted on another substrate, such as a printed circuit board, using various transfer techniques. However, during these transfer steps, each micro LED chip is generally difficult to handle due to its small size and fragile structure. Furthermore, the electrodes formed on a target substrate, such as a display device, are typically spaced apart at a pitch equivalent to the electrode pitch of a conventional pixel, where multiple subpixels are arranged on a two-dimensional plane.

[0007] The above information disclosed in this "Background" section is intended solely to provide an understanding of the background of the concept of the present invention, and therefore may include information that does not constitute prior art. Summary of the Invention [Problem to be solved by the invention]

[0008] A light emitting chip constructed in accordance with the principles and some exemplary embodiments of the present invention can protect the light emitting stack during various transfer processes.

[0009] Light-emitting chips, such as micro LEDs, constructed in accordance with the principles of the present invention and some exemplary embodiments thereof, and displays using the same, have a simplified structure and can reduce the time required for the assembly process during manufacturing.

[0010] Light emitting packages, such as micro LEDs, constructed in accordance with the principles of the present invention and some exemplary embodiments can be mounted in conventional display devices with reinforced internal structures for ease of handling and transportation.

[0011] Light emitting packages, e.g., micro LEDs, constructed in accordance with the principles of the present invention and some exemplary embodiments have a reinforced structure created by not removing a substrate of the light emitting stack, such as the growth substrate of one of the LED stacks.

[0012] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the inventive concepts. [Means for solving the problem]

[0013] A light-emitting package according to an exemplary embodiment includes a first LED subunit, a second LED subunit arranged on the first LED subunit, a third LED subunit arranged on the second LED subunit, a plurality of connection electrodes electrically connected to at least one of the first, second, and third LED subunits, the plurality of connection electrodes having side surfaces and arranged to cover the side surfaces of at least one of the first, second, and third LED subunits, a first passivation layer surrounding at least the side surfaces of the connection electrodes, an insulating layer having a first surface and a second surface opposing each other, the first surface facing the LED subunit, and a first electrode arranged on the second surface of the insulating layer and connected to at least one of the connection electrodes.

[0014] The plurality of connection electrodes may overlap at least one of the first, second and third LED subunits.

[0015] The device may further include a substrate on which the first LED subunit is disposed, and the substrate may be exposed from the first passivation layer.

[0016] The first passivation layer may be disposed between the plurality of connection electrodes.

[0017] The first electrode may include a plurality of contact electrodes corresponding to one of the plurality of connection electrodes, and the plurality of contact electrodes may be spaced apart from one another at a first pitch, and the plurality of connection electrodes may be spaced apart from one another at a second pitch, and the first pitch may be greater than the second pitch.

[0018] The first LED subunit may extend vertically along a first direction, and the first electrode may extend away from the first LED subunit along the first direction.

[0019] The light emitting package may further include an auxiliary electrode disposed on the second surface of the insulating layer, and a second passivation layer surrounding at least a side surface of the auxiliary electrode and spaced apart from the first passivation layer.

[0020] The light emitting package may further include a substrate having a top surface and a side surface, the substrate having the first LED subunit disposed thereon, an auxiliary electrode disposed on the second surface of the insulating layer, and a second passivation layer surrounding at least a side surface of the auxiliary electrode, A silicon layer may cover the top and sides of the substrate.

[0021] The light emitting package may further include a substrate on which the first LED subunit is disposed. The first LED subunit may include a first light emitting stack, the second LED subunit may include a second light emitting stack, and the third LED subunit may include a third light emitting stack. The first, second, and third light emitting stacks may have successively smaller overlapping areas with the substrate, and at least one of the light emitting stacks may include a micro LED having a surface area of ​​about 10,000 square microns or less.

[0022] The first passivation layer may include at least one of a black epoxy molding compound and a polyimide film, and the first passivation layer may cover an upper surface of the third LED subunit.

[0023] The light emitting package may further include a second passivation layer disposed between the third LED subunit and the plurality of connecting electrodes.

[0024] At least one of the plurality of connection electrodes may cover a part of the side surface and a part of the top surface of the second passivation layer.

[0025] The first passivation layer may be disposed between the plurality of connection electrodes.

[0026] The first passivation layer may be in contact with the second passivation layer between the plurality of connection electrodes.

[0027] The first passivation layer and the second passivation layer may comprise the same material.

[0028] The first electrode may include a plurality of contact electrodes corresponding to one of the plurality of connection electrodes, and the plurality of contact electrodes may be spaced apart from one another at a first pitch, and the plurality of connection electrodes may be spaced apart from one another at a second pitch, the first pitch being greater than the second pitch.

[0029] The light emitting package may further include a substrate on which the first LED subunit is disposed, wherein an angle defined between a side surface of the second passivation layer and a top surface of the substrate may be less than approximately 80°.

[0030] The first passivation layer may expose a top surface of the substrate.

[0031] The light emitting package includes an auxiliary electrode having a side surface formed on the second surface of the insulating layer, and a third passivation layer surrounding at least a side surface of the auxiliary electrode and spaced apart from the first passivation layer and the second passivation layer. It may further include:

[0032] The light emitting package may further include a substrate having a top surface and a side surface on which the first LED subunit is disposed, an auxiliary electrode disposed on the second surface of the insulating layer, and a third passivation layer substantially surrounding the auxiliary electrode, and the first passivation layer may cover at least a portion of the top surface and side surface of the substrate.

[0033] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. [Brief explanation of the drawings]

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and, together with the description, serve to explain the concepts of the invention.

[0035] [Figure 1] 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with an exemplary embodiment of the present invention. [Figure 2] 1 is a schematic cross-sectional view of a light emitting stack constructed in accordance with an exemplary embodiment. [Figure 3A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 3B] 3B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 3A according to an exemplary embodiment. [Figure 4A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 4B] 4B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 4A according to an exemplary embodiment. [Figure 5A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 5B]5B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 5A according to an exemplary embodiment. [Figure 6A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 6B] 6B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 6A according to an exemplary embodiment. [Figure 7A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 7B] 7B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 7A, according to an exemplary embodiment. [Figure 8A] 1A to 1C are plan views illustrating a manufacturing process of a light-emitting chip according to an exemplary embodiment. [Figure 8B] 8B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 8A, according to an exemplary embodiment. [Figure 9A] 1 is a schematic plan view of a light-emitting chip configured in accordance with an exemplary embodiment; [Figure 9B] 9B is a schematic cross-sectional view taken along line AA' of FIG. 9A. [Figure 9C] 9B is a schematic cross-sectional view taken along line BB' of FIG. 9A. [Figure 10] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 11] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 12] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 13] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 14] 2A to 2C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to an exemplary embodiment. [Figure 15] 1 is a schematic bottom view of a light emitting module according to an exemplary embodiment showing the basic structure; [Figure 16] 10 is a schematic cross-sectional view of a light emitting package according to another exemplary embodiment. [Figure 17] 10 is a schematic cross-sectional view of a light emitting package according to yet another exemplary embodiment. [Figure 18] 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with another exemplary embodiment of the present invention. [Figure 19A] 10A to 10C are plan views illustrating a manufacturing process of a light-emitting chip according to another exemplary embodiment. [Figure 19B] 19B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 19A according to another exemplary embodiment. [Figure 20A] 10A to 10C are plan views illustrating a manufacturing process of a light-emitting chip according to another exemplary embodiment. [Figure 20B] 20B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 20A according to another exemplary embodiment. [Figure 21] 20A-20C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 18 according to another exemplary embodiment. [Figure 22] 20A-20C are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 18 according to another exemplary embodiment. [Figure 23] 10 is a schematic cross-sectional view of a light emitting package according to yet another exemplary embodiment. [Figure 24] 10 is a schematic cross-sectional view of a light emitting package according to yet another exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0036] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable terms that are non-limiting examples of apparatus or methods that employ one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various exemplary embodiments. Furthermore, various exemplary embodiments may differ, but are not necessarily exclusive. For example, the particular shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0037] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing illustrative features of various details of some of the ways in which the concepts of the present invention may be actually practiced. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be combined, separated, interchanged, and / or rearranged in other ways without departing from the concepts of the present invention.

[0038] The use of cross-hatching and / or shading in the accompanying drawings is generally intended to clarify boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading does not convey or indicate preferences or requirements for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or other characteristics, attributes, or properties of the elements, unless specified. Additionally, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or explanation purposes. Where example embodiments may be implemented differently, certain processing sequences may be performed differently than described. For example, two processes described as successive may be performed substantially simultaneously or in the reverse order of the described order. Additionally, like reference numerals refer to like elements.

[0039] When an element or layer is described as being "on," "connected to," or "coupled" to another element or layer, it means that it is directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, it is understood that an element or layer may be directly on, connected to, or coupled to the other element or layer. References to being "directly on" or "directly connected to" or "directly coupled to" a layer or element refer to no intervening elements or layers. Thus, the term "connected" can refer to physical, electrical, and / or fluid connections, with or without intervening elements. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, but may be interpreted more broadly. For example, the D1, D2, and D3 axes may be orthogonal to one another, or may represent different directions that are not orthogonal to one another. For purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z, e.g., XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Terms such as "first" and "second" may be used herein to describe various types of elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below could be referred to as a second element without departing from the teachings of the present disclosure.

[0041] For purposes of explanation, spatially relative terms such as below, under, lower, above, upper, over, higher, and side (e.g., as in a sidewall) may be used herein to describe the relationship of an element to other elements shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Additionally, the device may be in other orientations (e.g., rotated 90 degrees or at other orientations), in which case the spatially relative descriptors used herein should be interpreted accordingly.

[0042] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. Furthermore, as used herein, the terms "comprises," "comprising," "includes," and / or "including" identify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that the terms "substantially," "about," and other similar terms are used herein as terms of approximation, rather than degree, and are utilized to account for inherent variations in measurements, calculations, and provided values ​​that would be recognized by one of ordinary skill in the art.

[0043] Various exemplary embodiments are described herein with reference to cross-section and / or exploded view illustrations that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments disclosed herein should not be construed as necessarily limited to the shapes of the particular illustrated regions and are to include, for example, deviations in shapes that result from manufacturing. As such, the regions illustrated in the figures are schematic in nature and the shapes of these regions may not reflect the actual shapes of regions of a device, and as such are not intended to be necessarily limiting.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms as defined in commonly used dictionaries, unless expressly so defined herein, should be interpreted to have a meaning consistent with the meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0045]

[0014] Exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. As used herein, a light emitting stack, a light emitting chip, a light emitting package, or a light emitting module according to exemplary embodiments may include a micro LED having a surface area of ​​less than about 10,000 square microns, as known in the art. In other exemplary embodiments, the micro LED may have a surface area of ​​less than about 4,000 square microns or less than about 2,500 square microns, depending on the particular application.

[0046] FIG. 1 is a schematic cross-sectional view of a light emitting package constructed in accordance with an exemplary embodiment of the present invention.

[0047] 1, a light-emitting package 110 according to the illustrated exemplary embodiment includes a light-emitting chip 100, a molding layer 91 (or a first molding layer) surrounding at least the side surfaces of the light-emitting chip 100, an insulating layer 11p, and lead electrodes 11pc. An array of light-emitting chips may be formed on a substrate 11, and the light-emitting chip 100 included in the light-emitting package 110 in FIG. 1 is exemplarily an individual chip separated from the array, which is further processed to form the light-emitting package 110.

[0048] The light-emitting chip 100 according to the exemplary embodiment may include at least two or more light-emitting subunits or light-emitting stacks arranged along a direction intersecting the longitudinal direction of the substrate 11, e.g., a vertical direction. In this manner, the light-emitting chip 100 can display light of various colors depending on the operating state of each light-emitting stack. Conventional light-emitting devices, however, can display various colors by combining multiple light-emitting cells emitting light of a single color. More specifically, conventional light-emitting devices typically include light-emitting cells emitting different colors, e.g., red, green, and blue, spaced apart along a two-dimensional plane to achieve a full-color display. Therefore, conventional light-emitting cells may occupy a relatively large area. However, the light-emitting chip 100 configured according to the exemplary embodiment can emit light of various colors by stacking multiple light-emitting stacks, thereby achieving a high level of integration and implementing a full color spectrum in a much smaller area than conventional light-emitting devices.

[0049] Furthermore, when a light-emitting chip 100 including a light-emitting stack structure is mounted on another substrate to manufacture, for example, a display device, the stack structure allows for a significant reduction in the number of chips to be mounted compared to conventional light-emitting devices. Thus, the manufacture of a display device employing a light-emitting stack structure can be substantially simplified, particularly when hundreds of thousands or millions of pixels are formed in a single display device. The light-emitting chip 100 may include a light-emitting stack structure as shown in FIG. 2 and a plurality of connection electrodes connected to the light-emitting stack structure, as will be described in detail below.

[0050] The molding layer 91 may surround at least the side surfaces of the light-emitting chip 100 to protect the light-emitting chip 100 from external impact. The bonding layer 91 may expose the substrate 11 of the light emitting chip 100 to enhance light efficiency. The insulating layer 11p may be made of an organic insulating material or an inorganic insulating material such as SiO2, SiNx, or Al2O3. The lead electrodes 11pc may include a material. The lead electrodes 11pc may be electrically connected to the light emitting chip 100, which will be described later in detail, through openings formed in the insulating layer 11p. The lead electrodes 11pc may be spaced apart from each other at a predetermined pitch P (see FIG. 15). For example, the pitch P between the lead electrodes 11pc may correspond to the pitch of electrodes on a target substrate such as a circuit board or a display device. In this manner, the light emitting package 110 according to the exemplary embodiment can be mounted on a conventional display device without changing the configuration of the target substrate of the display device. The light emitting subunit or the light emitting stack may extend longitudinally, and the lead electrodes 11pc may extend away from the light emitting subunit or the light emitting stack along the longitudinal direction.

[0051] FIG. 2 is a schematic cross-sectional view of a light emitting stack constructed in accordance with an exemplary embodiment.

[0052] Referring to FIG. 2 , the illustrated light-emitting stack structure according to the exemplary embodiment includes a first LED subunit, a second LED subunit, and a third LED subunit disposed on a substrate 11. The first LED subunit may include a first light-emitting stack 20, the second LED subunit may include a second light-emitting stack 30, and the third LED subunit may include a third light-emitting stack 40. While the drawing shows a light-emitting stack structure including three light-emitting stacks 20, 30, and 40, the concept of the present invention is not limited to a particular number of light-emitting stacks formed in the light-emitting stack structure. For example, in some exemplary embodiments, the light-emitting stack structure may include two or more light-emitting stacks therein. The light-emitting stack structure will be described below with reference to an exemplary embodiment including three light-emitting stacks 20, 30, and 40.

[0053] The substrate 11 may include a light-transmitting insulating material for transmitting light. However, in some exemplary embodiments, the substrate 11 may be semi-transparent, transmitting only light having a specific wavelength, or partially transparent, transmitting only a portion of light having a specific wavelength. The substrate 11 may also be a growth substrate on which the third light-emitting stack 40 can be epitaxially grown, such as a sapphire substrate. However, the concept of the present invention is not limited thereto. In some exemplary embodiments, the substrate 11 may include various other transparent insulating materials. For example, the substrate 11 may include glass, quartz, silicon, an organic polymer, or an organic-inorganic composite material, such as silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or gallium oxide (Ga2O3). As another example, substrate 11 in some exemplary embodiments may be a printed circuit board or composite substrate that includes electrical wiring therein to provide light emitting signals and common voltages to each of the light emitting stacks formed thereon.

[0054] Each of the first, second, and third light-emitting stacks 20, 30, and 40 is configured to emit light toward the substrate 11. Therefore, for example, light emitted from the first light-emitting stack 20 may pass through the second and third light-emitting stacks 30 and 40. According to an exemplary embodiment, the light emitted from each of the first, second, and third light-emitting stacks 20, 30, and 40 may have different wavelength bands, and the light-emitting stack disposed farther from the substrate 11 may emit light having a longer wavelength band. For example, the first, second, and third light-emitting stacks 20, 30, and 40 may emit red light, green light, and blue light, respectively. However, the concept of the present invention is not limited thereto. As another example, the first, second, and third light-emitting stacks 20, 30, and 40 may emit red light, blue light, and green light, respectively. As yet another example, in another exemplary embodiment, one or more light-emitting stacks may emit light having substantially the same wavelength band. As yet another example, the light-emitting stack structure may be configured to emit light having a wavelength band that is different from that of the present technology. When including micro-LEDs having a surface area of ​​less than about 10,000 square microns, or in other exemplary embodiments, less than about 4,000 square microns or about 2,500 square microns, as known in the art, the small form factor of the micro-LEDs allows light emitting stacks located farther from the substrate 11 to emit light having a shorter wavelength band than light emitted from those located closer to the substrate 11 without adversely affecting operation. In this case, the micro-LEDs can be operated at lower operating voltages, and therefore, separate color filters between the light emitting stacks may not be necessary. Hereinafter, the first, second, and third light emitting stacks 20, 30, and 40 will be illustratively described as emitting red, green, and blue light, respectively, according to exemplary embodiments.

[0055] The first light emitting stack 20 includes a first-type semiconductor layer 21, an active layer 23, and a second-type semiconductor layer 25. According to an exemplary embodiment, the first light emitting stack 20 may include a semiconductor material that emits red light, such as, but not limited to, aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), and gallium phosphide (GaP). In addition, a first bottom contact electrode 25p may be disposed below the second-type semiconductor layer 25 of the first light emitting stack 20.

[0056] The second light emitting stack 30 includes a first-type semiconductor layer 31, an active layer 33, and a second-type semiconductor layer 35. According to an exemplary embodiment, the second light emitting stack 30 may include a semiconductor material that emits green light, such as, but not limited to, indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), or aluminum gallium phosphide (AlGaP). A second bottom contact electrode 35p is disposed below the second-type semiconductor layer 35 of the second light emitting stack 30.

[0057] The third light emitting stack 40 includes a first-type semiconductor layer 41, an active layer 43, and a second-type semiconductor layer 45. According to an exemplary embodiment, the third light emitting stack 40 may include a semiconductor material that emits blue light, such as, but not limited to, gallium nitride (GaN), indium gallium nitride (InGaN), or zinc selenide (ZnSe). A third bottom contact electrode 45p is disposed on the second-type semiconductor layer 45 of the third light emitting stack 40.

[0058] According to exemplary embodiments, the first-type semiconductor layers 21, 31, and 41, respectively, and the second-type semiconductor layers 25, 35, and 45, respectively, of the first, second, and third light emitting stacks 20, 30, and 40 may have a single-layer structure or a multi-layer structure, and in some exemplary embodiments, may include a superlattice layer. Furthermore, the active layers 23, 33, and 43 of the first, second, and third light emitting stacks 20, 30, and 40 may have a single quantum well structure or a multiple quantum well structure.

[0059] The first, second, and third bottom contact electrodes 25p, 35p, and 45p may each contain a transparent conductive material for transmitting light. For example, the bottom contact electrodes 25p, 35p, and 45p may contain, but are not limited to, tin oxide (SnO), indium oxide (InO), etc. The transparent conductive oxide (TCO) may include zinc oxide (ZnO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), or other transparent conductive oxides (TCOs).

[0060] A first adhesive layer 61 is disposed between the first light-emitting stack 20 and the second light-emitting stack 30, and a second adhesive layer 63 is disposed between the second light-emitting stack 30 and the third light-emitting stack 40. The first adhesive layer 61 and the second adhesive layer 63 may contain a non-conductive material that transmits light. For example, the first adhesive layer 61 and the second adhesive layer 63 may each contain an optically transparent non-conductive material such as an OCA (Optical Conductive Acrylic Acid) or an OCA (Optical Conductive Acrylic Acid). Clear Adhesive), but is not limited to, epoxy, polyimide, SU8, SOG (Spin-on Glass), BCB (Ben zocyclobutene) and the like.

[0061] According to an exemplary embodiment, each of the first, second, and third light emitting stacks 20, 30, and 40 may be driven independently. More specifically, a common voltage Sc is applied to one of the first and second type semiconductor layers of each light emitting stack, and a respective light emitting signal S is applied to the other of the first and second type semiconductor layers of each light emitting stack. R , S G and S B may be applied. For example, the exemplary According to an embodiment, the first-type semiconductor layers 21, 31, 41 of each light-emitting stack may be n-type, and the second-type semiconductor layers 25, 35, 45 of each light-emitting stack may be p-type. In this case, the third light-emitting stack 40 may have a stacking order reversed compared to the first light-emitting stack 20 and the second light-emitting stack 30, such that the p-type semiconductor layer 45 is disposed above the active layer 43, in order to simplify the manufacturing process. Hereinafter, according to the illustrated exemplary embodiment, the first-type and second-type semiconductor layers may be interchangeably referred to as p-type and n-type semiconductor layers, respectively.

[0062] Although the light emitting stack structures according to the illustrated exemplary embodiments have a common p-type structure, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the first-type semiconductor layers 21, 31, and 41 of each light emitting stack may be p-type, and the second-type semiconductor layers 25, 35, and 45 of each light emitting stack may be n-type, forming a common n-type light emitting stack structure. Furthermore, in some exemplary embodiments, the stacking order of each light emitting stack is not limited to that shown in the drawings, and may be variously changed. Hereinafter, the light emitting stack structures according to the illustrated exemplary embodiments will be described with reference to the common p-type light emitting stack structure.

[0063] According to exemplary embodiments, the light-emitting stack structure may further include various additional components to improve the purity and efficiency of light emitted therefrom. For example, in some exemplary embodiments, a wavelength pass filter may be formed between adjacent light-emitting stacks to prevent or at least suppress light having shorter wavelengths from traveling toward a light-emitting stack emitting a longer wavelength. Furthermore, in some exemplary embodiments, a textured portion may be formed on the light-emitting surface of at least one light-emitting stack to balance the brightness of the light between the light-emitting stacks. For example, because green light is generally more visible than red or blue light, in some exemplary embodiments, textured portions may be formed on light-emitting stacks emitting red or blue light to improve the light efficiency and balance the visibility of the light emitted from the light-emitting stacks.

[0064] Hereinafter, a method for forming a light emitting chip will be described based on an exemplary embodiment with reference to the drawings.

[0065] Figures 3A, 4A, 5A, 6A, 7A, and 8A are plan views illustrating manufacturing processes of the light-emitting chip included in the light-emitting package of Figure 1 according to exemplary embodiments. Figures 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views taken along line A-A' of the corresponding plan views shown in Figures 3A, 4A, 5A, 6A, 7A, and 8A according to exemplary embodiments.

[0066] Returning to FIG. 2, the first-type semiconductor layer 41, the third active layer 43, and the second-type semiconductor layer 45 of the third light-emitting stack 40 are formed by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). The third p-type semiconductor layer 45 may be sequentially grown on the substrate 11 by vapor deposition or molecular beam epitaxy (MBE). The third bottom contact electrode 45p may be formed on the third p-type semiconductor layer 45 by physical vapor deposition or chemical vapor deposition, for example, and may include a transparent conductive oxide (TCO). When the third light-emitting stack 40 emits blue light according to an exemplary embodiment, the substrate 11 includes Al2O3 (e.g., a sapphire substrate), and the third bottom contact electrode 45p may be formed of tin oxide (SnO), indium oxide (InO2), zinc oxide (ZnO), indium tin oxide (ITO), or oxide. The first light-emitting stack 20 and the second light-emitting stack 30 may each be formed by sequentially growing a first-type semiconductor layer, an active layer, and a second-type semiconductor layer on a temporary substrate, and then forming a lower contact electrode containing a transparent conductive oxide on the second-type semiconductor layer by, for example, chemical vapor deposition.

[0067] According to exemplary embodiments, the first and second light-emitting stacks 20 and 30 may be adjacent to each other with the first adhesive layer 61 interposed therebetween, and at least one of the temporary substrates of the first and second light-emitting stacks 20 and 30 may be removed, for example, by a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, a textured portion may be formed on the exposed light-emitting stack to improve light extraction efficiency. Thereafter, the first and second light-emitting stacks 20 and 30 may be adjacent to the third light-emitting stack 40 with the second adhesive layer 63 interposed therebetween, and the remaining temporary substrate of the first and second light-emitting stacks 20 and 30 may be removed, for example, by a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, a textured portion may be formed on the exposed remaining light-emitting stack to improve light extraction efficiency.

[0068] In another exemplary embodiment, the second adhesive layer 63 may be formed on the third light-emitting stack 40. The second light-emitting stack 30 may then be adjacent to the third light-emitting stack 40 with the second adhesive layer 63 interposed therebetween, and the temporary substrate of the second light-emitting stack 30 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. A first adhesive layer 61 may then be formed on the second light-emitting stack 30. As a result, the first light-emitting stack 20 may be adjacent to the second light-emitting stack 30 with the first adhesive layer 61 sandwiched therebetween. Once the first light-emitting stack 20 is bonded to the second light-emitting stack 30, which is bonded to the third light-emitting stack 40, the temporary substrate of the first light-emitting stack 20 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. In some exemplary embodiments, one or more surfaces of one light-emitting stack may be textured before or after being bonded to another light-emitting stack to improve light extraction efficiency.

[0069] 3A and 3B , various portions of each of the first, second, and third light emitting stacks 20, 30, and 40 may be patterned, such as via an etching process, to expose portions of the first-type semiconductor layer 21, the first bottom contact electrode 25p, the first-type semiconductor layer 31, the second bottom contact electrode 35p, the third bottom contact electrode 45p, and the first-type semiconductor layer 41. According to the illustrated exemplary embodiment, the first light emitting stack 20 has the smallest area among the light emitting stacks 20, 30, and 40. However, the concept of the present invention is not limited to the relative sizes of the light emitting stacks 20, 30, and 40.

[0070] 4A and 4B, a portion of the upper surface of the first-type semiconductor layer 21 of the first light-emitting stack 20 may be patterned by wet etching or the like, and a first upper contact electrode 21n (hereinafter also referred to as a first n-type contact electrode) may be formed thereon. The first upper contact electrode 21n may have a single layer structure or a multilayer structure and may include, but is not limited to, Al, Ti, Cr, Ni, Au, Ag, Sn, W, Cu, or an alloy thereof, such as an Au-Te alloy or an Au-Ge alloy. In an exemplary embodiment, the first upper contact electrode 21n has a thickness of approximately 100 nm and may include a metal with high reflectivity to increase light emission efficiency in the downward direction toward the substrate 11.

[0071] 5A and 5B, a first insulating layer 81 may be disposed on at least a portion of the side surfaces of the first light-emitting stack 20, the second light-emitting stack 30, and the third light-emitting stack 40. The first insulating layer 81 may be made of various organic or inorganic materials such as polyimide, SiO2, SiNx, and Al2O3. The first insulating layer 81 may include an insulating material. For example, the first insulating layer 81 may include a distributed Bragg reflector (DBR). As another example, the first insulating layer 81 may include a black organic polymer. In some exemplary embodiments, an electrically floating metal reflective layer may be further disposed on the first insulating layer 81 to reflect light emitted from the light-emitting stacks 20, 30, and 40 toward the substrate 11. In some exemplary embodiments, the first insulating layer 81 may have a single-layer structure or a multi-layer structure formed of two or more insulating layers having different refractive indices.

[0072] According to an exemplary embodiment, a portion of the first insulating layer 81 may be removed to form first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH. The first contact hole 20CH is defined on the first n-type contact electrode 21n to expose a portion of the first n-type contact electrode 21n. The second contact hole 30CH may expose a portion of the first-type semiconductor layer 31 of the second light-emitting stack 30. The third contact hole 40CH may expose a portion of the first-type semiconductor layer 41 of the third light-emitting stack 40. The fourth contact hole 50CH may expose portions of the first, second, and third bottom contact electrodes 25p, 35p, and 45p. The fourth contact hole 50CH may include a second sub-contact hole 50CHb exposing a portion of the first bottom contact electrode 25p and a first sub-contact hole 50CHa exposing the second and third bottom contact electrodes 35p and 45p. However, in some exemplary embodiments, a single first sub-contact hole CHa may expose each of the first, second, and third bottom contact electrodes 25p, 35p, and 45p.

[0073] 6A and 6B, the first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are formed on a first insulating layer 81 in which the first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH are formed. The first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd can be formed, for example, by forming a conductive layer on substantially the entire surface of the substrate 11 and patterning the conductive layer using a photolithography process or the like.

[0074] The first pad 20pd is formed to overlap the region where the first contact hole 20CH is formed, so that the first pad 20pd can be connected to the first upper contact electrode 21n of the first light-emitting stack 20 through the first contact hole 20CH. The second pad 30pd is formed to overlap the region where the second contact hole 30CH is formed, so that the second pad 30pd can be connected to the first-type semiconductor layer 31 of the second light-emitting stack 30 through the second contact hole 30CH. The third pad 40pd is formed to overlap the region where the third contact hole 40CH is formed, so that the third pad 40pd can be connected to the first-type semiconductor layer 41 of the third light-emitting stack 40 through the third contact hole 40CH. Furthermore, the fourth pad 50pd is formed so as to overlap the region in which the fourth contact hole 50CH is formed, more specifically, the region in which the first sub-contact hole 50CHa and the second sub-contact hole 50CHb are formed, and the fourth pad 50pd may be connected to the first, second and third lower contact electrodes 25p, 35p, 45p of the first, second and third light-emitting stacks 20, 30 and 40 via the first sub-contact hole 50CHa and the second sub-contact hole 50CHb.

[0075] 7A and 7B, a second insulating layer 83 may be formed on the first insulating layer 81. The second insulating layer 83 may be made of various materials such as polyimide, SiO2, SiNx, and Al2O3. The second insulating layer 83 may include an organic or inorganic insulating material. For example, the second insulating layer 83 may include a Distributed Bragg Reflector (DBR). As another example, the second insulating layer 83 may include a black organic polymer. Some exemplary embodiments In some embodiments, an electrically floating metal reflective layer may be further disposed on the second insulating layer 83 to reflect light emitted from the light-emitting stacks 20, 30, and 40 toward the substrate 11. In some exemplary embodiments, the second insulating layer 83 may have a single-layer structure or a multi-layer structure formed of two or more insulating layers having different refractive indices. Next, the second insulating layer 83 is patterned to form first, second, third, and fourth through-holes 20ct, 30ct, 40ct, and 50ct therein.

[0076] The first through-hole 20ct formed in the first pad 20pd exposes a portion of the first pad 20pd. The second through-hole 30ct formed in the second pad 30pd exposes a portion of the second pad 30pd. The third through-hole 40ct formed in the third pad 40pd exposes a portion of the third pad 40pd. The fourth through-hole 50ct formed in the fourth pad 50pd exposes a portion of the fourth pad 50pd. In the illustrated exemplary embodiment, the first, second, third, and fourth through-holes 20ct, 30ct, 40ct, and 50ct may be defined in the regions where the first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are formed, respectively.

[0077] 8A and 8B, the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp are formed on a second insulating layer 83 in which the first, second, third, and fourth through holes 20ct, 30ct, 40ct, and 50ct are formed. The first bump electrode 20bp is formed to overlap the region in which the first through hole 20ct is formed, and the first bump electrode 20bp is connected to the first pad 20pd via the first through hole 20ct. The second bump electrode 30bp may be formed to overlap the region in which the second through hole 30ct is formed, and the second bump electrode 30bp is connected to the second pad 30pd via the second through hole 30ct. The third bump electrode 40bp may be formed so as to overlap the area in which the third through hole 40ct is formed, and the third bump electrode 40bp may be connected to the third pad 40pd via the third through hole 40ct.

[0078] The fourth bump electrode 50bp is formed to overlap the region where the fourth through hole 50ct is formed, and the fourth bump electrode 50bp is connected to the fourth pad 50pd via the fourth through hole 50ct. More specifically, the fourth pad 50pd is connected to the second-type semiconductor layers 25, 35, and 45 of the first, second, and third light-emitting stacks 20, 30, and 40 via the first sub-contact hole 50CHa and the second sub-contact hole 50CHb defined in the first, second, and third lower contact electrodes 25p, 35p, and 45p of the first, second, and third light-emitting stacks 20, 30, and 40. In particular, the fourth pad 50pd is connected to the first lower contact electrode 25p via the second sub-contact hole 50CHb, and to the second and third lower contact electrodes 35p and 45p via the first sub-contact hole 50CHa. In this way, the fourth pad 50pd can be connected to the second and third lower contact electrodes 35p and 45p through one first sub-contact hole 50CHa, which simplifies the manufacturing process of the light emitting chip 100 and reduces the area occupied by the contact holes of the light emitting chip 100. Furthermore, at least a portion of the fourth bump electrode 50bp may overlap with the fourth pad 50pd. The fourth bump electrode 50bp is connected to the fourth pad 50pd through the fourth through-hole 50ct at the overlapping portion between the fourth bump electrode 50bp and the fourth pad 50pd, with the second insulating layer 83 interposed therebetween.

[0079] The first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp may be formed by depositing a conductive layer containing at least one of Ni, Ag, Au, Pt, Ti, Al, Cr, Wi, TiW, Mo, Cu, TiCu, etc. on the substrate 11 and patterning the layer. Hereinafter, the first pad 20pd and the first bump electrode 20bp will be collectively referred to as the first contact portion 20C, and the second pad 30pd and the second bump electrode 30 The third pad 40pd and the third bump electrode 40bp may be collectively referred to as the second contact portion 30C, the third pad 40pd and the third bump electrode 40bp may be collectively referred to as the third contact portion 40C, and the fourth pad 50pd and the fourth bump electrode 50bp may be collectively referred to as the fourth contact portion 50C.

[0080] According to exemplary embodiments, the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C may be formed at various locations. For example, if the light emitting chip 100 has a substantially rectangular shape as shown in the drawings, the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C may be disposed around each corner of the substantially rectangular shape. However, the concept of the present invention is not limited thereto. In some exemplary embodiments, the light emitting chip 100 may be formed to have various shapes, and the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C may be formed at other locations depending on the shape of the light emitting device.

[0081] The first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are insulated from one another by being spaced apart. Furthermore, the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp are insulated from one another by being spaced apart. According to an exemplary embodiment, the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp may cover at least a portion of the side surfaces of the first, second, and third light-emitting stacks 20, 30, and 40, respectively, thereby facilitating on-site dissipation of heat generated from the first, second, and third light-emitting stacks 20, 30, and 40.

[0082] It should be noted that the concept of the present invention is not limited to a specific structure of the contact portions 20C, 30C, 40C, and 50C. For example, in some exemplary embodiments, the bump electrode 20bp, 30bp, 40bp, or 50bp may be omitted from at least one of the contact portions 20C, 30C, 40C, and 50C. In this case, the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C may be connected to the connection electrodes 20ce, 30ce, 40ce, and 50ce, respectively.

[0083] FIG. 9A is a schematic plan view of a light-emitting chip configured according to an exemplary embodiment, and FIGS. 9B and 9C are cross-sectional views taken along lines AA' and BB', respectively, of FIG. 9A.

[0084] 9A and 9B, first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce may be formed on the light-emitting stack structure at intervals. The first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce may be electrically connected to the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp, respectively, and may transmit external signals to the light-emitting stacks 20, 30, and 40, respectively. More specifically, according to the illustrated exemplary embodiment, the first connection electrode 20ce may be connected to the first bump electrode 20bp, which is connected to the first upper contact electrode 21n via the first pad 20pd, and may be electrically connected to the first-type semiconductor layer 21 of the first light-emitting stack 20. The second connection electrode 30ce may be connected to the second bump electrode 30bp via the second pad 30pd and electrically connected to the first-type semiconductor layer 31 of the second light-emitting stack 30. The third connection electrode 40ce may be connected to the third bump electrode 40bp connected to the third pad 40pd and electrically connected to the first-type semiconductor layer 41 of the third light-emitting stack 40. The fourth connection electrode 50ce may be connected to the fourth bump electrode 50bp connected to the fourth pad 50pd and electrically connected to the second-type semiconductor layers 25, 35, 45 of the light-emitting stacks 20, 30, and 40 via the first, second, and third bottom contact electrodes 25p, 35p, 45p, respectively.

[0085] According to the illustrated exemplary embodiment, the connection electrodes 20ce, 30ce, 40ce and 5 Each of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially elongated shape protruding vertically from the substrate 11. The connecting electrodes 20ce, 30ce, 40ce, and 50ce may include a metal such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof. For example, each of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may include two or more metals or multiple different metal layers to reduce stresses imposed thereon by the elongated shape of the connecting electrodes 20ce, 30ce, 40ce, and 50ce. In another exemplary embodiment, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include Cu, an additional metal may be deposited or plated thereon to inhibit oxidation of the Cu. In some exemplary embodiments, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include Cu / Ni / Sn, the Cu may prevent Sn from penetrating into the light-emitting stack. In some exemplary embodiments, the connecting electrodes 20ce, 30ce, 40ce, and 50ce may include a seed layer for forming a metal layer during a plating process, which is described in more detail below.

[0086] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially flat upper surface to facilitate electrical connection between the light emitting stack and external wiring or electrodes, as described below. According to an exemplary embodiment, the light emitting chip may be less than about 10,000 square microns, as known in the art, or in other exemplary embodiments, When the micro LED includes a micro LED having a surface area of ​​less than about 4,000 μm² or about 2,500 μm², the connecting electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one portion of the first, second, and third light emitting stacks 20, 30, and 40, as shown in the drawings. More specifically, the connecting electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on the side of the light emitting stack structure. In this manner, the lower surface area of ​​the connecting electrodes is larger than the upper surface, thereby forming a larger contact area between the connecting electrodes 20ce, 30ce, 40ce, and 50ce and the light emitting stack structure. Therefore, the connecting electrodes 20ce, 30ce, 40ce, and 50ce may be more stably formed on the light emitting stack structure. For example, the length (or height) L of one side surface L of the connecting electrodes 20ce, 30ce, 40ce, and 50ce facing outward may be different from the length L' of the other side surface facing the center of the light-emitting chip 100. More specifically, the length L of one side surface L of the connecting electrodes facing outward may be greater than the length L' of the other side surface L of the connecting electrodes facing the center of the light-emitting chip 100. For example, the difference between the lengths L and L' of the two opposing side surfaces of the connecting electrodes may be greater than the thickness (or height) of one of the light-emitting stacks 20, 30, and 40. This may increase the contact area between the connecting electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting stack structure, thereby strengthening the structure of the light-emitting chip. Furthermore, the connecting electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on the side surface of the light-emitting stack structure, thereby more efficiently dissipating heat generated from the light-emitting stack structure to the outside.

[0087] According to an exemplary embodiment, the difference between the length L of one side of the connecting electrode facing outward and the length L' of the other side facing the center of the light emitting chip 100 may be about 3 μm. In this case, the light emitting stack structure may be formed thin. In particular, the first light emitting stack 20 may have a thickness of about 1 μm, the second light emitting stack 30 may have a thickness of about 0.7 μm, the third light emitting stack 40 may have a thickness of about 0.7 μm, and the first and second adhesive layers 61 and 63 may each have a thickness of about 0.2 μm to about 0.3 μm, but are not limited thereto. According to another exemplary embodiment, the difference between the length L of one side of the connecting electrode facing outward and the length L' of the other side of the connecting electrode facing the center of the light emitting chip 100 may be about 10 μm to about 16 μm. In this case, the light emitting stack structure can be formed relatively thick and have a more stable structure. In particular, the first light emitting stack 20 may have a thickness of about 4 μm to about 5 μm, the second light emitting stack 30 may have a thickness of about 3 μm, and the third light emitting stack 40 may have a thickness of about 3 μm. The first adhesive layer 61 and the second adhesive layer 63 may have a thickness of about 4 μm to about 5 μm. Each of the connecting electrodes may have a thickness of about 3 μm, but is not limited to this. According to yet another exemplary embodiment, the difference between the length L of one side of the connecting electrode facing outward and the length L' of the other side of the connecting electrode facing the center of the light emitting chip 100 may be about 25% of the length of the longest side. However, the concept of the present invention is not limited to a specific difference in length between the opposing side surfaces of the connecting electrode, and the difference in length between the opposing side surfaces of the connecting electrode may vary.

[0088] In some exemplary embodiments, at least one of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may overlap a side surface of each of the light-emitting stacks 20, 30, and 40, thereby achieving temperature balance among the light-emitting stacks 20, 30, and 40 and efficiently dissipating heat generated inside to the outside. In addition, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include a reflective material such as a metal, the connecting electrodes 20ce, 30ce, 40ce, and 50ce can reflect light emitted from at least one or more of the light-emitting stacks 20, 30, and 40, thereby improving light efficacy.

[0089] The method for forming the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce is not particularly limited. For example, according to exemplary embodiments, a seed layer may be deposited on the light-emitting stack as a conductive surface, and the seed layer may be patterned using photolithography or the like so that the seed layer is positioned in the desired location where the connection electrodes are to be formed. The seed layer may then be plated with a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof, and the seed layer may then be removed. In some exemplary embodiments, additional metal may be deposited or plated on the plated metal (e.g., the connection electrodes) using, for example, electroless nickel immersion gold (ENIG) to prevent or at least suppress oxidation of the plated metal. In some exemplary embodiments, the seed layer may remain on each connection electrode.

[0090] According to an exemplary embodiment, when the bump electrodes 20bp, 30bp, 40bp, and 50bp are omitted from the contact portions 20C, 30C, 40C, and 50C, the pads 20pd, 30pd, 40pd, and 50pd may be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce. For example, after forming through holes 20ct, 30ct, 40ct, and 50ct that partially expose the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C, a seed layer may be deposited as a conductive surface on the light-emitting stack, and the seed layer may be patterned using photolithography or the like so that the seed layer is positioned in the desired position where the connection electrode should be formed. In this case, the seed layer may overlap at least a portion of each of the pads 20pd, 30pd, 40pd, and 50pd. According to exemplary embodiments, a seed layer may be deposited to a thickness of about 1000 Å, and then the seed layer may be plated with a metal such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof, and the seed layer may be removed. In some exemplary embodiments, additional metal may be deposited or plated on the plated metal (e.g., connection electrodes), such as with electroless nickel immersion gold (ENIG), to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer may remain on each connection electrode.

[0091] 10, 11, 12, 13, and 14 are schematic cross-sectional views illustrating manufacturing steps for the light emitting package of FIG. 1 according to exemplary embodiments.

[0092] 10, an array of light emitting chips 100 formed on a substrate 11 may be separated from one another and transferred at a desired pitch to a carrier substrate 95. For example, in some exemplary embodiments, the light emitting chips 100 may be transferred at a pitch that matches the pitch of electrodes of a target device, such as a display device.

[0093] According to an exemplary embodiment, the singulated light emitting chips 100 may be transferred to a carrier substrate 95 with an adhesive layer 15 interposed therebetween. The carrier substrate 95 is not particularly limited as long as it stably mounts the light emitting chips 100 with the adhesive layer 15 interposed therebetween. The adhesive layer 15 may be a tape, but the concept of the present invention is not limited thereto as long as the adhesive layer 15 stably attaches the light emitting chips 100 to the carrier substrate 95 while allowing the light emitting chips 100 to be peeled off in a subsequent process. After the light emitting chips 100 are mounted on the carrier substrate 95, as shown in FIG. 11 , a molding layer 91 may be formed to cover at least the side surfaces of the light emitting chips 100. According to an exemplary embodiment, the molding layer 91 may transmit a portion of the light emitted from the light emitting chips 100 and may reflect, diffract, and / or absorb a portion of external light to prevent the external light from being reflected by the light emitting chips 100 in a direction that may be visible to a user. The molding layer 91 may cover at least the sides of the light emitting chip 100 to protect the light emitting chip 100 from external moisture and stress, as well as strengthen the structural structure of the light emitting package to facilitate subsequent transfer and / or mounting processes.

[0094] The molding layer 91 may be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce so as to cover a portion of the first light-emitting stack 20 (e.g., an upper structure of the light-emitting stack structure) disposed between the connection electrodes 20ce, 30ce, 40ce, and 50ce. In this manner, the molding layer 91 protects the light-emitting structure from external impacts that may be applied in subsequent processes, and provides a sufficient contact area for the light-emitting chip 100, facilitating handling in subsequent transport processes. Furthermore, the molding layer 91 prevents light from leaking to the side surfaces of the light-emitting chip 100, and can prevent or at least suppress interference of light emitted from adjacent light-emitting chips 100.

[0095] According to exemplary embodiments, the upper surface of molding layer 91 may be substantially flush with the upper surfaces of connection electrodes 20ce, 30ce, 40ce, and 50ce by polishing or the like. Molding layer 91 according to exemplary embodiments may include, but is not limited to, epoxy molding compound (EMC) and may be formed in various colors, such as black or transparent. For example, in some exemplary embodiments, molding layer 91 may include a photosensitive polyimide dry film (PID).

[0096] The molding layer 91 may be formed by various methods known in the art, such as lamination, plating, and / or printing. For example, the molding layer 91 may be formed by a vacuum lamination process in which an organic polymer sheet is placed on the light emitting chip 100 and high temperature and pressure are applied in a vacuum to provide a substantially flat top surface of the light emitting package 110 and thereby improve light uniformity.

[0097] 12, the insulating layer 11p may be formed on substantially the entire molding layer 91 and the light emitting chip 100. The insulating layer 11p may be made of an organic insulating material, SiO2, S, or the like. It may also contain inorganic insulating materials such as iOx.

[0098] Referring to FIG. 13, an opening may be formed in the insulating layer 11p. The opening may overlap at least a part of each of the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce of the light emitting chip 100. Next, a conductive layer may be formed on the insulating layer 11p and patterned to form the lead electrode 11pc. The lead electrode 11pc may be formed by a photolithography process without being limited thereto. The opening in the insulating layer 11p overlaps at least a part of each of the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce, and the lead electrode 11pc may be formed by a photolithography process. Since the conductive layer substantially fills the opening, the lead electrode 11pc may be electrically connected to each of the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce. The lead electrodes 11pc may be spaced apart to be insulated from one another and extend outward from the light-emitting chip 100 to a desired extent to form a fan-out structure. This allows the light-emitting package 110 including the light-emitting chip 100 and the lead electrode 11pc to be easily mounted on a circuit board or the like, even if the light-emitting chip 100 is very small. In some exemplary embodiments, the lead electrode 11pc may include a metal such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof. In some exemplary embodiments, the lead electrode 11pc may be surface-treated with ENIG to facilitate electrical connection with the connection electrode of the light-emitting chip 100 by partially melting it at a high temperature.

[0099] Referring to FIG. 14 , the adhesive layer 15 and the carrier substrate 95 may be removed from the light emitting chip 100 on which the insulating layer 11p is disposed. Then, the light emitting chip 100 including the lead electrode 11pc may be cut into a desired shape to form a light emitting package 110. For example, the light emitting package 110 (or light emitting module) shown in FIG. 15 includes four light emitting chips 100 (2×2) disposed on the insulating layer 11p. However, the concept of the present invention is not limited to a specific number of light emitting chips 100 formed in the light emitting package 110. For example, in some exemplary embodiments, the light emitting package 110 may include one or more light emitting chips 100 formed on the insulating layer 11p. In addition, the concept of the present invention is not limited to a specific arrangement of the one or more light emitting chips 100 in the light emitting package 110. For example, the one or more light emitting chips 100 in the light emitting package 110 may be arranged in an n×m array, where n and m are natural numbers.

[0100] According to an exemplary embodiment, the lead electrodes 11pc of the light-emitting package 110 may be spaced apart from one another at a predetermined pitch P corresponding to the pitch of electrodes of a target device such as a circuit board. For example, the pitch P between the lead electrodes 11pc may be larger than the pitch P' between adjacent connection electrodes of the light-emitting chip 100. In this way, even if the layout of the electrodes on the circuit board is designed for a conventional light-emitting device, the light-emitting package 110 can be easily mounted on a target board or a circuit board.

[0101] According to exemplary embodiments, the lead electrode 11pc of the light-emitting package 110 may be bonded to an electrode on a circuit board or the like by, for example, anisotropic conductive film (ACF) bonding. Because ACF bonding can be performed at a lower temperature than other bonding methods, electrically bonding the lead electrode 11pc to an electrode on a circuit board or the like by ACF bonding may protect the light-emitting chip 100 from exposure to high temperatures during bonding. However, the concept of the present invention is not limited to a specific bonding method. For example, in some exemplary embodiments, the light-emitting package 110 may be bonded to an electrode on a circuit board or the like using an anisotropic conductive paste (ACP) containing at least one of Cu and Sn, solder, a ball grid area (BGA), or microbumps. In this case, the lead electrode 11pc may have a larger contact area than the connection electrodes 20ce, 30ce, 40ce, and 50ce. This may facilitate the bonding process between the light-emitting package 110 and a circuit board or the like, even if the light-emitting package 110 is very small.

[0102] FIG. 16 is a schematic cross-sectional view of a luminous package according to another exemplary embodiment, and FIG. 17 is a schematic cross-sectional view of a luminous package according to another exemplary embodiment.

[0103] Referring to FIG. 16, a light emitting package 120 according to an exemplary embodiment has the same structure as that of FIG. 16, except that the light emitting package 120 further includes an extended electrode 11c and a second molding layer 92. 1 and 2. The light-emitting package 110 is substantially the same as the light-emitting package 110 of JP-A-2010-146664. According to an exemplary embodiment, a plurality of extended electrodes 11c may be formed on the lead electrode 11pc disposed on the insulating layer 11p, and electrically connected to the connecting electrodes 20ce, 30ce, 40ce, and 50ce of the light-emitting chip 100, respectively.

[0104] The extended electrodes 11c may be spaced apart from one another and generally have a substantially elongated shape, although the concept of the present invention is not limited to any particular shape for the extended electrodes 11c. The extended electrodes 11c according to exemplary embodiments may include, but are not limited to, metals such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof. For example, the extended electrodes 11c may include two or more metals or multiple different metal layers to reduce stresses imposed thereon by their elongated shape. In some exemplary embodiments, if the extended electrodes 11c include Cu, an additional metal may be deposited or plated thereon to inhibit oxidation of the Cu. In some exemplary embodiments, if the extended electrodes 11c include Cu / Ni / Sn, the Cu may prevent Sn from penetrating into the light-emitting stack. The extended electrodes 11c may also be formed by, but are not limited to, a metal plating process.

[0105] According to the illustrated exemplary embodiment, each of the extended electrodes 11c may be formed near a distal end of the lead electrode 11pc facing away from the light emitting chip 100. In this manner, the extended electrodes 11c are formed near each corner of the light emitting package 120, thereby providing structural support to the light emitting package 120. In some exemplary embodiments, to further improve structural reliability, the extended electrodes 11c may not overlap with the connecting electrodes 20ce, 30ce, 40ce, and 50ce.

[0106] The second molding layer 92 may be formed on the insulating layer 11p and may surround at least the side surfaces of the extended electrodes 11c. The second molding layer 92 may include an organic polymer or an inorganic polymer. In some exemplary embodiments, at least one of the first molding layer 91 and the second molding layer 92 may further include pillars of silica or alumina, for example. In some exemplary embodiments, the second molding layer 92 may be formed by various methods known in the art, such as lamination, plating, and / or printing. For example, the second molding layer 92 may be formed by a vacuum lamination process in which an organic polymer sheet is placed on the light emitting chip 100 and high temperature and pressure are applied in a vacuum to provide a substantially flat top surface of the light emitting package 120 and thereby improve light uniformity. In this manner, the light emitting package 120 may have a reinforced package structure. In some exemplary embodiments, the first and second molding layers 91 and 92 may include substantially the same material or different materials.

[0107] 17, a light emitting package 130 according to an exemplary embodiment is substantially the same as the light emitting package 120 of FIG. 16, except that a first molding layer 91 is formed on the substrate 11 of the light emitting chip 100 to prevent external light from being reflected by the substrate 11 toward a direction visible to a user. In this case, in some exemplary embodiments, a portion of the first molding layer 91 covering the upper surface of the substrate 11 facing away from the insulating layer 11p may have a thickness of less than approximately 100 μm to transmit at least 50% of the light emitted from the light emitting chip 100.

[0108] FIG. 18 is a schematic cross-sectional view of a light emitting package constructed in accordance with another exemplary embodiment of the present invention.

[0109] Referring to FIG. 18, a light-emitting package 210 according to an exemplary embodiment includes a light-emitting chip 2 1. The light emitting package 210 includes a first molding layer 91' surrounding at least the side surfaces of the light emitting chip 200, an insulating layer 11p', lead electrodes 11pc', and a first molding layer 91' surrounding at least the side surfaces of the light emitting chip 200. The light emitting package 210 is substantially the same as the light emitting package 110 of FIG. 1 except for the shape of the connection electrodes and the fact that the light emitting chip 200 includes a passivation layer 90 formed between the connection electrodes, but will be described in more detail below. Note that the insulating layer 11p' and the lead electrodes 11pc' are substantially the same as the insulating layer 11p and lead electrodes 11pc described above, and therefore, to avoid redundancy, repeated description thereof will be omitted.

[0110] According to an exemplary embodiment, the lead electrodes 11pc′ of the light-emitting package 110 may be spaced apart from one another at a predetermined pitch corresponding to the pitch of electrodes of a target device such as a circuit board. In this way, even if the layout of the electrodes on the circuit board is designed for a conventional light-emitting device, the light-emitting package 210 can be easily mounted on a target substrate or circuit board of an end device such as a display device.

[0111] 19A and 20A are plan views illustrating a manufacturing process of a light-emitting chip according to another exemplary embodiment, and FIG. 19B and 20B are cross-sectional views taken along line A-A' of the corresponding plan views shown in FIG. 19A and FIG. 20A according to another exemplary embodiment.

[0112] 19A and 19B, a light emitting chip 200 according to an exemplary embodiment includes a light emitting stack structure, connection electrodes 20ce', 30ce', 40ce', and 50ce' (see FIGS. 20A and 20B), and a passivation layer 90 formed on the light emitting stack structure. The light emitting stack structure is substantially similar to the configuration shown in FIGS. 8A and 8B. However, according to the illustrated exemplary embodiment, the passivation layer 90 may be formed to cover at least a portion of the upper surface of the light emitting stack structure shown in FIGS. 8A and 8B. More specifically, as shown in FIG. 20B, the passivation layer 90 may cover at least a portion of the upper surface of the first light emitting stack 20 disposed on the upper portion of the stack structure, thereby protecting the light emitting stack structure from external stress during manufacturing.

[0113] According to the illustrated exemplary embodiment, the passivation layer 90 may form an inclined angle with respect to the substrate 11. For example, the inclination angles G and G' (see FIG. 20B ) formed between the passivation layer 90 and the substrate 11 may be less than approximately 80°. If the inclination angles G and G' are greater than approximately 80°, the passivation layer 90 may not be able to sufficiently cover the steps formed on the side surfaces of the light-emitting stack. In some exemplary embodiments, the inclination angles G and G' between the passivation layer 90 and the substrate 11 may be greater than approximately 60° and less than approximately 70°. In this manner, the connection electrodes 20ce', 30ce', 40ce', and 50ce' (see FIGS. 20A and 20B ) to be formed on the passivation layer 90 may also be stably formed on the light-emitting stack. In some exemplary embodiments, the edges formed between the top surface and side surfaces of passivation layer 90 may form a smooth angle such that connecting electrodes 20ce', 30ce', 40ce', and 50ce' formed thereon have a substantially uniform thickness. However, the inventive concept is not limited in this respect, and in some exemplary embodiments, substantially sharp edges may be formed between the top surface and side surfaces of passivation layer 90.

[0114] 20A and 20B, according to the illustrated exemplary embodiment, first, second, third, and fourth connection electrodes 20ce', 30ce', 40ce', and 50ce' spaced apart from one another are formed on the passivation layer 90. As described above, the first, second, third, and fourth connection electrodes 20ce', 30ce', 40ce', and 50ce' are electrically connected to the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp, respectively, similar to the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce of the light emitting chip 100, and are used to transmit external signals to the light emitting stacks 20, 30, and 40, respectively. The first connection electrode 20ce' may be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n via the first pad 20pd, and electrically connected to the first-type semiconductor layer 21 of the first light-emitting stack 20. The second connection electrode 30ce' may be connected to the second bump electrode 30bp via the second pad 30pd, and electrically connected to the first-type semiconductor layer 31 of the second light-emitting stack 30. The third connection electrode 40ce' may be connected to the third bump electrode 40bp connected to the third pad 40pd, and electrically connected to the first-type semiconductor layer 41 of the third light-emitting stack 40. In addition, the fourth connection electrode 50ce' may be connected to the fourth bump electrode 50bp connected to the fourth pad 50pd, and electrically connected to the second-type semiconductor layers 25, 35 and 45 of the light-emitting stacks 20, 30 and 40, respectively, via the first, second and third lower contact electrodes 25p, 35p and 45p.

[0115] The method for forming the first, second, third, and fourth connection electrodes 20ce', 30ce', 40ce', and 50ce' is not particularly limited. For example, according to exemplary embodiments, a conductive layer may be deposited on the passivation layer 90 and patterned using photolithography or the like so that each conductive layer overlaps a portion of the first bump electrode 20bp, the second bump electrode 30bp, the third bump electrode 40bp, and the fourth bump electrode 50bp exposed by the passivation layer 90. The conductive layer (e.g., the connection electrodes) according to exemplary embodiments may include a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof. In this case, a separate plating step may be omitted. In some exemplary embodiments, an additional metal may be deposited on the conductive layer using electroless nickel immersion gold (ENIG), for example, to prevent or at least suppress oxidation of the connection electrodes 20ce', 30ce', 40ce', and 50ce'.

[0116] According to the illustrated exemplary embodiment, each of the connecting electrodes 20ce', 30ce', 40ce', and 50ce' may have a curved shape that protrudes away from the substrate 11 to substantially cover the light emitting stack structure and the passivation layer 90. As shown in the drawings, each of the connecting electrodes 20ce', 30ce', 40ce', and 50ce' may have a substantially flat upper surface to facilitate electrical connection between the light emitting stack structure and external wiring or electrodes and to enhance adhesion of the light emitting chip 200 to other elements, such as a PCB, during subsequent bonding and transfer steps. The connecting electrodes 20ce', 30ce', 40ce', and 50ce' according to the illustrated exemplary embodiment may surround at least a portion of each light emitting stack 20, 30, and 40 to protect the light emitting stack structure, thereby making the light emitting chip 200, together with the passivation layer 90, have a more stable structure that can withstand various subsequent processes. For example, the connection electrodes 20ce', 30ce', 40ce', and 50ce' that substantially surround the light emitting stack structure can absorb at least a part of the stress directly applied to the light emitting stack structure, and protect the light emitting chip during manufacturing.

[0117] According to the illustrated exemplary embodiment, the third connection electrode 40ce is shown as asymmetric with respect to the first connection electrode 20ce. More specifically, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' may have a portion that does not overlap with the passivation layer 90. For example, FIG. 20B shows that the portion of the third connection electrode 40ce' that does not overlap with the passivation layer 90 has a larger area than that of the first connection electrode 20ce' near two opposing ends of the substrate 11. However, the concept of the present invention is not limited in this respect, and in some exemplary embodiments, each of the connection electrodes 20ce', 30ce', 40ce', and 50ce' may be symmetric with respect to one another. For example, the portions of the connection electrodes 20ce', 30ce', 40ce', and 50ce' that do not overlap with the passivation layer 90 may have the same area as one another.

[0118] In the drawing, the passivation layer 90 is formed on the connecting electrodes 20ce', 30ce', and 40ce'. and 50ce' are not formed between the portions of the connection electrodes 20ce', 30ce', 40ce', and 50ce' that are disposed on the upper surface of the passivation layer 90, but the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the passivation layer 90 may be formed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' so that the upper surface of the passivation layer 90 is substantially flush with the upper surfaces of the connection electrodes 20ce', 30ce', 40ce', and 50ce'. This can further strengthen adhesion between the light emitting chip 200 and a printed circuit board or the like in a subsequent process. Note that the portions of the passivation layer 90 that are disposed between the connection electrodes 20ce', 30ce', 40ce', and 50ce' may be formed before or after forming the connection electrodes 20ce', 30ce', 40ce', and 50ce'. Note that the components of the light emitting chip 200 according to the illustrated exemplary embodiment are substantially the same as the components of the light emitting chip 100 described above, and therefore, repeated description of substantially the same components will be omitted to avoid redundancy.

[0119] 21 and 22 are schematic cross-sectional views illustrating a manufacturing process of a light emitting package according to another exemplary embodiment.

[0120] 21, the array of light emitting chips 200 formed on the substrate 11 may be separated from one another and transferred to a carrier substrate 95′ at a desired pitch. For example, in some exemplary embodiments, the light emitting chips 200 may be transferred at a pitch that matches the pitch of electrodes of a target device, such as a circuit board of a display device.

[0121] According to an exemplary embodiment, the singulated light emitting chips 200 may be mounted to a carrier substrate 95′ with an adhesive layer 15′ interposed therebetween. The carrier substrate 95′ and the adhesive layer 15′ are not particularly limited and may be substantially the same as the carrier substrate 95 and the adhesive layer 15, respectively, described above with reference to FIG.

[0122] 22 , after the light emitting chip 200 is mounted on the carrier substrate 95′, a molding layer 91′ (or a first molding layer) may be formed to substantially cover the light emitting chip 200. According to an exemplary embodiment, the molding layer 91′ may transmit a portion of the light emitted from the light emitting chip 200, and may also reflect, diffract, and / or absorb a portion of the external light to prevent the external light from being reflected by the light emitting chip 200 in a direction that can be viewed by a user. The molding layer 91′ may substantially cover the light emitting chip 200 to protect the light emitting chip 200 from external moisture and stress, and may also strengthen the structural configuration of the light emitting package to facilitate subsequent transfer and / or mounting processes.

[0123] According to the illustrated exemplary embodiment, the molding layer 91′ may be formed between the connection electrodes 20ce′, 30ce′, 40ce′, and 50ce′ of the light emitting chip 200 and may cover at least a portion of the passivation layer 90. The molding layer 91′ according to the exemplary embodiment may include, but is not limited to, an epoxy molding compound (EMC) and may be formed in various colors, such as black or transparent. For example, in some exemplary embodiments, the molding layer 91′ may include a photosensitive polyimide dry film (PID). The molding layer 91′ may be formed by various methods known in the art, such as lamination, plating, and / or printing. For example, the molding layer 91′ may be formed by a vacuum lamination process in which an organic polymer sheet is placed on the light emitting chip 200 and high temperature and high pressure are applied in a vacuum to provide a substantially flat upper surface of the light emitting package and thereby improve light uniformity. In some exemplary embodiments, molding layer 91' and passivation layer 90 may comprise substantially the same material or different materials from each other.

[0124] Returning to Figure 18, an insulating layer 11p' may be disposed on the light-emitting chips 200 substantially covered with the molding layer 91', and the array of light-emitting chips 200 formed on the substrate 11 may be singulated by various known methods in the art, thereby providing the light-emitting package 210 of Figure 18.

[0125] FIG. 23 is a schematic cross-sectional view of a luminescent package according to yet another exemplary embodiment, and FIG. 24 is a schematic cross-sectional view of a luminescent package according to yet another exemplary embodiment.

[0126] 23, a light emitting package 220 according to the illustrated exemplary embodiment is substantially the same as the light emitting package 210 of FIG. 18, except that the light emitting package 220 further includes an extended electrode 11c′ and a second molding layer 92′. According to the exemplary embodiment, the extended electrodes 11c′ may be respectively formed on lead electrodes 11pc′ disposed on an insulating layer 11p′, and electrically connected to the connection electrodes 20ce′, 30ce′, 40ce′, and 50ce′ of the light emitting chip 200, respectively.

[0127] The extended electrodes 11c' may be spaced apart from one another and generally have a substantially elongated shape, although the concept of the present invention is not limited to one particular shape for the extended electrodes 11c'. The extended electrodes 11c' according to exemplary embodiments may include, but are not limited to, metals such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof. For example, the extended electrodes 11c' may include two or more metals or multiple different metal layers to reduce stresses imposed thereon by their elongated shape. In some exemplary embodiments, if the extended electrodes 11c' include Cu, an additional metal may be deposited or plated thereon to inhibit oxidation of the Cu. In some exemplary embodiments, if the extended electrodes 11c' include Cu / Ni / Sn, the Cu may prevent Sn from penetrating into the light-emitting stack. The extended electrodes 11c' may also be formed by a metal plating process, without being limited thereto.

[0128] According to the illustrated exemplary embodiment, each of the extended electrodes 11c' may be formed near a distal end of the lead electrode 11pc' facing away from the light emitting chip 200. In this manner, the extended electrodes 11c' are formed near each corner of the light emitting package 220, so that the extended electrodes 11c' can structurally support the light emitting package 220. In some exemplary embodiments, to enhance structural stability, the extended electrodes 11c' may not overlap with the connecting electrodes 20ce', 30ce', 40ce', and 50ce'.

[0129] The second molding layer 92′ may be disposed on the insulating layer 11p′ and substantially surround the extended electrode 11c′. The second molding layer 92′ may include an organic polymer or an inorganic polymer. In some exemplary embodiments, at least one of the first and second molding layers 91′ and 92′ may further include pillars of silica or alumina, for example. In some exemplary embodiments, the second molding layer 92′ may be formed by various methods known in the art, such as lamination, plating, and / or printing. For example, the second molding layer 92′ may be formed by a vacuum lamination process, in which an organic polymer sheet is placed on the light-emitting chip 200 and high temperature and pressure are applied in a vacuum to provide a substantially flat top surface of the light-emitting package 220 and improve light uniformity. In this manner, the light-emitting package 220 may have an enhanced package structure.

[0130] Referring to FIG. 24, a light emitting package 230 according to yet another exemplary embodiment includes a first molding layer 91′ formed on the substrate 11 of the light emitting chip 200 to prevent external light from being reflected by the substrate 11 toward a direction that can be seen by a user. 23. In this case, in some exemplary embodiments, in order to transmit at least 50% of the light emitted from the light emitting chip 200, a portion of the first molding layer 91′ covering the upper surface 11pa′ of the substrate 11 facing away from the insulating layer 11p′ may have a thickness of less than about 100 μm.

[0131] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not intended to be limited to such embodiments, but rather is intended to cover the broader scope of the appended claims and various obvious modifications and equivalents that will be apparent to those skilled in the art.

Claims

1. A substrate; a first light emitting element disposed on the substrate and including a first semiconductor stack; a second light emitting element disposed on the substrate and including a second semiconductor stack; a third light emitting element disposed on the substrate and including a third semiconductor stack; a connection electrode disposed on the substrate and electrically connected to at least one of the first light-emitting element, the second light-emitting element, or the third light-emitting element; a passivation layer covering at least one side surface of the first light-emitting element, the second light-emitting element, or the third light-emitting element; an insulating layer having a first surface and a second surface opposite to each other, the first surface facing at least one of the first semiconductor stack, the second semiconductor stack, or the third semiconductor stack; Including, the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are stacked in this order on the substrate; The first semiconductor stack, the second semiconductor stack, and the third semiconductor stack have successively smaller overlapping areas with the substrate, At least one of the connection electrodes includes a first region extending outward and a second region extending toward a center of at least one of the first semiconductor stack, the second semiconductor stack, or the third semiconductor stack; At least one of the connection electrodes includes a region overlapping with at least one side surface of the first semiconductor stack, the second semiconductor stack, or the third semiconductor stack. Light-emitting device.

2. 10. The light emitting device of claim 1, wherein the first region has a different thickness than the second region.

3. The light emitting device of claim 2 , wherein the thickness of the first region is greater than the thickness of the second region.

4. The light emitting device according to claim 1 , wherein the connecting electrode comprises two or more metals.

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