Semiconductor Devices

Abstract

To provide a small semiconductor device.SOLUTION: A semiconductor device includes a first layer, a second layer, and a third layer formed on a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal grown on the substrate. The third semiconductor layer of the third transistor is formed over the first semiconductor layer and the second semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, and electronic devices may include semiconductor elements and semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] Portable information terminals such as smartphones, tablet devices, and goggle-type displays (head-mounted displays) are becoming increasingly popular. Along with the widespread use of information terminals, various communication standards have been established. For example, the LTE-Advanced standard, also known as the fourth-generation mobile communication system (4G), has begun operation.

[0005] In recent years, advances in information technology, such as the Internet of Things (IoT), which connects electronic devices other than information terminals (e.g., in-vehicle electronic devices, household electrical appliances, homes, buildings, or wearable devices) to the Internet, have led to an increase in the amount of data handled by electronic devices. Furthermore, there is a demand for improved communication speeds for electronic devices such as information terminals.

[0006] To realize IoT, an increasing number of electronic devices will be connected to the Internet, which requires an increase in the number of electronic devices that can be connected at one time. Furthermore, as many electronic devices are connected to the Internet at once, a communication time lag (or delay) occurs. Therefore, in order to accommodate various information technologies, including IoT, a new communication standard called the fifth-generation mobile communication system (5G) is being considered, which will achieve faster communication speeds than 4G, more simultaneous connections, and shorter latency. 5G will use communication frequencies in the 3.7 GHz, 4.5 GHz, and 28 GHz bands.

[0007] Patent Document 1 discloses a semiconductor device in which transistors containing different semiconductor materials are stacked.

[0008] 5G-compatible semiconductor devices are made using semiconductors that use a single element, such as Si, as their main component, or compound semiconductors that use multiple elements, such as Ga and As, as their main components. Furthermore, oxide semiconductors, a type of metal oxide, are attracting attention.

[0009] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0010] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] International Publication No. 2015-147835 [Non-patent literature]

[0012] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0013] It is known that electronic devices generate heat due to the increase in communication speed. Electronic devices have semiconductor devices, which have the problem of malfunctioning due to increased leakage current in high-temperature environments. In addition, electronic devices connected to 5G networks, including IoT, are required to be highly portable and compact. Such electronic devices require multiple devices, such as a power supply control device that supplies power for high-speed operation, a signal processing control device, an arithmetic processing device, and a storage device, which results in a problem of the electronic devices becoming large.

[0014] An object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Another object is to provide a small-sized semiconductor device or the like. Another object is to provide a semiconductor device or the like with high productivity. Another object is to provide a semiconductor device or the like with reduced power consumption. Another object is to provide a semiconductor device or the like with stable operation. Another object is to provide a semiconductor device or the like with high reliability.

[0015] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0016] One embodiment of the present invention is a semiconductor device having a first layer, a second layer, and a third layer formed over a substrate. A first transistor in the first layer has a first semiconductor layer containing silicon (Si). A second transistor in the second layer has a second semiconductor layer containing Ga. A third transistor in the third layer has a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal grown on the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.

[0017] In the above structure, the third transistor is preferably arranged at a position having a region overlapping with the first transistor.

[0018] In the above structure, the third transistor is preferably arranged at a position having a region overlapping with the second transistor.

[0019] In the above structure, the semiconductor device further includes a fourth layer. The fourth transistor included in the fourth layer includes at least one of In and Zn. The fourth transistor is preferably disposed at a position having an overlapping region with the third transistor.

[0020] In the above configuration, it is preferable that a sensor module be disposed on the side of the first layer opposite to the side on which the first transistor is formed. [Effects of the Invention]

[0021] According to one embodiment of the present invention, a semiconductor device or the like with reduced power consumption can be provided. Alternatively, a semiconductor device or the like with stable operation can be provided. Alternatively, a semiconductor device or the like with high reliability can be provided. Alternatively, a semiconductor device or the like with high productivity can be provided. Alternatively, a novel semiconductor device or the like can be provided. Alternatively, a small-sized semiconductor device or the like can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a diagram illustrating a semiconductor device. [Figure 2] FIG. 2 is a diagram illustrating the semiconductor device. [Figure 3] FIG. 3 is a diagram illustrating a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating a semiconductor device. [Figure 5] FIG. 5 is a diagram illustrating a semiconductor device. [Figure 6] 6A and 6B are diagrams illustrating a semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a wireless transceiver. [Figure 8] 8A and 8B are diagrams illustrating an example of the configuration of a wireless transceiver. [Figure 9] FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. [Figure 11]11A to 11C are diagrams showing examples of the configuration of a transistor. [Figure 12] 12A to 12C are diagrams showing examples of the configuration of a transistor. [Figure 13] 13A to 13C are diagrams showing examples of the configuration of a transistor. [Figure 14] FIG. 14 is a diagram illustrating a configuration example of a semiconductor device. [Figure 15] Figure 15A is a diagram explaining the classification of IGZO crystal structures, Figure 15B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 15C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 16] Figure 16A is a top view of a semiconductor wafer, and Figure 16B is an enlarged view of a chip. [Figure 17] Fig. 17A is a flowchart illustrating an example of a manufacturing process for an electronic component, and Fig. 17B is a schematic perspective view of the electronic component. [Figure 18] FIG. 18 is a diagram illustrating an example of an electronic device. [Figure 19] 19A to 19F are diagrams showing an example of an electronic device. [Figure 20] Figure 20 shows the hierarchical structure of IoT networks and trends in required specifications. [Figure 21] Figure 21 is an image diagram of factory automation. [Figure 22] 22A to 22C are diagrams showing the structure of an OS-FET used in calculating the cutoff frequency. [Figure 23] FIG. 23 is a diagram showing the calculation results of the cutoff frequency of an OS-FET. DETAILED DESCRIPTION OF THE INVENTION

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0025] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0026] In addition, in top views (also called "plan views"), perspective views, and the like, some components may be omitted to make the drawings easier to understand.

[0027] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0028] In this specification and the like, the resistance value of a "resistor" may be determined by the length of the wiring, or by connecting a conductive layer having a different resistivity from the conductive layer used in the wiring, or by doping an impurity into a semiconductor layer.

[0029] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0030] In this specification, the terms "above," "upper," "lower," or "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, the expression "conductive layer D above conductive layer C" does not require that conductive layer D be formed in direct contact with conductive layer C, and does not exclude cases where other components are included between conductive layer C and conductive layer D. Furthermore, the terms "above" or "lower" do not exclude cases where components are arranged diagonally.

[0031] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0032] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only an extending wiring. Furthermore, "direct connection" includes a case where wiring formed by different conductive layers is connected via a contact and functions as a single wiring.

[0033] Furthermore, in this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0034] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0035] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0036] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0037] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0038] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0039] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0040] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0041] In this specification, the high power supply voltage VDD (hereinafter simply referred to as "VDD," "H voltage," or "H") refers to a power supply voltage that is higher than the low power supply voltage VSS (hereinafter simply referred to as "VSS," "L voltage," or "L"). VSS refers to a power supply voltage that is lower than VDD. The ground voltage (hereinafter simply referred to as "GND" or "GND voltage") can also be used as VDD or VSS. For example, when VDD is the ground voltage, VSS is a voltage lower than the ground voltage, and when VSS is the ground voltage, VDD is a voltage higher than the ground voltage.

[0042] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0043] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0044] In this specification, the term "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. The term "drain region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0045] In addition, in drawings, etc., to make it easier to understand the voltages of wiring, electrodes, etc., an "H" indicating an H voltage or an "L" indicating an L voltage may be added next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a voltage change occurs may be marked with a "H" or "L" in a box. Furthermore, when a transistor is in the off state, an "x" symbol may be added next to the transistor.

[0046] (Embodiment 1) A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of a semiconductor device 10 included in an electronic device.

[0047] Note that the configuration of the semiconductor device exemplified in this specification and elsewhere is merely an example, and does not necessarily include all of the components. The semiconductor device may include necessary components among those shown in this specification and elsewhere. The semiconductor device may also include components other than those shown in this specification and elsewhere.

[0048] The semiconductor device 10 includes, for example, an antenna array 11, a transmission / reception control device 12, a signal processing device 13, a processor 14, a GPU (Graphics Processing Unit) 15, a power control device 16, a PLD (Programmable Logic Device) 17, a storage device 18, and a display device 19. The transmission / reception control device 12 will be described in detail with reference to FIG. 7.

[0049] FIG. 2 is a diagram illustrating a semiconductor device 10. The semiconductor device 10 includes layers L1, L2, L3, and L4 formed on a substrate. For example, the first transistor included in layer L1 includes a first semiconductor layer containing Si. The second transistor included in layer L2 includes a second semiconductor layer containing Ga. The third transistor included in layer L3 includes a third semiconductor layer containing at least one of In and Zn. The first to third transistors are formed on or above the substrate containing Si. The layer L4 does not include a semiconductor layer.

[0050] The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using crystals grown on the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer. The semiconductor layer of the transistor is a layer in which a channel formation region of the transistor is formed.

[0051] The transmission / reception control device 12 includes a transmission / reception control device 12A and a transmission / reception control device 12B. The power control device 16 includes a power control device 16A and a power control device 16B. For example, the transmission / reception control device 12A, the signal processing device 13, the processor 14, the GPU 15, the power control device 16A, and the PLD 17 are formed on the layer L1. The transmission / reception control device 12B and the power control device 16B are formed on the layer L2. The storage device 18 and the display device 19 are formed on the layer L3. Also, FIG. 2 shows an example in which an antenna array 11 for wireless communication is formed on the layer L4.

[0052] The memory device 18 formed in the layer L3 can be formed of a third transistor having a third semiconductor layer. However, the display device 19 can be formed of a third transistor having a third semiconductor layer different from that of the memory device 18. Specifically, the layer L3 includes a layer L3A and a layer L3B on the layer L3A. For example, the memory device 18 can be formed of a transistor formed in the layer L3A. The display device 19 can be formed of a transistor formed in the layer L3B. In other words, third transistors can be stacked in the layer L3. Note that, although FIG. 2 illustrates an example in which transistors used in different circuits are stacked, the number of third transistors stacked in the layer L3 is not limited.

[0053] 3 is a diagram illustrating the semiconductor device 10 in detail. A transmission / reception control device 12A, a signal processing device 13, a processor 14, a GPU 15, a power control device 16A, and a PLD 17 are formed on a layer L1. A transmission / reception control device 12B and a power control device 16B are formed on a layer L2. A memory device 18 is formed on a layer L3A. The memory device 18 includes memory devices 18A to 18F. A display device 19 is formed on a layer L3B. The display device 19 includes a gate driver 19A and a display area 19B. An antenna array 11 for wireless communication is formed on a layer L4. The antenna array 11 includes a plurality of antennas 11A.

[0054] The transmission / reception control device 12A formed on the layer L1 has the function of processing signals transmitted and received via the antenna 11 A. The transmission / reception control device 12B formed on the layer L2 has either a transistor or a diode capable of supplying sufficient power to be instantaneously used by the transmission / reception control device 12A.

[0055] The signal processing device 13 can provide a control signal to the gate driver 19A via the layer L3A and further provide image data to the display area 19B. Therefore, the signal processing device 13 can function as an image processing device. The signal processing device 13 can perform expansion and conversion of image data using the GPU 15. The expansion and conversion includes filtering processing of the display image, pixel count conversion processing, etc.

[0056] The processor 14 controls the semiconductor device 10. The GPU 15 can perform some of the calculations at high speed when performing learning or inference of artificial intelligence (AI) processed by the signal processing device 13 or the like. As an example, inference of AI often involves matrix calculations using neural networks. The matrix calculations can be performed efficiently and quickly by using the GPU 15.

[0057] The power supply control device 16A formed on the layer L1 can control the supply of power to the transmission / reception control device 12, the signal processing device 13, the processor 14, the GPU 15, the PLD 17, the storage device 18, or the display device 19. The power supply control device 16B formed on the layer L2 has either a transistor or a diode capable of supplying sufficient power to be used by the semiconductor device 10.

[0058] The PLD 17 can provide different functions by updating its logical configuration. As an example, the PLD 17 can function as a storage device. The signal processing device can temporarily store previous display data displayed on the display device 19 (described later) and easily detect the difference between the previous display data and the display data received by the transmission / reception control device 12. As another example, the PLD 17 can extend part of the calculation function of the signal processing device 13 or the GPU 15. For example, the number of parallel operations can be extended when performing parallel calculations.

[0059] Next, the layer L2 will be described. The layer L2 is formed by crystal growth on the substrate of the layer L1. Therefore, the first transistor formed using the layer L1 is arranged so as not to overlap with the second transistor formed using the layer L2. The second semiconductor layer of the second transistor preferably contains Ga. Furthermore, the second semiconductor layer of the second transistor preferably contains nitrogen or oxygen.

[0060] Layer L2 includes a transmission / reception control device 12B and a power supply control device 16B. The transmission / reception control device 12B can supply a large amount of power for instantaneous use by the transmission / reception control device 12A. The power supply control device 16B also supplies power to the transmission / reception control device 12A, signal processing device 13, processor 14, GPU 15, power supply control device 16A, and PLD 17, which are arranged on layer L1. The power supply control device 16B can also supply power to a storage device 18 formed on layer L3A and a display device 19 formed on layer L3B.

[0061] Next, the layer L3 will be described. First, the layer L3A formed on the layer L1 will be described.

[0062] A storage device 18A is preferably arranged on the transmission / reception control device 12A. A storage device 18B is preferably arranged on the signal processing device 13. A storage device 18C is preferably arranged on the processor 14. A storage device 18F is preferably arranged on the GPU 15. A storage device 18D is preferably arranged on the power supply control device 16A. A storage device 18E is preferably arranged on the PLD 17.

[0063] Note that any of the memory devices 18A to 18F can function as a data saving register. As another example, any of the memory devices 18A to 18F can function as a data management memory. As another example, any of the memory devices 18A to 18F can function as a FIFO memory (First in First out memory) that accommodates different processing speeds between the devices. For example, the FIFO memory temporarily stores data received by the transmission / reception control device 12, and the signal processing device 13 can read the data from the FIFO memory using the processor 14. In this case, the transmission / reception control device 12 can operate at an operating frequency different from that of the signal processing device 13 or the processor 14. It is also preferable that the memory device 18E stores multiple pieces of logic information to be configured in the PLD 17.

[0064] The memory device 18 includes a third transistor. The third semiconductor layer of the third transistor preferably contains oxygen and at least one of In, Ga, and Zn. Therefore, the third semiconductor layer of the third transistor can be referred to as including an oxide semiconductor. A transistor including an oxide semiconductor (OS), which is a type of metal oxide, in a semiconductor layer in which a channel of the transistor is formed is called an "OS transistor" or an "OS-FET." It is known that the electrical characteristics of an OS transistor vary little with temperature. Furthermore, because the energy gap of the semiconductor layer of an OS transistor is large, the OS transistor can exhibit extremely low off-state current, with a current value of several yA per 1 μm of channel width. Therefore, it is preferable to apply an OS transistor to a memory device. The OS transistor will be described in detail in Embodiment 2.

[0065] Here, a memory device using an OS transistor will be described. When an OS transistor is used in a memory device, the memory device can be called an "OS memory."

[0066] The OS memory can suppress the degradation of data stored in the OS memory even when the power supply is stopped. Furthermore, the OS memory can provide a storage device suitable for high density storage because it can reduce the capacity to store data. Furthermore, by utilizing the extremely low off-state current characteristics of the OS transistor, the OS memory can retain written information for more than one year, or even more than ten years. Therefore, the OS memory can be considered a nonvolatile memory.

[0067] Furthermore, because OS memory writes charge to nodes via OS transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, because there is no charge injection or extraction into or from the floating gate or charge trapping layer, OS memory allows for virtually unlimited data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, making it highly reliable.

[0068] Furthermore, OS memory does not involve structural changes at the atomic level, as occurs in magnetic memory or resistance change memory, etc. Therefore, OS memory has better rewrite endurance than magnetic memory and resistance change memory.

[0069] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Furthermore, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device with stable operation and high reliability can be realized even in a high-temperature environment.

[0070] Furthermore, the OS transistor can be formed by sputtering during a back-end-of-line (BEOL) process for forming wiring for a semiconductor device. Therefore, a single semiconductor device 10 can be formed using transistors with different transistor characteristics. In other words, the use of OS transistors makes it easy to form a system on chip (SoC).

[0071] The OS transistor may have a back gate. The back gate is disposed so that the channel formation region of the third semiconductor layer is sandwiched between the gate and the back gate. The back gate can function similarly to the gate. The threshold voltage of the transistor can be changed by changing the voltage of the back gate. The voltage of the back gate may be the same as that of the gate, or may be GND or any other voltage.

[0072] In addition, since the gate and back gate are generally formed of conductive layers, they have the function of preventing electric fields generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly, electrostatic shielding function against static electricity), which means that fluctuations in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity can be prevented.

[0073] Next, the layer L3B will be described. The display device 19 is formed by the transistors included in the layer L3B. Although not described in detail in this specification, the display region 19B has a plurality of pixels, each of which has a light-emitting element. It is preferable to use an organic light-emitting device (OLED) or a light-emitting device (LED) as the light-emitting element.

[0074] Next, layer L4 will be described. The antenna array 11 has a plurality of antennas 11A. The antennas 11A are preferably formed of a light-transmitting conductive layer. The light-transmitting conductive layer may be made of indium oxide, ITO, indium zinc oxide, zinc oxide, zinc oxide doped with gallium, or the like.

[0075] Fig. 4 is a diagram illustrating a semiconductor device 10A having a different configuration from the semiconductor device 10 shown in Fig. 2. In the configuration described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted.

[0076] The semiconductor device 10A differs from the semiconductor device 10 in that the layer L3B includes the display device 19, the memory device 18G, and the memory device 18H. The third transistors included in the display device 19, the memory device 18G, and the memory device 18H are formed in the same process.

[0077] FIG. 5 is a diagram illustrating the semiconductor device 10A in detail. The semiconductor device 10A differs from the semiconductor device 10 shown in FIG. 3 in that the layer L3B has a portion overlapping with the layer L2. For example, a storage device 18G is preferably disposed on the transmission / reception control device 12B. The storage device 18G stores setting information for the transmission / reception control device 12B. A storage device 18H is preferably disposed on the power supply control device 16B. The storage device 18H stores setting information for the power supply control device 16B. The storage devices 18G and 18H preferably use OS memory.

[0078] FIG. 6A is a block diagram showing the configuration of a semiconductor device 10B different from the semiconductor device 10 shown in FIG. 1. The semiconductor device 10B shown in FIG. 6A has a sensor module 20. FIG. 6B is a diagram illustrating the semiconductor device 10B having a different configuration from the semiconductor device 10 shown in FIG. 2. The semiconductor device 10B has a layer L5 below the layer L1 (opposite the layer L2). The sensor module 20 is disposed on the layer L5. The sensor module 20 can be electrically connected to the layer L1 using a through silicon via (TSV). The sensor module 20 can be an image sensor, an infrared sensor, an ultrasonic sensor, a touch sensor, or the like.

[0079] As an example, a case will be described in which the sensor module 20 is an image sensor. The semiconductor device 10B can display information captured by the sensor module 20 as an image on the display device 19.

[0080] The semiconductor device 10B can be configured as an SoC that includes wireless communication, a signal processing unit that performs image data expansion and conversion, a display device, and a sensor module, thereby reducing the number of components. Therefore, the semiconductor device 10B is suitable for use in mobile terminals including goggle-type displays, which require small and lightweight semiconductor devices.

[0081] 7 is a diagram illustrating an example of the configuration of a wireless transceiver 900 as an example of the transmission / reception control device 12. The wireless transceiver 900 includes a low noise amplifier (LNA) 901, a band pass filter (BPF) 902, a mixer (MIX) 903, a band pass filter 904, a demodulator (DEM) 905, a power amplifier (PA) 911, a band pass filter 912, a mixer 913, a band pass filter 914, a modulator (MOD) 915, a duplexer (DUP) 921, a local oscillator (LO) 922, and an antenna 931.

[0082] <Receive> A signal 941 transmitted from another semiconductor device or a base station or the like is input as a received signal to the low-noise amplifier 901 via the antenna 931 and the duplexer 921. The duplexer 921 has a function of realizing transmission and reception of a radio signal with one antenna.

[0083] Low-noise amplifier 901 has the function of amplifying a weak received signal to a signal with a strength that can be processed by radio transceiver 900. Signal 941 amplified by low-noise amplifier 901 is supplied to mixer 903 via band-pass filter 902.

[0084] Bandpass filter 902 has the function of attenuating frequency components outside a required frequency band from among the frequency components contained in signal 941, and passing the required frequency band.

[0085] Mixer 903 has the function of superheterodyne mixing signal 941 that has passed through bandpass filter 902 and signal 943 generated by local oscillator 922. Mixer 903 mixes signal 941 and signal 943 and supplies a signal having a difference frequency component and a sum frequency component of the two signals to bandpass filter 904.

[0086] The bandpass filter 904 has a function of passing one of the two frequency components. For example, it passes the difference frequency component. The bandpass filter 904 also has a function of removing noise components generated in the mixer 903. The signal that has passed through the bandpass filter 904 is supplied to the demodulator 905. The demodulator 905 has a function of converting the supplied signal into a control signal, a data signal, or the like, and outputting the signal. The signal output from the demodulator 905 is supplied to various processing devices (such as an arithmetic device or a storage device).

[0087] <Send> The modulator 915 has a function of generating a basic signal for transmitting a control signal, a data signal, etc. from the wireless transceiver 900 to another semiconductor device or a base station. The basic signal is supplied to the mixer 913 via a bandpass filter 914.

[0088] The bandpass filter 914 has the function of removing noise components that occur when the fundamental signal is generated by the modulator 915 .

[0089] Mixer 913 has the function of superheterodyne mixing the fundamental signal that has passed through bandpass filter 914 with signal 944 generated by local oscillator 922. Mixer 913 mixes the fundamental signal with signal 944 and supplies a signal having a difference frequency component and a sum frequency component between the two to bandpass filter 912.

[0090] Bandpass filter 912 has a function of passing one of two frequency components. For example, it passes the sum frequency component. Bandpass filter 912 also has a function of removing noise components generated in mixer 913. The signal that has passed through bandpass filter 912 is supplied to power amplifier 911.

[0091] Power amplifier 911 has a function of amplifying the supplied signal to generate signal 942. Signal 942 is radiated from antenna 931 via duplexer 921 to the outside.

[0092] 8A and 8B, a wireless transceiver 900A, which is a modification of the above-described wireless transceiver 900, will be described. To reduce repetition of the description, differences from wireless transceiver 900 will be mainly described.

[0093] The wireless transceiver 900A is compatible with the 5G communication standard and therefore has multiple antennas 931. It also has multiple duplexers 921, multiple low-noise amplifiers 901, and multiple power amplifiers 911. The wireless transceiver 900A also has a decoder circuit 906 (DEC) and a decoder circuit 916.

[0094] 8A shows a case where there are five antennas 931, five duplexers 921, five low-noise amplifiers 901, and five power amplifiers 911. In FIG. 8A, the first antenna 931 is shown as antenna 931[1], and the fifth antenna 931 is shown as antenna 931[5]. The duplexers 921, the low-noise amplifiers 901, and the power amplifiers 911 are also denoted in the same manner as the antenna 931. Note that the number of antennas 931, the duplexers 921, the low-noise amplifiers 901, and the power amplifiers 911 is not limited to five.

[0095] The antenna 931[1] is electrically connected to the duplexer 921[1]. The duplexer 921[1] is electrically connected to the low-noise amplifier 901[1] and the power amplifier 911[1]. The antenna 931[5] is electrically connected to the duplexer 921[5]. The duplexer 921[5] is electrically connected to the low-noise amplifier 901[5] and the power amplifier 911[5]. The second to fourth antennas 931 are also electrically connected to the second to fourth duplexers 921, just like the antenna 931[1]. The second to fourth duplexers 921 are also electrically connected to the second to fourth low-noise amplifiers 901 and the second to fourth power amplifiers 911, just like the duplexer 921[1].

[0096] The decoder circuit 906 is electrically connected to a plurality of low-noise amplifiers 901. In FIG. 8A, five low-noise amplifiers 901 are connected to the decoder circuit 906. The decoder circuit 916 is also electrically connected to a plurality of power amplifiers 911. In FIG. 8A, five power amplifiers 911 are connected to the decoder circuit 916.

[0097] The decoder circuit 906 has a function of selecting one or more of the low-noise amplifiers 901[1] to 901[5]. The decoder circuit 906 also has a function of sequentially selecting the low-noise amplifiers 901[1] to 901[5]. Similarly, the decoder circuit 916 has a function of selecting one or more of the power amplifiers 911[1] to 911[5]. The decoder circuit 916 also has a function of sequentially selecting the power amplifiers 911[1] to 911[5].

[0098] 8B shows an example of a connection between the decoder circuit 906 and the low-noise amplifier 901[1] and the low-noise amplifier 901[2]. The decoder circuit 906 is electrically connected to the memory element 111 (referred to as memory element 111[1]) included in the low-noise amplifier 901[1] via a terminal 124 to which the memory element 111[1] is electrically connected. The decoder circuit 906 is also electrically connected to the memory element 111 (referred to as memory element 111[2]) included in the low-noise amplifier 901[2] via a terminal 124 to which the memory element 111[2] is electrically connected.

[0099] The memory element 111 includes a transistor 112 and a capacitor 113. A gate of the transistor 112 is electrically connected to a terminal 124. One of the source and the drain of the transistor 112 is electrically connected to a terminal 123. The other of the source and the drain of the transistor 112 is electrically connected to one electrode of the capacitor 113 and the gate of the transistor 115. Note that the node 114 is formed on a wiring to which the other of the source and the drain of the transistor 112, one electrode of the capacitor 113, and the gate of the transistor 115 are electrically connected. The terminal 124 is electrically connected to one of the source and the drain of a transistor 116 in the decoder circuit 906. Note that the transistor 112 is preferably an OS transistor. The memory element 111 using an OS transistor can be referred to as an OS memory.

[0100] The terminal 123 electrically connected to the memory element 111[1] and the terminal 123 electrically connected to the memory element 111[2] are electrically connected to a wiring 126. A voltage (charge) written to the node 114 is supplied through the wiring 126.

[0101] The decoder circuit 906 has a function of supplying a signal for turning on or off the transistor 112 to a terminal 124 electrically connected to any of the memory elements 111. By sequentially selecting the memory elements 111 included in the low-noise amplifier 901 using the decoder circuit 906, a different voltage can be written to the node 114 for each memory element 111. In other words, a voltage suitable for each of the multiple low-noise amplifiers 901 can be written to the node 114.

[0102] The decoder circuit 916 also functions in the same way as the decoder circuit 906 for the multiple power amplifiers 911 .

[0103] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0104] (Embodiment 2) In this embodiment, a structure of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0105] FIG. 9 shows a part of a cross-sectional structure of a semiconductor device. The semiconductor device shown in FIG. 9 includes a transistor 550, a transistor 500, a transistor 650, and a capacitor 600. FIG. 11A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 11C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 corresponds to the transistor 112, the transistor 550 corresponds to the transistor 116, and the transistor 650 corresponds to the transistor 115, all of which are shown in the above embodiment. The capacitor 600 corresponds to the capacitor 113. The wirings 2001 to 2006 can be electrically connected to other transistors or the like. The wiring 2005 is electrically connected to the wiring 2006.

[0106] In this specification, the expression "stacked transistors are arranged in an overlapping position" is sometimes used. The term "transistor range" refers to a range that includes a channel formation region of a transistor and a region in which a semiconductor layer of the transistor functions as a source or a drain.

[0107] 9, the transistor 500 is arranged so as to overlap with the transistor 550, which means that part of one of the source or drain regions of the transistor 500 overlaps with one of the source or drain regions of the transistor 550. Furthermore, part of the one of the source or drain regions of the transistor 500 overlaps with one of the source or drain regions of the transistor 550.

[0108] 9, for the sake of explanation, an example is shown in which transistor 500 is arranged in a position overlapping transistor 550 and transistor 650. However, transistor 550 is a transistor included in layer L1, and transistor 650 is a transistor included in layer L2. Furthermore, transistor 500 is a transistor included in layer L3.

[0109] The transistor 500 is an OS transistor. The off-state current of the transistor 500 is extremely low. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of refresh operations of the storage node can be reduced or no refresh operations are required, thereby reducing the power consumption of the semiconductor device.

[0110] In FIG. 9, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0111] The transistor 550 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b.

[0112] 11C , in the transistor 550, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 550 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0113] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0114] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0115] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0116] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0117] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0118] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0119] The SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have occurred in the surface layer, or an SOI substrate formed using the Smart Cut method or the ELTRAN (registered trademark: Epitaxial Layer Transfer) method, which cleaves a semiconductor substrate by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0120] 10 illustrates a transistor 550A as the third transistor included in the layer L3A and a transistor 500 as the third transistor included in the layer L3B. Note that in FIG. 10, the transistor 550A is electrically connected to the transistor 500. However, when the transistor 550A is included in a memory device and the transistor 500 is included in a display device, the transistor 550A is not necessarily connected to the transistor 500.

[0121] 9 and the transistor 500 or 550A shown in FIG. 10 are merely examples, and the present invention is not limited to these configurations. Appropriate transistors may be used depending on the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit including only OS transistors (meaning transistors of the same conductivity type, such as only n-channel transistors), the transistor 550A may have the same configuration as the transistor 500, as shown in FIG. 10. The details of the transistor 500 will be described later.

[0122] Here, the transistor 650 will be described. The transistor 650 is formed on the same substrate as the transistor 550. The transistor 650 is formed using a semiconductor layer formed on a single crystal silicon substrate, a sapphire substrate, or an SOI substrate. The semiconductor layer preferably has a crystal structure containing gallium. Examples of semiconductor layers containing gallium include gallium nitride (hereinafter, referred to as GaN) and gallium oxide (GaOx).

[0123] A semiconductor device using GaN for the semiconductor layer 654 will be described with reference to Fig. 9. For example, GaN can be formed by providing a low-temperature buffer layer 652 on the substrate 311 and epitaxially growing single-crystal GaN on the low-temperature buffer layer 652. The single-crystal GaN formed by epitaxial growth corresponds to the semiconductor layer 654. Note that Fig. 9 shows an example in which a single-crystal silicon substrate is used for the substrate 311.

[0124] When forming the transistor 650, it is preferable to use a semiconductor layer in which a semiconductor layer 656 is epitaxially grown on a semiconductor layer 654. The semiconductor layer 654 is preferably GaN, and the semiconductor layer 656 is preferably AlGaN. For example, aluminum nitride (AlN) is known to have excellent material properties, such as a band gap (6.2 eV) approximately twice that of GaN, an electrostatic breakdown field (12 MV / cm) approximately four times that of GaN, and a thermal conductivity (2.9 W / cmK) approximately 1.5 times that of GaN. Therefore, AlN and AlGaN, an alloy of AlN and GaN, are preferable materials for high-power, high-frequency devices. A high-electron mobility transistor (HEMT) with an AlGaN channel region can operate at a higher voltage than a HEMT with a GaN channel region. At the interface between GaN and AlGaN, a two-dimensional electron gas (2DEG) is generated due to the polarization effect between GaN and AlGaN. In other words, in a transistor with a HEMT structure, the 2DEG serves as the channel region.

[0125] The conductor 330 is provided over the semiconductor layer 656. The conductor 330 corresponds to the source or drain of the transistor 650.

[0126] The insulator 324 is sandwiched between the conductor 658 and the semiconductor layer 656. The conductor 658 can also be a gate electrode, and the insulator 324 can also be a gate insulator of the transistor 650. The insulator 324 can be made of silicon oxide, aluminum oxide, hafnium oxide, or the like. For example, the insulator 324 containing any one of silicon oxide, aluminum oxide, and hafnium oxide reduces the off-state current of the transistor 650. To describe the gate insulator in more detail, the gate insulator is preferably a SiO2 film, an Al2O3 film, or a HfO2 film.

[0127] Furthermore, the transistor 650 preferably has a recessed gate structure. FIG. 9 illustrates an example in which the transistor 650 has a recessed gate structure. The recessed gate structure of the transistor 650 reduces the off-state current of the transistor 650. The recessed gate structure is formed by etching the semiconductor layer 656 at a position overlapping the gate electrode that forms the channel formation region, thereby thinning the semiconductor layer 656. The region of the semiconductor layer 656 thinned by etching is called the recessed region. The recessed region has a high threshold voltage due to enhanced depletion of the 2DEG. Furthermore, the non-recessed region can pass a large current due to the increased concentration of the 2DEG.

[0128] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 550.

[0129] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0130] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0131] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0132] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 550, or the like to a region where the transistor 500 is provided.

[0133] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be suitably used. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0134] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0135] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0136] Furthermore, insulators 320, 322, 324, and 326 are embedded with conductors 328 and 330, which are connected to capacitor 600 or transistor 500. Conductor 330 functions as a source or drain electrode of transistor 650. Conductors 328 and 330 also function as plugs or wiring. Conductors that function as plugs or wiring may be collectively designated by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a portion of a conductor may function as a wiring, and a portion of a conductor may function as a plug.

[0137] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0138] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 9, the insulator 350, the insulator 352, and the insulator 354 are stacked in this order. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug connected to the transistor 550, a plug connected to the transistor 650, or a wiring. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0139] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 or the transistor 650 can be separated from the transistor 500 by a barrier layer, and diffusion of hydrogen from the transistor 550 or the transistor 650 to the transistor 500 can be suppressed.

[0140] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0141] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 9, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using the same material as the conductors 328 and 330.

[0142] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 or the transistor 650 can be separated from the transistor 500 by a barrier layer, and diffusion of hydrogen from the transistor 550 or the transistor 650 to the transistor 500 can be suppressed.

[0143] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 9, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0144] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 or the transistor 650 can be separated from the transistor 500 by a barrier layer, and diffusion of hydrogen from the transistor 550 or the transistor 650 to the transistor 500 can be suppressed.

[0145] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 9, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0146] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 or the transistor 650 can be separated from the transistor 500 by a barrier layer, and diffusion of hydrogen from the transistor 550 or the transistor 650 to the transistor 500 can be suppressed.

[0147] 14 shows an example in which the transistor 550 is connected to the transistor 650 through the conductor 366. However, the wiring connecting the transistor 550 to the transistor 650 is not limited to the conductor 366.

[0148] Although the above describes a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386, the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0149] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0150] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the region where the transistor 550 is provided, or the region where the transistor 650 is provided to the region where the transistor 500 is provided. Therefore, the insulator 510 and the insulator 514 can be formed using a material similar to that of the insulator 324.

[0151] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550 or the transistor 650. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0152] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0153] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0154] For example, the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulators 512 and 516 can be made of a silicon oxide film or a silicon oxynitride film.

[0155] A conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503) are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600, the transistor 550, or the transistor 650. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0156] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 or the transistor 650 can be separated from the transistor 500 by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 or the transistor 650 to the transistor 500 can be suppressed.

[0157] Above the insulator 516 is the transistor 500 .

[0158] As shown in Figures 11A and 11B, transistor 500 has conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, insulator 520 arranged on insulator 516 and conductor 503, insulator 522 arranged on insulator 520, insulator 524 arranged on insulator 522, oxide 530a arranged on insulator 524, oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, insulator 580 arranged on conductors 542a and 542b and having an opening formed therebetween overlapping conductors 542a and 542b, insulator 545 arranged on the bottom and side surfaces of the opening, and conductor 560 arranged on the surface on which insulator 545 is formed.

[0159] 11A and 11B, it is preferable that insulator 544 be disposed between oxide 530a, oxide 530b, conductor 542a, and conductor 542b and insulator 580. It is preferable that conductor 560 have conductor 560a disposed inside insulator 545 and conductor 560b disposed so as to be embedded inside conductor 560a. It is preferable that insulator 574 be disposed on insulator 580, conductor 560, and insulator 545, as shown in FIGS.

[0160] In this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0161] Note that although the transistor 500 has a two-layer structure of the oxide 530a and the oxide 530b in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the oxide 530b may be a single layer or a stack of three or more layers.

[0162] Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistors 500 illustrated in FIGS. 9, 10, 11A, and 14 are merely examples and are not limited to these structures. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0163] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0164] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0165] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the voltage applied to the conductor 503 independently of the voltage applied to the conductor 560. In particular, applying a negative voltage to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative voltage to the conductor 503 can reduce the drain current when the voltage applied to the conductor 560 is 0 V compared to when no negative voltage is applied.

[0166] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a voltage is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0167] In this specification, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (S-channel) structure. In this specification, the S-channel structure is characterized in that the side and periphery of the oxide 530 in contact with the conductors 542a and 542b, which function as source and drain electrodes, are I-type, just like the channel formation region. Furthermore, the side and periphery of the oxide 530 in contact with the conductors 542a and 542b can be I-type, just like the channel formation region, because they are in contact with the insulator 544. In this specification, I-type can be treated as the same as high-purity intrinsic oxide, as described later. The S-channel structure disclosed in this specification differs from the fin type and planar type structures. The S-channel structure enhances resistance to the short-channel effect, or in other words, can provide a transistor that is less susceptible to the short-channel effect.

[0168] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductors 503a and 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0169] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0170] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0171] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single-layer structure.

[0172] The insulators 520, 522, and 524 function as a second gate insulating film.

[0173] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen." In other words, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V O H.) functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0174] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0175] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O The reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO, which may be removed from the oxide 530 or an insulator near the oxide 530. Some of the hydrogen may also be gettered to the conductor 542.

[0176] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0177] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0178] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0179] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0180] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0181] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film allows for a reduction in gate voltage during transistor operation while maintaining the physical film thickness.

[0182] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0183] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0184] Furthermore, it is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a layered structure that is thermally stable and has a high dielectric constant.

[0185] 11A and 11B, the second gate insulating film has a three-layer structure including insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0186] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. Note that the oxide semiconductor preferably contains at least one of In and Zn. For example, the oxide 530 may be a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like).

[0187] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in other embodiments.

[0188] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0189] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0190] Preferably, oxide 530 has a configuration of multiple oxide layers with different atomic ratios of each metal atom. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of element M to In in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0191] The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.

[0192] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0193] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0194] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0195] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0196] 11, the conductor 542a and the conductor 542b are shown as a single layer, but they may be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0197] Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0198] 11A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as either a source region or a drain region, and the region 543b functions as the other. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0199] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0200] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0201] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0202] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen, the insulator 544 is not an essential component. It can be designed appropriately depending on the desired transistor characteristics.

[0203] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b through the insulator 545. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen.

[0204] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0205] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0206] By using an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0207] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0208] The insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate voltage during transistor operation while maintaining the physical film thickness. Furthermore, a layered structure that is thermally stable and has a high dielectric constant can be achieved.

[0209] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 11A and 11B, but may have a single-layer structure or a stacked structure of three or more layers.

[0210] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The oxygen-suppressing function of the conductor 560a can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 545, which can reduce the conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, an oxide semiconductor that can be used for the oxide 530 can be used for the conductor 560a. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0211] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Because the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0212] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of an excess oxygen region in a later step.

[0213] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0214] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0215] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0216] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0217] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0218] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0219] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0220] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0221] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0222] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0223] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0224] Furthermore, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0225] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using the same materials as the conductor 328 and the conductor 330.

[0226] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0227] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 has a conductor 610, a conductor 620, and an insulator 630.

[0228] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed in the same process.

[0229] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0230] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0231] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed using the same process as other components such as the conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0232] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0233] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0234] Examples of substrates that can be used in the semiconductor device of one embodiment of the present invention include glass substrates, quartz substrates, sapphire substrates, ceramic substrates, metal substrates (e.g., stainless steel substrates, substrates having stainless steel foil, tungsten substrates, and substrates having tungsten foil), semiconductor substrates (e.g., single-crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor substrates), and silicon-on-insulator (SOI) substrates. Plastic substrates that have heat resistance sufficient to withstand the processing temperatures of this embodiment may also be used. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Crystallized glass, for example, can also be used.

[0235] Alternatively, flexible substrates, laminated films, paper containing fibrous materials, or base films can be used as the substrate. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Synthetic resins such as acrylic are also included. Polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride are also included. Polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, and paper are also included. In particular, transistors manufactured using semiconductor substrates, single-crystal substrates, or SOI substrates can be manufactured to have small size, high current capacity, and minimal variations in characteristics, size, and shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0236] Alternatively, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. The release layer can be used to separate a semiconductor device, after it has been partially or entirely completed, from the substrate and transfer it to another substrate. In this case, the transistors, resistors, and / or capacitors can be transferred to a substrate with poor heat resistance or a flexible substrate. The release layer may be, for example, a laminated structure of an inorganic film such as a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0237] That is, a semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which a semiconductor device may be transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture semiconductor devices that are flexible, durable, heat-resistant, lightweight, or thin.

[0238] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0239] <Transistor variation 1> A transistor 500A illustrated in FIGS. 12A to 12C is a modification of the transistor 500 having the structure illustrated in FIGS. 11A and 11B. FIG. 12A is a top view of the transistor 500A, FIG. 12B is a cross-sectional view of the transistor 500A in the channel length direction, and FIG. 12C is a cross-sectional view of the transistor 500A in the channel width direction. Note that some elements are omitted from the top view in FIG. 12A for clarity. Note that the structures illustrated in FIGS. 12A to 12C can also be applied to other transistors, such as the transistor 550, included in the semiconductor device of one embodiment of the present invention.

[0240] 12A to 12C differs from the transistor 500 shown in FIGS. 11A and 11B in that the transistor 500A includes an insulator 552, an insulator 513, and an insulator 404. The transistor 500A also differs from the transistor 500 in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. The transistor 500A also differs from the transistor 500 in that the transistor 500A does not include the insulator 520.

[0241] 12A to 12C, an insulator 513 is provided over an insulator 512. Furthermore, an insulator 404 is provided over the insulator 574 and the insulator 513.

[0242] 12A to 12C , the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 513. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 513.

[0243] The insulators 513 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 513 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500A. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0244] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0245] <Transistor variation 2> An example configuration of a transistor 500B will be described using Figures 13A, 13B, and 13C. Figure 13A is a top view of the transistor 500B. Figure 13B is a cross-sectional view of the L1-L2 portion indicated by the dashed-dotted line in Figure 13A. Figure 13C is a cross-sectional view of the W1-W2 portion indicated by the dashed-dotted line in Figure 13A. Note that in the top view of Figure 13A, some elements are omitted for clarity.

[0246] The transistor 500B is a modified example of the transistor 500 and can be substituted for the transistor 500. Therefore, to avoid repetition of the description, the differences from the transistor 500 will be mainly described.

[0247] The conductor 560 functioning as the first gate electrode includes a conductor 560a and a conductor 560b on the conductor 560a. The conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, the conductor 560a is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0248] The conductor 560a has the function of suppressing oxygen diffusion, which improves the material selectivity of the conductor 560b. That is, the presence of the conductor 560a suppresses oxidation of the conductor 560b, thereby preventing a decrease in conductivity.

[0249] Furthermore, it is preferable to provide an insulator 544 so as to cover the top surface and side surfaces of the conductor 560 and the side surfaces of the insulator 545. Note that the insulator 544 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0250] Providing the insulator 544 can suppress oxidation of the conductor 560. Furthermore, including the insulator 544 can suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 into the transistor 500B.

[0251] In the transistor 500B, the conductor 560 overlaps part of the conductor 542a and part of the conductor 542b, and therefore the parasitic capacitance of the transistor 500B is likely to be larger than that of the transistor 500. Therefore, the operating frequency of the transistor 500B tends to be lower than that of the transistor 500. However, the transistor 500B has higher productivity than the transistor 500 because it does not require a step of forming an opening in the insulator 580 or the like and filling it with the conductor 560, the insulator 545, or the like.

[0252] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0253] (Embodiment 3) In this embodiment, an oxide semiconductor, which is a type of metal oxide, will be described.

[0254] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0255] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 15A. Fig. 15A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0256] As shown in FIG. 15A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0257] The structure within the bold frame in Figure 15A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "amorphous" or "crystal."

[0258] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 15B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 15B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 15B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 15B is 500 nm.

[0259] As shown in Figure 15B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 15B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0260] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 15C. Figure 15C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 15C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0261] As shown in FIG. 15C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0262] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 15A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0263] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0264] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0265] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0266] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0267] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0268] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0269] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0270] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current and field-effect mobility of transistors. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0271] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0272] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0273] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0274] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0275] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0276] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0277] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0278] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0279] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0280] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0281] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0282] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0283] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0284] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0285] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0286] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0287] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0288] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0289] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0290] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0291] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0292] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0293] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0294] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0295] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0296] (Fourth embodiment) In this embodiment, an application example of the above-described semiconductor device will be described.

[0297] [Semiconductor wafers, chips] 16A illustrates a top view of a substrate 711 before dicing. The substrate 711 can be, for example, a semiconductor substrate (also referred to as a "semiconductor wafer"). A plurality of circuit regions 712 are provided over the substrate 711. The circuit region 712 can include a semiconductor device according to one embodiment of the present invention, a CPU, an RF tag, an image sensor, or the like.

[0298] Each of the multiple circuit regions 712 is surrounded by an isolation region 713. Separation lines (also called "dicing lines") 714 are set at positions overlapping the isolation regions 713. By cutting the substrate 711 along the separation lines 714, chips 715 including the circuit regions 712 can be cut out from the substrate 711. An enlarged view of the chips 715 is shown in FIG. 16B.

[0299] Furthermore, a conductor or a semiconductor layer may be provided in the separation region 713. By providing a conductor or a semiconductor layer in the separation region 713, ESD that may occur during the dicing process can be mitigated, and a decrease in the yield of the dicing process can be prevented. Furthermore, the dicing process is generally performed while pure water, in which carbon dioxide or the like is dissolved to reduce the resistivity, is flowed over the cutting area for the purposes of cooling the substrate, removing shavings, preventing static electricity, etc. By providing a conductor or a semiconductor layer in the separation region 713, the amount of pure water used can be reduced. This can reduce the production cost of the semiconductor device. Furthermore, the productivity of the semiconductor device can be increased.

[0300] It is preferable to use a material having a band gap of 2.5 eV to 4.2 eV, preferably 2.7 eV to 3.5 eV, for the semiconductor layer provided in the separation region 713. Use of such a material allows the accumulated charge to be slowly discharged, thereby suppressing the sudden movement of charge due to ESD and making it difficult for electrostatic breakdown to occur.

[0301] [Electronic Components] An example of applying chip 715 to an electronic component will be described with reference to Fig. 17. The electronic component is also called a semiconductor package or an IC package. There are multiple standards and names for electronic components depending on the terminal lead-out direction and terminal shape.

[0302] The electronic component is completed by combining the semiconductor device shown in the above embodiment with components other than the semiconductor device in an assembly process (post-process).

[0303] The following describes the post-process using the flowchart shown in Figure 17A. After the element substrate having the semiconductor device shown in the above embodiment is completed in the pre-process, a "backside grinding process" is performed to grind the backside of the element substrate (the surface on which the semiconductor device, etc. is not formed) (step S721). By thinning the element substrate by grinding, warping of the element substrate can be reduced, and electronic components can be made smaller.

[0304] Next, a "dicing process" is performed to separate the element substrate into a plurality of chips (chips 715) (step S722). Then, a "die bonding process" is performed to individually pick up the separated chips and bond them onto a lead frame (step S723). The bonding between the chip and the lead frame in the die bonding process is performed using a method appropriate for the product, such as bonding with resin or bonding with tape. It is also possible to bond the chip onto an interposer substrate instead of a lead frame.

[0305] Next, a "wire bonding process" is performed (step S724), in which the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. Silver wires or gold wires can be used for the thin metal wires. The wire bonding can be ball bonding or wedge bonding.

[0306] The wire-bonded chip is then subjected to the "encapsulation process (molding process)" in which it is encapsulated with epoxy resin or the like (step S725). The encapsulation process fills the interior of the electronic component with resin, protecting the circuitry built into the chip and the wires connecting the chip to the leads from external mechanical forces, and also reducing the deterioration of characteristics (reduced reliability) due to moisture and dust.

[0307] Next, a "lead plating process" is performed to plate the leads of the lead frame (step S726). Plating prevents the leads from rusting, allowing for more reliable soldering when mounting the device on a printed circuit board later. Next, a "forming process" is performed to cut and form the leads (step S727).

[0308] Next, a "marking process" is carried out to print (mark) the surface of the package (step S728), and then an "inspection process" (step S729) is carried out to check whether the external shape is good or not, whether there are any malfunctions, etc., and the electronic component is completed.

[0309] 17B shows a perspective schematic diagram of a completed electronic component. In FIG. 17B, a perspective schematic diagram of a QFP (Quad Flat Package) is shown as an example of an electronic component. Electronic component 750 shown in FIG. 17B includes leads 755 and a semiconductor device 753. The semiconductor device described in the above embodiment can be used as semiconductor device 753.

[0310] 17B is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined and electrically connected on the printed circuit board 752 to complete a board (mounted board 754) on which electronic components are mounted. The completed mounted board 754 is used in electronic devices and the like.

[0311] [Electronic equipment] Next, examples of electronic devices including the semiconductor device or the electronic component according to one embodiment of the present invention will be described.

[0312] Examples of electronic devices using a semiconductor device or electronic component according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Disc) players. Examples of such devices include image playback devices that play back still images or videos stored on recording media such as CDs, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, mobile phones, car phones, portable game consoles, tablet terminals, large game consoles such as pachinko machines, calculators, portable information terminals (also referred to as "mobile information terminals"), electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids.

[0313] Mobile bodies propelled by electric motors using power from power storage devices are also included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid electric vehicles (HEVs) that combine an internal combustion engine with an electric motor, plug-in hybrid electric vehicles (PHEVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0314] A semiconductor device or electronic component according to one embodiment of the present invention can be used in a communication device or the like built into these electronic devices.

[0315] The electronic device may have sensors (including those that can measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), etc.

[0316] Electronic devices can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0317] 18 and 19A to 19F illustrate examples of electronic devices. In FIG. 18, a display device 8000 is an example of an electronic device including a semiconductor device 8004 according to one embodiment of the present invention. Specifically, the display device 8000 corresponds to a display device for receiving TV broadcasts and includes a housing 8001, a display portion 8002, a speaker portion 8003, a semiconductor device 8004, a power storage device 8005, and the like. The semiconductor device 8004 according to one embodiment of the present invention is provided inside the housing 8001. The semiconductor device 8004 can store control information, a control program, and the like. The semiconductor device 8004 has a communication function, allowing the display device 8000 to function as an IoT device. The display device 8000 can receive power from a commercial power source or use power stored in the power storage device 8005.

[0318] The display unit 8002 can be a liquid crystal display device, a light-emitting display device in which each pixel has a light-emitting element such as an organic EL element, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), an FED (Field Emission Display), or other display device.

[0319] The display device includes all display devices for displaying information, such as those for receiving TV broadcasts, those for personal computers, and those for displaying advertisements.

[0320] 18 , a stationary lighting device 8100 is an example of an electronic device including a semiconductor device 8103 according to one embodiment of the present invention. Specifically, the lighting device 8100 includes a housing 8101, a light source 8102, a semiconductor device 8103, a power storage device 8105, and the like. FIG. 18 illustrates an example in which the semiconductor device 8103 is provided inside a ceiling 8104 on which the housing 8101 and the light source 8102 are installed; however, the semiconductor device 8103 may be provided inside the housing 8101. The semiconductor device 8103 can store information such as the light emission luminance of the light source 8102, a control program, and the like. The semiconductor device 8103 has a communication function, which allows the lighting device 8100 to function as an IoT device. The lighting device 8100 can receive power from a commercial power source or use power stored in a power storage device.

[0321] Note that although the lighting device 8100 in FIG. 18 is a stationary lighting device provided on the ceiling 8104, the semiconductor device according to one embodiment of the present invention can also be used in a stationary lighting device provided on a side wall 8405, a floor 8406, a window 8407, or the like, other than the ceiling 8104, or can also be used in a tabletop lighting device.

[0322] Furthermore, an artificial light source that artificially obtains light using electric power can be used as the light source 8102. Specifically, examples of the artificial light source include discharge lamps such as incandescent lamps and fluorescent lamps, and light-emitting elements such as LEDs and organic EL elements.

[0323] In FIG. 18 , an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device including a semiconductor device 8203 according to one embodiment of the present invention. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a semiconductor device 8203, a power storage device 8205, and the like. Although FIG. 18 illustrates the case where the semiconductor device 8203 is provided in the indoor unit 8200, the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor device 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The semiconductor device 8203 can store control information, a control program, and the like for the air conditioner. The semiconductor device 8203 has a communication function, allowing the air conditioner to function as an IoT device. The air conditioner can receive power from a commercial power source or use power stored in the power storage device 8205.

[0324] Note that although FIG. 18 illustrates an example of a separate air conditioner including an indoor unit and an outdoor unit, the semiconductor device according to one embodiment of the present invention can also be used in an integrated air conditioner in which the functions of the indoor unit and the outdoor unit are combined in one housing.

[0325] 18 , an electric refrigerator-freezer 8300 is an example of an electronic device including a semiconductor device 8304 according to one embodiment of the present invention. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a semiconductor device 8304, a power storage device 8305, and the like. In FIG. 18 , the power storage device 8305 is provided inside the housing 8301. The semiconductor device 8304 can store control information, a control program, and the like for the electric refrigerator-freezer 8300. The semiconductor device 8304 has a communication function, which allows the electric refrigerator-freezer 8300 to function as an IoT device. The electric refrigerator-freezer 8300 can receive power from a commercial power source or use power stored in the power storage device 8305.

[0326] 19A shows an example of a wristwatch-type portable information terminal. The portable information terminal 6100 includes a housing 6101, a display portion 6102, a band 6103, operation buttons 6105, and the like. The portable information terminal 6100 also includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. By using the semiconductor device or electronic component according to one embodiment of the present invention in the portable information terminal 6100, the portable information terminal 6100 can function as an IoT device.

[0327] 19B shows an example of a mobile phone. A mobile information terminal 6200 includes a display portion 6202 incorporated in a housing 6201, operation buttons 6203, a speaker 6204, a microphone 6205, and the like.

[0328] The portable information terminal 6200 also includes a fingerprint sensor 6209 in an area overlapping with the display portion 6202. The fingerprint sensor 6209 may be an organic optical sensor. Since fingerprints are different for each person, personal authentication can be performed by acquiring a fingerprint pattern with the fingerprint sensor 6209. Light emitted from the display portion 6202 can be used as a light source for acquiring the fingerprint pattern with the fingerprint sensor 6209.

[0329] The portable information terminal 6200 includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. When the portable information terminal 6200 includes the semiconductor device or electronic component according to one embodiment of the present invention, the portable information terminal 6200 can function as an IoT device.

[0330] 19C shows an example of a cleaning robot. The cleaning robot 6300 has a display unit 6302 arranged on the top surface of a housing 6301, a plurality of cameras 6303 arranged on the side, a brush 6304, an operation button 6305, various sensors, and the like. Although not shown, the cleaning robot 6300 is provided with tires, a suction port, and the like. The cleaning robot 6300 can move by itself, detect dust 6310, and suck up the dust from a suction port arranged on the bottom surface.

[0331] For example, the cleaning robot 6300 can analyze an image captured by the camera 6303 and determine whether or not there is an obstacle such as a wall, furniture, or a step. Furthermore, if an object that may become entangled in the brush 6304, such as a wire, is detected through image analysis, the cleaning robot 6300 can stop rotation of the brush 6304. The cleaning robot 6300 includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. By using the semiconductor device or electronic component according to one embodiment of the present invention in the cleaning robot 6300, the cleaning robot 6300 can function as an IoT device.

[0332] 19D shows an example of a robot. The robot 6400 shown in FIG. 19D includes a computing device 6409, an illuminance sensor 6401, a microphone 6402, an upper camera 6403, a speaker 6404, a display unit 6405, a lower camera 6406, an obstacle sensor 6407, and a movement mechanism 6408.

[0333] The microphone 6402 has a function of detecting the user's speaking voice, environmental sounds, etc. The speaker 6404 has a function of emitting sound. The robot 6400 can communicate with the user using the microphone 6402 and the speaker 6404.

[0334] The display unit 6405 has a function of displaying various information. The robot 6400 can display information desired by the user on the display unit 6405. The display unit 6405 may be equipped with a touch panel. The display unit 6405 may also be a detachable information terminal, which can be installed in a fixed position on the robot 6400 to enable charging and data transfer.

[0335] The upper camera 6403 and the lower camera 6406 have a function of capturing images of the periphery of the robot 6400. In addition, the obstacle sensor 6407 can detect the presence or absence of an obstacle in the moving direction when the robot 6400 moves forward using the moving mechanism 6408. The robot 6400 can recognize the surrounding environment and move safely using the upper camera 6403, the lower camera 6406, and the obstacle sensor 6407. The light-emitting device of one embodiment of the present invention can be used for the display portion 6405.

[0336] The robot 6400 includes a secondary battery and a semiconductor device or electronic component according to one embodiment of the present invention. By using the semiconductor device or electronic component according to one embodiment of the present invention in the robot 6400, the robot 6400 can function as an IoT device.

[0337] Fig. 19E shows an example of an aircraft. Aircraft 6500 shown in Fig. 19E has propeller 6501, camera 6502, battery 6503, etc., and has the function of flying autonomously.

[0338] For example, image data captured by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of obstacles when moving. The electronic component 6504 can also estimate the remaining battery charge from a change in the storage capacity of the battery 6503. The flying object 6500 includes a semiconductor device or electronic component according to one embodiment of the present invention therein. By using the semiconductor device or electronic component according to one embodiment of the present invention in the flying object 6500, the flying object 6500 can function as an IoT device.

[0339] 19F illustrates an example of an automobile. The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, and the like. The automobile 7160 includes a semiconductor device or an electronic component according to one embodiment of the present invention inside. By using the semiconductor device or the electronic component according to one embodiment of the present invention in the automobile 7160, the automobile 7160 can function as an IoT device.

[0340] The configurations, structures, methods, and the like shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like shown in other embodiment modes and embodiments.

[0341] (Embodiment 5) A normally-off CPU (also referred to as an "Noff-CPU") can be realized using the OS transistor described in this specification. Note that an Noff-CPU is an integrated circuit including a normally-off transistor that is in a non-conducting state (also referred to as an "off state") even when the gate voltage is 0 V.

[0342] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from the standby state. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0343] The Noff-CPU can be suitably used in small-scale systems such as IoT terminal devices (also called "endpoint microcomputers") 803 in the field of IoT (Internet of Things).

[0344] Figure 20 shows the hierarchical structure of an IoT network and trends in required specifications. In Figure 20, power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of an IoT network is broadly divided into an upper cloud field 801 and a lower embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, and home appliances.

[0345] The higher the layer, the more important it is to have high processing performance rather than low power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs, and the like are used. Furthermore, the lower the layer, the more important it is to have low power consumption rather than high processing performance, and the number of devices increases explosively. A semiconductor device according to one embodiment of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.

[0346] The term "endpoint" refers to the terminal area of ​​the embedded field 802. Devices used as endpoints include, for example, microcomputers used in factories, home appliances, infrastructure, agriculture, and the like.

[0347] FIG. 21 illustrates an image of factory automation as an application example of an endpoint microcontroller. A factory 884 is connected to a cloud 883 via an Internet line. The cloud 883 is connected to a home 881 and an office 882 via the Internet line. The Internet line may be a wired communication system or a wireless communication system. For example, in the case of a wireless communication system, a semiconductor device according to one embodiment of the present invention may be used in a communication device to perform wireless communication in accordance with a communication standard such as a fourth-generation mobile communication system (4G) or a fifth-generation mobile communication system (5G). The factory 884 may be connected to factories 885 and 886 via the Internet line.

[0348] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to a cloud 883 and transmitting and receiving information. The master device 831 is also connected to a plurality of industrial robots 842 included in an IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet ("Ethernet" is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0349] A factory manager can connect to a factory 884 via a cloud 883 from a home 881 or office 882 to know the operating status, etc. He can also check for incorrect or missing items, give instructions on where to put them, measure takt time, etc.

[0350] In recent years, the introduction of IoT into factories has been progressing worldwide under the name of "smart factories." In smart factory cases, there have been reported cases where endpoint microcomputers are used not only for simple inspection and auditing but also for fault detection and anomaly prediction.

[0351] Small-scale systems such as endpoint microcontrollers often consume little power overall during operation, so the power saving effect of a Noff-CPU during standby operation is significant. On the other hand, in the embedded field of IoT, quick response is sometimes required, and the use of a Noff-CPU makes it possible to achieve fast recovery from standby operation.

[0352] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples. [Example]

[0353] Example 1 In this example, the results of determining the cutoff frequency of an OS-FET that can be used in a semiconductor device according to one embodiment of the present invention by simulation will be described.

[0354] Cutoff frequency (f T ) can be calculated using the following formula 1.

[0355]

number

[0356] where C g is the gate capacitance of the OS-FET, g m is the transconductance. The transconductance g at a particular drain voltage mcan be calculated from the following formula 2.

[0357]

number

[0358] In the above formula 2, V g is the gate voltage of the OS-FET, I d is the drain current, V d is the drain voltage.

[0359] The cutoff frequency was calculated using Silvaco's device simulator Atlas 3D. Figures 22A to 22C show the structure of the OS-FET used in the calculation. Figure 22A is a schematic cross-sectional view in the L-length direction at the center of the channel of the OS-FET. Figure 22B is a schematic cross-sectional view in the W-width direction at the center of the channel of the OS-FET. Figure 22C is a schematic cross-sectional view in the W-width direction at the source or drain region of the OS-FET.

[0360] 22A to 22C, the OS-FET includes a BGE, a BGI1, a BGI2, an OS1, an OS2, a SD, a TGI, and a TGE. The BGE functions as a back gate electrode, and the TGE functions as a gate electrode (also called a top gate electrode). The OS1 and the OS2 are metal oxides having a stacked structure. The SD functions as one of a source electrode and a drain electrode, or the other of a source electrode and a drain electrode. The BGI1 and the BGI2 function as gate insulating films having a stacked structure provided between the BGE and the OS1, and the TGI functions as a gate insulating film provided between the OS2 and the TGE.

[0361] The metal oxide with an atomic ratio of In:Ga:Zn=1:3:4 was used as OS1, and the metal oxide with an atomic ratio of In:Ga:Zn=4:2:3 was used as OS2.

[0362] Furthermore, L in FIG. 22A, that is, the width of TGE, indicates the channel length, and W in FIG. 22B, that is, the width of OS1 and OS2, indicates the channel width.

[0363] Next, Table 1 shows the calculation conditions.

[0364] [Table 1]

[0365] The calculation results of the cutoff frequency of the OS-FET obtained under the above conditions are shown in Figure 23. In Figure 23, the horizontal axis represents the drain voltage of the OS-FET (unit: V), and the vertical axis represents the cutoff frequency f T (Unit: GHz) In the above calculation, the gate voltage and the drain voltage are set to the same value. The channel length and the channel width of the OS-FET are set to 30 nm and 30 nm, respectively.

[0366] Looking at the results in Figure 23, the cutoff frequency of the OS-FET was 38.6 GHz when the drain voltage was 1 V, 71.5 GHz when the drain voltage was 2 V, 104.4 GHz when the drain voltage was 3 V, 132.8 GHz when the drain voltage was 4 V, and 160.1 GHz when the drain voltage was 5 V. Calculations confirmed that a cutoff frequency of 100 GHz or more can be obtained by setting the drain voltage to 3 V or more.

[0367] The above calculation results show that an OS-FET can be suitably used for a semiconductor device according to one embodiment of the present invention.

[0368] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes. [Explanation of symbols]

[0369] : L1: layer, L2: layer, L3: layer, L3A: layer, L3B: layer, L4: layer, 5G: local, 10: semiconductor device, 10A: semiconductor device, 10B: semiconductor device, 11: antenna array, 11A: antenna, 12: transmission / reception control device, 12A: transmission / reception control device, 12B: transmission / reception control device, 13: signal processing device, 14: processor, 15: GPU, 16: power supply control device, 16A: power supply control device, 16B: power supply control device, 17: PLD, 18: storage device, 18A: storage device, 18B: storage device, 18C: storage device, 18D: storage device, 18E: storage device, 18F: storage Device, 18G: memory device, 18H: memory device, 19: display device, 19A: gate driver, 19B: display area, 20: sensor module, 24: capacitance, 111: memory element, 112: transistor, 113: capacitance, 114: node, 115: transistor, 116: transistor, 123: terminal, 124: terminal, 126: wiring, 311: substrate, 313: semiconductor area, 314a: low resistance area, 314b: low resistance area, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 404: insulator, 500: transistor, 500A: transistor, 500B: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 513: insulator, 514: insulator, 516: insulator, 518: conductor, 520: Insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 545: insulator, 546: conductor, 548: conductor, 550: transistor, 550A: transistor, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitor, 610: conductor,612: conductor, 620: conductor, 630: insulator, 640: insulator, 650: transistor, 652: low-temperature buffer layer, 54: semiconductor layer, 656: semiconductor layer, 658: conductor, 711: substrate, 712: circuit area, 713: separation area, 714: separation line, 715: chip, 750: electronic component, 752: printed circuit board, 753: semiconductor device, 754: mounting board, 755: lead, 801: cloud field, 802: embedded field, 804: power consumption, 805: processing performance, 831: master device, 832: M2M interface, 841: IoT end device, 8 42: Industrial robot, 881: Home, 882: Office, 883: Cloud, 884: Factory, 885: Factory, 886: Factory, 900: Wireless transceiver, 900A: Wireless transceiver, 901: Low noise amplifier, 902: Band pass filter, 903: Mixer, 904: Band pass filter, 905: Demodulator, 906: Decoder circuit, 911: Power amplifier, 912: Band pass filter, 913: Mixer, 914: Band pass filter, 915: Modulator, 916: Decoder circuit, 921: Duplexer, 922: Local oscillator, 931: Antenna, 941: Signal, 94 2: Signal, 943: Signal, 944: Signal, 2001: Wiring, 2005: Wiring, 2006: Wiring, 6100: Mobile information terminal, 6101: Housing, 6102: Display unit, 6103: Band, 6105: Operation button, 6200: Mobile information terminal, 6201: Housing, 6202: Display unit, 6203: Operation button, 6204: Speaker, 6205: Microphone, 6209: Fingerprint sensor, 6300: Cleaning robot, 6301: Housing, 6302: Display unit, 6303: Camera, 6304: Brush, 6305: Operation button, 6310: Dust, 6400: Robot, 6401: Illuminance sensor sensor, 6402: microphone, 6403: upper camera, 6404: speaker, 6405: display unit, 6406: lower camera, 6407: obstacle sensor, 6408: moving mechanism, 6409: computing unit, 6500: flying object, 6501: propeller, 6502: camera, 6503: battery, 6504: electronic component, 7160: automobile, 8000: display device, 8001: housing, 8002: display unit, 8003: speaker unit, 8004: semiconductor device, 8005: power storage device, 8100: lighting device, 8101: housing, 8102: light source, 8103: semiconductor device, 8104: ceiling,8105: Power storage device, 8200: Indoor unit, 8201: Housing, 8202: Air outlet, 8203: Semiconductor device, 8204: Outdoor unit, 8205: Power storage device, 8300: Electric refrigerator-freezer, 8301: Housing, 8302: Refrigerator door, 8303: Freezer door, 8304: Semiconductor device, 8305: Power storage device, 8405: Side wall, 8406: Floor, 8407: Window,

Claims

1. a first layer, a second layer, and a third layer formed on a substrate; the second layer has a region located above the first layer; the first transistor included in the first layer includes a first semiconductor layer including Si and having a channel formation region of the first transistor; the second transistor included in the second layer includes a second semiconductor layer containing Ga and a third semiconductor layer containing Ga and having a channel formation region of the second transistor; the third transistor included in the third layer has a fourth semiconductor layer containing at least one of In and Zn; the first semiconductor layer of the first transistor is formed using the substrate; the second semiconductor layer of the second transistor is formed using a crystal grown by crystal growth, the third semiconductor layer of the second transistor is formed using a crystal grown on the second semiconductor layer, a lower surface of the second semiconductor layer of the second transistor has a region in contact with an upper surface of a layer having a region in contact with an upper surface of the substrate; a first insulating layer having a region in contact with an upper surface of a gate insulating layer of the first transistor and a region in contact with an upper surface of a gate electrode, the first insulating layer having a region in contact with a side surface of the third semiconductor layer of the second transistor; The semiconductor device, wherein the fourth semiconductor layer of the third transistor is formed above the first semiconductor layer and the third semiconductor layer.

2. In claim 1, The semiconductor device, wherein the third transistor is disposed at a position having an area overlapping with the first transistor.

3. In claim 1, The semiconductor device, wherein the third transistor is disposed at a position having an area overlapping with the second transistor.

4. In any one of claims 1 to 3, the semiconductor device has a fourth layer; The semiconductor device includes a fifth transistor in the fourth layer, the fifth semiconductor layer containing at least one of In and Zn.

5. In any one of claims 1 to 4, The second transistor is a semiconductor device having a recessed gate structure.

Images