Imaging device

Abstract

To provide an imaging device having an image processing function and being capable of high-speed operation.SOLUTION: An imaging device has an additional function such as image processing. The imaging device can keep analog data acquired by imaging operation in pixels and take out data in which the analog data and an optional weight coefficient are multiplied. In the imaging device, the data can be stored in a memory cell and a pooling process for the data stored in a plurality of such memory cells can be performed. One or more of the memory cells, a pooling processing circuit, and a pixel readout circuit and the pixel are disposed so as to have an overlapping region; therefore, the enlargement of the area of the imaging device can be suppressed while enabling the additional function.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, memory devices, imaging devices, and operation methods thereof or manufacturing methods thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a pixel circuit that uses a transistor that includes an oxide semiconductor and has extremely low off-state current.

[0005] Furthermore, Patent Document 2 discloses a technique for adding a calculation function to an imaging device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-123087 Summary of the Invention [Problem to be solved by the invention]

[0007] Imaging devices installed in mobile devices and the like are generally equipped with a function for capturing high-resolution images. In the next generation, imaging devices are expected to be equipped with even more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted to digital data, and after being output externally, image processing is performed as needed. If this processing can be performed within the imaging device, cooperation with external devices will be faster, improving user convenience. It will also reduce the load and power consumption of peripheral devices. Furthermore, if complex data processing can be performed in the analog data state, the time required for data conversion can also be shortened.

[0009] Furthermore, when adding functions to an imaging device, it is preferable that the elements such as additional circuits have a stacked structure. For example, by arranging multiple circuits so that they overlap with pixel circuits, it is possible to suppress an increase in area and form a compact imaging device with high functionality.

[0010] Therefore, an object of one embodiment of the present invention is to provide an imaging device capable of image processing. Another object is to provide a high-performance and small-sized imaging device. Another object is to provide an imaging device that can operate at high speed. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to an imaging device that has an image processing function and is capable of high-speed operation.

[0013] One embodiment of the present invention is an imaging device that includes a plurality of pixel blocks and a first circuit, each of which includes a plurality of pixels and a memory cell, and which stores analog data calculated based on data generated by the plurality of pixels, and which has a function of reading out a maximum value of the analog data stored in the memory cell of each of the plurality of pixel blocks.

[0014] The memory cell preferably has an area overlapping with at least one of the pixel and the first circuit.

[0015] Another embodiment of the present invention is a pixel circuit including a plurality of pixel blocks, a first circuit, a second circuit, and a third circuit, each of the plurality of pixel blocks including a plurality of pixels and a memory cell, each of the plurality of pixels having a function of retaining first data in response to a reset operation, each of the plurality of pixels having a function of retaining second data in response to a photoelectric conversion operation, each of the plurality of pixels having a function of generating third data by adding a weighting coefficient and the first data, and each of the plurality of pixels having a function of generating fourth data by adding a weighting coefficient and the second data, and the first circuit is configured to retain the first data in response to a reset operation. the first circuit has a function of generating fifth data in accordance with the difference between the sum of first data held in the plurality of pixels and the sum of third data generated by the plurality of pixels, the first circuit has a function of generating sixth data in accordance with the difference between the sum of second data held in the plurality of pixels and the sum of fourth data generated by the plurality of pixels, the second circuit has a function of generating seventh data in accordance with the difference between the fifth data and the sixth data, the seventh data is stored in the memory cells, and the third circuit has a function of reading out the maximum value of the seventh data stored in the memory cells of each of the plurality of pixel blocks.

[0016] The pixel has a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor, and one electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor, the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one electrode of the first capacitor, and the gate of the third transistor, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, and the other electrode of the first capacitor can be electrically connected to one of the source or drain of the fifth transistor.

[0017] The memory cell has a sixth transistor, a seventh transistor, and a second capacitor, and one of the source or drain of the sixth transistor, one electrode of the second capacitor, and the gate of the seventh transistor can be electrically connected.

[0018] The sixth transistor and the seventh transistor preferably have a metal oxide in a channel formation region, and the metal oxide preferably contains In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0019] The first circuit and the second circuit may be correlated double sampling circuits.

[0020] The third circuit may include a plurality of current mirror circuits.

[0021] The first to third circuits preferably include a transistor having silicon in a channel formation region.

[0022] It is preferable that any one or more of the first to third circuits and the pixel have an overlapping region. Also, any one or more of the first to third circuits and the pixel may have an overlapping region with the memory cell. [Effects of the Invention]

[0023] By using one embodiment of the present invention, an imaging device capable of performing image processing can be provided. Alternatively, a highly functional and small imaging device can be provided. Alternatively, an imaging device capable of high-speed operation can be provided. Alternatively, an imaging device with low power consumption can be provided. Alternatively, an imaging device with high reliability can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a driving method of the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device. [Figure 2] FIG. 2 is a block diagram illustrating the imaging device. [Figure 3] FIG. 3 is a diagram illustrating a pixel selection operation. [Figure 4] FIG. 4 is a diagram illustrating a pixel selection operation. [Figure 5] FIG. 5 is a diagram illustrating a pixel selection operation. [Figure 6] 6A and 6B are diagrams illustrating pixels. [Figure 7] 7A and 7B are diagrams illustrating pixels. [Figure 8] FIG. 8 is a diagram for explaining the circuit 201 and the circuit 202. As shown in FIG. [Figure 9] 9A and 9B are timing charts illustrating the operation of the imaging device. [Figure 10] 10A and 10B are diagrams for explaining the arrangement of pixels and memory cells. [Figure 11] 11A and 11B are diagrams for explaining the arrangement of pixels and memory cells. [Figure 12] Fig. 12A is a diagram illustrating a memory circuit, and Fig. 12B and Fig. 12C are diagrams illustrating a memory cell. [Figure 13] FIG. 13 is a diagram illustrating the circuit 203. [Figure 14] 14A is a diagram illustrating the circuit 230a, and FIG. 14B is a diagram illustrating the circuit 240. [Figure 15] 15A and 15B are diagrams illustrating the circuit 204. FIG. [Figure 16] FIG. 16 is a diagram illustrating a memory cell. [Figure 17] 17A and 17B are diagrams showing examples of the configuration of a neural network. [Figure 18] 18A to 18D are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 19]19A to 19C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 20] FIG. 20 is a cross-sectional view illustrating a pixel. [Figure 21] 21A to 21C are diagrams illustrating a Si transistor. [Figure 22] FIG. 22 is a cross-sectional view illustrating a pixel. [Figure 23] FIG. 23 is a cross-sectional view illustrating a pixel. [Figure 24] FIG. 24 is a cross-sectional view illustrating a pixel. [Figure 25] 25A to 25D illustrate an OS transistor. [Figure 26] FIG. 26 is a cross-sectional view illustrating a pixel. [Figure 27] FIG. 27 is a cross-sectional view illustrating a pixel. [Figure 28] FIG. 28 is a cross-sectional view illustrating a pixel. [Figure 29] FIG. 29 is a cross-sectional view illustrating a pixel. [Figure 30] 30A to 30C are perspective views (cross-sectional views) illustrating pixels. [Figure 31] 31A1 to 31A3 and 31B1 to 31B3 are perspective views of a package and a module that house an imaging device. [Figure 32] 32A to 32F are diagrams illustrating an electronic device. [Figure 33] FIG. 33 is a diagram illustrating an automobile. DETAILED DESCRIPTION OF THE INVENTION

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0026] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0027] Furthermore, a single conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0028] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0029] One aspect of the present invention is an imaging device with additional functions such as image processing, which stores analog data (image data) acquired during imaging in pixels and can extract analog data obtained by multiplying the analog data by an arbitrary weighting coefficient.

[0030] Furthermore, the analog data is stored in memory cells, and a pooling process can be performed to read out the maximum value from the analog data stored in multiple memory cells. The memory cells, the circuit that performs the pooling process, and one or more pixel readout circuits are arranged so that the pixels overlap with each other, so that the area of ​​the imaging device can be prevented from increasing while providing additional functions.

[0031] The pooled data can be input into a neural network or the like to perform processing such as image recognition. In one embodiment of the present invention, a huge amount of image data can be stored in pixels in the form of analog data, allowing for efficient processing.

[0032] <Imaging device> 1 is a block diagram illustrating an imaging device of one embodiment of the present invention. The imaging device includes a pixel array 300, a circuit 201, a circuit 202, a circuit 203, a circuit 204, a circuit 301, a circuit 302, a circuit 303, a circuit 304, and a circuit 305. Note that each of the circuits 201 to 204 and the circuits 301 to 305 is not limited to a single circuit configuration and may be configured by a combination of multiple circuits. Alternatively, multiple circuits described above may be integrated. Furthermore, circuits other than those described above may be connected.

[0033] The pixel array 300 has an imaging function and an arithmetic function. The circuits 201 to 204 have an arithmetic function or a data conversion function. The circuits 301 to 304 have a selection function. The circuit 305 has a function of supplying potentials for product-sum calculation to the pixels. A shift register, a decoder, or the like can be used as the circuit having the selection function. Note that the circuit 204 may be provided outside the imaging device.

[0034] The pixel array 300 includes a plurality of pixel blocks 200. As shown in FIG. 2, the pixel block 200 includes a plurality of pixels 100 arranged in a matrix, and each pixel 100 is electrically connected to a circuit 201 via a wiring 113. Note that the circuit 201 can also be provided within the pixel block 200.

[0035] The pixel block 200 includes at least one memory cell 150. The memory cell 150 may be provided in a region overlapping with the pixel 100. The memory cell 150 is electrically connected to a circuit 202 through a wiring 141. The memory cell 150 is electrically connected to a circuit 203 through a wiring 142.

[0036] The circuits 301 and 302 have a selection function for operating the pixel 100. The circuits 304 and 305 have a selection function for operating the memory cell 150. Although not shown, a selection circuit or a sequential circuit for controlling input and output of data may be provided as appropriate between the pixel block 200 and the circuit 201, between the pixel block 200 and the circuit 203, between the circuit 201 and the circuit 202, between the circuit 203 and the circuit 204, or the like.

[0037] Each pixel 100 can acquire image data and generate data by adding the image data and a weighting factor. While FIG. 2 shows an example in which the pixel block 200 has 3×3 pixels 100, this is not limiting. For example, the number of pixels 100 can be 2×2, 4×4, or the like. Alternatively, the number of pixels 100 in the horizontal and vertical directions can be different. Furthermore, some pixels 100 can be shared between adjacent pixel blocks.

[0038] For example, the configuration shown in FIG. 3 allows the number of pixels 100 included in the pixel block 200 to be variable. FIG. 3 shows a plurality of pixels 100 arranged in rows [n-1] to [n+1] and columns [m-1] to [m+1] (n and m are integers of 2 or greater). A selection switch is provided within each pixel 100, and the selection switch is controlled to be turned "ON" or "OFF" by a selection signal supplied to row wirings RL[n-1] to RL[n+1]. The selection switch is electrically connected to one of column wirings CL[m-1] to CL[m+1]. At least one of the column wirings is electrically connected to a circuit 201[m-1].

[0039] A conductive switch SW[m-1] is provided between the column wirings CL[m-1] and CL[m], and a conductive switch SW[m] is provided between the column wirings CL[m] and CL[m+1]. The conductive switches are controlled to be "ON" or "OFF" by selection signals supplied to signal lines G1 and G2. When the selection switch is turned "ON," adjacent column wirings can be made conductive.

[0040] For example, as shown in FIG. 4, when a signal to turn on the selection switch is supplied to the row wirings RL[n-1] and RL[n] and a signal to turn on the conductive switch SW[m-1] is supplied to the signal line G1, 2×2 pixels 100 (pixels 100[n-1,m-1], pixels 100[n-1,m], pixels 100[n,m-1], pixels 100[n,m]) are selected. In addition, the column wirings CL[m-1] and CL[m] become conductive. Therefore, the 2×2 pixels 100 and the circuit 201[m-1] are electrically connected.

[0041] Furthermore, when a signal to turn on the selection switch is supplied to the row wiring RL[n+1] and a signal to turn on the conductive switch SW[m] is supplied to the signal line G2, the 3×3 pixels 100 are electrically connected to the circuit 201, similar to the configuration shown in FIG. 2.

[0042] In this configuration, the rows and columns to be selected can be changed arbitrarily, making it possible to perform calculations with different strides.

[0043] 5, by making only one row of pixels 100 selectable and turning all of the conductive switches "OFF," one column wiring and one pixel 100 can be brought into a conductive state. Here, as shown in FIG. 5, if a circuit 201 is electrically connected to each column wiring, information from each pixel 100 can be read out. In other words, high-resolution image data can be read out. Note that the number of circuits 201 may be less than the number of column wirings, and data may be read out by the circuit 201 by selecting the wiring.

[0044] The pixel block 200, the circuit 201, and the circuit 202 can operate as a multiply-accumulate circuit. The pixel block 200 is electrically connected to the circuit 201 through a wiring 113, and the circuit 201 is electrically connected to the circuit 202 through a wiring 140.

[0045] Data (analog data) of the product-sum operation is stored in a memory cell 150 via a wiring 141. The analog data stored in the memory cell 150 is read out to a circuit 203 via a wiring 142. The circuit 203 can compare analog data stored in a plurality of memory cells 150 and output the maximum value. That is, the circuit 203 can function as a pooling circuit.

[0046] At least one of the circuit 201, the circuit 202, and the circuit 203 is preferably provided to have a region overlapping with the pixel 100. Alternatively, at least one of the circuit 201, the circuit 202, the circuit 203, and the pixel is preferably provided to have a region overlapping with the memory cell 150. With this configuration, the area of ​​the entire imaging device can be reduced, and a small, highly functional imaging device can be formed. Furthermore, with a stacked structure, the length of wiring electrically connecting the pixel 100, the memory cell 150, the circuit 201, the circuit 202, and the circuit 203 can be shortened, thereby enabling high-speed operation with reduced power consumption.

[0047] <Pixel circuit> Pixel 100 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a transistor 106, and a transistor 108, as shown in FIG. 6A.

[0048] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, one electrode of the capacitor 104, and the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 108. The other electrode of the capacitor 104 is electrically connected to one of the source or drain of the transistor 106.

[0049] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 114. The gate of the transistor 102 is electrically connected to a wiring 116. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 115. The gate of the transistor 103 is electrically connected to a wiring 117. The other of the source and the drain of the transistor 105 is electrically connected to a GND wiring or the like. The other of the source and the drain of the transistor 108 is electrically connected to a wiring 113. The other of the source and the drain of the transistor 106 is electrically connected to a wiring 111. The gate of the transistor 106 is electrically connected to a wiring 112. The gate of the transistor 108 is electrically connected to a wiring 122.

[0050] Here, the electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 104, and the gate of the transistor 105 is referred to as a node N.

[0051] The wirings 114 and 115 can function as power supply lines. For example, the wiring 114 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. The wirings 112, 116, 117, and 122 can function as signal lines that control the conduction of each transistor. The wiring 111 can function as a wiring that supplies a potential corresponding to a weighting coefficient to the pixel 100. The wiring 113 can function as a wiring that electrically connects the pixel 100 and the circuit 201.

[0052] Note that the wiring 113 may be electrically connected to an amplifier circuit or a gain adjustment circuit.

[0053] A photodiode can be used as the photoelectric conversion device 101. If it is desired to increase the light detection sensitivity at low illuminance, it is preferable to use an avalanche photodiode.

[0054] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 105 can have a function of controlling the current flowing from the circuit 201 in accordance with the potential of the node N. The transistor 108 can have a function of selecting a pixel. The transistor 106 can have a function of supplying a potential corresponding to a weighting coefficient to the node N.

[0055] As shown in FIG. 6B, the transistors 105 and 108 may have a configuration in which one of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 108, the other of the source or drain of the transistor 105 is connected to a wiring 113, and the other of the source or drain of the transistor 108 is electrically connected to a GND wiring or the like.

[0056] 6A and 6B, the connection direction of a pair of electrodes of the photoelectric conversion device 101 may be reversed. In this case, the wiring 114 may function as a low-potential power supply line, and the wiring 115 may function as a high-potential power supply line.

[0057] The transistors 102 and 103 are preferably OS transistors (OS transistors) that use metal oxide in their channel formation regions. OS transistors have extremely low off-state current. By using OS transistors as the transistors 102 and 103, the period during which charge can be held at the node N can be significantly extended. Furthermore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration and operation method. Furthermore, while image data is held at the node N, multiple calculations can be performed using the image data.

[0058] On the other hand, it may be desirable for the transistor 105 to have excellent amplification characteristics. It may also be preferable to use high-mobility transistors that can operate at high speed as the transistors 106 and 108. Therefore, the transistors 105, 106, and 108 may be transistors that use silicon in their channel formation regions (Si transistors).

[0059] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Furthermore, all transistors may be OS transistors. Alternatively, all transistors may be Si transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single-crystal silicon).

[0060] The potential of the node N in the pixel 100 is determined by the sum of a reset potential supplied from the wiring 115 and a potential (image data) generated by photoelectric conversion by the photoelectric conversion device 101. Alternatively, the potential is determined by capacitively coupling a potential corresponding to a weighting factor supplied from the wiring 111. Therefore, the transistor 105 can pass a current corresponding to the data in which an arbitrary weighting factor has been added to the image data.

[0061] 7A, a back gate (second gate) may be provided to the transistor 105, and one of the source and drain of the transistor 106 may be electrically connected to the back gate. A capacitor 109 may be provided in which one electrode of the transistor 106 is connected to the back gate. The capacitor 109 functions as a storage capacitor. Note that the capacitor 109 may not be provided.

[0062] As shown in FIG. 7B, a transistor may have a back gate (second gate). By electrically connecting the back gate to the front gate, the on-state current of the transistor can be increased. Furthermore, by supplying an appropriate constant potential to the back gate, the threshold voltage of the transistor can be controlled. Note that the structure in which a transistor has a back gate can also be applied to other circuits described in this specification. Furthermore, a circuit may be configured by mixing transistors with and without a back gate.

[0063] The above is an example of the circuit configuration of the pixel 100, and the photoelectric conversion operation can be performed with other circuit configurations.

[0064] <Circuit 201, Circuit 202> 2, the pixels 100 in the pixel block 200 are electrically connected to each other by wirings 113. The circuit 201 can perform calculations using the sum of currents flowing through the transistors 105 of the pixels 100.

[0065] 8. The circuit 201 includes a capacitor 222, a transistor 223, a transistor 224, a transistor 225, a transistor 226, and a transistor 227 as a voltage conversion circuit. An appropriate analog potential (Bias) is applied to the gate of the transistor 227.

[0066] One electrode of the capacitor 222 is electrically connected to one of the source or drain of the transistor 223 and the gate of the transistor 224. One of the source or drain of the transistor 224 is electrically connected to one of the source or drain of the transistor 225 and one of the source or drain of the transistor 226. The other electrode of the capacitor 222 is electrically connected to the wiring 113 and one of the source or drain of the transistor 227.

[0067] Here, a point (wiring) connecting one electrode of the capacitor 222, one of the source or drain of the transistor 223, and the gate of the transistor 224 is referred to as a node C.

[0068] The other of the source and the drain of the transistor 223 is electrically connected to a wiring 218. The other of the source and the drain of the transistor 224 is electrically connected to a wiring 219. The other of the source and the drain of the transistor 225 is electrically connected to a reference power supply line such as a GND wiring. The other of the source and the drain of the transistor 226 is electrically connected to a wiring 140. The other of the source and the drain of the transistor 227 is electrically connected to a wiring 217. The gate of the transistor 223 is electrically connected to a wiring 216. The gate of the transistor 225 is electrically connected to a wiring 215. The gate of the transistor 226 is electrically connected to a wiring 213.

[0069] The wirings 217, 218, and 219 can function as power supply lines. For example, the wiring 218 can function as a wiring that supplies a reset potential (Vr) for readout. The wirings 217 and 219 can function as high-potential power supply lines. The wirings 213, 215, and 216 can function as signal lines that control the conduction of each transistor.

[0070] The transistor 223 can have a function of resetting the potential of the node C to the potential of the wiring 218. The transistors 224 and 225 can have a function as a source follower circuit. The transistor 226 can have a function of controlling reading. Note that the circuit 201 has a function as a correlated double sampling circuit (CDS circuit) and can be replaced with a circuit having the same function.

[0071] In one embodiment of the present invention, offset components other than the product of image data (X) and a weighting coefficient (W) are removed to extract the target WX. WX can be calculated using data acquired from the same pixel with exposure (with imaging) and without exposure (without imaging), and data when weights are applied to each of the data.

[0072] The current (I p ) is the sum of kΣ(XV th ) 2 , the current (I p ) is the sum of kΣ(W+XV th ) 2 In addition, the current (I ref ) is the sum of kΣ(0-V th ) 2 , the current (I ref ) is the sum of kΣ(WV th ) 2 where k is a constant, V th is the threshold voltage of transistor 105.

[0073] First, calculate the difference (data A) between the data with exposure and the data with weighting added to it. kΣ((XV th ) 2 -(W+XV th ) 2 )=kΣ(-W 2 -2W·X+2W·V th )

[0074] Next, calculate the difference (data B) between the data without exposure and the weighted data. kΣ((0-V th ) 2 -(WV th ) 2 )=kΣ(-W 2 +2W·V th )

[0075] Then, take the difference between data A and data B. kΣ(-W 2-2W·X+2W·V th -(-W 2 +2W·V th ))=kΣ(-2W·X). In other words, it is possible to remove offset components other than the product of the image data (X) and the weighting coefficient (W).

[0076] The circuit 201 can generate data A and data B. The difference between data A and data B can be calculated by the circuit 202. As shown in FIG. 8, the circuit 202 can have the same configuration as the circuit 201. Note that the circuit 202 may have a different configuration, and the operation of the circuit 202 may be replaced by a processing operation performed by software.

[0077] <Image capture operation> 9A is a timing chart illustrating the operation of calculating the difference (data A) between exposed data and weighted data in pixel block 200 and circuit 201. For convenience, the timing at which each signal is converted is shown together, but in practice, it is preferable to stagger the timings to take into account delays within the circuit. In the following description, high potential is represented by "H" and low potential by "L."

[0078] First, in a period T1, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel 100 is set to a reset potential. In addition, the potential of the wiring 111 is set to "L", the potentials of the wirings 112_1 to 112_3 (the wirings 112 in the first to third rows) are set to "H", and a weighting coefficient of 0 is written.

[0079] The potential of the wiring 116 is maintained at "H" until the period T2, and the potential of the wiring 117 is set to "L", so that the potential X (image data) is written to the node N by photoelectric conversion of the photoelectric conversion device 101.

[0080] During period T3, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the potential X flows through the transistor 105 of each pixel 100. Furthermore, by setting the potential of the wiring 216 to "H," the potential Vr of the wiring 218 is written to the node C. The operations during periods T1 to T3 correspond to obtaining data with exposure, and the data is initialized to the potential Vr of the node C.

[0081] During period T4, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W11 (weighting added to the pixels in the first row), and the potential of wiring 112_1 is set to "H," so that the weighting coefficient W11 is added to node N of pixel 100 in the first row through capacitive coupling of capacitor 104.

[0082] During period T5, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W12 (weighting to be added to the pixels in the second row), and the potential of wiring 112_2 is set to "H," so that the weighting coefficient W12 is added to node N of pixel 100 in the second row through the capacitive coupling of capacitor 104.

[0083] In period T6, the potential of the wiring 111 is set to a potential corresponding to weighting coefficient W13 (weighting to be added to the pixels in the third row) and the potential of the wiring 112_3 is set to "H", so that the weighting coefficient W13 is added to the node N of the pixels 100 in the third row by the capacitive coupling of the capacitor 104. The operations in periods T4 to T6 correspond to the generation of data in which a weight is added to the data with imaging.

[0084] During period T7, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the potential W11+X flows through the transistors 105 of the pixels 100 in the first row. A current corresponding to the potential W12+X flows through the transistors 105 of the pixels 100 in the second row. A current corresponding to the potential W13+X flows through the transistors 105 of the pixels 100 in the third row.

[0085] Here, the potential of the other electrode of capacitor 222 changes in accordance with the current flowing through wiring 113, and this change Y is added to the potential Vr of node C through capacitive coupling. Therefore, the potential of node C becomes "Vr+Y." If we consider Vr=0, then Y is the difference itself, and data A has been calculated.

[0086] In addition, the potential of the wiring 213 is set to "H" and the potential of the wiring 215 is set to "V bias By setting an appropriate analog potential such as "," the circuit 201 can output a signal potential according to the data A of the pixel block 200 in the first row by a source follower operation.

[0087] 9B is a timing chart illustrating the operation of pixel block 200 and circuit 201 to calculate the difference (data B) between unexposed data and data to which a weight has been applied. Data B may be acquired as needed. For example, if there is no change in the input weight, the acquired data B may be stored in memory and data B may be read from the memory. Multiple pieces of data B corresponding to multiple weights may be stored in the memory. Either data A or data B may be acquired first.

[0088] First, during periods T1 and T2, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel 100 is set to a reset potential (0). At the end of period T2, the potential of the wiring 117 is set to "L", and the potential of the wiring 116 is set to "L". That is, during this period, the potential of the node N is the reset potential regardless of the operation of the photoelectric conversion device 101.

[0089] In addition, in the period T1, the potential of the wiring 111 is set to "L", the potential of the wirings 112_1, 112_2, and 112_3 is set to "H", and the weighting coefficient is written as 0. This operation may be performed during a period in which the potential of the node N is the reset potential.

[0090] During period T3, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the reset potential flows through the transistor 105 of each pixel 100. Furthermore, by setting the potential of the wiring 216 to "H," the potential Vr of the wiring 218 is written to the node C. The operation during periods T1 to T3 corresponds to the acquisition of data without exposure, and the data is initialized to the potential Vr of the node C.

[0091] During period T4, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W11 (weighting added to the pixels in the first row), and the potential of wiring 112_1 is set to "H," so that the weighting coefficient W11 is added to node N of pixel 100 in the first row through capacitive coupling of capacitor 104.

[0092] During period T5, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W12 (weighting to be added to the pixels in the second row), and the potential of wiring 112_2 is set to "H," so that the weighting coefficient W12 is added to node N of pixel 100 in the second row through the capacitive coupling of capacitor 104.

[0093] During period T6, the potential of the wiring 111 is set to a potential corresponding to weighting coefficient W13 (weighting to be added to the pixels in the third row) and the potential of the wiring 112_3 is set to "H", thereby adding weighting coefficient W13 to node N of the pixels 100 in the third row through capacitive coupling of capacitor 104. The operations during periods T4 and T6 correspond to the generation of data in which weighting is added to data without imaging.

[0094] During period T7, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the potential W11+0 flows through the transistor 105 of the pixels 100 in the first row. A current corresponding to the potential W12+0 flows through the transistor 105 of the pixels 100 in the second row. A current corresponding to the potential W13+0 flows through the transistor 105 of the pixels 100 in the third row.

[0095] Here, the potential of the other electrode of capacitor 222 changes in accordance with the current flowing through wiring 113, and this change Y is added to the potential Vr of node C. Therefore, the potential of node C becomes "Vr+Z." If we consider Vr=0, then Z is the difference itself, and data B has been calculated.

[0096] In addition, the potential of the wiring 213 is set to “H” and the potential of the wiring 215 is set to an appropriate analog potential (V bias ), the circuit 201 can output a signal potential according to the data B of the pixel block 200 in the first row by a source follower operation.

[0097] The data A and data B output from the circuit 201 by the above operation are sequentially input to the circuit 202. In the circuit 202, similar to the circuit 201, an operation is performed to find the difference between the data A and the data B, and it is possible to remove unnecessary offset components other than the product of the image data (potential X) and the weighting coefficient (potential W).

[0098] In the above operation, the potential of node C of circuit 201 is initialized to the same potential "Vr" in both the operation of acquiring data A and the operation of acquiring data B. Then, in the subsequent difference calculation, "(Vr+Y)-(Vr+Z)"="YZ", and the component of potential "Vr" is removed. Furthermore, as described above, other unnecessary offset components are also removed, so that the product of image data (potential X) and weighting coefficient (potential W) can be extracted.

[0099] This operation corresponds to the initial operation of a neural network that performs inference, etc. Therefore, at least one calculation can be performed within the imaging device before a large amount of image data is output externally, reducing the load of external calculations and data input / output, speeding up processing, and reducing power consumption.

[0100] Alternatively, as an alternative to the above, the potential of node C of circuit 201 may be initialized to different potentials during the data A acquisition operation and the data B acquisition operation. For example, assume that node C is initialized to potential "Vr1" during the data A acquisition operation and to potential "Vr2" during the data B acquisition operation. In this case, the subsequent difference calculation results in "(Vr1+Y)-(Vr2+Z)" = "(Vr1-Vr2)+(YZ)." As in the above operation, "YZ" is extracted as the product of the image data (potential X) and the weighting coefficient (potential W), and then "Vr1-Vr2" is added to it. Here, "Vr1-Vr2" corresponds to the bias used to adjust the threshold value in the calculation of the intermediate layer of the neural network.

[0101] Furthermore, the weighting functions as a filter for a convolutional neural network (CNN), but may also amplify or attenuate data. For example, if the weighting coefficient (W) during the acquisition operation of data A is the product of the filtering and amplification, filtered data corrected to a bright image can be extracted. Data B is data without imaging, and can also be considered black level data. Therefore, the operation of calculating the difference between data A and data B can be said to be an operation that promotes the visualization of an image captured in a dark place. In other words, brightness correction using a neural network becomes possible.

[0102] As described above, one embodiment of the present invention allows for bias generation through the operation of the imaging device. Functional weighting can also be added within the imaging device. This reduces the load on external computations and can be used for a variety of applications. For example, in addition to subject inference, some of the following processes can be performed within the imaging device: image data resolution correction, brightness correction, color image generation from monochrome images, 3D image generation from 2D images, restoration of missing information, video generation from still images, correction of out-of-focus images, and blurred image generation.

[0103] <Memory cell> 2, at least one memory cell 150 is provided for each pixel block 200. The memory cell 150 stores the product-sum operation results of data acquired by the plurality of pixels 100 in the pixel block 200.

[0104] As mentioned above, the pixels 100 included in the pixel block 200 are not fixed and can be selected arbitrarily. Therefore, the pixel block 200 is configured to always have at least one memory cell 150, regardless of the stride number.

[0105] For example, if the pixel block 200 has 3×3 pixels 100, it is preferable to arrange the pixels 100 and memory cells 150 in the configuration shown in Fig. 10A to accommodate a stride of 1. The configuration shown in Fig. 10A has approximately the same number of pixels 100 and memory cells 150.

[0106] 10A is a schematic diagram and does not show the absolute positional relationship between the pixel 100 and the memory cell 150. For example, in a combination of one pixel 100 and one memory cell 150, the memory cell 150 may be located at any position above, below, left, right, or diagonally of the pixel 100 when viewed from above. Alternatively, the pixel 100 and the memory cell 150 may be provided on different layers and may have overlapping regions.

[0107] 10A shows how the result of a product-sum operation on 3×3 pixels 100 in a pixel block 200 surrounded by a dashed line is written to a central memory cell 150. FIG. 10B shows the next operation at stride 1, in which the result of a product-sum operation on 3×3 pixels 100 in a pixel block 200 shifted by one pixel in the row direction from FIG. 10A is written to a central memory cell 150. Note that the memory cell 150 into which the result of the product-sum operation is written is not limited to the memory cell 150 located in the center, and may be a memory cell 150 located in another position.

[0108] When the number of pixels 100 and the number of memory cells 150 are the same and pixel blocks 200 are selected with a stride of 1, the number of memory cells 150 will be greater than the total number of pixel blocks 200, and therefore writing will not be performed on some of the memory cells 150. Therefore, the number of memory cells 150 may be reduced as appropriate.

[0109] 11A is preferable in order for the pixel block 200 to have 3×3 pixels 100 and to support a stride of 2. The configuration shown in Fig. 11A is a configuration in which, based on the pixels 100 arranged in a matrix, the number of pixels 100 arranged in every other row and every other column is approximately the same as the number of memory cells 150.

[0110] 11A shows how the results of a product-sum operation on 3×3 pixels 100 in a pixel block 200 surrounded by a dashed line are written to memory cells 150. FIG. 11B shows the next operation at stride 2, in which the results of a product-sum operation on 3×3 pixels 100 in a pixel block 200 shifted by two pixels in the row direction from FIG. 11A are written to memory cells 150.

[0111] In this way, when the stride number is fixed to 2 or more, the number of memory cells 150 can be made smaller than the number of pixels 100. Note that, as shown in Figures 10A and 10B, when the number of pixels 100 and the number of memory cells 150 are approximately the same, any stride number can be accommodated.

[0112] 12A is a diagram showing the connection relationship between the memory cell 150, the circuit 304, and the circuit 305. It is preferable to use OS transistors as the transistors that configure the memory cell 150. Here, a configuration including the memory cell 150, the circuit 304, and the circuit 305 is referred to as a memory circuit 151.

[0113] The memory circuit 151 has m (m is an integer of 1 or more) memory cells 150 in a column and n (n is an integer of 1 or more) memory cells in a row, for a total of m×n memory cells 150, which are arranged in a matrix.

[0114] 12B and 12C are diagrams illustrating memory cells 150a and 150b that can be applied to memory cell 150. In the following description, bit lines can be connected to circuit 305 (column driver). Word lines can be connected to circuit 304 (row driver). Bit lines are also electrically connected to circuits 202 and 203, but are not shown here.

[0115] For example, a decoder or a shift register can be used for the circuit 304 (row driver) and the circuit 305 (column driver). Note that a plurality of circuits 304 (row drivers) and circuits 305 (column drivers) may be provided.

[0116] 12B shows an example of a circuit configuration of a gain cell type (also called a "2Tr1C type") memory cell 150a having two transistors and one capacitor. The memory cell 150a has a transistor 273, a transistor 272, and a capacitor 274.

[0117] One of the source or drain of the transistor 273 is connected to one electrode of the capacitor 274, the other of the source or drain of the transistor 273 is connected to the wiring WBL, the gate of the transistor 273 is connected to the wiring WL, and the back gate of the transistor 273 is connected to the wiring BGL. The other electrode of the capacitor 274 is connected to the wiring RL. One of the source or drain of the transistor 273 is connected to the wiring RBL, the other of the source or drain of the transistor 273 is connected to the wiring SL, and the gate of the transistor 272 is connected to one electrode of the capacitor 274.

[0118] The wiring WBL functions as a write bit line. The wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor 274. When writing data and while the data is being held, it is preferable to apply a reference potential to the wiring RL.

[0119] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 273. By applying any potential to the wiring BGL, the threshold voltage of the transistor 273 can be increased or decreased.

[0120] Data is written by applying a high-level potential to the wiring WL, turning on the transistor 273, and electrically connecting the wiring WBL and one electrode of the capacitor 274. Specifically, when the transistor 273 is turned on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to one electrode of the capacitor 274 and the gate of the transistor 272. After that, a low-level potential is applied to the wiring WL, turning off the transistor 273, thereby holding the potential of one electrode of the capacitor 274 and the potential of the gate of the transistor 272.

[0121] Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor 272 and the potential of one of the source and drain of the transistor 273 are determined by the potential of the gate of the transistor 272 and the potential of the other of the source and drain of the transistor 273. Therefore, by reading the potential of the wiring RBL connected to one of the source and drain of the transistor 273, the potential held in one electrode of the capacitor 274 (or the gate of the transistor 272) can be read. In other words, information written in this memory cell can be read from the potential held in one electrode of the capacitor 274 (or the gate of the transistor 272). Alternatively, it can be known whether or not information is written in this memory cell.

[0122] 12C, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. The memory cell 150b shown in FIG. 12C is configured such that the wiring WBL and the wiring RBL of the memory cell 150a are combined into a single wiring BIL, and the other of the source or the drain of the transistor 273 and one of the source or the drain of the transistor 273 are connected to the wiring BIL. In other words, the memory cell 150b is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0123] Note that in the memory cell 150a and the memory cell 150b, it is preferable to use an OS transistor as the transistor 273. A memory device using an OS transistor as the transistor 273 and using a 2Tr1C type memory cell such as the memory cell 150a and the memory cell 150b is called a non-volatile oxide semiconductor random access memory (NOSRAM). Note that the circuit configuration of the memory cell can be changed as appropriate.

[0124] <Circuit 203> The circuit 203 functions as a pooling circuit. A plurality of memory cells 150, in which analog data to be pooled is written, are electrically connected to the circuit 203. The circuit 203 can read out the maximum value of the analog data.

[0125] The circuit 203 may have the configuration shown in FIG. 13, for example. The circuit 203 includes a circuit 230a, a circuit 230b, a circuit 240, a circuit 250, and a plurality of current mirror circuits. In this configuration, the magnitudes of two analog data input to the circuit 230a are compared. The larger of these two analog data is then determined to be significant and compared with the analog data input to the circuit 230b. The larger of these two analog data is then determined to be significant and compared with the analog data input to the circuit 240, and the larger of these two analog data is determined to be significant. The output of the circuit 240 is then converted into a voltage by the circuit 250 and output to an external device (such as the circuit 204). In other words, the maximum value can be read from the analog data written to the four memory cells 150. The number of target memory cells 150 can be changed by appropriately modifying the circuit configuration.

[0126] Here, the current mirror circuit has two p-channel transistors, each with one of its source or drain electrically connected to a power supply line (high-potential power supply line). The gates of the two transistors are electrically connected, and the other of the source or drain of one of the transistors is electrically connected to the gate. Here, one transistor is called the input transistor, and the other transistor is called the output transistor.

[0127] The circuit 230a has terminals a1, a2, and a3. The circuit 230b has terminals b1, b2, and b3. The circuit 240 has terminals c1, c2, and c3.

[0128] The other of the source or drain of the output-side transistor of the current mirror circuit CM is electrically connected to the terminal a1 of the circuit 230a. The other of the source or drain of the input-side transistor of the current mirror circuit CM is electrically connected to the other of the source or drain of the transistor 272 of the memory cell 150 via the selection circuit 155. Therefore, a current of the same value as the current flowing through the transistor 272 of the memory cell 150 is supplied to the terminal a1.

[0129] The selection circuit 155 is electrically connected to a plurality of memory cells 150, and any one selected memory cell 150 can be electrically connected to the current mirror circuit CM. Note that the selection circuit 155 may not be provided in some cases. Alternatively, the selection circuit 155 may be an element of the circuit 203.

[0130] Terminal a2 of circuit 230a, terminal b2 of circuit 230b, and terminal c2 of circuit 240 are also electrically connected to different memory cells 150 via selection circuit 155 and current mirror circuit CM.

[0131] The other of the source and drain of the input-side transistor of the current mirror circuit CMa is electrically connected to terminal a3 of the circuit 230a, and the other of the source and drain of the output-side transistor of the current mirror circuit CMa is electrically connected to terminal b1 of the circuit 230b. A current of the same value as the larger of the currents input to terminal a1 and terminal a2 flows through terminal a3 of the circuit 230a, and a current of the same value as that of terminal a3 flows through terminal b1 of the circuit 230b.

[0132] The other of the source or drain of the input transistor of the current mirror circuit CMb is electrically connected to the terminal b3 of the circuit 230b, and the other of the source or drain of the output transistor of the current mirror circuit CMb is electrically connected to the terminal c1 of the circuit 240. The terminal b3 of the circuit 230b is configured so that a current of the same value as the larger of the currents input to the terminal b1 and the terminal b2 flows, and a current of the same value as that of the terminal b3 flows to the terminal c1 of the circuit 240.

[0133] A current having the same value as the larger of the currents input to terminals c1 and c2 flows through terminal c3 of circuit 240. Therefore, terminal c3 of circuit 240 serves as a readout terminal for the maximum value of the analog data stored in each memory cell 150 that is input to terminals a1, a2, b2, and c2.

[0134] 14A shows a configuration example of the circuit 230a. Note that the circuit 230b can also have a similar configuration by replacing the terminal a1 with the terminal b1, the terminal a2 with the terminal b2, and the terminal a3 with the terminal b3.

[0135] The circuit 230a includes a current mirror circuit CM1 and a current mirror circuit CM2. The current mirror circuits CM1 and CM2 each include three n-channel transistors, each of which has one of its source and drain electrically connected to a power supply line (a low-potential power supply line, a reference potential line such as GND). The gates of the three transistors are electrically connected, and the other of the source and drain of one transistor is electrically connected to the gate. Here, the one transistor is called the input transistor, and the other two transistors are called output transistors.

[0136] Terminal a1 is electrically connected to the other of the source or drain of the input side transistor of current mirror circuit CM1, the gates of the three transistors of current mirror circuit CM1, and the other of the source or drain of one output side transistor of current mirror circuit CM2.

[0137] Terminal a2 is electrically connected to the other of the source or drain of the input transistor of current mirror circuit CM2, the gates of three output transistors of current mirror circuit CM2, and the other of the source or drain of one output transistor of current mirror circuit CM1.

[0138] The terminal a3 is electrically connected to one of the source or drain of the other output transistor (transistor Tr1) of the current mirror circuit CM1 and one of the source or drain of the other output transistor (transistor Tr2) of the current mirror circuit CM2. The other of the source or drain of the transistor Tr1 and the other of the source or drain of the transistor Tr2 are electrically connected to a power supply line (a low-potential power supply line, a reference potential line such as GND).

[0139] In the above configuration, for example, at the beginning of the circuit operation, the current (I a1 ) flows into terminal a2 (I a2 ), the resistance of one output transistor of the current mirror circuit CM1 becomes lower than the resistance of the input transistor of the current mirror circuit CM2.

[0140] Here, the current input to the terminal a2 flows through one of the output transistors of the current mirror circuit CM1, and the potential of the gate of the transistor in the current mirror circuit CM2 decreases. a1 ) is the current (I a2 ), a current flows into the terminal a3 via the transistor Tr1. a1 ) will flow. Conversely, the current flowing into terminal a2 (I a2 ) flows into terminal a1 (I a1 ), the terminal a3 flows a current (I a2 ) will flow a current of the same value.

[0141] An example configuration of circuit 240 is shown in FIG. 14B. Circuit 240 has current mirror circuits CM3 and CM4. Current mirror circuits CM3 and CM4 each have two n-channel transistors, each with one of the source and drain electrically connected to terminal c3. The gates of the two transistors are electrically connected, and the other of the source and drain of one of the transistors is electrically connected to the gate. Here, one of the transistors is called the input transistor, and the other transistor is called the output transistor.

[0142] Terminal c1 is electrically connected to the other of the source or drain of the input transistor of current mirror circuit CM3, the gates of the two transistors of current mirror circuit CM3, and the other of the source or drain of the output transistor of current mirror circuit CM4.

[0143] Terminal c2 is electrically connected to the other of the source or drain of the input side transistor of current mirror circuit CM4, the gates of two transistors of current mirror circuit CM4, and the other of the source or drain of the output side transistor of current mirror circuit CM3.

[0144] In the above configuration, for example, at the beginning of the circuit operation, the current (I c1 ) flows into terminal c2 (I c2 ), the resistance of the output transistor of the current mirror circuit CM3 becomes lower than the resistance of the input transistor of the current mirror circuit CM2.

[0145] Here, the current input to the terminal c2 flows to the output side transistor of the current mirror circuit CM3, and the potential of the gate of the transistor of the current mirror circuit CM4 decreases. c1 ) is the current (I c2 ), the current (I c1 ) flows into terminal c2. Conversely, the current (I c2 ) flows into terminal c1 (I c1 ), the current (I c2 ) will be played.

[0146] The circuit 240 may have a configuration in which the terminal a1 of the circuit in FIG. 14A is replaced with the terminal c1, the terminal a2 with the terminal c2, and the terminal a3 with the terminal c3.

[0147] The current output from circuit 240 to circuit 250 undergoes voltage conversion and, if necessary, binarization, and can then be output externally (such as circuit 204). Circuit 250 may include a circuit that performs activation function calculations. This circuit may be, for example, a comparator circuit. The comparator circuit compares input data with a set threshold value and outputs the result as binary data. In other words, pixel block 200 and circuits 201 to 203 can function as elements of a neural network.

[0148] <Circuit 204> FIG. 15A is a diagram illustrating the circuit 204. Data output from the circuit 203 is input sequentially to the circuit 204. The circuit 204 can be configured to include, for example, a latch circuit and a shift register. This configuration enables parallel-serial conversion to be performed, and data input in parallel can be output as serial data to the wiring 311. There are no limitations on the connection destination of the wiring 311. For example, the wiring 311 can be connected to a neural network, a storage device, a communication device, or the like.

[0149] 15B, the circuit 204 may have a neural network. The neural network has memory cells arranged in a matrix, each holding a weighting coefficient. Data output from the circuit 203 is input to memory cells 320, where a product-sum operation can be performed. Note that the number of memory cells shown in FIG. 15B is an example and is not limited thereto.

[0150] The neural network shown in FIG. 15B includes memory cells 320 and reference memory cells 325 arranged in a matrix, a circuit 330, a circuit 350, a circuit 360, and a circuit 370.

[0151] 16 shows an example of a memory cell 320 and a reference memory cell 325. The reference memory cell 325 is provided in any one column. The memory cell 320 and the reference memory cell 325 have the same configuration, and each include a transistor 161, a transistor 162, and a capacitor 163.

[0152] One of the source or drain of the transistor 161 is electrically connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, the point where one of the source or drain of the transistor 161, the gate of the transistor 162, and one electrode of the capacitor 163 are connected is referred to as a node NM.

[0153] A gate of the transistor 161 is electrically connected to a wiring WL. The other electrode of the capacitor 163 is electrically connected to a wiring RW. One of the source and the drain of the transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.

[0154] In the memory cell 320, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WD. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BL.

[0155] In the reference memory cell 325, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WDref. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BLref.

[0156] The wiring WL is electrically connected to the circuit 330. The circuit 330 can be a decoder, a shift register, or the like.

[0157] The wiring RW is electrically connected to the circuit 301. Binary data output from the circuit 301 is written to each memory cell. Note that a sequential circuit such as a shift register may be provided between the circuit 301 and each memory cell.

[0158] The wiring WD and the wiring WDref are electrically connected to the circuit 350. The circuit 350 may be a decoder, a shift register, or the like. The circuit 350 may also include a D / A converter or an SRAM. The circuit 350 can output the weighting coefficient written to the node NM.

[0159] The wiring BL and the wiring BLref are electrically connected to the circuit 360. The circuit 360 can have the same structure as the circuit 201. The circuit 360 can obtain a signal obtained by removing the offset component from the result of the product-sum operation.

[0160] Circuit 360 is electrically connected to circuit 370. Circuit 370 can also be described as an activation function circuit. The activation function circuit has a function of performing calculations to convert the signal input from circuit 360 according to a predefined activation function. Examples of the activation function that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function. The signal converted by the activation function circuit is output to the outside as output data.

[0161] As shown in FIG. 17A, a neural network NN can be configured with an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, output layer OL, and intermediate layer HL each have one or more neurons (units). The intermediate layer HL may have one layer or two or more layers. A neural network with two or more intermediate layers HL can also be called a DNN (deep neural network). Learning using a deep neural network can also be called deep learning.

[0162] Input data is input to each neuron in the input layer IL. An output signal from a neuron in the previous or next layer is input to each neuron in the hidden layer HL. An output signal from a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron may be connected to all neurons in the previous or next layer (fully connected), or may be connected to only a portion of the neurons in the previous or next layer.

[0163] Figure 17B shows an example of a neuron's operation. It shows neuron N and two neurons in the previous layer that output signals to neuron N. Neuron N receives the output x1 of a neuron in the previous layer and the output x2 of a neuron in the previous layer. Neuron N then calculates the sum x1w1+x2w2 of the multiplication result (x1w1) of output x1 and weight w1 and the multiplication result (x2w2) of output x2 and weight w2, and then adds a bias b as needed to obtain the value a=x1w1+x2w2+b. The value a is then transformed by the activation function h, and neuron N outputs the output signal y=ah.

[0164] In this way, the computation by a neuron includes the sum of the product of the output of the neuron in the previous layer and the weight, i.e., the sum-of-products computation (x1w1+x2w2 above). This sum-of-products computation can be performed by software using a program, or by hardware.

[0165] In one embodiment of the present invention, a product-sum operation is performed using an analog circuit as hardware. When an analog circuit is used for the product-sum operation circuit, the circuit scale of the product-sum operation circuit can be reduced, or the number of accesses to a memory can be reduced, thereby improving the processing speed and reducing power consumption.

[0166] The product-sum circuit preferably includes an OS transistor. Since the off-state current of an OS transistor is extremely small, the OS transistor is suitable as a transistor constituting an analog memory of the product-sum circuit. Note that the product-sum circuit may be configured using both a Si transistor and an OS transistor.

[0167] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0168] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0169] <Structure example> FIG. 18A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0170] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 19A. Note that the term "layer" may be replaced with "region" in some cases.

[0171] 19A is a pn junction photodiode, and for example, a p-type semiconductor may be used for the layer 565a and an n-type semiconductor may be used for the layer 565b. Alternatively, an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.

[0172] The pn junction photodiode can be typically formed using single crystal silicon. Photodiodes using single crystal silicon as a photoelectric conversion layer have a relatively wide spectral sensitivity characteristic, from ultraviolet light to near-infrared light, and can detect light of various wavelengths when combined with an optical conversion layer (described later).

[0173] Alternatively, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode, such as gallium arsenic phosphate (GaAsP), gallium phosphate (GaP), indium gallium arsenic (InGaAs), lead sulfur (PbS), lead selenium (PbSe), indium arsenic (InAs), indium antimony (InSb), or mercury cadmium tellurium (HgCdTe).

[0174] The compound semiconductor is preferably a compound semiconductor (also called a Group 3-5 compound semiconductor) having a Group 13 element (aluminum, gallium, indium, etc.) and a Group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.), or a compound semiconductor (also called a Group 2-6 compound semiconductor) having a Group 12 element (magnesium, zinc, cadmium, mercury, etc.) and a Group 16 element (oxygen, sulfur, selenium, tellurium, etc.).

[0175] Compound semiconductors can change their band gap depending on the combination of constituent elements and their atomic ratio, making it possible to form photodiodes that are sensitive to a wide range of wavelengths, from ultraviolet light to infrared light.

[0176] The wavelength of ultraviolet light can generally be defined as being around 0.01 μm to around 0.38 μm, the wavelength of visible light as being around 0.38 μm to around 0.75 μm, the wavelength of near-infrared light as being around 0.75 μm to around 2.5 μm, the wavelength of mid-infrared light as being around 2.5 μm to around 4 μm, and the wavelength of far-infrared light as being around 4 μm to around 1000 μm.

[0177] For example, to form a photodiode photosensitive from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode photosensitive from ultraviolet light to near-infrared light, the aforementioned silicon or GaAsP or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode photosensitive from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode photosensitive from near-infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode photosensitive from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.

[0178] The photodiode using the compound semiconductor may have a pin junction instead of a pn junction. The pn junction and the pin junction are not limited to a homojunction structure, but may also have a heterojunction structure.

[0179] For example, in a heterojunction, one layer of a pn junction structure can be made of a first compound semiconductor, and the other layer can be made of a second compound semiconductor different from the first compound semiconductor. Alternatively, one or two layers of a pin junction structure can be made of a first compound semiconductor, and the remaining layers can be made of a second compound semiconductor different from the first compound semiconductor. Note that either the first or second compound semiconductor can be a simple semiconductor such as silicon.

[0180] Note that the photoelectric conversion layer of the photodiode may be formed using a different material for each pixel. By using this configuration, an imaging device having two or three types of pixels, such as pixels that detect ultraviolet light, pixels that detect visible light, and pixels that detect infrared light, can be formed.

[0181] 19B, the photoelectric conversion device 101 included in the layer 561 may be a stack of layers 566a, 566b, 566c, and 566d. The photoelectric conversion device 101 shown in FIG. 19B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0182] The layer 566a is preferably a low-resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0183] The layer 566d is preferably a conductive layer that has a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0184] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material, which is a p-type semiconductor, and the layer 566c is made of an n-type semiconductor such as gallium oxide.

[0185] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In these photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. Furthermore, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production, such as the ability to fabricate thin-film photoelectric conversion layers. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering.

[0186] Selenium-based materials can include crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium. These have photosensitivity from ultraviolet light to visible light. Also usable are compounds of copper, indium, and selenium (CIS) and compounds of copper, indium, gallium, and selenium (CIGS). These have photosensitivity from ultraviolet light to near-infrared light.

[0187] The n-type semiconductor is preferably formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer and can reduce dark current.

[0188] 19C, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e. The photoelectric conversion device 101 shown in FIG. 19C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0189] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0190] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C 70 or derivatives thereof can be used.

[0191] The photoelectric conversion layer can be a mixed layer (bulk heterojunction structure) of n-type and p-type organic semiconductors. There are various types of organic semiconductors, and it is sufficient to select a material that has photosensitivity to the desired wavelength for the photoelectric conversion layer.

[0192] A silicon substrate, for example, can be used as the layer 563 shown in FIG. 18A. The silicon substrate has Si transistors and the like. Using the Si transistors, in addition to pixel circuits, circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, and the like can be formed. Furthermore, memory circuits such as DRAMs (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), and the like may also be formed. In this embodiment, the above circuits excluding the pixel circuits are referred to as functional circuits.

[0193] For example, some or all of the transistors included in the pixel circuit (pixel 100) and the functional circuits (circuits 201, 202, 203, 204, 301, 302, 303, 304, 305, and the like) described in Embodiment 1 can be provided in the layer 563.

[0194] Furthermore, the layer 563 may be a laminate of multiple layers as shown in FIG. 18B. Although FIG. 18B illustrates three layers, 563a, 563b, and 563c, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and functional circuits can be distributed across multiple layers and stacked on top of each other, making it possible to manufacture a compact, highly functional imaging device.

[0195] Alternatively, the pixel may have a stacked structure of layers 561, 562, and 563 as shown in FIG. 18C.

[0196] The layer 562 can include OS transistors. One or more of the functional circuits described above may be formed using OS transistors. Alternatively, one or more of the functional circuits may be formed using Si transistors included in the layer 563 and OS transistors included in the layer 562. Alternatively, the layer 563 may be used as a support substrate such as a glass substrate, and pixel circuits and functional circuits may be formed using OS transistors included in the layer 562.

[0197] For example, a normally-off CPU (also referred to as an "NoffCPU (registered trademark)") can be realized using OS transistors and Si transistors. Note that an NoffCPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when the gate voltage is 0 V.

[0198] The NoffCPU can stop the power supply to circuits within the NoffCPU that are not in operation, putting those circuits into standby mode. When power supply is stopped and the circuit is in standby mode, no power is consumed. This allows the NoffCPU to minimize power consumption. The NoffCPU can also retain information necessary for operation, such as setting conditions, for a long period of time even if power supply is stopped. To return from standby mode, it is only necessary to resume power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from standby mode. In this way, the NoffCPU can reduce power consumption without significantly reducing operating speed.

[0199] Furthermore, layer 562 may be a laminate of multiple layers as shown in FIG. 18D. While FIG. 18D illustrates two layers, layers 562a and 562b, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 with a layer formed on layer 561.

[0200] The semiconductor material used for an OS transistor can be a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors that prioritize reliability. Furthermore, CAC-OS exhibits high mobility, making it suitable for transistors that operate at high speed.

[0201] Because of the large energy gap of the semiconductor layer, OS transistors exhibit extremely low off-state currents of a few yA / μm (current value per 1 μm of channel width). Furthermore, unlike Si transistors, OS transistors have characteristics such as the absence of impact ionization, avalanche breakdown, and short-channel effects, making them suitable for the formation of high-voltage, highly reliable circuits. Furthermore, OS transistors are less susceptible to variations in electrical characteristics due to non-uniformity in crystallinity, which is a problem with Si transistors.

[0202] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (one or more metals selected from aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, hafnium, and the like). The In-M-Zn oxide can typically be formed by a sputtering method. Alternatively, it may be formed by an atomic layer deposition (ALD) method.

[0203] The atomic ratio of the metal elements in a sputtering target used to form an In-M-Zn-based oxide by sputtering preferably satisfies In≧M and Zn≧M. Preferred atomic ratios of the metal elements in such sputtering targets are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratios of the semiconductor layer to be formed each have a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target.

[0204] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3or less, more preferably 1 × 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 An oxide semiconductor having a carrier density above or equal to this can be used. Such an oxide semiconductor is called a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and stable characteristics.

[0205] Note that the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0206] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0207] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0208] Furthermore, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons acting as carriers are generated, increasing the carrier density and making the semiconductor layer more likely to be n-type. As a result, transistors using oxide semiconductors that contain nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0209] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0210] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0211] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0212] The semiconductor layer may also have a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0213] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0214] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single-crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0215] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single-crystal semiconductor layer.

[0216] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0217] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0218] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into mosaics, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0219] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0220] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0221] The crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals are connected together with their c-axis orientation and no orientation in the ab plane.

[0222] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. CAC-OS is a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element in CAC-OS.

[0223] Note that CAC-OS does not include a stacked structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0224] In addition, GaO X3The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0225] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0226] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the better. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0227] CAC-OS has the characteristic that no clear peaks are observed when measured using the θ / 2θ scan by the out-of-plane X-ray diffraction (XRD) method, which indicates that the ab-plane and c-axis orientations of the measured region are not observed.

[0228] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nanobeam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern indicates that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0229] For example, in the case of CAC-OS made of In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0230] CAC-OS has a different structure from IGZO compounds, in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0231] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited.X2 Zn Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud-like shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0232] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0233] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to X2 Zn Y2 O Z2 , or InO X1 The conductivity due to the gate insulating layer and the gate insulating layer work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ) can be achieved.

[0234] Furthermore, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0235] <Laminated structure 1> Next, the layered structure of the imaging device will be described using cross-sectional views. Note that the elements such as the insulating layer and conductive layer shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted. Furthermore, the layered structure shown below can be formed using a bonding process, a polishing process, or the like, as necessary.

[0236] FIG. 20 is an example of a cross-sectional view of a laminate having layers 560, 561, and 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0237] <layer 563b> The layer 563b can have a functional circuit provided on the silicon substrate 611. Here, the transistor 227, the transistor 223, the transistor 224, and the capacitor 222 included in the circuit 201 are shown as part of the functional circuit.

[0238] The layer 563b includes a silicon substrate 611 and insulating layers 612, 613, 614, 616, 617, and 618. The insulating layer 612 functions as a protective film. The insulating layers 613, 613, 616, and 617 function as an interlayer insulating film and a planarizing film. The insulating layer 618 and the conductive layer 619 function as a bonding layer. The conductive layer 619 is electrically connected to the gate of the transistor 105.

[0239] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The lamination layer will be described later.

[0240] Conductors that can be used as wiring, electrodes, and plugs for electrical connection between devices may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may also be made of multiple layers composed of different materials.

[0241] <Layer 563a> The layer 563a includes elements of the pixel 100 and may also include elements of a functional circuit. Here, the transistor 102 and the transistor 108 are shown as some of the elements of the pixel 100. In the cross-sectional view shown in FIG. 20, electrical connection between them is not shown.

[0242] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638, and conductive layers 636 and 639.

[0243] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as interlayer insulating films and planarizing films. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 from the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. Alternatively, the insulating layer 638 may be formed of the same material as the insulating layer 631.

[0244] The conductive layer 639 is electrically connected to the other of the source and the drain of the transistor 105 and the conductive layer 619. The conductive layer 636 is electrically connected to the wiring 114 (see FIG. 6).

[0245] The Si transistor shown in Fig. 20 is a fin type having a channel formation region in a silicon substrate (silicon substrates 611 and 632). A cross section in the channel width direction (a cross section taken along A1-A2 in layer 563a in Fig. 20) is shown in Fig. 21A. The Si transistor may also be a planar type, as shown in Fig. 21B.

[0246] 21C, the transistor may have a silicon thin film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 611.

[0247] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 20 shows a configuration in which the organic photoconductive film shown in Fig. 19C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Here, the layer 567a is the cathode, and the layer 567e is the anode.

[0248] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655.

[0249] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101 and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. An organic insulating film or the like is preferably used as the element isolation layer.

[0250] The layer 567a, which corresponds to the cathode of the photoelectric conversion device 101, is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e, which corresponds to the anode of the photoelectric conversion device 101, is electrically connected to the conductive layer 636 included in the layer 563a via the conductive layer 655.

[0251] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0252] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. The metal layer may also be stacked with a dielectric film that functions as an anti-reflection film.

[0253] When the photoelectric conversion device 101 is sensitive to visible light, a color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters for each pixel. For example, as shown in the perspective view (including cross section) of FIG. 30A, a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to each different pixel.

[0254] Furthermore, in a suitable combination of the photoelectric conversion device 101 and the optical conversion layer 672, if a wavelength cut filter is used in the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0255] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths shorter than visible light in the optical conversion layer 672. Alternatively, a far-infrared imaging device can be formed by using a filter that blocks light with wavelengths shorter than near-infrared light in the optical conversion layer 672. Alternatively, an ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths longer than visible light in the optical conversion layer 672.

[0256] Note that a plurality of different optical conversion layers may be arranged within a single imaging device. For example, as shown in FIG. 30B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR may be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0257] 30C, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels, respectively. In this configuration, visible light images and ultraviolet light images can be acquired simultaneously.

[0258] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting this light with the photoelectric conversion device 101. An imaging device having such a configuration may also be used as a radiation detector or the like.

[0259] Scintillators contain a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with such radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, or the like dispersed in resin or ceramics can be used.

[0260] Imaging using infrared or ultraviolet light can provide the imaging device with inspection functions, security functions, sensor functions, etc. For example, imaging using infrared light can be used for non-destructive testing of produce, sorting of agricultural products (such as a sugar content meter function), vein authentication, medical testing, etc. Furthermore, imaging using ultraviolet light can detect ultraviolet light emitted from a light source or flame, allowing for management of light sources, heat sources, production equipment, etc.

[0261] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, thereby enabling efficient photoelectric conversion. The microlens array 673 is preferably formed from a resin or glass that is highly translucent to light of the target wavelength.

[0262] <Laminating> Next, the bonding of the layer 563b and the layer 563a will be described.

[0263] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0264] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0265] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0266] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferred for ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0267] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded together at the boundary between them.

[0268] The conductive layers 619 and 639 may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0269] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Furthermore, it is possible to obtain connection between the insulating layer 618 and the insulating layer 631 with sufficient mechanical strength.

[0270] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0271] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0272] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0273] For example, a method can be used in which the surface is polished, cleaned, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0274] By the above-described bonding, the circuit included in the layer 563b can be electrically connected to the elements of the pixel 100 included in the layer 563a.

[0275] <Modification of laminate structure 1> FIG. 22 shows a modified example of the stacked structure shown in FIG. 20, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and a bonding surface is also provided between the layer 561 and the layer 563a.

[0276] Layer 561 includes photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers 685, 686.

[0277] The photoelectric conversion device 101 is a pn junction photodiode, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example is shown in which a pn junction photodiode is formed on a silicon substrate. The photoelectric conversion device 101 is a buried photodiode, and a thin p-type region (part of layer 565b) provided on the surface side (current extraction side) of layer 565a can suppress dark current and reduce noise.

[0278] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer.

[0279] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. The insulating layer 665 can prevent carriers generated in the photoelectric conversion device 101 from flowing into adjacent pixels. The insulating layer 665 also has the function of preventing stray light from entering. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0280] The insulating layer 664 can be formed using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using an STI (Shallow Trench Isolation) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin can be used as the insulating layer 665. The insulating layer 665 may have a multi-layer structure. A space may be provided in part of the insulating layer 665. The space may contain a gas such as air or an inert gas. The space may also be under reduced pressure.

[0281] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions buried in the insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0282] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. A conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0283] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have regions buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0284] Here, the conductive layers 683, 684, 685, and 686 are the same bonding layers as the above-described conductive layers 619 and 639. The insulating layers 638 and 661 are the same bonding layers as the above-described insulating layers 618 and 631.

[0285] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to either the source or the drain of the transistor 102. Also, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 114 (see FIG. 6). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 563a.

[0286] 23 shows a modified example different from the above, in which the transistor 102 is provided in the layer 561. In this configuration, one of the source and the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and the drain acts as a node N. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred, and an imaging device with low noise can be obtained.

[0287] The other of the source and the drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692. The gate of the transistor 105 included in the layer 563 is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0288] <Laminated structure 2> 24 is an example cross-sectional view of a stack having layers 560, 561, 562, and 563 and no bonding surface. A Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Note that the structures of the layers 563, 561, and 560 are the same as those shown in FIG. 20, and therefore description thereof will be omitted here.

[0289] <layer 562> A layer 562 is formed over the layer 563. The layer 562 includes OS transistors. Here, the transistors 102 and 108 are shown. In the cross-sectional view shown in FIG. 24, electrical connection between the two is not shown.

[0290] The layer 562 includes insulating layers 621, 622, 623, 624, 625, 626, and 628. A conductive layer 627 is also provided. The conductive layer 627 can be electrically connected to the wiring 114 (see FIG. 6).

[0291] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 function as an interlayer insulating film and a planarizing film. The insulating layer 624 functions as a protective film.

[0292] The blocking layer is preferably a film that has a function of preventing hydrogen diffusion. In Si devices, hydrogen is required to terminate dangling bonds. However, hydrogen near an OS transistor can generate carriers in the oxide semiconductor layer, reducing reliability. Therefore, a hydrogen blocking film is preferably provided between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0293] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0294] The other of the source and the drain of the transistor 108 is electrically connected to the gate of the transistor 105 through a plug. The conductive layer 627 is electrically connected to the wiring 114 (see FIG. 3A).

[0295] One of the source and drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561.

[0296] 25A shows the details of an OS transistor. The OS transistor shown in Fig. 25A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0297] The OS transistor can have a structure including a channel formation region 708, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0298] As shown in FIG. 25B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0299] Alternatively, as shown in FIG. 25C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0300] Although the OS transistor has a back gate 735, it may not have a back gate. The back gate 735 may be electrically connected to the front gate of the transistor provided opposite to it, as shown in the cross-sectional view of the transistor in the channel width direction in FIG. 25D. Note that FIG. 25D illustrates the cross section of the transistor taken along line B1-B2 in FIG. 25A as an example, but the same applies to transistors with other structures. Furthermore, a fixed potential different from that of the front gate may be supplied to the back gate 735.

[0301] <Modification of laminate structure 2> 26 is a modified example of the stacked structure shown in FIG. 25, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 562 are different, and a bonding surface is provided between the layer 561 and the layer 562.

[0302] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode, and has the same configuration as that shown in FIG.

[0303] In the layer 562, an insulating layer 648 is formed over the insulating layer 628. Furthermore, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0304] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0305] Here, the conductive layers 688 and 689 are the same bonding layer as the above-mentioned conductive layers 619 and 639. The insulating layer 648 is the same bonding layer as the above-mentioned insulating layers 618 and 631.

[0306] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to either the source or the drain of the transistor 102. Also, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 114 (see FIG. 6). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 562.

[0307] When stacking multiple Si devices, multiple polishing and bonding processes are required. This poses challenges such as a large number of steps, the need for specialized equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking them on a semiconductor substrate on which other devices are already formed, eliminating the need for bonding processes.

[0308] Note that the structure in which the transistor 102 is provided in the layer 561 shown in FIG. 23 may be applied to this structure.

[0309] 27, a reflective layer 629 may be provided between the photoelectric conversion device 101 and the OS transistor. Most of the light (indicated by the arrow) incident on the photoelectric conversion device 101 is absorbed by the semiconductor layer of the photoelectric conversion device. However, some light with a long wavelength may pass through the photoelectric conversion device 101 and reach the underlying device.

[0310] Irradiation of light onto an OS transistor can cause noise, such as an increase in off-state current. The noise can be reduced by providing the reflective layer 629. Furthermore, fixing the potential of the reflective layer 629 to a GND potential or the like can act as an electromagnetic shield, further reducing noise.

[0311] Furthermore, the light reflected by the reflective layer 629 returns to the semiconductor layer of the photoelectric conversion device 101 and contributes to photoelectric conversion, thereby increasing the sensitivity of the photoelectric conversion device 101. The reflective layer 629 can be formed from a metal material similar to the conductors that can be used for the wiring, electrodes, and plugs described above.

[0312] It is preferable that the surface of the reflective layer 629 is configured to efficiently reflect light incident on the photoelectric conversion device 101. As such a configuration, the practitioner can appropriately select an optimum structure, such as providing irregularities on the surface of the reflective layer 629 or making the surface of the reflective layer 629 into a mirror-like state.

[0313] The memory cells 150 may be provided in the layer 562, for example. The circuit 203 having a pooling function may be provided in the layer 563, for example.

[0314] 28 shows a configuration in which transistors 102, 108, etc., which are elements of the pixel circuit, and transistor 272, etc., which are elements of the memory cell 150, are provided on the same surface of a layer 562. Also, a transistor 271 (corresponding to the input side transistor of the current mirror circuit CM), which is an element of the circuit 203, is provided on a layer 563. The transistor 272 is electrically connected to the transistor 271 via a plug or the like.

[0315] 29 shows a stacked structure in which transistors 102, 105, 108, and the like, which are elements of the pixel circuit, overlap with transistors 272, 273, and the like, which are elements of the memory cell 150, in the layer 562. This structure reduces the circuit area, enabling the formation of a highly functional and compact imaging device. Furthermore, the distance of the wiring electrically connecting the stacked elements can be shortened, enabling high-speed operation with low power consumption.

[0316] 28 and 29 show an example in which memory cell 150 is formed using OS transistors. In the case in which memory cell 150 is formed using Si transistors, the transistors constituting memory cell 150 can be provided in layer 563a shown in FIGS.

[0317] 28 and 29 may be applied to the structure shown in Fig. 23 in which the transistor 102 is provided in the layer 561. Also, the structure of the photoelectric conversion device 101 shown in Fig. 24 may be applied.

[0318] <Package, Module> 31A1 is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see FIG. 31A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0319] 31A2 is a perspective view of the underside of the package. The underside of the package has a BGA (Ball Grid Array) with solder balls as bumps 440. Note that the package is not limited to a BGA, and may have an LGA (Land Grid Array) or a PGA (Pin Grid Array), etc.

[0320] 31A3 is a perspective view of the package, with part of the cover glass 420 and adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0321] 31B1 is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (FIG. 31B3), a lens cover 421, and a lens 435. An IC chip 490 (FIG. 31B3) having functions such as a drive circuit for the imaging device and a signal conversion circuit is also provided between the package substrate 411 and the image sensor chip 451, and the camera module is configured as a SiP (System in Package).

[0322] 31B2 is a perspective view of the appearance of the bottom side of the camera module. The bottom and side surfaces of package substrate 411 have a QFN (quad flat no-lead package) configuration with mounting lands 441 provided. Note that this configuration is just one example, and a QFP (quad flat package) or the aforementioned BGA may also be provided.

[0323] 31B3 is a perspective view of the module, omitting a portion of lens cover 421 and lens 435. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0324] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0325] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0326] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable types, portable data terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio player, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS.

[0327] 32A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the mobile phone.

[0328] 32B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal.

[0329] FIG. 32C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling, enabling imaging of the entire periphery. The imaging device and its operating method according to one embodiment of the present invention can be applied to the elements for acquiring images in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0330] 32D shows a video camera including a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. An imaging device and an operation method thereof according to one embodiment of the present invention can be applied to the video camera.

[0331] 32E shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, etc. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this digital camera.

[0332] 32F shows a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and therefore easily worn on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal.

[0333] FIG. 33 illustrates an external view of an automobile as an example of a moving object. The automobile 890 includes a plurality of cameras 891 and the like, and can acquire information on the front, rear, left, right, and above the automobile 890. The imaging device and its operation method according to one embodiment of the present invention can be applied to the camera 891. The automobile 890 also includes various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar. The automobile 890 analyzes images acquired by the camera 891 in a plurality of imaging directions 892, determines surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. The camera 891 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0334] In an imaging device according to one embodiment of the present invention, the obtained image data can be subjected to arithmetic processing such as neural network processing, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0335] Although an automobile has been described above as an example of a moving body, the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen-powered automobile, and the like. Furthermore, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and a system using artificial intelligence can be provided to these moving bodies by applying a computer according to one embodiment of the present invention. [Explanation of symbols]

[0336] a1: terminal, a2: terminal, a3: terminal, b1: terminal, b2: terminal, b3: terminal, c1: terminal, c2: terminal, c3: terminal, CM: current mirror circuit, CMa: current mirror circuit, CMb: current mirror circuit, CM1: current mirror circuit, CM2: current mirror circuit, CM3: current mirror circuit, CM4: current mirror circuit, G1: signal line, G2: signal line, Tr1: transistor, Tr2: transistor, 100: pixel, 101: photoelectric conversion device, 102: transistor, 103: transistor, 104: capacitor, 105: transistor , 106: transistor, 108: transistor, 109: capacitor, 111: wiring, 112: wiring, 112_1: wiring, 112_2: wiring, 112_3: wiring, 113: wiring, 114: wiring, 115: wiring, 116: wiring, 117: wiring, 122: wiring, 122_1: wiring, 122_2: wiring, 122_3: wiring, 140: wiring, 141: wiring, 142: wiring, 150: memory cell, 150a: memory cell, 150b: memory cell, 151: memory circuit, 155: selection circuit, 161: transistor, 162: transistor, 163: capacitor, 2 00: pixel block, 201: circuit, 202: circuit, 203: circuit, 204: circuit, 212: wiring, 213: wiring, 215: wiring, 216: wiring, 217: wiring, 218: wiring, 219: wiring, 222: capacitor, 223: transistor, 224: transistor, 225: transistor, 226: transistor, 227: transistor, 230: circuit, 230a: circuit, 230b: circuit, 240: circuit, 250: circuit, 271: transistor, 272: transistor, 273: transistor, 274: capacitor, 300: pixel array, 301: circuit , 302: Circuit, 303: Circuit, 304: Circuit, 305: Circuit, 311: Wiring, 320: Memory cell, 325: Reference memory cell, 330: Circuit, 350: Circuit, 360: Circuit, 370: Circuit, 410: Package substrate, 411: Package substrate, 420: Cover glass, 421: Lens cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image sensor chip, 451: Image sensor chip, 460: Electrode pad, 461: Electrode pad, 470: Wire, 471: Wire, 490: IC chip, 545: Semiconductor layer,546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer, 614: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 6 26: insulating layer, 627: conductive layer, 628: insulating layer, 629: reflective layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672: optical conversion layer, 672B: color filter, 672G: color filter, 672IR: infrared filter, 6 72R: color filter, 672UV: ultraviolet filter, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 691: conductive layer, 692: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 708: channel formation region, 735: back gate, 890: automobile, 891: camera, 892: imaging direction, 911: housing, 912: display unit, 9 13: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: support stand, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation keys, 975: lens, 976: connection unit, 977: speaker, 978: microphone, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

[Claim 1] a plurality of pixel blocks and a first circuit; each of the plurality of pixel blocks includes a plurality of pixels and a memory cell; the memory cell includes a first transistor, a second transistor, and a first capacitor; one of the source and the drain of the first transistor, one electrode of the first capacitor, and the gate of the second transistor are electrically connected to one another; one of the plurality of pixels includes a photoelectric conversion device, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor; one electrode of the photoelectric conversion device is electrically connected to one of the source and drain of the third transistor; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor and the gate of the fifth transistor; one of a source or a drain of the fifth transistor is electrically connected to one of a source or a drain of the sixth transistor; the other of the source and the drain of the fifth transistor is electrically connected to one electrode of the second capacitor; the other electrode of the second capacitor is electrically connected to a back gate of the fifth transistor and one of the source and the drain of the seventh transistor; the memory cells store analog data calculated in accordance with data generated by the plurality of pixels; the first circuit has a function of reading out a maximum value of the analog data stored in the memory cells of each of the plurality of pixel blocks; Imaging device.

Images