Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving the on resistance characteristic.SOLUTION: Inside a trench 5 forming a trench gate structure, a deposition insulating layer 6 is provided on a collector side relative to a gate electrode 8. Inside an n- type drift layer 2, a p type column region 14 and an n type blocking region 15 are provided selectively. The n type blocking region 15 is provided on the collector side relative to a bottom part of the trench 5 so that the impurity concentration of the n- type drift layer 2 at a position of limiting the voltage resistance will not become high. The p type column region 14 is provided between the adjacent trenches 5 apart from the trenches 5, and is electrically connected to an emitter electrode 10. The p type column region 14 penetrates an n+ type emitter region 4 and a p- type base region 3, is in contact with the n+ type emitter region 4 and the p- type base region 3, has a constant width before reaching the n type blocking region 15, and has uniform impurity concentration.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, as a semiconductor device (hereinafter referred to as MOS type semiconductor device) with a MOS gate (insulated gate made of metal-oxide-semiconductor) structure used in a power device, a device having a trench gate structure in which a MOS gate is embedded in a trench formed in a semiconductor substrate is well known. In a MOS type semiconductor device with this trench gate structure, there is generally a trade-off between high breakdown voltage and low on-resistance. As a MOS type semiconductor device that improves this trade-off, a device has been proposed that includes a floating region of a conductivity type different from that of the drift layer, which is provided so as to surround the bottom (drain side end) of the trench in which the MOS gate is embedded (see, for example, Patent Document 1 below).

[0003] The structure of a conventional MOS type semiconductor device will be described. FIG. 6 is a cross-sectional view showing the structure of a main part of a conventional semiconductor device. FIG. 6 shows the structure of a unit cell (functional unit of an element) arranged in an active region through which current flows when in an on-state. FIG. 6 corresponds to FIG. 1 of Patent Document 1 listed below. As shown in FIG. 6, a conventional semiconductor device 100 has n - The first main surface of the drift layer 102 is provided with a MOS gate structure, and the second main surface is provided with an n + The MOS gate structure has a p - Type base region 103, n + The n-type source region 104, the trench 105, the deposited insulating layer 106, the gate insulating film 107, and the gate electrode 108. + The source region 104 is p - It is selectively provided inside the mold base region 103 .

[0004] The trench 105 has a depth of n + type source region 104 and p - through the n-type base region 103 -The deposited insulating layer 106 is embedded in the trench 105 on the drain side. The gate electrode 108 is provided on the source side of the deposited insulating layer 106 inside the trench 105. The gate electrode 108 is connected to the p-type drift layer 102 with a gate insulating film 107 provided on the side wall of the trench 105 in between. - type base region 103 and n + Opposite to the n-type source region 104. - A floating p-type diffusion region (hereinafter referred to as a p-type buried region) 109 is provided inside the drift layer 102. The bottom of the trench 105 is located inside the p-type buried region 109. Reference numerals 110 and 111 denote a source electrode and a drain electrode, respectively.

[0005] The conventional semiconductor device 100 has n - By providing a structure (hereinafter referred to as a floating structure) with a floating p-type buried region 109 inside the n-type drift layer 102, the following characteristics are obtained. - The inside of the p-type drift layer 102 - type base region 103 and n - A depletion layer (not shown) spreads from the pn junction 121 between the p-type drift layer 102 and the p-type buried region 109. When this depletion layer reaches the p-type buried region 109, the p-type buried region 109 is punched through, and the p - type base region 103 and n - The potential from the pn junction 121 between the n-type drift layer 102 and the p-type buried region 109 is fixed. - The p-type drift layer 102 includes a p-type buried region 109 and an n-type buried region 109. - A depletion layer (not shown) also spreads from the pn junction 122 between the type drift layer 102 and the pn junction 122 .

[0006] In this way p - type base region 103 and n - A depletion layer spreads from the pn junction 121 between the p-type buried region 109 and the n-type drift layer 102, and the electric field intensity peaks near the pn junction 121. -A depletion layer spreads from the pn junction 122 between the n-type drift layer 102 and the n-type drift layer 104, and a peak of the electric field strength is also formed near the pn junction 122. In other words, the peak of the electric field strength can be distributed to two locations. This reduces the maximum peak value of the electric field strength, and increases the breakdown voltage. Furthermore, since a high breakdown voltage can be ensured, - A low on-resistance can be achieved by increasing the impurity concentration in the type drift layer 102. Regarding the mechanism of such a floating structure, calculation results of the electric field strength distribution are disclosed in detail (see, for example, Patent Document 2 below).

[0007] For example, in a typical MOS semiconductor device used in an inverter circuit or the like, the drain voltage Vd is generally changed by controlling the on / off state of the semiconductor device using the gate voltage Vg. FIG. 7 is a characteristic diagram showing the voltage waveform of a conventional semiconductor device. Specifically, as shown in FIG. 7, in the on state (hereinafter referred to as the first state A) where a gate voltage Vg equal to or higher than the threshold voltage is applied, n - Since the depletion layer does not extend to the n-type drift layer, the drain voltage Vd is low and the device operates in a low on-resistance state. On the other hand, while the off state is maintained without applying the gate voltage Vg (hereinafter referred to as the second state B), - The depletion layer expands in the drift layer (high on-resistance state), and the drain voltage Vd is maintained at a high level. In other words, the depletion layer expands to maintain the breakdown voltage between the drain and source. Then, by transitioning from the off state to the on state again (hereinafter referred to as the third state C), the width of the depletion layer that expanded in the second state narrows, and the device again operates in a low on-resistance state. After that, the second state B and the third state C are alternately repeated. In this way, in a normal MOS semiconductor device (a MOS semiconductor device without a floating structure), in the second state B, - p inside the drift layer - Type base region and n - The depletion layer spreads from the pn junction between the ion-type drift layer and the p - Type base region and n -The width of the depletion layer extending from the pn junction with the type drift layer is p - Type base area to n - The supply of holes to the drift layer causes instantaneous narrowing.

[0008] However, in the conventional semiconductor device 100 with a floating structure shown in FIG. 6, it is difficult to return from a high on-resistance state to a low on-resistance state in the third state C compared to a normal MOS type semiconductor device. The reason for this is as follows. In the conventional semiconductor device 100, in the second state B, - type base region 103 and n - a pn junction 121 between the p-type buried region 109 and the n-type drift layer 102; - In the third state C, the depletion layer spreads from the pn junction 122 connected to the source electrode 110. - Although holes are supplied to the base region 103 from the outside, because the p-type buried region 109 is in a floating state, no holes are supplied to the p-type buried region 109 from the outside. Therefore, in the third state C, the supply of holes from the p-type buried region 109 itself is not enough to quickly narrow the depletion layer that has expanded toward the drain side of the p-type buried region 109. That is, the amount of holes required to narrow the depletion layer in the third state C is insufficient, and it takes time for the depletion layer that has expanded to the drain side of the p-type buried region 109 to narrow again. As a result, as shown by the dotted line in Figure 7, in the third state C, the drain voltage Vd gradually decreases and reaches its minimum value. Therefore, the device does not immediately return to a low on-resistance state, adversely affecting the transient on-resistance characteristics. In particular, when the chip size is large, the amount of holes required to narrow the depletion layer in the third state C increases, resulting in a delay in the hole supply. Generally, the chip size at which the on-resistance characteristics are adversely affected is several mm square or larger.

[0009] As another device of the conventional floating structure, a device is provided along the gate insulating film provided on the side wall of the trench and p - The p-type base region is connected to the floating p-type diffusion region (p-type buried region), and serves as a hole supply path to the floating p-type diffusion region when the transistor is on. -- An apparatus equipped with a mold diffusion region has been proposed (see, for example, Patent Document 3 listed below).

[0010] The structure shown in Patent Document 3 below will be described. FIG. 8 is a cross-sectional view showing the structure of another example of a conventional semiconductor device. FIG. 8 shows a cross-sectional structure of a gate electrode 108 embedded in a trench 105 having a linear planar shape, cut parallel to the longitudinal direction of the trench 105. FIG. 8 corresponds to FIG. 4 of Patent Document 3 below. A conventional semiconductor device 200 shown in FIG. 8 differs from the conventional semiconductor device 100 shown in FIG. 6 in that n - The inside of the p-type drift layer 102 -- The point is that the mold diffusion region 112 is provided. -- The p-type diffusion region 112 is provided along a portion of the sidewall of the trench 105 in the deposited insulating layer 106. - The p-type base region 103 and the p-type buried region 109 are connected.

[0011] p -- The n-type diffusion region 112 has a very low impurity concentration. - The depletion layer extending from the pn junction between the p-type buried region 109 and the p-type drift layer 102 creates an ultra-high resistance region. Therefore, in the off state, the p-type buried region 109 is in a floating state similar to the conventional semiconductor device 100 shown in FIG. 6 (Patent Documents 1 and 2 listed below). Therefore, similar to the floating structure described above, the drain-source breakdown voltage is maintained, and a high breakdown voltage can be achieved. On the other hand, in the on state, the p -- The p-type buried region 109 is fixed to the source potential by the p-type diffusion region 112, so that n - Holes are supplied to the type drift layer 102. Therefore, the amount of holes supplied in the on state can be increased.

[0012] In FIG. 8, reference numerals 115 to 119 respectively denote the trench, deposited insulating layer, gate insulating film, gate electrode, and p-type buried region of the termination structure 202. The trench 115, deposited insulating layer 116, gate insulating film 117, gate electrode 118, and p-type buried region 119 of the termination structure 202 have the same structures as the trench 105, deposited insulating layer 106, gate insulating film 107, gate electrode 108, and p-type buried region 109 of the active region 201. The gate electrode 118 is provided in the trench 115 closest to the active region 201, and the remaining trenches 115 are filled with the deposited insulating layer 116. The termination structure 202 surrounds the active region 201 and has n - This is a region that relaxes the electric field on the first main surface side of the type drift layer 102 and maintains the breakdown voltage. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-142243 [Patent Document 2] Japanese Patent Application Publication No. 9-191109 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-242852 Summary of the Invention [Problem to be solved by the invention]

[0014] However, although Patent Documents 1 and 2 can reduce the electric field strength near the bottom of trench 105, they do not disclose preventing extraction of minority carriers (holes) in the on-state. Furthermore, even if Patent Documents 1 and 2 are applied to a device utilizing the conductivity modulation effect, such as an insulated gate bipolar transistor (IGBT), the conductivity modulation effect is not improved. Furthermore, when Patent Document 3 is applied to a device utilizing the conductivity modulation effect, such as an IGBT, holes are extracted from p-type buried region 109, which is fixed to the source potential, in the on-state. This makes it difficult for conductivity modulation to occur, resulting in a problem of degraded on-resistance characteristics.

[0015] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor device capable of improving the on-resistance characteristics. [Means for solving the problem]

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A base region of a second conductivity type is provided on the first main surface side of a drift layer of a first conductivity type. An emitter region of a first conductivity type is selectively provided inside the base region. The emitter region has a higher impurity concentration than the drift layer. A trench penetrates the emitter region and the base region to reach the drift layer. An insulating layer having a first thickness is provided at the bottom of the trench. A gate insulating film having a second thickness is provided on the sidewall of the trench. A gate electrode is provided inside the gate insulating film and on the insulating layer. A gate trench portion includes the insulating layer, the gate insulating film, and the gate electrode. The emitter electrode is insulated from the gate electrode by an interlayer insulating film. A high-concentration region of a second conductivity type is provided between adjacent gate trench portions, deeper toward the second main surface side of the drift layer than the bottom of the trench. The high-concentration region has a higher impurity concentration than the base region. An end of the high-concentration region on the second main surface side. In contact with A blocking region of a first conductivity type is provided surrounding the drift layer. The blocking region has a higher impurity concentration than the drift layer. The emitter region and the high-concentration region are connected to the emitter electrode. The blocking region is provided at a position deeper than the bottom of the trench toward the second main surface of the drift layer. The high-concentration region penetrates the emitter region and the base region, contacts the emitter region and the base region, has a constant width until it reaches the blocking region, and has a uniform impurity concentration. The drift layer, the base region, the emitter region, the high-concentration region, and the blocking region are made of silicon carbide.

[0017] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A base region of a second conductivity type is provided on the first main surface side of a drift layer of a first conductivity type. A source region of a first conductivity type is selectively provided inside the base region. The source region has a higher impurity concentration than the drift layer. A trench penetrates the source region and the base region to reach the drift layer. An insulating layer having a first thickness is provided at the bottom of the trench. A gate insulating film having a second thickness is provided on the sidewall of the trench. A gate electrode is provided inside the gate insulating film and on the insulating layer. A gate trench portion includes the insulating layer, the gate insulating film, and the gate electrode. The source electrode is insulated from the gate electrode by an interlayer insulating film. A high-concentration region of a second conductivity type is provided between adjacent gate trench portions, deeper toward the second main surface side of the drift layer than the bottom of the trench. The high-concentration region has a higher impurity concentration than the base region. An end of the high-concentration region on the second main surface side. In contact with A blocking region of a first conductivity type is provided surrounding the drift layer. The blocking region has a higher impurity concentration than the drift layer. The source region and the high-concentration region are connected to the source electrode. The blocking region is provided at a position deeper than the bottom of the trench toward the second main surface of the drift layer. The high-concentration region penetrates the source region and the base region, contacts the source region and the base region, has a constant width until it reaches the blocking region, and has a uniform impurity concentration. The drift layer, the base region, the source region, the high-concentration region, and the blocking region are made of silicon carbide. [Effects of the Invention]

[0018] The semiconductor device according to the present invention has the effect of improving the on-resistance characteristics. [Brief explanation of the drawings]

[0019] [Figure 1]1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing the structure of a main part of a conventional semiconductor device. [Figure 7] FIG. 10 is a characteristic diagram showing a voltage waveform of a conventional semiconductor device. [Figure 8] FIG. 10 is a cross-sectional view showing the structure of another example of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0020] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0021] (Embodiment 1) The structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 1 shows the cross-sectional structure of the semiconductor device according to the first embodiment in an off state. The off state is a state in which the semiconductor device does not operate, and is a state in which the gate voltage is at least 0 V or less (a state in which no gate voltage is applied to the gate electrode or a negative gate voltage is applied). The on state is a state in which the semiconductor device operates, and is a state in which the gate voltage is a threshold voltage or more (gate voltage≧threshold voltage). As shown in FIG. 1, in the semiconductor device according to the first embodiment, n - Mold drift layer (semiconductor layer) A MOS gate structure having a trench gate structure is provided on the first main surface side of the semiconductor substrate 2. The MOS gate structure is p - n-type base region (first semiconductor region) 3 + The semiconductor device includes a first emitter region (second semiconductor region) 4, a trench 5, a deposited insulating layer (insulating layer) 6, a gate insulating film 7, and a gate electrode 8.

[0022] n - The second main surface side of the drift layer 2 is + A type collector layer (fourth semiconductor region) 1 is provided. + The collector layer 1 is an n - The diffusion region may be formed by, for example, ion implantation in the surface layer of the second main surface of the drift layer 2, or may be a p + It may be made of a starting substrate (semiconductor chip). + The collector layer 1 is p + When using a starting substrate of type n - The drift layer 2 is p + p type collector layer 1 + The epitaxial layer is deposited on the front surface of the starting substrate. - The base region 3 is an n - The first main surface of the drift layer 2 is provided on the p - The base region 3 is an n - It may be an epitaxial layer deposited on the first main surface of the n-type drift layer 2, -It may be a diffusion region formed in the surface layer of the first main surface of the mold drift layer 2 by, for example, ion implantation.

[0023] p - The lower the impurity concentration of the base region 3, the lower the threshold voltage. - It is preferable that the n-type inversion layer is low enough to prevent a channel (n-type inversion layer) from being formed (the n-type base region 3 is not turned on) in the portion of the n-type base region 3 facing the gate electrode 8. + The emitter region 4 is p - It is selectively provided inside the mold base region 3. + The n-type emitter region 4 may be an epitaxial layer or a diffusion region formed by, for example, ion implantation. + type emitter region 4 and p - through the base region 3 - The deposited insulating layer 6 reaches the mold drift layer 2. The deposited insulating layer 6 is provided on the collector side inside the trench 5. That is, the deposited insulating layer 6 is embedded in the bottom of the trench 5 (the collector-side end).

[0024] The gate electrode 8 is provided on the surface (emitter side) of the deposited insulating layer 6 inside the trench 5. The gate electrode 8 is disposed on the p - Type base region 3, n + Type emitter region 4 and n - The collector-side end of the gate electrode 8 faces the p-type drift layer 2. - Type base region 3 and n - The n-type drift layer 2 is located closer to the collector than the pn junction 21. - The inside of the drift layer 2 is - A p-type diffusion region (p-type buried region (third semiconductor region)) 9 ​​is selectively provided apart from the n-type base region 3. The p-type buried region 9 surrounds the bottom of the trench 5. -The p-type buried region 9 is buried inside the p-type drift layer 2 and faces the gate electrode 8 across the deposited insulating layer 6. That is, the bottom of the trench 5 is located inside the p-type buried region 9.

[0025] The p-type buried region 9 may extend toward the emitter side along the inner wall of the trench 5 to such an extent that it does not face the gate electrode 8 across the gate insulating film 7 provided on the side wall of the trench. In other words, the thickness t1 of the deposited insulating layer 6 is thick enough that the p-type buried region 9 and the gate electrode 8 do not face each other across the gate insulating film 7 provided on the side wall of the trench 5. The p-type buried region 9 is n - The p-type buried region 9 has a function of alleviating the electric field applied to the p-type drift layer 2. The p-type buried region 9 may be a diffusion region formed by, for example, ion implantation. The impurity concentration of the p-type buried region 9 can be changed in various ways according to the design conditions, and may be high enough to prevent degeneration of the energy level (the Fermi level does not move into the valence band). For example, the impurity concentration of the p-type buried region 9 is high enough to prevent the entire p-type buried region 9 from being depleted even when a high voltage is applied to the collector, and may be, for example, n - The impurity concentration is set to be equal to or higher than that of the type drift layer 2.

[0026] n - p-type drift layer 2 - In the off-state, a p-type inversion layer 12 is formed along the gate insulating film 7 in the area between the p-type base region 3 and the p-type buried region 9 (the area shown by hatching in the figure). - The n-type base region 3 and the p-type buried region 9 are electrically connected. Therefore, in the off state, the p-type buried region 9 is fixed to the emitter potential. - p-type drift layer 2 - In order to generate a p-type inversion layer 12 in the portion sandwiched between the p-type base region 3 and the p-type buried region 9, - The impurity concentration of the n-type drift layer 2, the thickness t2 of the gate insulating film 7, and the work function of the gate electrode 8 are appropriately set. - p-type drift layer 2 -The impurity concentration in the portion sandwiched between the p-type base region 3 and the p-type buried region 9 is set low enough to generate a p-type inversion layer 12 (that is, to have holes) in the off state.

[0027] n - p-type drift layer 2 - The impurity concentration of the portion sandwiched between the n-type base region 3 and the p-type buried region 9 is - The impurity concentration of the n-type drift layer 2 may be different from that of the other portions. - The impurity concentration of the drift layer 2 is 1×10 14 / cm 3 More than 1×10 16 / cm 3 If it is within the range of - p-type drift layer 2 - The impurity concentration of the portion sandwiched between the p-type base region 3 and the p-type buried region 9 is, for example, 1×10 17 / cm 3 The thickness t2 of the gate insulating film 7 is about n - p-type drift layer 2 - The thickness t2 of the gate insulating film 7 may be set thin enough to generate a p-type inversion layer 12 in the portion sandwiched between the p-type base region 3 and the p-type buried region 9. In other words, the thickness t2 of the gate insulating film 7 may satisfy the above-mentioned condition, and may be thinner than the thickness of the deposited insulating layer 6 or may be the same thickness as the deposited insulating layer 6, for example.

[0028] For example, the thickness t2 of the gate insulating film 7 is set to 100 nm, and n - p-type drift layer 2 - The impurity concentration of the portion sandwiched between the p-type base region 3 and the p-type buried region 9 is set to 1×10 17 / cm 3 In this case, a p-type inversion layer 12 is formed when the gate voltage is about −10 V. - p-type drift layer 2 - The impurity concentration of the portion sandwiched between the p-type base region 3 and the p-type buried region 9 is 1×10 17 / cm 3If the gate voltage is about −15 V or less, the p-type inversion layer 12 can be formed even in an application (product) in which the gate voltage is shifted to a lower level of about −15 V. - The impurity concentration of the drift layer 2 is uniformly 5×10 14 / cm 3 If the breakdown voltage is about -2V or less (for example, 13 kV class), the p-type inversion layer 12 can be formed even if the gate voltage is about -2V.

[0029] Furthermore, even if the gate voltage is about 0 V, it is possible to form a p-type inversion layer 12 by appropriately setting the work function of the gate electrode 8. In this case, the gate electrode 8 is, for example, - The difference in work function between the n-type drift layer 2 and the n-type drift layer 3 - p-type drift layer 2 - The portion sandwiched between the p-type base region 3 and the p-type buried region 9 (n - The gate electrode 8 may be made of an electrode material having a work function that generates holes in the gate electrode drift layer 2 (near the interface with the gate insulating film 7). 18 / cm 3 Alternatively, a p-type silicon carbide (SiC) semiconductor having a high impurity concentration or doped polysilicon (doped poly-Si) doped with p-type impurities may be used. - Type base region 3 and n + The collector electrode (second electrode) 11 is in contact with the p-type emitter region 4 and is electrically insulated from the gate electrode 8 by an interlayer insulating film (not shown). + The mold contacts the collector layer 1.

[0030] Although not particularly limited, for example, when the semiconductor device according to the first embodiment has a breakdown voltage of 13 kV, n + type emitter region 4 and p + The collector layer 1 has a sufficiently high impurity concentration (1×10 18 / cm 3 The thickness is about 0.1 μm or more. -The impurity concentration of the base region 3 depends on the thickness t2 of the gate insulating film 7, but is 1×10 15 / cm 3 More than 1×10 17 / cm 3 The following is the extent of the above. - The thickness of the n-type drift layer 2 is approximately 100 μm or more and 150 μm or less. - The impurity concentration of the drift layer 2 is in the range described above, and is preferably 5×10 14 / cm 3 The depth of the trench 5 is about 1 μm or more and 3 μm or less. The thickness t2 of the gate insulating film 7 is about 50 nm or more and 200 nm or less. The impurity concentration of the p-type buried region 9 is 1×10 18 / cm 3 It is more than enough.

[0031] Next, the operation of the semiconductor device according to the first embodiment will be described. The emitter electrode 10 is either grounded or has a negative voltage applied to it (emitter potential≦0). The collector electrode 11 has a positive voltage applied to it (collector potential>0). In this state, p - Type base region 3 and n - The pn junction 21 between the n-type drift layer 2 and the n-type drift layer 2 is reverse biased. - Type base region 3 and n - A depletion layer (not shown) spreads inside the n-type drift layer 2, blocking the path (channel) of electrons, which are conduction carriers. At this time, when no gate voltage or a negative gate voltage (gate voltage≦0V) is applied to the gate electrode 8, no current flows between the emitter and collector. In other words, the off state is maintained. While the off state is maintained, n - p-type drift layer 2 - A p-type inversion layer 12 is formed along the gate insulating film 7 in the area between the p-type base region 3 and the p-type buried region 9. - The p-type base region 3 and the p-type buried region 9 are electrically connected. - The base (emitter) potential is fixed at approximately the same potential as the p-type base region 3, and the p-type buried region 9 and n -The pn junction 22 between the first and second drift layers 2 is also reverse biased.

[0032] On the other hand, when the voltage applied to the gate electrode 8 is set to the threshold voltage or higher (gate voltage≧threshold voltage), p - Type base region 3, n + Type emitter region 4 and n - An n-type inversion layer (channel (not shown)) is formed along the gate insulating film 7 in the portion sandwiched between the n-type drift layer 2 and the n-type drift layer 2 (the portion facing the gate electrode 8). + n-type emitter region 4, n-type inversion layer and n - The n-type drift layer 2 serves as a path for electrons, which are conduction carriers. + n-type emitter region 4, n-type inversion layer and n - The electrons pass through the n-type drift layer 2 to the collector electrode 11, and a current flows between the emitter and the collector. This state is the on state. In the on state, - p-type drift layer 2 - Since no p-type inversion layer 12 is formed in the portion sandwiched between the base region 3 and the p-type buried region 9, the p-type buried region 9 is in a floating state. Then, by again applying a voltage to the gate electrode 8 that is at least 0 V or less (gate voltage≦0 V), the semiconductor device transitions from the on state to the off state. In this way, the on / off state of the semiconductor device is controlled by the voltage applied to the gate electrode 8.

[0033] Even in a state where the gate voltage is greater than 0 and less than the threshold voltage (0<gate voltage<threshold voltage), an n-type inversion layer (channel) is not formed, just as when the gate voltage is 0V or less. However, in reality, after an instruction value for off control (gate voltage<threshold voltage) is applied to the gate electrode 8 from the outside, the semiconductor device according to the first embodiment is in a transition state until it stops operating, and does not completely stop, until the gate voltage becomes 0V. For this reason, in the above explanation, the state where the gate voltage is at least 0V or less, at which the operation of the semiconductor device according to the first embodiment completely stops, is referred to as the off state, but -The gate voltage when the p-type inversion layer 12 is formed in the p-type drift layer 2, - If it is possible to adjust the gate voltage (i.e., threshold voltage) so that it is equal to the gate voltage when an n-type inversion layer (channel) is formed in the base region 3 (on state), the off state may be set when the gate voltage is less than the threshold voltage (gate voltage<threshold voltage).

[0034] In the above description, a device utilizing the conductivity modulation effect such as an IGBT is used as an example, but the present invention may also be applied to an insulated gate field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). + Instead of type collector layer 1, n + A drain layer is provided, and an n + The emitter region 4, the emitter electrode 10 and the collector electrode 11 are n-type. + The semiconductor material of the semiconductor device according to the first embodiment may be a silicon (Si) semiconductor or a semiconductor having a wider band gap than silicon (hereinafter referred to as a wide band gap semiconductor), such as a silicon carbide semiconductor.

[0035] As described above, according to the first embodiment, in the on-state, the p-type buried region is in a floating state, and therefore extraction of minority carriers (holes) from the p-type buried region to the emitter electrode does not occur. Therefore, conductivity modulation is not hindered in devices that utilize the conductivity modulation effect, such as IGBTs. This prevents deterioration of the on-resistance characteristics. In other words, the on-resistance characteristics can be improved compared to, for example, the case in Patent Document 3, in which the p-type buried region is fixed to the emitter potential in the on-state.

[0036] Furthermore, when the p-type buried region is in a floating state in the off state as in the above-mentioned Patent Document 3, depending on the potential state of the p-type buried region, the potential difference between the gate electrode and the p-type buried region may become large, and a high electric field may be concentrated in the deposited insulating layer. On the other hand, according to the first embodiment, in the off state, the p-type buried region is in a floating state due to the p-type inversion layer. - The p-type buried region is electrically connected to the emitter base region and fixed at the emitter potential (for example, ground). As a result, even if a high voltage is applied to the collector electrode, the potential difference between the gate electrode and the p-type buried region (the voltage applied to the deposited insulating layer) is about the same as the gate voltage, so a high electric field does not concentrate in the deposited insulating layer. In addition, by fixing the p-type buried region to the emitter potential, - The portion of the drift layer along the gate insulating film is also maintained at a potential close to the emitter potential, and the voltage applied to the gate insulating film is approximately the same as the gate voltage. Therefore, a high electric field is not concentrated on the gate insulating film. This improves the breakdown voltage characteristics compared to conventional devices, preventing malfunctions and dielectric breakdown. Furthermore, because a high electric field is not concentrated on the gate oxide film, the upper limit of the collector voltage can be increased to a level that generates an electric field close to the maximum electric field strength of the semiconductor material. This allows, for example, wide bandgap semiconductors to be used, enabling high breakdown voltages close to the characteristic limits of the wide bandgap semiconductor material.

[0037] Furthermore, according to the first embodiment, when in the off state, n - A p-type inversion layer is formed inside the p-type drift layer, and this p-type inversion layer - Since the p-type base region and the p-type buried region can be electrically connected, for example, as in Patent Document 3, - This eliminates the need to form a diffusion region to connect the p-type base region and the p-type buried region, thereby simplifying the manufacturing process compared to conventional methods.

[0038] (Embodiment 2) Next, the structure of the semiconductor device according to the second embodiment will be described. Fig. 2 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that n - Inside the n-type drift layer 2, - The n-type diffusion region (hereinafter referred to as n-type blocking region (fifth semiconductor region)) 13 has a higher impurity concentration than the n-type drift layer 2. The n-type blocking region 13 is in the on state. - This acts as a barrier against minority carriers (holes) inside the n-type drift layer 2, enhancing the accumulation effect of minority carriers. - Since the carrier density of the drift layer 2 can be increased, the on-resistance can be reduced.

[0039] The n-type blocking region 13 is - p-type drift layer 2 - Between the p-type base region 3 and the p-type buried region 9, - It is preferable that the p-type base region 3 and the p-type buried region 9 are provided apart from each other. The reason for this is as follows. - Type base region 3 and n - The electric field strength near the pn junction 21 between the n-type drift layer 2 and the n-type buried region 9 or the electric field strength near the bottom of the trench 5 (near the p-type buried region 9 and the deposited insulating layer 6) determines the breakdown voltage. - This is because it is preferable not to provide the n-type blocking region 13 so that the impurity concentration of the p-type drift layer 2 does not become high. - By providing the n-type blocking region 13 between the base region 3 and the p-type buried region 9, the n-type blocking region 13 can be provided without substantially changing the electric field strength at the bottom of the trench 5 and the p-type buried region 9. This allows for a low on-resistance without reducing the breakdown voltage.

[0040] The impurity concentration of the n-type blocking region 13 is n -The impurity concentration of the n-type blocking region 13 is higher than the impurity concentration of the n-type drift layer 2. The impurity concentration of the n-type blocking region 13 is set to a high impurity concentration (for example, 1×10 17 / cm 3 The thickness of the n-type blocking region 13 is, for example, about several μm. The n-type blocking region 13 may be an epitaxial layer or may be a diffusion region formed by, for example, ion implantation. When forming the n-type blocking region 13 made of an epitaxial layer, for example, p + p type collector layer 1 + On the starting substrate, - After depositing the n-type drift layer 2 and the n-type blocking region 13, - By depositing the n-type drift layer 2, - The thickness of the n-type drift layer 2 can be adjusted. When forming the n-type blocking region 13 made of a diffusion region by ion implantation, for example, the acceleration energy of the ion implantation can be changed in various ways to obtain the n-type blocking region 13. - In this case, n-type blocking region 13 may be formed at a predetermined depth from the first main surface of n-type drift layer 2.

[0041] The n-type blocking region 13 is - For example, p - Type base region 3 and n - The n-type blocking region 13 may face the entire surface of the pn junction 21 between the n-type drift layer 2 and the n-type blocking region 13. The n-type blocking region 13 may also be provided closer to the collector than the bottom of the trench 5. In this case, by appropriately setting the impurity concentration and thickness of the n-type blocking region 13, it is possible to minimize the decrease in breakdown voltage.

[0042] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, by providing an n-type blocking region, it is possible to further improve the on-resistance characteristics.

[0043] (Embodiment 3) Next, the structure of the semiconductor device according to embodiment 3 will be described. Fig. 3 is a cross-sectional view showing the structure of the semiconductor device according to embodiment 3. The semiconductor device according to embodiment 3 differs from the semiconductor device according to embodiment 2 in that the p-type buried region 9 is always in a floating state (both in the on state and the off state).

[0044] In the third embodiment, in the off state, n - Inside the drift layer 2, - Type base region 3 and n - A depletion layer (not shown) spreads from the pn junction 21 between the n-type drift layer 2 and the n-type drift layer 2, and the electric field intensity peaks near the pn junction 21. - The inside of the drift layer 2 is provided with a p-type buried region 9 and an n-type buried region 10. - A depletion layer (not shown) also spreads from the pn junction 22 between the n-type drift layer 2 and the n-type drift layer 2, and a peak of the electric field intensity is also formed near the pn junction 22. - The peak of the electric field strength can be distributed to two locations inside the n-type drift layer 2, and the maximum peak value of the electric field strength can be reduced. This improves the breakdown voltage. - By providing n-type blocking region 13 inside drift layer 2, the on-resistance characteristics can be improved as in the second embodiment.

[0045] As described above, according to the third embodiment, the same effects as those of the second embodiment can be obtained.

[0046] (Fourth embodiment) Next, the structure of a semiconductor device according to a fourth embodiment will be described. FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the third embodiment in that a p-type region (hereinafter referred to as a p-type column region (third semiconductor region)) 14, which is deeper than the trenches 5 and is always fixed to the emitter potential, is provided in the portion sandwiched between adjacent trenches 5. In the fourth embodiment, no p-type buried region is provided. Also, an n-type blocking region (fifth semiconductor region) 15 is provided in the portions that determine the breakdown voltage (near the deposited insulating layer 6 and between the p-type column region 14 and n-type semiconductor region 15, which will be described later). - n at the pn junction 23 between the - The trench 5 is provided closer to the collector than the bottom of the trench 5 so that the impurity concentration of the drift layer 2 does not become too high.

[0047] The p-type column region 14 is provided between adjacent trenches 5 at a distance from the trenches 5, and is electrically connected to the emitter electrode 10. The depth of the p-type column region 14 is deeper than the depth of the trenches 5. For example, the p-type column region 14 is + type emitter region 4 and p - through the base region 3, - The p-type column region 14 may reach the n-type blocking region 15 provided inside the n-type drift layer 2. By providing the p-type column region 14 deeper than the trench 5, the p-type column region 14 and the n-type - This allows the electric field to be concentrated at the pn junction 23 between the p-type column region 14 and the p-type drift layer 2, thereby reducing the electric field strength near the deposited insulating layer 6. The impurity concentration of the p-type column region 14 can be varied in accordance with the design conditions, and may be high enough to prevent degeneration of the energy level.

[0048] As described above, according to the fourth embodiment, n - By providing an n-type blocking region inside the n-type drift layer, the on-resistance characteristics can be improved as in the second embodiment.

[0049] (Embodiment 5) Next, the structure of the semiconductor device according to the fifth embodiment will be described. Fig. 5 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment differs from the semiconductor device according to the fourth embodiment in that the p-type column region (seventh semiconductor region) 16 - The point where the p-type base region 3 and the p-type buried region (sixth semiconductor region) 9 are connected is the point where the p-type base region 3 and the p-type buried region (sixth semiconductor region) 9 are connected. - The p-type base region 3, the p-type column region 16, and the p-type buried region 9 constitute a p-type region that is always fixed to the emitter potential, and is provided in a portion sandwiched between adjacent trenches 5 at a depth deeper than the trenches 5, similar to the p-type column region of the fourth embodiment. Specifically, the p-type column region 16 is - p-type drift layer 2 - The n-type blocking region 15 is provided between the p-type base region 3 and the p-type buried region 9 along the gate insulating film 7 provided on the side wall of the trench 5. The configuration of the n-type blocking region 15 is the same as that in the fourth embodiment.

[0050] As described above, according to the fifth embodiment, the same effects as those of the fourth embodiment can be obtained.

[0051] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Furthermore, in each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0052] As described above, the semiconductor device according to the present invention is useful as a MOS semiconductor device having a trench gate structure and high breakdown voltage. [Explanation of symbols]

[0053] 1 p + Mold collector layer 2n - Mold drift layer 3 p - Type-based domain 4n + Type emitter area 5. Trench 6 Deposited insulating layer 7 Gate insulating film 8 gate electrode 9 p-type buried region 10 Emitter electrode 11 Collector electrode 12 p-type inversion layer 13,15 n-type blocking region 14,16 p-type column region 21 p - Type base region and n - pn junction between the GaN drift layer and the 22 p-type buried region and n - pn junction between the GaN drift layer and the 23 p-type column region and n - pn junction between the GaN drift layer and the

Claims

1. a second conductivity type base region provided on the first main surface side of the first conductivity type drift layer; an emitter region of a first conductivity type selectively provided inside the base region and having a higher impurity concentration than the drift layer; a gate trench portion including: a trench that penetrates the emitter region and the base region to reach the drift layer; an insulating layer having a first thickness provided at a bottom of the trench; a gate insulating film having a second thickness provided on a sidewall of the trench; and a gate electrode provided inside the gate insulating film and on the insulating layer; an emitter electrode insulated from the gate electrode by an interlayer insulating film; a second conductivity type high concentration region having a higher impurity concentration than the base region, the high concentration region being provided between adjacent gate trench portions and deeper toward the second main surface of the drift layer than the bottom of the trench; a blocking region of the first conductivity type having a higher impurity concentration than the drift layer, the blocking region being provided in contact with and surrounding an end portion of the high concentration region on the second main surface side; Equipped with the emitter region and the heavily doped region are connected to the emitter electrode; the blocking region is provided at a position deeper than a bottom of the trench toward the second main surface of the drift layer, the high concentration region has a constant width between the emitter region and the base region, the high concentration region being in contact with the emitter region and the base region and reaching the blocking region, and the high concentration region has a uniform impurity concentration; 10. A semiconductor device comprising: a first region for forming a first gate electrode on a first surface of the first semiconductor layer; a second region for forming a first gate electrode on the first surface of the first semiconductor layer;

2. a collector layer of a second conductivity type provided on the second main surface side of the drift layer and having a higher impurity concentration than the base region; a collector electrode in contact with the collector layer; 2. The semiconductor device according to claim 1, further comprising:

3. a second conductivity type base region provided on the first main surface side of the first conductivity type drift layer; a first conductivity type source region selectively provided inside the base region and having a higher impurity concentration than the drift layer; a gate trench portion including: a trench that penetrates the source region and the base region to reach the drift layer; an insulating layer having a first thickness provided at a bottom of the trench; a gate insulating film having a second thickness provided on a sidewall of the trench; and a gate electrode provided inside the gate insulating film and on the insulating layer; a source electrode insulated from the gate electrode by an interlayer insulating film; a second conductivity type high concentration region having a higher impurity concentration than the base region, the high concentration region being provided between adjacent gate trench portions and deeper toward the second main surface of the drift layer than the bottom of the trench; a blocking region of the first conductivity type having a higher impurity concentration than the drift layer, the blocking region being provided in contact with and surrounding an end portion of the high concentration region on the second main surface side; Equipped with the source region and the heavily doped region are connected to the source electrode; the blocking region is provided at a position deeper than a bottom of the trench toward the second main surface of the drift layer, the high concentration region has a constant width between the source region and the base region, the high concentration region being in contact with the source region and the base region and reaching the blocking region, and the high concentration region has a uniform impurity concentration; 10. The semiconductor device according to claim 9, wherein the drift layer, the base region, the source region, the high concentration region, and the blocking region are made of silicon carbide.

4. a drain layer of a first conductivity type provided on the second main surface side of the drift layer and having a higher impurity concentration than the base region; a drain electrode in contact with the drain layer; 4. The semiconductor device according to claim 3, further comprising:

5. 5. The semiconductor device according to claim 1, wherein the first thickness of the insulating layer is greater than the second thickness of the gate insulating film.

6. 6. The semiconductor device according to claim 1, wherein the second thickness of the gate insulating film is 50 nm or more and 200 nm or less.

7. 7. The semiconductor device according to claim 1, wherein the high concentration region is a column region that forms a pn junction surface between the high concentration region and the drift layer and that is perpendicular to the first main surface.

8. the blocking region is provided inside the drift layer, 8. The semiconductor device according to claim 1, wherein the drift layer is an epitaxial layer.

9. 9. The semiconductor device according to claim 1, wherein the drift layer has a thickness of 100 μm or more and 150 μm or less.

10. The drift layer has a thickness of 1×10 14 / cm 3 1x10 or more 16 / cm 3 10. The semiconductor device according to claim 1, wherein the semiconductor device has the following impurity concentration:

11. The base region is 1×10 15 / cm 3 1x10 or more 17 / cm 3 11. The semiconductor device according to claim 1, wherein the semiconductor device has the following impurity concentration:

12. 12. The semiconductor device according to claim 1, wherein the high concentration region is provided away from the gate trench portion.

13. 13. The semiconductor device according to claim 1, wherein the drift layer surrounds the bottom of the trench.

14. 14. The semiconductor device according to claim 1, wherein the base region has a region where a channel is formed in a portion facing the gate electrode.

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