Image pickup element and electronic device

Abstract

An imaging element according to an embodiment comprises: a pixel region in which pixels, that include a photoelectric converting unit and a first capacitor that accumulates charges based on photoelectric conversion by the photoelectric converting unit, are arrayed in a two-dimensional matrix shape, the pixel region having a first pixel group in which pixels are disposed adjacent to each other in oblique directions, and a second pixel group in which pixels are disposed adjacent to the pixels of the first pixel group in the upward, downward, leftward, and rightward directions; and a driving unit that generates driving signals for driving the pixels in the pixel region, wherein the driving unit maintains the accumulated charges of the first capacitor in the second pixel group at an initial state in a first period for reading signals based on the accumulated charges of the first capacitor in the pixel region.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging element and an electronic device. [Background technology]

[0002] Current photoelectric conversion elements using InGaAs are capable of imaging in the near-infrared (NIR) and short-wave infrared (SWIR) ranges, and are therefore used in industrial inspection equipment as well as general photography. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-286104 Summary of the Invention [Problem to be solved by the invention]

[0004] If the photoelectric conversion layer cannot separate each pixel, the generated carriers may move to adjacent pixels, resulting in color mixture.

[0005] Therefore, the present disclosure provides an imaging element and an electronic device that can further suppress color mixing. [Means for solving the problem]

[0006] In order to solve the above problems, according to the present disclosure, there is provided a pixel region in which pixels, each including a photoelectric conversion unit and a first capacitance that accumulates charge based on photoelectric conversion of the photoelectric conversion unit, are arranged in a two-dimensional matrix, the pixel region having a first pixel group in which pixels adjacent in a diagonal direction are arranged, and a second pixel group in which pixels adjacent in a vertical and horizontal direction to pixels of the first pixel group are arranged; a driver that generates a drive signal that drives the pixels in the pixel region, An imaging element is provided in which the driving unit maintains the first capacitance in the second pixel group in a reset state that suppresses accumulation of the accumulated charge in the first capacitance in the pixel region during a first period of signal readout based on the accumulated charge in the first capacitance.

[0007] The driving unit may maintain the first pixel group in a reset state that suppresses accumulation of the first capacitance accumulated charge during a second period that is different from a first period for reading out a signal based on the accumulated charge of the first capacitance of the pixel region.

[0008] The signals of the first pixel group read out during the first period may be corrected using the signals of the first pixel group read out during the second period.

[0009] The signals of the second pixel group read out during the second period may be corrected using the signals of the second pixel group read out during the first period.

[0010] The photoelectric conversion portion may be a photoelectric conversion element using InGaAs.

[0011] The drive section may maintain a reset state in which the pixels of the second pixel group are prevented from accumulating charge in response to exposure during a first exposure period in which the pixels of the first pixel group are exposed.

[0012] The drive section may expose the pixels of the second pixel group to light in a second exposure period following the first exposure period, and maintain a reset state that suppresses charge accumulation in the pixels of the first pixel group.

[0013] The first exposure period and the second exposure period may have different lengths.

[0014] The pixels of the first pixel group may be exposed to light through a polarizing element that polarizes light in a first direction, and the pixels of the second pixel group may be exposed to light through a polarizing element that polarizes light in a second direction different from the first direction.

[0015] The pixel includes the photoelectric conversion unit and a second capacitor that accumulates charges generated in the photoelectric conversion unit; a transfer transistor that transfers the charge stored in the second capacitor to the first capacitor; the first capacitance; an amplifying transistor that amplifies the charge of the first capacitor and outputs a signal with a level corresponding to the charge; may have at least

[0016] The transfer transistors of the pixels of the first pixel group arranged in the same row of the pixel region may be connected to the drive unit via a first control line, and the transfer transistors of the pixels of the second pixel group arranged in the same row of the pixel region may be connected to the drive unit via a second control line different from the first control line.

[0017] The pixel is a second reset transistor that sets the second capacitor to an initial state; a first reset transistor that sets the first capacitor to an initial state; It may further include:

[0018] The second reset transistors of the pixels of the first pixel group arranged in the same row of the pixel region may be connected to the drive unit via a third control line, and the second reset transistors of the pixels of the second pixel group arranged in the same row of the pixel region may be connected to the drive unit via a fourth control line different from the third control line.

[0019] The drive unit may maintain the transfer transistors in the second pixel group in a non-conductive state and may set the first capacitance to an initial state using the first reset transistor, and then read out signals for the first period.

[0020] The drive unit may maintain the transfer transistors in the first pixel group in a non-conductive state and may set the first capacitance to an initial state using the first reset transistor, and then perform signal readout for the second period.

[0021] The drive section may maintain the second reset transistors in the second pixel group in a conductive state during the first exposure period.

[0022] The drive section may maintain the second reset transistors in the first pixel group in a conductive state during the second exposure period.

[0023] An electronic device having an imaging device may be provided.

[0024] An electronic device having an imaging element, The image processing device may further include an image processing unit that performs interpolation processing on the first image data based on the first exposure period and the second image data based on the second exposure period, and performs synthesis processing on the first image data and the second image data. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a diagram showing an example of the configuration of an electronic device 1 according to an embodiment of the present invention. [Figure 2] FIG. 1 is a diagram showing an example of the arrangement of an image sensor according to an embodiment. [Figure 3A] FIG. 2 is a diagram showing an example of the configuration of a first pixel. [Figure 3B] FIG. 4 is a diagram showing an example of the configuration of a second pixel. [Figure 4] FIG. 10 is a diagram showing an example of wiring of transistors that can be controlled individually between the first pixel group and the second pixel group. [Figure 5] 1A and 1B are a schematic partial cross-sectional view of a photoelectric conversion element and a planar layout of each element. [Figure 6] FIG. 2 is a schematic partial cross-sectional view of a photoelectric conversion element. [Figure 7] FIG. 10 is a diagram schematically showing the ratio of extinction axis light in a pixel and its adjacent pixels on the top, bottom, left, and right sides. [Figure 8] FIG. 2 is a diagram showing an example of driving a global shutter system according to the first embodiment. [Figure 9] FIG. 10 is a diagram showing a schematic diagram of state changes of the SN CI capacitance and the FD CI capacitance. [Figure 10] FIG. 10 is a diagram showing a driving example of Comparative Example 1. [Figure 11] FIG. 4 is a diagram schematically showing the parasitic capacitance between pixels in Comparative Example 1 and the parasitic capacitance between pixels in this embodiment. [Figure 12] FIG. 4 is a diagram schematically showing a driving method in mode 2 according to the present embodiment. [Figure 13] FIG. 10 is a diagram showing a driving example of Comparative Example 2. [Figure 14] FIG. 10 is a diagram showing an example of driving a global shutter system according to the second embodiment. [Figure 15] FIG. 4 is a diagram schematically showing image data of a first pixel group and image data of a second pixel group. [Figure 16] FIG. 11 is a schematic partial cross-sectional view of a photoelectric conversion element of a pixel according to a third embodiment. [Figure 17] FIG. 2 is a diagram showing the arrangement relationship between polarizing filters and pixels. [Figure 18] FIG. 10 is a plan view showing a part of a pixel region 11 according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of a photoelectric conversion element, a manufacturing method thereof, and an imaging device will be described with reference to the drawings. The following description will focus on the main components of the photoelectric conversion element, the manufacturing method thereof, and the imaging device, but the photoelectric conversion element, the manufacturing method thereof, and the imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0027] (First embodiment) Fig. 1 is a diagram showing an example of the configuration of an electronic device 1 according to this embodiment. As shown in Fig. 1, the electronic device 1 is an electronic device capable of capturing images up to the near-infrared (NIR) and short-wave infrared (SWIR) regions, for example. The electronic device 1 includes, for example, an optical system 2, a control unit 3, an image sensor 4, an image processing unit 5, a memory 6, a storage unit 7, a display unit 8, an interface (I / F) unit 9, and an input device 12.

[0028] Here, a digital still camera, a digital video camera, a mobile phone or smartphone with an imaging function, etc. can be used as the electronic device 1. It is also possible to use a surveillance camera, an in-vehicle camera, a medical camera, etc.

[0029] The image sensor 4 includes a plurality of photoelectric conversion elements arranged in, for example, a matrix. The image sensor 4 is configured to be able to independently control the image capture timing of the first pixel group and the second pixel group. The detailed configuration of the image sensor 4 will be described later.

[0030] The optical system 2 includes a main lens made up of one or a combination of multiple lenses and a mechanism for driving the main lens, and forms an image of image light (incident light) from a subject on the light receiving surface of the image sensor 4 via the main lens. The optical system 2 also includes an autofocus mechanism that adjusts the focus in accordance with a control signal and a zoom mechanism that changes the zoom ratio in accordance with a control signal. The electronic device 1 may also have a detachable optical system 2 that can be replaced with another optical system 2.

[0031] The image processing unit 5 performs predetermined image processing on the image data output from the imaging element 4. For example, the image processing unit 5 is connected to a memory 6 such as a frame memory, and writes the image data output from the imaging element 4 into the memory 6. The image processing unit 5 performs predetermined image processing on the image data written into the memory 6, and writes the processed image data back into the memory 6.

[0032] The storage unit 7 is a non-volatile memory such as a flash memory or a hard disk drive, and stores the image data output from the image processing unit 5 in a non-volatile manner. The display unit 8 includes a display device such as an LCD (Liquid Crystal Display) and a drive circuit for driving the display device, and can display an image based on the image data output from the image processing unit 5. The I / F unit 9 is an interface for transmitting the image data output from the image processing unit 5 to an external device. For example, a USB (Universal Serial Bus) can be used as the I / F unit 9. However, the I / F unit 9 is not limited to this, and may be an interface connectable to a network via wired or wireless communication.

[0033] The input device 12 includes an operator for receiving user input, etc. If the electronic device 1 is, for example, a digital still camera, a digital video camera, a mobile phone with an imaging function, or a smartphone, the input device 12 may include a shutter button for instructing the imaging element 4 to capture an image, or an operator for realizing the function of the shutter button.

[0034] The control unit 3 includes a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory), and controls the overall operation of the electronic device 1 using the RAM as a work memory in accordance with a program pre-stored in the ROM. For example, the control unit 3 can control the operation of the electronic device 1 in response to a user input received by the input device 12. The control unit 3 can also control the autofocus mechanism in the optical system 2 based on the image processing results of the image processing unit 5.

[0035] Fig. 2 is a diagram showing an example of the configuration of the image sensor 4 according to this embodiment. As shown in Fig. 2, the image sensor 4 is configured to include a pixel region 111 in which pixels 101 and 102 are arranged in a two-dimensional matrix (two-dimensional array), and its driving circuits (peripheral circuits) including a vertical driving circuit 112, a column signal processing circuit 113, a horizontal driving circuit 114, an output circuit 115, and a driving control circuit 116.

[0036] The first pixel group is composed of a plurality of pixels 101, and the second photoelectric conversion element group is composed of a plurality of pixels 102. In this first pixel group, the pixels 101 are arranged diagonally adjacent to each other. In this second pixel group, the pixels 102 adjacent to the pixel 101 in the vertical and horizontal directions are arranged. That is, the pixels 102 of the second pixel group are arranged diagonally, and the pixels 101 of the first pixel group and the pixels 102 of the second pixel group are arranged in a checkerboard pattern. For ease of explanation, each pixel of the first pixel group is labeled 101 and each pixel of the second pixel group is labeled 102, but this is not limiting. For example, even if each pixel 102 is considered to be part of the first pixel group and each pixel 101 is considered to be part of the second pixel group, the drive control according to this embodiment will be the same.

[0037] The drive control circuit 116 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114, based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. The generated clock signals and control signals are then input to the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114. In this embodiment, the vertical drive circuit 112 and the drive control circuit 116 correspond to a drive unit. In this embodiment, the drive unit is composed of the vertical drive circuit 112 and the drive control circuit 116, but is not limited to this. For example, the drive unit may be any circuit or element that can control the drive of each pixel in the pixel region 111.

[0038] The vertical drive circuit 112 is configured with, for example, a shift register, and is capable of selectively scanning each of the pixels 101, 102 in the pixel region 111 in the vertical direction in row units. Furthermore, the vertical drive circuit 112 is also capable of driving using a global shutter system that individually controls the imaging timing of the first pixel group and the second pixel group during imaging. A pixel signal (image signal) based on a signal (either a current or a voltage) generated in accordance with the amount of light received by each of the pixels 101, 102 is sent to a column signal processing circuit 113 via signal lines (data output lines) VLS1, VLS2.

[0039] The column signal processing circuit 113 is disposed, for example, for each column of pixels 101 and 102, and performs signal processing such as noise reduction and signal amplification on the image signals output from the photoelectric conversion elements PD for one row using signals from black reference pixels (not shown, but formed around the effective pixel area) for each image sensor. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 113 and connected between the horizontal signal line 118. That is, in this embodiment, a VSL1 line is provided for each column of pixels 101, and a VSL2 line is provided for each column of pixels 102. This allows the pixels 101 and 102 in the same column to perform signal processing such as noise reduction and signal amplification on the image signals output from the photoelectric conversion elements PD for one row using signals from black reference pixels (not shown, but formed around the effective pixel area, for example) for each image sensor, at independent timings.

[0040] The horizontal drive circuit 114 is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuits 113 and output signals from each of the column signal processing circuits 113 to a horizontal signal line 118.

[0041] The output circuit 115 processes the signals sequentially supplied from each of the column signal processing circuits 113 via a horizontal signal line 118 and outputs the processed signals.

[0042] 3A, 3B, and 4 will be used to explain exemplary configurations of pixels 101 and 102. FIG. 3A is a diagram showing an exemplary configuration of pixel 101. FIG. 3B is a diagram showing an exemplary configuration of pixel 102. FIG. 4 is a diagram showing an example of wiring for transistors that can be controlled individually between the first pixel group and the second pixel group.

[0043] 3A, the pixel 101 has a photoelectric conversion element PD made of InGaAs (n-InGaAs, for example, n-InGaAs). The pixel 101 is also configured with, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit, and has an overflow gate transistor OFG1 (hereinafter sometimes simply referred to as transistor OFG1), which is a P-type MOS (Metal Oxide Semiconductor) transistor, a transfer transistor TRG1, a reset transistor RST, an amplification transistor Amp, a path selection transistor Sel, an SN CI capacitance, and an FD CI capacitance, which are N-type MOS (Metal Oxide Semiconductor) transistors. In this embodiment, the photoelectric conversion element PD corresponds to the photoelectric conversion unit, the SN CI capacitance corresponds to the second capacitance, the transfer transistors TRG1 and TRG2 correspond to the transfer transistors, the FD CI capacitance corresponds to the first capacitance, the amplifying transistor Amp corresponds to the amplifying transistor, the overflow gate transistor OFG1 corresponds to the second reset transistor, and the reset transistor RST corresponds to the first reset transistor. Furthermore, although the SN CI capacitance and the FD CI capacitance are illustrated with capacitor symbols, the SN CI capacitance and the FD CI capacitance may be composed of floating capacitance, parasitic capacitance, or the like, in addition to capacitors.

[0044] In pixel 101, the cathode of photodiode PD is connected to a connection point SN where the source of overflow gate transistor OFG1 and the source of transfer transistor TRG1 are connected. The drain of overflow gate transistor OFG1 is connected to the power supply line of power supply VDR. In addition, the drain of transfer transistor TRG1 is connected to a connection point FD where one end of the FD CI capacitance, the source of reset transistor RST, and the gate of amplifier transistor Amp are connected. The drain of reset transistor RST is connected to the power supply line of power supply VDR.

[0045] One end of the CI capacitance for SN is connected to the connection point SN, and the other end is connected to the power supply line of the power supply VDD. Similarly, the other end of the CI capacitance for FD is connected to the power supply line of the power supply VDD.

[0046] The drain of the amplifier transistor Amp is connected to the power supply line of the power supply VDD, and the source is connected to the drain of the path selection transistor Sel, whose source is connected to the vertical signal line VSL1. The amplifier transistor Amp and a current source constitute a so-called source follower.

[0047] A drive signal Strg1, for example a pulse, is supplied to the gate of the transfer transistor TRG1 from the vertical drive circuit 112 via a signal line Ltrg1 (see FIG. 4). A drive signal Sofg1, for example a pulse, is supplied to the gate of the transistor OFG1 from the vertical drive circuit 112 via a signal line Lofg1 (see FIG. 4). The transfer transistor TRG1 and the transistor OFG1 are turned on (conductive) when the drive signals Strg1 and Sofg1 are high, and turned off (non-conductive) when the drive signals Strg1 and Sofg1 are low. In this embodiment, the conductive state of a transistor is referred to as the on or on state, and the non-conductive state is referred to as the off or off state.

[0048] The reset transistor RST is turned on when the drive signal Srst from the vertical drive circuit 112 is high and turned off when the drive signal Srst is low. Similarly, the path selection transistor Sel is turned on when the drive signal Ssel from the vertical drive circuit 112 is high and turned off when the drive signal Ssel is low.

[0049] As shown in FIG. 3B, pixel 102 has the same configuration as pixel 101. To distinguish between pixel 101 and pixel 102, independently controllable elements and signals for pixel 101 are designated by 1, and independently controllable elements and signals for pixel 102 are designated by 2. That is, pixel 102 has a photoelectric conversion element PD made of InGaAs (n-InGaAs, e.g., n-InGaAs). Furthermore, pixel 102 is configured, for example, with a CMOS (Complementary Metal Oxide Semiconductor) circuit, and includes an overflow gate transistor OFG2, a transfer transistor TRG2, and a reset transistor RST, which are P-type MOS (Metal Oxide Semiconductor) transistors, and an amplification transistor Amp, a path selection transistor Sel, an SN CI capacitor, and an FD CI capacitor, which are N-type MOS (Metal Oxide Semiconductor) transistors. The source of path selection transistor Sel is connected to vertical signal line VSL1. The other connections are the same as those of pixel 101, and therefore the explanation will be omitted.

[0050] A drive signal Strg2, for example, a pulse, is supplied to the gate of the transfer transistor TRG2 from the vertical drive circuit 112 via a signal line Ltrg2 (see FIG. 4). A drive signal Sofg2, for example, a pulse, is supplied to the gate of the transistor OFG2 from the vertical drive circuit 112 via a signal line Lofg2 (see FIG. 4). The transfer transistor TRG2 and the transistor OFG2 are turned on when the drive signals Strg2 and Sofg2 are high and turned off when the drive signals Strg2 and Sofg2 are low. The reset transistor RST is turned on when the drive signal Srst from the vertical drive circuit 112 is high and turned off when the drive signal Srst is low. Similarly, the path selection transistor Sel is turned on when the drive signal Ssel from the vertical drive circuit 112 is high and turned off when the drive signal Ssel is low.

[0051] 4, a signal line Ltrg1 is connected to the gate of the transfer transistor TRG1 of the pixel 101 from the vertical drive circuit 112. A signal line Lofg1 is connected to the gate of the transistor OFG1 from the vertical drive circuit 112. On the other hand, a signal line Ltrg2 is connected to the gate of the transfer transistor TRG2 of the pixel 102 from the vertical drive circuit 112. A signal line Lofg2 is connected to the gate of the transistor OFG2 from the vertical drive circuit 112. In this way, the vertical drive circuit 112 can independently control the transfer transistor TRG1 and transistor OFG1, and the transfer transistor TRG2 and transistor OFG2, which are arranged in the same row.

[0052] 5 is a diagram showing a schematic partial cross-sectional view of the photoelectric conversion element PD in the pixels 101 and 102 and a planar layout of each element. As shown in FIG. 5, the photoelectric conversion element PD includes, for example, a support substrate 23, an insulating film 24, a first compound semiconductor layer 31, a second compound semiconductor layer 32, a reflective film 33, a photoelectric conversion layer 34, a second conductivity-type region 35, a covering layer 36, a first electrode 51, and a second electrode 52. The second electrode 52 is electrically connected to the second conductivity-type region 35. In this case, the first electrode 51 constituting each photoelectric conversion element PD is connected to a connection portion SN provided on the drive substrate 60. As a result, when, for example, infrared light is incident on the photoelectric conversion element PD from the first compound semiconductor layer 31 side, holes and electrons are generated as carriers in the photoelectric conversion layer 34. When a higher potential is applied to the first electrode 51 than to the second electrode 52, electrons, the number of which corresponds to the number of holes absorbed by the second electrode 52, are supplied from the first conductivity type region 31 to the connection portion SN via the first electrode 51. On the other hand, holes are extracted from the first second conductivity type region 35 and the second compound semiconductor layer 32 to the outside via the second electrode 52.

[0053] 6 is a schematic partial cross-sectional view of the photoelectric conversion element PD in the pixels 101 and 102. As shown in FIG. 6, it is difficult to provide a partition wall separating pixels in the photoelectric conversion layer 34 made of InGaAs. For this reason, for example, holes generated by entering the photoelectric conversion layer corresponding to pixel 101 are absorbed by the adjacent second electrode 52 as extinction axis light. Thus, when a typical photoelectric conversion element PD is driven, color mixing between pixels occurs due to the extinction axis light.

[0054] FIG. 7 is a diagram showing the ratio of extinction axis light in a pixel 101 and adjacent pixels 102 on the top, bottom, left, and right. As shown in FIG. 7, when holes generated by entering the photoelectric conversion layer corresponding to pixel 101 are absorbed by the second electrode 52 corresponding to pixel 101 at a ratio of, for example, 50%, the adjacent pixel 102 absorbs the extinction axis light at a ratio of, for example, 25%. Thus, when a typical photoelectric conversion element PD is driven, the extinction axis light causes color mixing between pixels, i.e., so-called crosstalk between pixels. It is believed that this crosstalk will worsen as miniaturization progresses. Furthermore, since there is no separation wall between pixels, the readout row and adjacent rows may be affected by color mixing, which may result in a deterioration in linearity.

[0055] On the other hand, it has been found that only a few percent, for example 2 or 3 percent, of the extinction axis light is absorbed by another pixel 101 diagonally adjacent to the pixel 101. Therefore, in this embodiment, color mixing between pixels is suppressed by drive control that staggers the imaging timing of the first pixel group and the second pixel group.

[0056] [Driving example of global shutter method according to this embodiment] Here, a driving example of the global shutter system according to the first embodiment will be described with reference to Fig. 8. Fig. 8 is a diagram showing a driving example of the global shutter system according to the first embodiment.

[0057] An example of driving the global shutter system according to the first embodiment shows an example in which imaging of the second pixel group and data readout of the pixel group (101, 102) are performed in the first frame, and imaging of the first pixel group and data readout of the pixel group (101, 102) are performed in the second frame. In this case, in the first frame, the FD CI capacitance of the first pixel group is maintained in a reset state in which charge accumulation is suppressed. On the other hand, in the second frame, the FD CI capacitance of the second pixel group is maintained in a reset state in which charge accumulation is suppressed. Therefore, in the first frame, a reset state signal is read out from the first pixel group, and a signal including an image signal is read out from the second pixel group. On the other hand, in the second frame, a reset state signal is read out from the second pixel group, and a signal including an image signal is read out from the first pixel group.

[0058] The lower diagram in Figure 8 shows the vertical synchronization signal XVS and the horizontal synchronization signal XHS. The horizontal axis represents time, and the vertical axis represents the vertical synchronization signal XVS and the horizontal synchronization signal XHS. Image G102 is a diagram schematically showing the driving state of pixels 102 in the pixel area 111. The vertical axis represents the row of the pixel area 111, and the horizontal axis represents time. Image G103 is a diagram schematically showing the driving state of pixels 101 in the pixel area 111. The vertical axis represents the row of the pixel area 111, and the horizontal axis represents time. The diagram below that shows the exposure state and data transfer time. The diagram in the upper left shows a timing chart of a global read of each pixel 102 and a timing chart of a rolling read of one row of each of the pixels 101 and 102. The diagram in the upper right shows a timing chart of a global read of each pixel 101 and a timing chart of a rolling read of one row of each of the pixels 101 and 102.

[0059] [Image capture and readout of the second pixel group] At timing t9 immediately before exposure at the beginning of the first frame period, the vertical drive circuit 112 simultaneously sets the drive signals Sofg1 and Sofg2 for each row to a high state, turning on (conducting) the transistors OFG1 and OFG2 included in all pixels 101 and 102 in the pixel region 111. At this time, the drive signals Strg1 and Strg2 are set to a low state, turning off (non-conducting) the transfer transistors TRG1 and TRG2. As a result, in each pixel 101 and 102, the charge accumulated in the SN CI capacitance is absorbed into the power supply line of the power supply VDR, initializing the SN CI capacitance. This state corresponds to the state in which the electronic shutters for all rows are simultaneously closed, as indicated by line SH(ALL) in Figure G102. Furthermore, the drive signal Srst from the vertical drive circuit 112 is set to a high state, turning on the transistors RST included in all pixels 101 and 102 in the pixel region 111. As a result, in each of the pixels 101 and 102, the charge accumulated in the FD CI capacitance is sucked up to the power supply line of the power supply VDR, and the FD CI capacitance is initialized.

[0060] Next, at timing t10, the vertical drive circuit 112 simultaneously sets the drive signals Sofg2 of each row to a low state, thereby turning off the transistors OFG2 included in all the pixels 102 in the pixel region 111. This starts exposure of one frame of the pixels 102 that make up the second pixel group.

[0061] Meanwhile, the vertical drive circuit 112 maintains the high state of the drive signal Sofg1 for each row until timing t14. That is, as shown in the signal area Sarea1, the electronic shutters of the pixels 101 that make up the first pixel group are maintained down. During this time, the charge accumulated in the SN CI capacitors of the pixels 101 that make up the first pixel group is maintained in a state where it is sucked up to the power supply line of the power supply VDR.

[0062] Next, at timing t11, the vertical drive circuit 112 simultaneously sets the drive signals Srst of each row to a low state, thereby turning off the transistors RST included in all the pixels 101 and 102 in the pixel area 111.

[0063] Next, at timing t13, the vertical drive circuit 112 simultaneously sets the drive signal Strg2 for each row to a high state, turning on the transistors TRG2 included in all pixels 102 in the pixel region 111. This causes the charge stored in the SN CI capacitances of the pixels 102 constituting the second pixel group to be simultaneously distributed to the FD CI capacitances. This state is shown by line GD (102 pixels) in Figure G102, and charge distribution for all rows of pixels 102 is performed simultaneously. Meanwhile, the drive signal Strg1 for each row is maintained in a low state during the first frame. This causes the FD CI capacitances of all pixels 102 to be maintained in their reset state.

[0064] Then, at timing t14, the vertical drive circuit 112 simultaneously sets the drive signal Strg2 for each row to a low state, turning off the transistor TRG2 included in the pixel 102. This ends the global shutter drive of the second pixel group. Meanwhile, because the drive signal Strg1 for each row is maintained in a low state throughout one frame period, charge distribution to the FD CI capacitance of the pixel 101 does not occur during one frame period. In other words, the FD CI capacitance of the pixel 101 is always maintained in a reset state during one frame period.

[0065] [Rolling lead in the first frame] Next, at timing t15, rolling read begins. The vertical drive circuit 112 simultaneously sets the drive signals Sofg1 and Sofg2 for each row to a high state, turning on the transistors OFG1 and OFG2 included in all pixels 101 and 102 in the pixel region 111 (to a conductive state). The on state (conductive state) of the transistors OFG1 and OFG2 is constantly maintained throughout one frame period. This resets the SN CI capacitances of all pixels 101 and 102.

[0066] Next, at timing t16, the drive signal Ssel is set to a high state, turning on the path selection transistor Sel. This causes the charge stored in the FD CI capacitance to be converted into a voltage, which is then read out, amplified by the amplifier transistor Amp, and output to the vertical signal line VSL2 via the path selection transistor Sel. In this case, the signal corresponding to the FD CI capacitance corresponding to pixel 102 contains an offset noise signal and a pixel signal. Therefore, the readout of this signal is referred to as a D-phase (Data Phase) readout, and the period during which the D-phase readout is performed is referred to as a D-phase period. This state is indicated by line RD (102 pixels) in Figure G102. As indicated by line RD (102 pixels), the charge stored in the FD CI capacitance of all rows is read out in chronological order for each row.

[0067] On the other hand, the FD CI capacitance corresponding to pixel 101 is maintained in a reset state, so it does not contain a pixel signal but only an offset noise signal. In other words, an offset noise signal is output when the D phase of the FD CI capacitance corresponding to pixel 101 is read out.

[0068] Next, at timing t17, the drive signal Ssel is set to a low state, turning the path selection transistor Sel off. Subsequently, at timing t18, the drive signal Ssel is set to a high state, turning the path selection transistor Sel on. Then, at timing t19, the drive signal Srst is set to a high state, turning the reset transistor Rst on, and resetting the FD CI capacitance. Until timing t20, the reset transistor RSt remains on, and a signal corresponding to the reset level voltage of the FD CI capacitance is output. This signal contains offset noise. Reading this signal from the FD CI capacitance is called P-phase (Pre-Charge) readout, and the period during which the P-phase readout is performed is called the P-phase period. This state is indicated by line RS (102 pixels) in Figure G102. As indicated by line RS (102 pixels), the reset levels of the FD CI capacitances of all rows are read out in chronological order for each row. Then, the readout process of the second pixels 102 in all rows in the pixel region 111 is completed within one frame period.

[0069] [Image capture and readout of the first pixel group] The first pixel group is imaged and read out in the second frame period following the first frame period. The image capturing and read out of the first pixel group are similar to the image capturing and read out of the second pixel group. That is, at timing t22 immediately before exposure at the beginning of the second frame period, the vertical drive circuit 112 simultaneously sets the drive signals Sofg1 and Sofg2 for each row to a high state, turning on the transistors OFG1 and OFG2 included in all pixels 101 and 102 in the pixel region 111 (conducting). At this time, the drive signals Strg1 and Strg2 are set to a low state, turning off the transfer transistors TRG1 and TRG2 (non-conducting). As a result, the charge accumulated in the SN CI capacitances in each pixel 101 and 102 is absorbed into the power supply line of the power supply VDR, and the SN CI capacitances are initialized. This state corresponds to the state in which the electronic shutters for all rows are simultaneously closed, as indicated by line SH(ALL) in Figure G103. Furthermore, the drive signal Srst from the vertical drive circuit 112 goes high, turning on the transistors RST included in all the pixels 101 and 102 in the pixel region 111. As a result, in each of the pixels 101 and 102, the charge accumulated in the FD CI capacitance is sucked up to the power supply line of the power supply VDR, and the FD CI capacitance is initialized.

[0070] Next, at timing t23, the vertical drive circuit 112 simultaneously sets the drive signals Sofg1 of each row to a low state, thereby turning off the transistors OFG1 included in all the pixels 101 in the pixel region 111. This starts exposure of one frame of the pixels 101 that make up the first pixel group.

[0071] Meanwhile, the vertical drive circuit 112 maintains the high state of the drive signal Sofg2 for each row until timing t27. That is, as shown in signal area Sarea2, the electronic shutters of the pixels 102 that make up the second pixel group are maintained down. During this time, the charge accumulated in the SN CI capacitors of the pixels 102 that make up the second pixel group is maintained in a state where it is sucked up to the power supply line of the power supply VDR.

[0072] Next, at timing t26, the vertical drive circuit 112 simultaneously sets the drive signal Strg1 for each row to a high state, turning on the transistors TRG1 included in all pixels 101 in the pixel region 111. This causes the charge stored in the SN CI capacitances of the pixels 101 constituting the first pixel group to be simultaneously distributed to the FD CI capacitances. This state is shown by line GD (103 pixels) in Figure G103, and charge distribution for all rows of pixels 103 is simultaneously performed. Then, at timing t27, the vertical drive circuit 112 simultaneously sets the drive signal Strg1 for each row to a low state, turning off the transistors TRG1 included in the pixels 101. This ends global shutter driving of the first pixel group. Meanwhile, because the drive signal Strg2 for each row is maintained in a low state throughout the entire second frame period, charge distribution to the FD CI capacitances of the pixels 102 does not occur during the 22nd frame period. That is, the FD CI capacitance of the pixel 101 is always maintained in a reset state for two frame periods.

[0073] [Rolling lead in the second frame] The rolling read for the second frame is driven in the same manner as the rolling read for the first frame. That is, first, at timing t15, the rolling read for the second frame starts. The vertical drive circuit 112 simultaneously sets the drive signals Sofg1 and Sofg2 for each row to a high state, turning on the transistors OFG1 and OFG2 included in all pixels 101 and 102 in the pixel area 111 (to a conductive state). The on state (conductive state) of the transistors OFG1 and OFG2 is always maintained throughout one frame period. This resets the SN CI capacitances of all pixels 101 and 102.

[0074] Next, at timing t16, the drive signal Ssel is set to a high state, turning on the path selection transistor Sel. This causes the charge accumulated in the FD CI capacitance to be converted into a voltage, which is read out, amplified by the amplifier transistor Amp, and output to the vertical signal line VSL2 via the path selection transistor Sel. In this case, the signal corresponding to the FD CI capacitance corresponding to pixel 101 contains an offset noise signal and a pixel signal. This state is shown by line RD (pixel 101) in Figure G103. As shown by line RD (pixel 101), the charge accumulated in the FD CI capacitance of all rows is read out in chronological order for each row.

[0075] On the other hand, the FD CI capacitance corresponding to pixel 102 is maintained in a reset state, so it does not contain a pixel signal but only an offset noise signal. In other words, an offset noise signal is output when the D phase of the FD CI capacitance corresponding to pixel 102 is read out.

[0076] Next, at timing t17, the drive signal Ssel is set to a low state, turning the path selection transistor Sel off. Subsequently, at timing t18, the drive signal Ssel is set to a high state, turning the path selection transistor Sel on. Then, at timing t19, the drive signal Srst is set to a high state, turning the reset transistor Rst on, and resetting the FD CI capacitance. The reset transistor RSt remains on until timing t20, and a signal based on the voltage of the reset level of the FD CI capacitance is output. As indicated by the line RS (101 pixels), the reset levels of the FD CI capacitances of all rows are read out in chronological order for each row. The readout process for the second pixels 101 of all rows in the pixel area 111 is then completed within one frame period.

[0077] Fig. 9 is a diagram schematically showing state changes of the SN CI capacitance and the FD CI capacitance in the driving method described in Fig. 8. The state changes of the N CI capacitance and the FD CI capacitance will be described using Fig. 9 while referring to Fig. 8. Image GSN is a diagram showing the SN CI capacitance of each pixel in the pixel area 111 in a two-dimensional matrix. On the other hand, image GFD is a diagram showing the FD CI capacitance of each pixel in the pixel area 111 in a two-dimensional matrix.

[0078] Phase I (the latter half of SN accumulation for pixel 102) is, for example, from timing t11 to t13, and the image GSN of Phase I shows that charge is accumulated in the SN CI capacitance corresponding to pixel 102. On the other hand, the FD CI capacitance is in a reset state, and no signal charge is accumulated therein.

[0079] Phase II (capacitance distribution) is, for example, from timing t13 to t14, and the image GSN of Phase II shows how the charge of the SN CI capacitance corresponding to pixel 102 is distributed to the FD CI capacitance. On the other hand, the image GSN shows how the charge of the SN CI capacitance corresponding to pixel 102 is distributed and stored in the FD CI capacitance.

[0080] Phase III (SN reset) is, for example, at timing t15, and the image GSN in Phase III shows a state in which the charges of the SN CI capacitances corresponding to all pixels are reset, while the charge of the SN CI capacitance corresponding to pixel 102 is distributed and accumulated in the FD CI capacitance.

[0081] Phase IV (the first half of SN accumulation for pixel 101) is the period from timing 23 to the end of rolling read for the first frame, for example, and image GSN for phase IV shows how charge is accumulated in the SN CI capacitance corresponding to pixel 101. On the other hand, it shows how charge in the FD CI capacitance corresponding to pixels 101 and 102 for FD CI capacitance is being rolled read. An image signal including an offset noise signal is generated from the FD CI capacitance charge of all pixels 102. On the other hand, since the FD CI capacitance of all pixels 101 is maintained in a reset state throughout the entire period of phases I to IV, an offset noise signal is generated from the FD CI capacitance charge of pixel 101.

[0082] Phase V (the latter half of SN accumulation for pixel 101) is, for example, from timing t24 to t26, and the image GSN of Phase V shows that charge is accumulated in the SN CI capacitance corresponding to pixel 102. On the other hand, the FD CI capacitance is in a reset state, and no signal charge is accumulated therein.

[0083] Phase VI (capacitance distribution) is, for example, from timing t26 to t27, and the image GSN of phase VI shows how the charge of the SN CI capacitance corresponding to pixel 101 is distributed to the FD CI capacitance. On the other hand, the charge of the SN CI capacitance corresponding to pixel 101 is distributed to and accumulated in the FD CI capacitance.

[0084] Phase VII (SN reset) is, for example, t15 in the second frame, and the image GSN of Phase VII shows a state in which the charges of the SN CI capacitances corresponding to all pixels are reset. On the other hand, the charge of the SN CI capacitance corresponding to pixel 101 is distributed and accumulated in the FD CI capacitance.

[0085] Phase VIII (the first half of the SN accumulation of pixel 102) is the period from timing t10 ​​to the end of the rolling read of the second frame, for example, and the image GSN of phase VIII shows how charge is accumulated in the SN CI capacitance corresponding to pixel 102. On the other hand, it shows how charge in the SN CI capacitance corresponding to pixels 101 and 102 of the FD CI capacitance is being rolled read. An image signal including an offset noise signal is generated from the FD CI capacitance charge of all pixels 101. On the other hand, since the FD CI capacitance of all pixels 102 is maintained in a reset state throughout the entire period of phases I to IV, an offset noise signal is generated from the FD CI capacitance charge of pixel 101.

[0086] In this way, during the period (Phase I, Phase VIII) when charge is accumulated in the SN CI capacitance of each pixel 102, the SN CI capacitance of each pixel 101 is maintained in a reset state, thereby suppressing color mixing from each pixel 102 to each pixel 101. Similarly, during the period (Phase IV, Phase V) when charge is accumulated in the SN CI capacitance of each pixel 101, the SN CI capacitance of each pixel 102 is maintained in a reset state, thereby suppressing color mixing from each pixel 101 to each pixel 102. Meanwhile, the imaging and readout of the second pixel group and the imaging and readout of the first pixel group overlap with the rolling read of the second pixel group and the imaging of the first pixel group. Similarly, the rolling read of the first pixel group and the imaging of the second pixel group overlap with each other. This enables efficient imaging while suppressing color mixing.

[0087] [Two modes of signal processing] The column signal processing circuit 113 according to this embodiment has two signal processing modes for signal processing. The first mode is a method of correcting a signal read out in a D phase period by a signal read out in a P phase period. In the first mode, there is no time difference between the D phase period and the P phase period, so the time correlation of the offset is high and the correction accuracy is high.

[0088] On the other hand, the reset transistor RST is on when reading out a signal during the P-phase period, but is off when reading out a signal during the D-phase period, resulting in different signal generation states. For example, it is thought that when the reset transistor RST is on and off, the bias potential due to the parasitic capacitance of the reset transistor RST may affect the potential of the FD CI capacitance.

[0089] Therefore, in the second mode, the offset signal of the image signal read out during the D-phase period (t16 to t17) (second frame) of each pixel 101 of the first pixel group during imaging is corrected using the offset signal (first frame) of each pixel 101 of the first pixel group read out during the D-phase period (t16 to t17) of each pixel 102 of the second pixel group during imaging. Similarly, the offset signal of the image signal read out during the D-phase period (t16 to t17) (first frame) of each pixel 102 of the second pixel group during imaging is corrected using the offset signal of each pixel 102 of the second pixel group read out during the D-phase period (t16 to t17) (second frame) of each pixel 101 of the first pixel group during imaging. Since both reset transistors RST are off, the signal generation states are equivalent, which, for example, suppresses the influence of parasitic capacitance of the reset transistor RST, resulting in higher correction accuracy.

[0090] 10 is a diagram showing a driving example of Comparative Example 1. In Comparative Example 1, accumulation of SN CI capacitances is performed simultaneously in all pixels 101 and 102, and rolling readout is performed for all pixels 101 and 102. In other words, image GSN in Phase I (the latter half of SN accumulation in pixels 101 and 102) shows a state in which charges are accumulated in the SN CI capacitances corresponding to all pixels 101 and 102. On the other hand, the FD CI capacitances are in a reset state, and no signal charges are accumulated.

[0091] The image GSN of Phase II (capacitance distribution) shows how the charges of the SN CI capacitances corresponding to all pixels 101 and 102 are distributed to the FD CI capacitances. On the other hand, the image shows how the charges of the SN CI capacitances corresponding to all pixels 101 and 102 are distributed and stored in the FD CI capacitances. The image GSN of Phase III (SN reset) shows the state in which the charges of the SN CI capacitances corresponding to all pixels are reset, while the charge of the SN CI capacitance corresponding to pixel 102 is distributed and stored in the FD CI capacitance.

[0092] The image GSN in Phase IV (the first half of the SN accumulation for pixels 101 and 102) shows that charges are accumulated in the SN CI capacitances corresponding to all pixels 101 and 102. On the other hand, it shows that the charge of the SN CI capacitance corresponding to pixel 102 of the FD CI capacitance is being read in a rolling manner. After that, the processing from Phase I is repeated.

[0093] In Comparative Example 1, imaging and readout of all pixels is completed in the I frame, but the color mixture described in Figures 6 and 7 occurs. Furthermore, in the drive of Comparative Example 1, the reset transistor RST is turned on during signal readout in the P phase period, and the reset transistor RST must be turned off during signal readout in the D phase period, resulting in different signal generation states. This may result in a decrease in correction accuracy, as in the first mode described above.

[0094] FIG. 11 is a diagram illustrating the parasitic capacitance between pixels in Comparative Example 1 and the parasitic capacitance between pixels in this embodiment. When charge is stored in the SN CI capacitance, the parasitic capacitance between the SN nodes is, for example, 0.3 (au) for the parasitic capacitance C10 between the pixels on the top, bottom, left, and right sides, and 0.03 (au) for the parasitic capacitance C12 between the diagonal pixels, a difference of about 10 times. Therefore, in the driving example of Comparative Example 1, the SN CI capacitance is affected by the bias potential of the parasitic capacitance C10 on the top, bottom, left, and right sides. On the other hand, in the driving method according to this embodiment, the pixels on the top, bottom, left, and right sides are always in a reset state, so the influence of the parasitic capacitance C10 between the pixels on the top, bottom, left, and right sides is suppressed.

[0095] FIG. 12 is a diagram schematically illustrating a driving method in mode 2 according to this embodiment. The upper side shows the driving state of pixel 102, which is a second pixel group, and the lower side shows the driving state of pixel 101, which is a first pixel group. As shown in FIG. 12, at t40, all SN CI capacitances and all FD CI capacitances are reset, and the SN CI capacitance and FD CI capacitance of pixel 101 are maintained in the reset state, and accumulation (exposure) of the SN CI capacitance of pixel 102 is performed until t41. Then, during the period from t41 to t42, D-phase readout of the FD CI capacitances corresponding to all pixels is performed. As a result, a pixel signal including an offset signal is output from pixel 102. Meanwhile, only an offset noise signal is output from pixel 101.

[0096] At t42, all SN CI capacitances and all FD CI capacitances are reset, and the SN CI capacitance and FD CI capacitance of pixel 102 are maintained in the reset state, and accumulation (exposure) of the SN CI capacitance of pixel 101 is performed until t43. Then, during the period from t43 to t44, D-phase readout of the FD CI capacitance corresponding to all pixels is performed. As a result, a pixel signal including an offset signal is output from pixel 101. Meanwhile, only an offset noise signal is output from pixel 102.

[0097] In signal processing in mode 2, the pixel signal corresponding to the CI capacitance for FD of pixel 102 read out during the period from t41 to t42 is corrected with an offset signal corresponding to the CI capacitance for FD of pixel 102 read out during the period from t43 to t44. Similarly, the offset signal corresponding to the CI capacitance for FD of pixel 101 read out during the period from t41 to t42 is used for correction with the image signal corresponding to the CI capacitance for FD of pixel 101 read out during the period from t43 to t44. As described above, in mode 2, the generation states of the pixel signal including a noise signal and the noise signal are equivalent, which suppresses the influence of the parasitic capacitance of the reset transistor RST, for example, and improves correction accuracy.

[0098] 13 is a diagram showing a driving example of Comparative Example 2. At t50, the SN CI capacitance of each pixel 101 in the first pixel group and all FD CI capacitances are collectively reset, and charge accumulation (exposure) of the SN CI capacitance of each pixel 101 in the first pixel group is performed until t51. Then, at t51, the charge of the SN CI capacitance of each pixel 101 is transferred to the FD CI capacitance of each pixel 101, and the FD CI capacitance of each pixel 101 is read out. This driving process is repeated for the first pixel group.

[0099] Meanwhile, for the second pixel group, the SN CI capacitance of each pixel 101 in the second pixel group and all FD CI capacitances are collectively reset at t51, and charge accumulation (exposure) of the SN CI capacitance of each pixel 101 in the first pixel group is performed until t52. Then, at t53, the charge of the SN CI capacitance of each pixel 101 is transferred to the FD CI capacitance of each pixel 102, and the FD CI capacitance of each pixel 102 is read out. As such, in the driving example of Comparative Example 2, exposure and readout of the first pixel group and the second pixel group are performed in parallel and alternately. Comparative Example 2 does not include driving for D-phase readout of the charge of the FD CI capacitance in the reset state. Therefore, only signal processing in Mode 1 according to this embodiment can be performed, which may result in a decrease in correction accuracy as described above.

[0100] As described above, according to this embodiment, the vertical drive circuit 112 maintains the accumulated charge of the FD CI capacitance in the second pixel group at an initial state during the first period (t41 to t42) of signal readout based on the accumulated charge of the FD CI capacitance in the pixel region 111. This enables offset noise signals in the second pixel group to be read out during the D-phase period. This makes it possible to correct the signals read out during the D-phase period of the second pixel group using noise signals read out during the D-phase period when the same drive is performed, improving correction accuracy. Furthermore, by switching the pixel groups to be imaged between the first and second frames, and resetting one pixel group during image capture while resetting the other pixel group during image capture, a time difference between the image captures is created, which suppresses crosstalk to adjacent pixels and also suppresses a decrease in linearity of the pixels with respect to input light.

[0101] (Second embodiment) The electronic device 1 according to the second embodiment differs from the electronic device 1 according to the first embodiment in that the exposure period is different for each pixel 101 of the first pixel group and each pixel 102 of the second pixel group. The differences from the electronic device 1 according to the first embodiment will be described below.

[0102] 14 is a diagram showing an example of driving using the global shutter method according to the second embodiment. In this example of driving using the global shutter method according to the second embodiment, the exposure time of the second pixel group, indicated by the period t10a to t13, is shorter than the exposure time of the first pixel group, indicated by the period t23 to t26. This allows each pixel 102 in the second pixel group to have photosensitivity up to a higher luminance than each pixel 101 in the first pixel group. On the other hand, each pixel 101 in the first pixel group has photosensitivity down to a lower luminance than each pixel 102 in the second pixel group.

[0103] 15 is a diagram schematically illustrating image data of the first pixel group and image data of the second pixel group. The image processing unit 5 (see FIG. 1) interpolates each pixel value of the image data of the first pixel group, and interpolates each pixel value of the image data of the second pixel group. The interpolated image data of the first pixel group and the image data of the second pixel group are then added together. This makes it possible to generate an image with a high dynamic range, i.e., an image with an expanded dynamic range.

[0104] (Third embodiment) The electronic device 1 according to the third embodiment differs from the electronic device 1 according to the first embodiment in that the photoelectric conversion element PD has a polarization filter. The differences from the electronic device 1 according to the first embodiment will be described below.

[0105] Fig. 16 is a diagram showing a schematic partial cross-sectional view of the photoelectric conversion element PD in the pixels 101 and 102 according to the third embodiment. As shown in Fig. 16, the pixels 101 and 102 according to the third embodiment have a polarizing filter F10. As a result, the pixels 101 and 102 capture an image of incident light that has passed through the polarizing filter F10.

[0106] 17 is a diagram showing the relative positions of the polarizing filter F10 and the pixels 101 and 102. Image A is a plan view showing a portion of the polarizing filter F10, image B is a plan view showing a schematic representation of pixel 102 corresponding to the horizontal polarizing filter of the polarizing filter F10, and image C is a plan view showing a schematic representation of pixel 101 corresponding to the vertical polarizing filter of the polarizing filter F10. Image D corresponds to image B and shows that pixel 101 below the vertical polarizing filter is imaged and read out. Image E corresponds to image C and shows that pixel 102 below the horizontal polarizing filter is imaged and read out.

[0107] In this way, imaging and readout of each pixel 101 of the first pixel group is performed, and imaging and readout of each pixel 102 of the second pixel group is performed. This makes it possible to suppress color mixing between the image signal obtained by the horizontal polarization filter and the image signal obtained by the vertical polarization filter. (Fourth embodiment) The electronic device 1 according to the fourth embodiment differs from the electronic device 1 according to the first embodiment in that the photoelectric conversion element PD has a light-shielding pole member DTI. The differences from the electronic device 1 according to the first embodiment will be described below.

[0108] Fig. 18 is a plan view showing a part of the pixel region 11 according to the fourth embodiment. Fig. A10 is a diagram showing an example in which light-shielding column members DT are provided at the corners of pixels 101 and 102. The light-shielding column members DT are made of oxide, aluminum, or the like, and are embedded in the first compound semiconductor layer 31, the reflective film 33, and the photoelectric conversion layer 34 (see Fig. 6). Figs. B10 and C10 are diagrams showing that after the pixel 101 is imaged and read out, the pixel 102 is imaged and read out.

[0109] In this way, by embedding the light-shielding column members DT, movement of electrons and holes between the pixels 101 and between the pixels 102 is suppressed. Therefore, extinction axis light between the pixels 101 and between the pixels 102 is also suppressed. This suppresses color mixing between the pixels 101 and between the pixels 102, making it possible to further suppress color mixing in the pixel region 11. This makes it possible to suppress color mixing even in polarization imaging of near-infrared (NIR) and short-wave infrared (SWIR) using a photoelectric conversion element using InGaAs.

[0110] The present technology can be configured as follows:

[0111] (1) a pixel region in which pixels, each including a photoelectric conversion unit and a first capacitance that accumulates electric charges based on the photoelectric conversion of the photoelectric conversion unit, are arranged in a two-dimensional matrix, the pixel region having a first pixel group in which pixels adjacent in a diagonal direction are arranged, and a second pixel group in which pixels adjacent in the up, down, left, and right directions to the pixels of the first pixel group are arranged; a driver that generates a drive signal that drives the pixels in the pixel region, The driving unit maintains the second pixel group in a reset state that suppresses accumulation of the accumulated charge in the first capacitor during a first period of signal readout based on the accumulated charge in the first capacitor of the pixel region.

[0112] (2) The imaging element described in (1), wherein the driving unit maintains the first pixel group in a reset state that suppresses accumulation of accumulated charge in the first capacitance during a second period different from a first period of signal readout based on accumulated charge in the first capacitance of the pixel region.

[0113] (3) The imaging element according to (2), wherein the signals of the first pixel group read out during the first period are corrected using the signals of the first pixel group read out during the second period.

[0114] (4) The imaging element according to (2), wherein the signals of the second pixel group read out during the second period are used to correct the signals of the second pixel group read out during the first period.

[0115] (5) The imaging element according to (4), wherein the photoelectric conversion section is a photoelectric conversion element using InGaAs.

[0116] (6) The imaging element according to (5), wherein the driving unit maintains a reset state that suppresses charge accumulation in the pixels of the second pixel group in response to the exposure during a first exposure period in which the pixels of the first pixel group are exposed.

[0117] (7) The imaging element described in (6), wherein the driving unit exposes the pixels of the second pixel group during a second exposure period following the first exposure period, and maintains a reset state that suppresses charge accumulation in the pixels of the first pixel group.

[0118] (8) The imaging element according to (7), wherein the first exposure period and the second exposure period have different lengths.

[0119] (9) The imaging element described in (1), wherein the pixels of the first pixel group are exposed through a polarizing element polarizing in a first direction, and the pixels of the second pixel group are exposed through a polarizing element polarizing in a second direction different from the first direction.

[0120] (10) The imaging element according to (1), wherein a light-shielding column member is provided at a corner of at least one pixel in the pixel region.

[0121] (11) The pixel includes the photoelectric conversion unit and a second capacitor that accumulates charges generated in the photoelectric conversion unit; a transfer transistor that transfers the charge stored in the second capacitor to the first capacitor; the first capacitance; an amplifying transistor that amplifies the charge of the first capacitor and outputs a signal with a level corresponding to the charge; The imaging element according to (7), comprising at least

[0122] (12) The image sensor of (11), wherein the transfer transistors of the pixels of the first pixel group arranged in the same row of the pixel region are connected to the drive unit via a first control line, and the transfer transistors of the pixels of the second pixel group arranged in the same row of the pixel region are connected to the drive unit via a second control line different from the first control line.

[0123] (13) The pixel is a second reset transistor that sets the second capacitor to an initial state; a first reset transistor that sets the first capacitor to an initial state; The imaging element according to (12), further comprising:

[0124] (14) The imaging element described in (13), wherein the second reset transistors of the pixels of the first pixel group arranged in the same row of the pixel region are connected to the driving unit via a third control line, and the second reset transistors of the pixels of the second pixel group arranged in the same row of the pixel region are connected to the driving unit via a fourth control line different from the third control line.

[0125] (15) The imaging element described in (13), wherein the driving unit maintains the transfer transistor in the second pixel group in a non-conductive state, and reads out signals for the first period after initializing the first capacitance using the first reset transistor.

[0126] (16) The imaging element described in (13), wherein the driving unit maintains the transfer transistor in the first pixel group in a non-conductive state, and performs signal readout for the second period after initializing the first capacitance using the first reset transistor.

[0127] (17) The imaging element according to (13), wherein the drive section maintains the second reset transistors in the second pixel group in a conductive state during the first exposure period.

[0128] (18) The imaging element according to (13), wherein the drive section maintains the second reset transistors in the first pixel group in a conductive state during the second exposure period.

[0129] (19) An electronic device having the imaging element described in (1).

[0130] (20) An electronic device having the imaging element according to (8), an image processing unit that performs interpolation processing on the first image data based on the first exposure period and the second image data based on the second exposure period, and performs synthesis processing on the first image data based on the first exposure period and the second image data based on the second exposure period;

[0131] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

Claims

1. a pixel region in which pixels, each including a photoelectric conversion unit and a second capacitance that accumulates charge based on photoelectric conversion of the photoelectric conversion unit, are arranged in a two-dimensional matrix, the pixel region having a first pixel group in which pixels adjacent in a diagonal direction are arranged, and a second pixel group in which pixels adjacent in a vertical and horizontal direction to pixels of the first pixel group are arranged; a driver that generates a drive signal that drives the pixels in the pixel region, The driving section maintains the second capacitance of one of the first pixel group and the second pixel group in a reset state during an exposure period of the other pixel group.

2. The pixel includes the photoelectric conversion unit and the second capacitance; A first capacitance; and a transfer transistor that transfers the charge stored in the second capacitor to the first capacitor; an amplifying transistor that amplifies the charge of the first capacitor and outputs a signal with a level corresponding to the charge; The imaging device according to claim 1 , comprising at least:

3. 3. The imaging element according to claim 2, wherein the driving unit maintains the first pixel group in a reset state that suppresses accumulation of the accumulated charge in the first capacitance in a second period different from a first period of signal readout based on the accumulated charge in the first capacitance in the pixel region.

4. The image sensor according to claim 3 , wherein the signals of the first pixel group read out during the first period are corrected using the signals of the first pixel group read out during the second period.

5. The imaging device according to claim 4 , wherein the photoelectric conversion section is a photoelectric conversion element using InGaAs.

6. The image sensor according to claim 5 , wherein the driving section maintains a reset state in which the pixels of the second pixel group are prevented from accumulating charges in response to the exposure during a first exposure period in which the pixels of the first pixel group are exposed to light.

7. 7. The imaging element according to claim 6, wherein the drive section exposes the pixels of the second pixel group to light during a second exposure period following the first exposure period, and maintains a reset state that suppresses charge accumulation in the pixels of the first pixel group.

8. The imaging device according to claim 7 , wherein the first exposure period and the second exposure period have different lengths.

9. 2. The imaging element of claim 1, wherein the pixels of the first pixel group are exposed to light through a polarizing element that polarizes in a first direction, and the pixels of the second pixel group are exposed to light through a polarizing element that polarizes in a second direction different from the first direction.

10. The imaging device according to claim 1 , wherein a light-shielding column member is provided at a corner of at least one pixel in the pixel region.

11. 9. The image sensor according to claim 8, wherein the transfer transistors of the pixels of the first pixel group arranged in the same row of the pixel region are connected to the drive unit via a first control line, and the transfer transistors of the pixels of the second pixel group arranged in the same row of the pixel region are connected to the drive unit via a second control line different from the first control line.

12. The pixel is a second reset transistor that sets the second capacitor to an initial state; a first reset transistor that sets the first capacitor to an initial state; The imaging device of claim 11 further comprising:

13. 13. The image sensor according to claim 12, wherein the second reset transistors of the pixels of the first pixel group arranged in the same row of the pixel region are connected to the drive unit via a third control line, and the second reset transistors of the pixels of the second pixel group arranged in the same row of the pixel region are connected to the drive unit via a fourth control line different from the third control line.

14. 13. The image sensor according to claim 12, wherein the drive unit maintains the transfer transistors in the second pixel group in a non-conductive state and resets the first capacitors using the first reset transistors, and then performs signal readout for the first period.

15. 13. The image sensor according to claim 12, wherein the drive unit maintains the transfer transistors in the first pixel group in a non-conductive state and resets the first capacitors using the first reset transistors, and then performs signal readout for the second period.

16. The image sensor according to claim 12 , wherein the drive section maintains the second reset transistors in the second pixel group in a conductive state during the first exposure period.

17. The image sensor according to claim 12 , wherein the drive section maintains the second reset transistors in the first pixel group in a conductive state during the second exposure period.

18. An electronic device comprising the imaging device according to claim 1.

19. An electronic device having the imaging device according to claim 8, an image processing unit that performs interpolation processing on the first image data based on the first exposure period and the second image data based on the second exposure period, and performs synthesis processing on the first image data and the second image data.

Images