Light-emitting device and display device including the same

Abstract

To provide a light emitting element with improved external light extraction efficiency and a display including the same.SOLUTION: A light emitting element according to one embodiment of the present specification includes a first semiconductor layer, a second semiconductor layer opposite the first semiconductor layer, and a light emitting layer between the first semiconductor layer and the second semiconductor layer, and the planar shape of the first semiconductor layer, the second semiconductor layer, and the light emitting layer includes at least one straight first side and at least one curved second side.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a light emitting device and a display device including the same, and more particularly to a light emitting device with improved external light extraction efficiency and a display device including the same. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and are therefore highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a light emitting device with improved light extraction efficiency and a display device including the same.

[0006] The present disclosure provides a light emitting device that allows light emitted from the light emitting device to be extracted toward the front surface of the display device, and a display device including the light emitting device.

[0007] However, the problems to be solved in this specification are not limited to those mentioned above, and other technical problems can be inferred from the following examples. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, a light-emitting element according to one embodiment of the present specification includes a first semiconductor layer, a second semiconductor layer facing the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer, and the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer include at least one first side that is linear and at least one second side that is curved.

[0009] In order to solve the above-mentioned problems, a display device according to one embodiment of the present specification includes a substrate including a plurality of sub-pixels, a plurality of transistors arranged on the substrate, and a light-emitting element arranged on the substrate in each of the plurality of sub-pixels.

[0010] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0011] The present invention allows light emitted from the light emitting device to be randomly reflected inside the light emitting device, thereby minimizing light that is trapped inside the light emitting device and cannot be extracted, thereby improving external light extraction efficiency.

[0012] In the present specification, light emitted in a side direction of the light emitting device can be extracted in a front direction of the display device, thereby improving the efficiency of light extraction to the outside.

[0013] The present invention can improve the luminance uniformity of light emitted in the lateral direction of the light emitting device.

[0014] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic cross-sectional view of a light emitting device according to an embodiment of the present specification. [Figure 2] 1 is a plan view schematically illustrating a planar shape of a light emitting device according to an embodiment of the present specification. [Figure 3] FIG. 10 is a plan view schematically showing another example of the planar shape of the light emitting device according to the embodiment of the present specification. [Figure 4] 10 is a plan view schematically illustrating still another example of the planar shape of a light emitting device according to an embodiment of the present specification. FIG. [Figure 5] 10 is a plan view schematically illustrating still another example of the planar shape of a light emitting device according to an embodiment of the present specification. FIG. [Figure 6a] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6b] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6c] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6d] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6e] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6f] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6g] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6h] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 6i] 1A and 1B are plan views for comparatively explaining effects depending on the planar shape of a light emitting element according to an example of this specification. [Figure 7]1 is a schematic configuration diagram of a display device according to an embodiment of the present specification. [Figure 8] FIG. 2 is a cross-sectional view of a subpixel of a display device according to an embodiment of the present specification. [Figure 9] FIG. 10 is a cross-sectional view of a subpixel of a display device according to another embodiment of the present specification. [Figure 10a] 3 shows a simulation result of a far-field emission pattern for the light emitting device shown in FIG. 2. [Figure 10b] 4 shows simulation results of a far-field emission pattern for the light-emitting device shown in FIG. 3. [Figure 10c] 5 is a simulation result of a far-field emission pattern for the light-emitting device shown in FIG. 4. [Figure 11] FIG. 10 is a plan view schematically showing the planar shapes of a light-emitting element and a reflective layer of a display device according to another example of the present specification. [Figure 12] FIG. 10 is a plan view schematically showing another example of the planar shapes of the light-emitting element and the reflective layer of the display device according to another example of the present specification. [Figure 13] FIG. 10 is a plan view schematically showing still another example of the planar shapes of a light-emitting element and a reflective layer of a display device according to another embodiment of the present specification. [Figure 14] FIG. 10 is a cross-sectional view of a subpixel of a display device according to still another embodiment of the present specification. DETAILED DESCRIPTION OF THE INVENTION

[0016] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely so that this disclosure will be complete and will fully convey the scope of the invention to those skilled in the art.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0018] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description. When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0019] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0020] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0021] Like reference numbers refer to like elements throughout the specification.

[0022] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0023] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0024] In the following, the present specification will be described with reference to the drawings.

[0025] FIG. 1 is a schematic cross-sectional view of a light-emitting device according to an embodiment of the present specification.

[0026] Referring to FIG. 1, the light emitting element ED includes a first semiconductor layer 121, a light emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a sealing layer 126.

[0027] The light emitting device ED may be formed in various structures, such as a lateral type, a vertical type, a flip type, etc. The lateral type light emitting device includes a first electrode and a second electrode horizontally disposed on both sides of the light emitting layer. The vertical type light emitting device includes a first electrode and a second electrode disposed above and below the light emitting layer. The flip type light emitting device has substantially the same structure as the lateral type light emitting device, except that the first electrode and the second electrode are horizontally disposed above the light emitting layer, whereas the flip type light emitting device has the first electrode and the second electrode horizontally disposed below the light emitting layer. In the following description, the light emitting device ED will be described assuming a vertical structure, but the type of the light emitting device ED is not limited thereto, and the light emitting device ED may be formed in a horizontal structure or a flip type structure by applying the technical concept of this specification.

[0028] A first semiconductor layer 121 is disposed under the light emitting element ED. The first semiconductor layer 121 may be a layer formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 may be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with n-type and p-type impurities. Here, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto. In this specification, the first semiconductor layer 121 is defined as an n-type semiconductor layer and a layer doped with n-type impurities, but is not limited thereto.

[0029] The light emitting layer 122 and the second semiconductor layer 123 are disposed on the first semiconductor layer 121 .

[0030] The light emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 can have a single layer or a multi-quantum well (MQW) structure and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0031] The second semiconductor layer 123 is disposed on the light emitting layer 122. The second semiconductor layer 123 may be a layer formed by doping a specific material with n-type and p-type impurities. For example, the second semiconductor layer 123 may be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with n-type and p-type impurities. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto. In this specification, the second semiconductor layer 123 is defined as a p-type semiconductor layer doped with p-type impurities, but is not limited thereto.

[0032] The first electrode 124 is disposed under the first semiconductor layer 121. The first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. For example, the first electrode 124 is disposed on the lower surface of the first semiconductor layer 121 and covers the surface of the lower surface of the first semiconductor layer 121.

[0033] The first electrode 124 may be made of a conductive material, for example, but is not limited to, an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. For example, the first electrode 124 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0034] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the upper surface of the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0035] The encapsulation layer 126 may be disposed to surround at least a portion of the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, and the second electrode 125. The encapsulation layer 126 may protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. For example, the encapsulation layer 126 may cover the side surfaces of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. The encapsulation layer 126 may cover the entire side surface of the first semiconductor layer 121, but is not limited to this.

[0036] The light emitting element ED may include light emitting elements that emit various colors, for example, the light emitting element ED may be any one of a red light emitting element, a blue light emitting element, and a green light emitting element, but is not limited thereto.

[0037] Fig. 2 is a plan view schematically showing the planar shape of a light-emitting device according to an embodiment of the present specification. Fig. 3 is a plan view schematically showing another example of the planar shape of a light-emitting device according to an embodiment of the present specification. Fig. 4 is a plan view schematically showing yet another example of the planar shape of a light-emitting device according to an embodiment of the present specification. Fig. 5 is a plan view schematically showing yet another example of the planar shape of a light-emitting device according to an embodiment of the present specification. In Figs. 2 to 5, the planar shapes are shown schematically without distinguishing the specific components of the light-emitting device ED.

[0038] The planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED can include a first side SI1 having a linear shape and a second side SI2 having a curved shape.

[0039] First, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may include a plurality of first sides SI1 and a plurality of second sides SI2. When the planar shapes of the first semiconductor layer, the light emitting layer, and the second semiconductor layer of the light emitting element include a plurality of first sides SI1 and a plurality of second sides SI2, the plurality of first sides SI1 and the plurality of second sides SI2 may be arranged alternately. Thus, the plurality of first sides SI1 may be arranged in positions facing each other, and the plurality of second sides SI2 may be arranged in positions facing each other.

[0040] 2 and 3 to describe a case where the planar shapes of the first semiconductor layer, the light emitting layer, and the second semiconductor layer of the light emitting element ED include a plurality of first sides SI1 and a plurality of second sides SI2, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have the first sides SI1 and the second sides SI2 alternately arranged in a clockwise direction. Therefore, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have the second sides SI2 arranged on both sides of the first side SI1.

[0041] 2, when the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED has four sides, two linear first sides SI1 may be arranged to face each other on the upper and lower sides, and two arc-shaped second sides SI2 may be arranged to face each other on the left and right sides. For example, the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have a Bunimovich stadium shape.

[0042] As shown in FIG. 3 , the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have curved corner regions. For example, the corner regions may have a rounded shape. For example, if the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED has eight sides, four linear first sides SI1 may be arranged facing each other on the upper, lower, left, and right sides, and four arc-shaped second sides SI2 may be arranged facing each other at the corner portions of the upper left, upper right, lower left, and lower right sides. For example, the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have a Sinai billiard shape. Although FIG. 3 illustrates the second side SI2 as being concave inward, this is not limiting and the second side SI2 may be arranged as being convex outward.

[0043] Next, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may include one first side SI1 and one second side. When the planar shapes of the first semiconductor layer, the light emitting layer, and the second semiconductor layer of the light emitting element include one first side SI1 and one second side, one end of the first side SI1 may be connected to one end of the second side. For example, both ends of the one first side SI1 and the one second side may be connected to each other.

[0044] 4 and 5 to describe a case where the planar shapes of the first semiconductor layer, the light emitting layer, and the second semiconductor layer of the light emitting element ED include one first side SI1 and one second side. The planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may include one first side SI1 and one second side. For example, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may include one linear first side SI1 and one arc-shaped second side. For example, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have both ends of the first side SI1 connected to both ends of the second side.

[0045] For example, as shown in FIG. 4, when the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED has two sides, an arc-shaped second side may be disposed on one side of a linear first side SI1, and both ends of the first side SI1 may be connected to both ends of the second side. The planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have a length of the first side SI1 that is shorter than the diameter of the second side. For example, the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may have a "D" shape, where a portion of a circle is cut in a straight line. When a portion of a circle is cut in a straight line, the first side SI1 may be a chord, or may not pass through the center. The shape of a circle cut into a straight line may have a "D" shape, and the area of ​​the "D" shape may be larger than the area of ​​a semicircle, but is not limited to this and may also be smaller than the area of ​​a semicircle.

[0046] 5, when the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED is composed of two sides, a circular arc-shaped second side may be disposed on one side of the linear first side SI1, and both ends of the first side SI1 may be connected to both ends of the second side. For example, the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may be such that the length of the first side SI1 is the same as the diameter of the second side. For example, the planar shape of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 of the light emitting element ED may be semicircular.

[0047] 6a to 6i are plan views for comparatively explaining the effects of different planar shapes of the light emitting device according to one embodiment of the present specification.

[0048] The effects of the present embodiment will be described in more detail below through examples and comparative examples. However, the following examples are for illustrative purposes only and do not limit the scope of the present embodiment. The examples and comparative examples are described based on the planar shape of the upper surface of the light-emitting element ED, and the planar shape of the examples and comparative examples is the same in all cases.

[0049] [Comparative Example 1] In Comparative Example 1, a square planar shape was prepared as shown in Fig. 6a, where L is the length of one of the sides of the square.

[0050] Comparative Example 2 In Comparative Example 2, a rectangular planar shape was prepared as shown in Fig. 6b, where L is the length of one of the sides of the regular square in Fig. 6a.

[0051] Comparative Example 3 In Comparative Example 3, a circular planar shape was prepared as shown in Fig. 6c, in which r is as shown in Equation 1 below.

number

[0052] Comparative Example 4 In Comparative Example 4, a hexagonal planar shape was prepared as shown in Fig. 6d, where r is as shown in the following equation 2.

number

[0053] Comparative Example 5 In Comparative Example 5, an octagonal planar shape was prepared as shown in Fig. 6e, where r is as shown in the following equation 3.

number

[0054] Comparative Example 6 In Comparative Example 6, a trapezoidal shape in plan view was prepared as shown in Fig. 6f. In Fig. 6f, D is as shown in the following equation 4. D is the height of the trapezoid.

number

[0055] [Example 1] In Example 1, a ball having a planar shape similar to that of Bunimovich Stadium was prepared as shown in Figures 2 and 6g. In Figure 6g, r is given by the following equation (5).

number

[0056] [Example 2] In Example 2, a "D"-shaped planar shape was prepared, as shown in Figures 4 and 6h, where r is the following equation (6).

number

[0057] [Example 3] In Example 3, a semicircular planar shape was prepared as shown in Figures 5 and 6i. In Figure 6i, r is as shown in the following equation (7).

number

[0058] The light extraction efficiency of the light emitting device manufactured as described above was measured. The light extraction efficiency was determined by measuring the amount of light extracted from the light emitting device ED. The results are shown in Table 1 below. Here, the light extraction efficiency refers to the ratio of light extracted to the outside of the light emitting device out of the light emitted from the light emitting device. [Table 1]

[0059] Referring to Table 1, it can be seen that Examples 1, 2, and 3, in which the planar shape has both straight and curved sides, have higher light extraction efficiencies than Comparative Example 1, in which the planar shape is a regular square, Comparative Example 2, in which the planar shape is a rectangle, Comparative Example 3, in which the planar shape is a circle, Comparative Example 4, in which the planar shape is a hexagon, Comparative Example 5, in which the planar shape is an octagon, and Comparative Example 6, in which the planar shape is a trapezoid.

[0060] Based on the experimental results, when both straight and curved sides are arranged in a planar shape, it is possible to improve the external light extraction efficiency.

[0061] 7 is a schematic diagram of a display device according to an embodiment of the present disclosure, in which for convenience of explanation, only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are shown among various components of the display device 100.

[0062] Referring to FIG. 7, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0063] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided by the timing controller TC. Although one gate driver GD is shown as being spaced apart from one side of the display panel PN in FIG. 7, the number and arrangement of the gate drivers GD are not limited thereto.

[0064] The data driver DD supplies data voltages to the data lines DL according to the data control signals and image data provided by the timing controller TC. The data driver DD converts the image data into data voltages using a reference gamma voltage and supplies the converted data voltages to the data lines DL.

[0065] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC then supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0066] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL intersect with each other on the display panel PN, and a plurality of sub-pixels SP may be formed at the intersections of the scan lines SL and the data lines DL.

[0067] A display area AA and a non-display area NA can be defined on the display panel PN.

[0068] The display area AA is an area where an image is displayed on the display device 100. A plurality of subpixels SP constituting a plurality of pixels PX and a pixel circuit for driving the subpixels SP may be arranged in the display area AA. The subpixels SP are the smallest unit constituting the display area AA, and n subpixels SP may form one pixel PX. Thin film transistors or the like for driving a plurality of light-emitting elements may be arranged in each of the subpixels SP. The light-emitting elements may be defined differently depending on the type of the display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel PN, the light-emitting elements may be LEDs (light-emitting diodes) or micro LEDs (micro LEDs, μLEDs). A plurality of signal lines are arranged in the display area AA to transmit various signals to the subpixels SP. For example, the signal lines may include a plurality of data lines DL for supplying data voltages to each of the subpixels SP and a plurality of scan lines SL for supplying scan signals to each of the subpixels SP. The plurality of scan lines SL may extend from the display area AA in one direction and be connected to the plurality of sub-pixels SP, and the plurality of data lines DL may extend from the display area AA in a direction different from the one direction and be connected to the plurality of sub-pixels SP. In addition, low potential power supply lines, high potential power supply lines, etc. may also be arranged in the display area AA, but are not limited thereto.

[0069] The non-display area NA is an area where no image is displayed and may be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, as well as driving ICs such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0070] Meanwhile, the non-display area NA may be located on the rear surface of the display panel PN, that is, on a surface without sub-pixels SP, or may be omitted, and is not limited to what is shown in the drawings.

[0071] Meanwhile, drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD may be implemented in the non-display area NA in a GIP (Gate In Panel) manner, or may be implemented between a plurality of sub-pixels SP in the display area AA in a GIA (Gate In Active Area) manner.

[0072] For example, the data driver DD and the timing controller TC may be formed on a separate flexible film and printed circuit board, and the display panel PN may be electrically connected to the data driver DD and the timing controller TC by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0073] As another example, if the gate driver GD is mounted within the display area AA using the GIA method, and side wiring SRL is formed to connect signal wiring on the front side of the display panel PN to pad electrodes on the rear side of the display panel PN, and a flexible film and a printed circuit board are bonded to the rear side of the display panel PN, the non-display area NA on the front side of the display panel PN can be minimized. Therefore, if the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN in the above manner, it may be possible to implement a zero bezel, which essentially does not have a bezel.

[0074] FIG. 8 is a cross-sectional view of a subpixel of a display device according to an embodiment of the present specification.

[0075] 8, the substrate 110 is a component for supporting various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also be made of a flexible material including a polymer or plastic.

[0076] A light-shielding layer LS is disposed in each of the sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident on the active layer ACT of the driving transistor DT below the substrate 110. The light-shielding layer LS blocks light incident on the active layer ACT of the driving transistor DT, thereby minimizing leakage current.

[0077] A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be formed of, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, and is not limited thereto.

[0078] The drive transistor DT is disposed on the buffer layer 111. The drive transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0079] The active layer ACT is disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0080] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0081] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0082] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114 to connect the source electrode SE and the drain electrode DE to the active layer ACT, respectively. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting the components below the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0083] A capacitor electrode C is disposed on the first interlayer insulating layer 113. The capacitor electrode C may be disposed to overlap the gate electrode GE with the first interlayer insulating layer 113 sandwiched therebetween. Thus, the capacitor electrode C can maintain the voltage of the gate electrode GE of the driving transistor DT for a certain period of time.

[0084] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0085] Meanwhile, in this specification, it has been described that the first interlayer insulating layer 113 and the second interlayer insulating layer 114, i.e., multiple insulating layers, are arranged between the gate electrode GE and the source electrode SE and drain electrode DE, but only one insulating layer may be arranged between the gate electrode GE and the source electrode SE and drain electrode DE, and the present invention is not limited to this.

[0086] Next, an auxiliary electrode BCNT is disposed on the gate insulating layer 112. The auxiliary electrode BCNT is an electrode for applying a voltage to the light-shielding layer LS below the buffer layer 111. For example, the light-shielding layer LS is electrically connected to other components disposed on the substrate 110 through the auxiliary electrode BCNT and can receive a voltage. The light-shielding layer LS receiving the voltage through the auxiliary electrode BCNT no longer operates as a floating gate, and it is possible to minimize a threshold voltage fluctuation of the driving transistor DT caused by the floating light-shielding layer LS.

[0087] The power supply wiring PL is disposed on the second interlayer insulating layer 114. The power supply wiring PL is electrically connected to the light emitting element together with the drive transistor DT, and can cause the light emitting element to emit light. For example, the power supply wiring PL may be, but is not limited to, a low potential power supply wiring that supplies a low potential power supply voltage or a high potential power supply wiring that supplies a high potential power supply voltage. The power supply wiring PL may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0088] An organic insulating layer 115 is disposed on the driving transistor DT and the power wiring PL. The organic insulating layer 115 can planarize the upper surface of the substrate 110 on which the driving transistor DT is disposed. The organic insulating layer 115 can be configured as a single layer or multiple layers and can be made of, for example, photoresist or an acrylic organic material, but is not limited thereto.

[0089] A plurality of first reflective electrodes RE1 and a plurality of second reflective electrodes RE2 spaced apart from each other are disposed on the organic insulating layer 115. The plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 electrically connect the plurality of light emitting elements ED to the power wiring PL and the driving transistor DT, and also function as a reflector that reflects light emitted from the plurality of light emitting elements ED upward or downward toward the substrate 110. The plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 are formed of a conductive material with excellent reflective properties and can reflect light emitted from the light emitting elements ED upward. For example, the plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 may be made of a metal material with excellent reflective properties, such as aluminum (Al), silver (Ag), copper (Cu), palladium (Pd), or an alloy thereof, but are not limited thereto.

[0090] The plurality of first reflective electrodes RE1 can electrically connect the light emitting element ED to the driving transistor DT. The plurality of first reflective electrodes RE1 can be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole formed in the organic insulating layer 115. The first reflective electrode RE1 can also be electrically connected to the second electrode 125 of the light emitting element ED.

[0091] The plurality of second reflective electrodes RE2 can electrically connect the power supply wiring PL and the light-emitting element ED. The plurality of second reflective electrodes RE2 can be electrically connected to the power supply wiring PL through contact holes formed in the organic insulating layer 115. The plurality of second reflective electrodes RE2 can be electrically connected to the common electrode CE through contact holes in the first planarization layer 116 and the second planarization layer 117. Therefore, the first electrode 124 and the first semiconductor layer 121 of the light-emitting element ED can be electrically connected to the power supply wiring PL through the plurality of second reflective electrodes RE2 and the common electrode CE.

[0092] A light emitting element ED is disposed on the first reflective electrode RE1 in each of the plurality of sub-pixels SP. The plurality of light emitting elements ED are elements that emit light in response to current and may include light emitting elements that emit red light, green light, blue light, etc., and various colors including white light can be realized by combining these light emitting elements. For example, the plurality of light emitting elements ED may be, but are not limited to, LEDs (Light Emitting Diodes) or micro LEDs.

[0093] The plurality of light emitting elements ED are light emitting elements for displaying images to a user viewing the display panel PN from the front surface of the substrate 110. Light emitted from the plurality of light emitting elements ED may travel toward the upper side of the substrate 110. At least a portion of the light emitted from the plurality of light emitting elements ED may be reflected by the plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 and travel toward the upper side of the substrate 110.

[0094] A black matrix BM is disposed between each of the light emitting elements ED on the organic insulating layer 115. The black matrix BM may be disposed to surround the periphery of the light emitting elements ED of the sub-pixels SP. The black matrix BM may shield a portion of light emitted from the light emitting elements ED toward adjacent sub-pixels SP, thereby preventing the light emitted from each of the sub-pixels SP from mixing with each other. The black matrix BM may guide the light emitted from the light emitting elements ED to be extracted toward the upper direction of the substrate 110 only in correspondence with the region of the sub-pixel SP where the light emitting element ED is disposed. The black matrix BM may also shield a portion of light emitted from the light emitting elements ED toward adjacent sub-pixels SP, thereby preventing the light from each of the sub-pixels SP from mixing with each other.

[0095] A first planarization layer 116 and a second planarization layer 117 are disposed on the plurality of light emitting elements ED. The first planarization layer 116 is disposed on the plurality of first reflective electrodes RE1, the plurality of second reflective electrodes RE2, and the plurality of light emitting elements ED, and the second planarization layer 117 is disposed on the first planarization layer 116. The first planarization layer 116 and the second planarization layer 117 are disposed to fill spaces between the black matrices BM to fix and protect the plurality of light emitting elements ED. The first planarization layer 116 and the second planarization layer 117 may be configured as a single layer or multiple layers and may be made of, for example, but not limited to, a photoresist or an acrylic organic material.

[0096] A common electrode CE is disposed on the front surface of the substrate 110 on the second planarization layer 117. The common electrode CE is an electrode for electrically connecting the power supply wiring PL and the plurality of light-emitting elements ED. The common electrode CE may be electrically connected to the plurality of second reflective electrodes RE2 through contact holes in the first planarization layer 116 and the second planarization layer 117. Thus, the common electrode CE may be electrically connected to the power supply wiring PL through the plurality of second reflective electrodes RE2. Furthermore, the common electrode CE may be electrically connected to the first electrodes 124 of the plurality of light-emitting elements ED through the contact holes in the second planarization layer 117.

[0097] The common electrode CE is made of a transparent conductive material and can transmit light emitted from the light emitting element ED. Light emitted from the light emitting element ED below the common electrode CE can pass through the common electrode CE and travel toward the upper side of the substrate 110. For example, the common electrode CE can be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0098] The display device 100 according to an embodiment of the present specification can extract light emitted from the light emitting element ED to the outside of the light emitting element ED, minimizing light that is trapped inside the light emitting element ED and cannot be extracted. A typical light emitting element has a planar shape that is a polygon formed by straight lines, such as a rectangle. In this case, the in-plane incident angle of light incident on the side of the light emitting element must be greater than the total reflection angle of light directed toward the outside of the light emitting element, resulting in a problem of light being trapped and lost without being extracted from inside the light emitting element due to total reflection inside the light emitting element. Therefore, in the light emitting element ED according to an embodiment of the present specification, the planar shapes of the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123 include a linear first side SI1 and a curved second side, and the first side SI1 and the second side SI1 may be plural and arranged alternately. In this case, the first sides SI1 may be arranged opposite each other, and the second sides may be arranged opposite each other. Therefore, since the planar shape of the light emitting device ED is made up of straight lines and curves, the light incident on the light emitting device ED may be reflected at random angles. Therefore, the light emitted from the light emitting device is reflected randomly inside the light emitting device, minimizing the amount of light that is trapped inside the light emitting device and cannot be extracted, thereby improving the external light extraction efficiency.

[0099] Fig. 9 is a cross-sectional view of a subpixel of a display device according to another embodiment of the present specification. The display device 100 in Fig. 9 is substantially the same as that in Fig. 8 except for the reflective layer RL and the plurality of first reflective electrodes RE1a, and therefore a duplicated description will be omitted.

[0100] Referring to FIG. 9, a first planarization layer 116 and a second planarization layer 117 may be disposed to surround the side surfaces of the light emitting element ED.

[0101] The first planarization layer 116 may be disposed on the organic insulating layer 115. The first planarization layer 116 may include an opening 116a in which the light emitting element ED is seated. The first planarization layer 116 may have an inclined surface around the light emitting element ED. The opening 116a may have an inclined surface. The first planarization layer 116 may be configured as a single layer or multiple layers and may be made of, for example, photoresist or an acrylic organic material, but is not limited thereto.

[0102] A first reflective electrode RE1a and a reflective layer RL may be disposed on the first planarization layer 116. The reflective layer RL may be disposed in a portion of the organic insulating layer 115 exposed by the opening 116a, and may be electrically connected to the first electrode 124 of the light-emitting element ED. The reflective layer RL may be disposed on the inclined surface. The reflective layer RL may be disposed from a portion of the organic insulating layer 115 exposed by the opening 116a to the inclined surface and a portion of the first planarization layer 116.

[0103] A first reflective electrode RE1a, which is integrally formed with the reflective layer RL and electrically connects the light emitting element ED to the driving transistor DT, may be included on the first planarization layer 116. The first reflective electrode RE1a may be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole formed in the organic insulating layer 115 and the first planarization layer 116.

[0104] A second reflective electrode RE2 may be disposed on the organic insulating layer 115. The second reflective electrode RE2 may electrically connect the plurality of light-emitting elements ED to the power wiring PL and the driving transistor DT. The second reflective electrode RE2 may electrically connect the light-emitting elements ED to the power wiring PL. The second reflective electrode RE2 may be electrically connected to the power wiring PL through a contact hole formed in the organic insulating layer 115. The second reflective electrode RE2 may be electrically connected to the common electrode CE through contact holes in the first planarization layer 116 and the second planarization layer 117. Therefore, the first electrode 124 and the first semiconductor layer 121 of the light-emitting element ED may be electrically connected to the power wiring PL through the second reflective electrode RE2 and the common electrode CE.

[0105] The first reflective electrode RE1a and the second reflective electrode RE2 can electrically connect the plurality of light-emitting elements ED to the power wiring PL and the driving transistor DT. The reflective layer RL, the first reflective electrode RE1a, and the second reflective electrode RE2 can function as a reflector that reflects light emitted from the plurality of light-emitting elements ED toward the upper side of the substrate 110.

[0106] The reflective layer RL, the first reflective electrode RE1a, and the second reflective electrode RE2 are formed of a conductive material with excellent reflective properties and can reflect light emitted from the light emitting element ED upward. For example, the reflective layers RL, the first reflective electrodes RE1a, and the second reflective electrodes RE2 may be made of a metal material with excellent reflective properties, such as aluminum (Al), silver (Ag), copper (Cu), palladium (Pd), or an alloy thereof, but are not limited thereto. The first reflective electrode RE1a and the second reflective electrode RE2 reflect light emitted from the light emitting element ED upward and may be referred to as a reflective layer.

[0107] A second planarization layer 117 may be disposed on the first planarization layer 116, the reflective layer RL, and the first reflective electrode RE1a. The second planarization layer 117 may be disposed on the first planarization layer 116 to fill the openings 116a of the first planarization layer 116. The first planarization layer 116 and the second planarization layer 117 may be disposed to fill the spaces between the black matrices BM, thereby fixing and protecting the plurality of light emitting elements ED.

[0108] In the display device 200 according to another embodiment of the present specification, the planar shape of the light emitting element ED is made up of straight lines and curves, and the light incident on the inside of the light emitting element ED is reflected at random angles, which minimizes the amount of light that is trapped inside the light emitting element and cannot be extracted, thereby improving the external light extraction efficiency.

[0109] In a display device 200 according to another embodiment of the present specification, a reflective layer RL may be used to extract light emitted toward the side of the light emitting element toward the front of the display device. Light emitted from the light emitting element may be extracted not only in one direction but also toward the side. In this case, the light extracted toward the side of the light emitting element is not extracted toward the front of the display device but is instead trapped inside the display device, resulting in poor light extraction efficiency. Therefore, in a display device 200 according to another embodiment of the present specification, an opening 116a for seating the light emitting element ED may be disposed in the first planarization layer 116, and an inclined surface may be formed in the opening 116a. A reflective layer RL may be disposed on an upper portion of the organic insulating layer 115 exposed by the opening 116a of the first planarization layer 116 and on the inclined surface of the first planarization layer 116. Therefore, the reflective layer RL may be disposed below the light emitting element ED and at a position surrounding the side of the light emitting element ED, allowing light emitted toward the side of the light emitting element ED to be extracted toward the front of the display device 200, thereby improving light extraction efficiency.

[0110] Reference is now made to Figures 10 to 13 for a more detailed description of a display device including a reflective layer surrounding a light emitting element.

[0111] FIG. 10a shows a simulation result of a far-field emission pattern for the light emitting device shown in FIG. 2. FIG. 10b shows a simulation result of a far-field emission pattern for the light emitting device shown in FIG. 3. FIG. 10c shows a simulation result of a far-field emission pattern for the light emitting device shown in FIG. 4. FIG. 11 is a plan view schematically showing the planar shapes of a light emitting device and a reflective layer of a display device according to another embodiment of the present specification. FIG. 12 is a plan view schematically showing another example of the planar shapes of a light emitting device and a reflective layer of a display device according to another embodiment of the present specification. FIG. 13 is a plan view schematically showing yet another example of the planar shapes of a light emitting device and a reflective layer of a display device according to another embodiment of the present specification. For convenience of explanation, FIGS. 11 to 13 only show the light emitting device ED and the reflective layer RL among various components of the display device 200.

[0112] 2 and 10a, the far-field emission pattern of the light-emitting element ED shown in FIG. 2 is such that the amount of light is uniformly spread along the linear shape of the first side SI1, but the amount of light may be concentrated in the direction of an emission azimuth angle φ of 35° to 45° (e.g., 40°) of the curved second side SI2.

[0113] 3 and 10b, the far field emission pattern of the light emitting element ED shown in FIG. 3 is such that the amount of light is uniformly spread along the linear shape of the first side SI1, but the amount of light may be concentrated in the direction of an emission azimuth angle φ of 40° to 50° (e.g., 45°) of the curved second side SI2.

[0114] 4 and 10c, the far-field emission pattern of the light-emitting element ED shown in FIG. 4 is such that the amount of light is uniformly spread along the linear shape of the first side SI1, but the amount of light may be concentrated in the direction of an emission azimuth angle φ of 45° to 55° (e.g., 50°) of the curved second side SI2.

[0115] In a display device 200 according to another embodiment of the present specification, the planar shape of the light emitting element ED is made up of straight lines and curved lines. The first side SI1 of the light emitting element ED has a straight line shape, and the emitted light is uniform along the first side SI1. However, the emitted light is concentrated at a specific angle along the curved second side SI2 of the light emitting element ED. Therefore, when a reflective layer surrounds the light emitting element and has the same shape as the light emitting element and is equally spaced apart along the second side SI2, as in the commonly used reflective layer shape, the emitted light may vary depending on the azimuth angle, resulting in brightness non-uniformity, as shown in Figures 10a to 10c.

[0116] Therefore, referring to Figures 11 to 13, in a display device 200 according to another embodiment of this specification, a notch N is formed in the planar shape of the reflective layer RL surrounding the light-emitting element ED at an azimuthal position where the amount of emitted light is concentrated, thereby dispersing the light in the azimuthal direction, thereby increasing the brightness uniformity and extracting the light.

[0117] In a display device 200 according to another embodiment of the present specification, the planar shape of the reflective layer RL surrounding the light-emitting element ED may include a plurality of third sides SI3, a plurality of fourth sides SI4, and a plurality of fifth sides SI5. When the planar shape of the reflective layer RL includes a plurality of third sides SI3, a plurality of fourth sides SI4, and a plurality of fifth sides SI5, the plurality of third sides SI3 may be positioned opposite each other, and the plurality of fourth sides SI4 may be positioned opposite each other, and in this case, the plurality of fifth sides SI5 may be positioned to connect the plurality of third sides SI3 and the plurality of fourth sides SI4. In this case, the plurality of fifth sides SI5 may be positioned to surround the curved second side SI2 of the light-emitting element ED.

[0118] 10a to 10c, in a display device 200 according to another embodiment of the present disclosure, the amount of light emitted from the light emitting device ED is uniform along the linear first side SI1 and concentrated in a specific direction along the curved second side SI2. For example, even if the amount of light emitted at both ends of the first side SI1 is greater in light intensity than the amount of light emitted at the maximum emission point θ at the position where the light is maximized along the second side SI2, the emission angle of the first side SI1 may be dispersed, resulting in a wide spread of the far field. As a result, the amount of light may be uniformly dispersed in the first side SI1 region even without a notch.

[0119] Therefore, in the display device 200 according to another embodiment of the present specification, the notch N included in the planar shape of the reflective layer RL can be disposed on at least one of the plurality of fifth sides SI5 surrounding the second side SI2 of the light emitting element ED. In the display device 200 according to another embodiment of the present disclosure, the planar shape of the reflective layer RL may be such that the notch N is located on a straight line of the maximum emission azimuth angle (i.e., emission vector) derived from the far-field pattern based on the maximum emission point of the position where light derived from the near-field emission pattern of the light emitting element ED is maximally emitted. Specifically, the notch N may be disposed such that the center of the notch N is located on a straight line of the maximum emission azimuth angle derived from the far-field pattern based on the maximum emission point derived from the near-field emission pattern of the light emitting element ED. For example, the shape of the notch N may include, but is not limited to, a curved groove concave toward the light emitting element ED.

[0120] 2 and 11, the maximum emission point θ derived from the near-field emission pattern of the light emitting device ED shown in FIG. 2 is 0°, and the maximum emission azimuth angle φ derived from the far-field pattern of the second light emitting device ED shown in FIG. 10a is 40°. As shown in FIG. 11, the position of the notch N included in the planar shape of the reflective layer RL may be formed at a position that is linear with the emission azimuth angle φ based on the maximum emission point θ (i.e., a 40° direction based on the 0° direction of the second side SI2 (the center of the second side SI2) at the center of the light emitting device ED). For example, the normal vector of the notch N included in the planar shape of the reflective layer RL may be 180° opposite to the maximum emission azimuth angle φ of the light emitting device ED.

[0121] 3 and 12, the maximum emission point θ derived from the near-field emission pattern of the light emitting device ED shown in Fig. 3 is 45°, and the maximum emission azimuth angle φ derived from the far-field pattern of the second light emitting device ED shown in Fig. 10b is 45°. As shown in Fig. 12, the position of the notch N included in the planar shape of the reflective layer RL may be formed at a position that is linear with the emission azimuth angle φ based on the maximum emission point θ (i.e., in a 45° direction based on the 45° direction of the second side SI2 at the center of the light emitting device ED).

[0122] 4 and 13, the maximum emission point θ derived from the near-field emission pattern of the light emitting device ED shown in Fig. 4 is 48°, and the maximum emission azimuth angle φ derived from the far-field pattern of the second light emitting device ED shown in Fig. 10c is 50°. As shown in Fig. 13, the position of the notch N included in the planar shape of the reflective layer RL may be formed at a position that is linear with the emission azimuth angle φ based on the maximum emission point θ (i.e., in a 50° direction based on the 48° direction of the second side SI2 at the center of the light emitting device ED).

[0123] In a display device 200 according to another embodiment of this specification, the planar shape of the reflective layer RL surrounding the light-emitting element ED is formed so that the notch N is located at an azimuthal position where the amount of emitted light is concentrated, so that the notch N disperses the light in the azimuthal direction in the area where the amount of emitted light is concentrated, thereby increasing the brightness uniformity and enabling the light to be extracted.

[0124] In the display device 200 according to other embodiments of the present specification, the shape and size of the notch N can be used without any restrictions, and the dispersion form and degree of the emitted light amount can be adjusted by adjusting the size and shape of the notch N and the angle of the inclined surface around the light-emitting element ED on which the reflective layer RL is arranged.

[0125] In the display device 200 according to another embodiment of this specification, the shorter the distance between the notch N included in the planar shape of the reflective layer RL and the light-emitting element ED, the more advantageous the light extraction may be, but this is not limited thereto, and the distance can be adjusted taking into account the margin of the transfer process.

[0126] In the display device 200 according to another embodiment of the present specification, the planar shape of the light emitting element ED is made up of straight lines and curves, and the light incident on the inside of the light emitting element ED is reflected at random angles, which minimizes the amount of light that cannot be extracted and is trapped inside the light emitting element, thereby improving the external light extraction efficiency.

[0127] The display device 200 according to another embodiment of the present specification can improve the efficiency of light extraction to the outside by arranging a reflective layer RL to surround the bottom and side of the light-emitting element ED, so that light emitted toward the side of the light-emitting element ED is extracted toward the front of the display device 200.

[0128] In a display device 200 according to another embodiment of the present specification, a notch N is formed in the planar shape of a reflective layer RL surrounding a light emitting element ED at a position in the azimuth direction where the amount of emitted light is concentrated. The notch N disperses light in the azimuth direction in the region where the amount of emitted light is concentrated, thereby improving light extraction efficiency and brightness uniformity.

[0129] 14 is a cross-sectional view of a subpixel of a display device according to another embodiment of the present disclosure. The display device 300 of FIG. 14 is substantially the same as that of FIG. 8 except for the first planarization layer 316 and the second planarization layer 317, and therefore, a redundant description will be omitted.

[0130] 14, a first planarization layer 316 and a second planarization layer 317 are disposed on a plurality of light emitting elements ED. The first planarization layer 316 is disposed on the plurality of light emitting elements ED, and the second planarization layer 317 is disposed on the first planarization layer 316. The first planarization layer 316 and the second planarization layer 317 may be disposed to surround the plurality of light emitting elements ED. The first planarization layer 316 and the second planarization layer 317 may be disposed to fill the spaces between the black matrices BM to fix and protect the plurality of light emitting elements ED. The first planarization layer 316 and the second planarization layer 317 may be configured as a single layer or multiple layers and may be made of, for example, but not limited to, a photoresist or an acrylic organic material.

[0131] At least a portion of the first planarization layer 316 and the second planarization layer 317 may include scattering particles P. The scattering particles P may be dispersed in the first planarization layer 316 and the second planarization layer 317. The scattering particles P may be made of a material that diffuses or scatters light. For example, the scattering particles P may be nanoparticles made of a material containing titanium (Ti). For example, the scattering particles P may be particles having a size on the nanometer (nm) level formed through a sol-gel process, but are not limited thereto.

[0132] A display device 300 according to another embodiment of the present specification may allow light emitted in a lateral direction of a light emitting element to be extracted toward the front surface of the display device. Light emitted from the light emitting element may be extracted not only in one direction but also in a lateral direction. In this case, the light extracted to the lateral direction of the light emitting element may be trapped inside the display device rather than being extracted toward the front surface of the display device, resulting in poor light extraction efficiency. Therefore, a display device 300 according to another embodiment of the present specification may include a first planarization layer 316 and a second planarization layer 317 disposed to surround a plurality of light emitting elements ED. The first planarization layer 316 and the second planarization layer 317 may include scattering particles P made of a material that diffuses or scatters light. Therefore, the first planarization layer 316 and the second planarization layer 317 disposed to surround a plurality of light emitting elements ED include scattering particles P, which allow light emitted in a lateral direction of the light emitting element ED to be extracted toward the front surface of the display device 300, thereby improving light extraction efficiency.

[0133] An embodiment of the present invention can also be described as follows.

[0134] According to an aspect of the present invention, a light-emitting element includes a first semiconductor layer, a second semiconductor layer facing the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer, and the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer include at least one first side that is linear and at least one second side that is curved.

[0135] According to another feature of the present specification, the first semiconductor layer, the second semiconductor layer, and the light emitting layer may have planar shapes in which one end of the first side is connected to one end of the second side.

[0136] According to another feature herein, the second side may be arc-shaped.

[0137] According to another feature of the present specification, the first semiconductor layer, the second semiconductor layer, and the light emitting layer may have a semicircular planar shape.

[0138] According to another feature of the present specification, the first semiconductor layer, the second semiconductor layer, and the light emitting layer may have a planar shape that is a "D" shape, which is a part of a circle cut by a straight line.

[0139] According to another feature of the present specification, the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light emitting layer include a plurality of first sides and a plurality of second sides, and the plurality of first sides may face each other, and the plurality of second sides may face each other.

[0140] According to another feature of the present disclosure, the first and second sides may be arranged alternately.

[0141] According to another feature of the present specification, the first semiconductor layer, the second semiconductor layer, and the light emitting layer may have planar shapes with rounded corner regions.

[0142] According to another feature of the present specification, the first semiconductor layer, the second semiconductor layer, and the light emitting layer may have a planar shape of a Bunimovich stadium.

[0143] According to another feature of the present specification, the first semiconductor layer, the second semiconductor layer, and the light emitting layer may have a planar shape of a Sinai billiard.

[0144] According to another feature of the present specification, the semiconductor device may further include a first electrode disposed on the first semiconductor layer, and a second electrode facing the first electrode and disposed on the second semiconductor layer.

[0145] According to an aspect of the present invention, a display device includes a substrate including a plurality of sub-pixels, a plurality of transistors disposed on the substrate, and a light-emitting element disposed on the substrate in each of the plurality of sub-pixels.

[0146] According to another feature of the present specification, the light-emitting device may further include a planarization layer disposed on the plurality of transistors and surrounding a side surface of the light-emitting element, and a reflective layer disposed on the planarization layer.

[0147] According to another feature of the present specification, a light-emitting element includes a first semiconductor layer, a second semiconductor layer facing the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer, wherein the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer include at least one first side that is linear and at least one second side that is curved, and the planar shape of the reflective layer can include a plurality of third sides, a plurality of fourth sides, and a plurality of fifth sides, wherein the plurality of third sides face each other, the plurality of fourth sides face each other, and the plurality of fifth sides connect the plurality of third sides and the plurality of fourth sides.

[0148] According to another feature of the present specification, a plurality of fifth sides are positioned to surround the second side, and the planar shape of the reflective layer may include a notch disposed on at least one of the plurality of fifth sides and recessed toward the light-emitting element. According to still another feature of the present specification, the light emitting device may further include a planarization layer disposed on the plurality of transistors and surrounding a side surface of the light emitting element, the planarization layer including scattering particles.

[0149] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present specification should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present specification. [Explanation of symbols]

[0150] 100 display device 110 Substrate 121 First semiconductor layer 122 Light-emitting layer 123 Second semiconductor layer

Claims

1. a first semiconductor layer; a second semiconductor layer facing the first semiconductor layer; a light emitting layer between the first semiconductor layer and the second semiconductor layer; Including, the first semiconductor layer, the second semiconductor layer, and the light emitting layer each have a planar shape including at least one first side that is linear and at least one second side that is curved; In each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light emitting layer, one end of the first side is connected to one end of the second side, The light-emitting element, wherein the first semiconductor layer, the second semiconductor layer, and the light-emitting layer each have a planar shape that is a "D" shape formed by cutting a part of a circle with a straight line.

2. The light-emitting element according to claim 1 , wherein the second side is arc-shaped.

3. The light-emitting element according to claim 1 , wherein the first semiconductor layer, the second semiconductor layer, and the light-emitting layer each have a semicircular planar shape.

4. A first semiconductor layer; a second semiconductor layer facing the first semiconductor layer; a light emitting layer between the first semiconductor layer and the second semiconductor layer; Including, the first semiconductor layer, the second semiconductor layer, and the light emitting layer each have a planar shape including at least one first side that is linear and at least one second side that is curved; a planar shape of each of the first semiconductor layer, the second semiconductor layer, and the light emitting layer includes a plurality of the first sides and a plurality of the second sides; The first sides are opposed to each other, and the second sides are opposed to each other. Light-emitting element.

5. The light-emitting element according to claim 4 , wherein the first sides and the second sides are alternately arranged.

6. The light-emitting element according to claim 4 , wherein the first semiconductor layer, the second semiconductor layer, and the light-emitting layer each have a planar shape with rounded corner regions.

7. The light emitting device according to claim 4 , wherein the first semiconductor layer, the second semiconductor layer, and the light emitting layer each have a planar shape resembling a Bunimovich stadium.

8. The light emitting device according to claim 4 , wherein the first semiconductor layer, the second semiconductor layer, and the light emitting layer each have a planar shape of a Sinai billiard.

9. The light emitting element according to claim 1 , further comprising: a first electrode disposed on the first semiconductor layer; and a second electrode facing the first electrode and disposed on the second semiconductor layer.

10. a substrate including a plurality of sub-pixels; a plurality of transistors disposed on the substrate; a light-emitting element disposed on the substrate in each of the plurality of sub-pixels; Including, The light-emitting element is a first semiconductor layer; a second semiconductor layer facing the first semiconductor layer; a light emitting layer between the first semiconductor layer and the second semiconductor layer; Including, the first semiconductor layer, the second semiconductor layer, and the light emitting layer each have a planar shape including at least one first side that is linear and at least one second side that is curved; Display device.

11. a planarization layer disposed on the plurality of transistors and surrounding a side surface of the light-emitting element; a reflective layer disposed on the planarization layer and surrounding the side surfaces of the light-emitting element; The display device of claim 10 further comprising:

12. the planar shape of the reflective layer includes a plurality of third sides, a plurality of fourth sides, and a plurality of fifth sides; The display device according to claim 11 , wherein the third sides are opposite to each other, the fourth sides are opposite to each other, and the fifth sides connect the third sides and the fourth sides.

13. the plurality of fifth sides are positioned so as to surround the second side, The display device according to claim 12 , wherein the planar shape of the reflective layer includes a notch that is disposed on at least one of the plurality of fifth sides and that protrudes toward the light emitting element.

14. a planarization layer disposed on the plurality of transistors and surrounding a side surface of the light-emitting element; The display device of claim 10 , wherein the planarization layer includes scattering particles.

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