Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device is provided with a silicon carbide substrate having a first main surface and a second main surface, the first main surface is provided with a gate trench which is defined by a side surface that penetrates a source region and a body region and reaches a drift region, and a bottom surface that is continuous with the side surface, and extends in a first direction parallel to the first main surface, the silicon carbide substrate is further provided with an electric field relaxation region provided between the bottom surface and the second main surface, extending in a first direction, and having a second conductive type, and a connection region electrically connecting a contact region and the electric field relaxation region, and having a second conductive type, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are on a virtual straight line extending in the first direction, and the contact region has a first region in contact with the connection region on a virtual straight line, and a second region provided at a position sandwiching the source region between the gate trench and the second region, in the second direction perpendicular to the first direction.

Description

[Technical Field]

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority to Japanese Application No. 2020-198539, filed on November 30, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] As one silicon carbide semiconductor device, a trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been disclosed in which contact regions connected to a body region are arranged discontinuously along a gate trench inside a contact hole formed in an interlayer insulating film (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2012-23291 Summary of the Invention

[0005] a source region having the first conductivity type and provided on the body region so as to be spaced from the drift region; and a contact region having the second conductivity type and provided on the body region; and a gate trench provided in the first main surface, the gate trench being defined by a side surface that passes through the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending in a first direction parallel to the first main surface. the silicon carbide substrate further comprises a source electrode connected to the contact region, and the silicon carbide substrate further comprises: an electric field relaxation region provided between the bottom surface and the second main surface, extending in the first direction, and having the second conductivity type; and a connection region, also having the second conductivity type, electrically connecting the contact region and the electric field relaxation region, wherein, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are on an imaginary line extending in the first direction, the connection region is in contact with the electric field relaxation region on the imaginary line, and the contact region has a first region in contact with the connection region on the imaginary line, and a second region provided in a position sandwiching the source region between the gate trench and the source region in a second direction perpendicular to the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a perspective cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a diagram showing the configuration of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a diagram showing a configuration of a first main surface of the silicon carbide semiconductor device according to the embodiment. [Figure 5]FIG. 5 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 4) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a first cross-sectional view illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a fifth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 17] FIG. 17 is a ninth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20]FIG. 20 is a twelfth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 21] FIG. 21 is a thirteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 22] FIG. 22 is a fourteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 23] FIG. 23 is a cross-sectional view (part 15) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 24] FIG. 24 is a sixteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 25] FIG. 25 is a cross-sectional view (part 17) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 26] FIG. 26 is a cross-sectional view (part 18) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 27] FIG. 27 is a 19th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 28] FIG. 28 is a twentieth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 29] FIG. 29 is a 21st cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 30] FIG. 30 is a diagram showing an example of a path of a short-circuit current. [Figure 31] FIG. 31 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Problem to be solved by this disclosure] Conventional MOSFETs with discontinuous contact regions do not provide sufficient short-circuit resistance.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve short-circuit resistance.

[0009] [Effects of this disclosure] According to the present disclosure, it is possible to improve short circuit resistance.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be given the same symbols, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual directions are represented by [], collective directions by <>, individual planes by (), and collective planes by {}. Furthermore, negative indices in crystallography are usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region provided on the body region to be spaced from the drift region and having the first conductivity type; and a contact region provided on the body region and having the second conductivity type, the first main surface including a gate trench defined by a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending in a first direction parallel to the first main surface; and a source electrode connected to the contact region, and the silicon carbide substrate further has: an electric field relaxation region provided between the bottom surface and the second main surface, extending in the first direction, and having the second conductivity type; and a connection region, having the second conductivity type, electrically connecting the contact region and the electric field relaxation region, wherein, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are on an imaginary line extending in the first direction, the connection region is in contact with the electric field relaxation region on the imaginary line, and the contact region has a first region in contact with the connection region on the imaginary line, and a second region provided in a position sandwiching the source region between the gate trench and the source region in a second direction perpendicular to the first direction.

[0013] When the silicon carbide semiconductor device is short-circuited, a portion of the short-circuit current flows from the portion of the source region sandwiched between the gate trench and the second region (the narrowed portion) in the second direction, along the side surface of the gate trench, toward the drift region. When the short-circuit current flows, heat is generated on the second main surface side of the gate trench, and this heat raises the temperature near the first main surface. As a result, the electrical resistance, particularly in the narrowed portion, increases, making it more difficult for the short-circuit current to flow, thereby improving the short-circuit resistance.

[0014] [2] In [1], the gate trenches may be provided in a plurality of positions at a first period so as to overlap with the imaginary line, and the connection region may be provided between the gate trenches adjacent to each other in the first direction when viewed in a plan view from a direction perpendicular to the first main surface. In this case, it is easy to ensure a large connection region and to reduce electrical resistance in the connection region.

[0015] [3] In [2], the first dimension of the second region in the first direction may be 0.20 to 0.50 times the first period, which makes it easy to ensure both an on-state current and an improved short-circuit resistance.

[0016] [4] In any of [1] to [3], when viewed in a plan view from a direction perpendicular to the first main surface, a portion of the source region located between the gate trench and the second region in the second direction may be spaced apart from the source electrode. In this case, direct contact between the source electrode and the narrowed portion of the source region is prevented, and the effect of improving short-circuit resistance due to an increase in electrical resistance of the narrowed portion is easily obtained.

[0017] [5] In any of [1] to [4], when viewed in a plan view from a direction perpendicular to the first main surface, a part of the electric field relaxation region and a part of the second region may overlap. In this case, the path of a short-circuit current is further restricted, and the effect of improving short-circuit resistance due to an increase in electrical resistance of the narrowed portion is easily obtained.

[0018] [6] In any of [1] to [5], the contact region may have the second region on both sides of the gate trench in the second direction, which makes it easier to reduce electrical resistance between the source electrode and the electric field buffer region.

[0019] [7] In any of [1] to [6], the first region may extend in the second direction, which makes it easier to connect the first region to a source electrode.

[0020] [8] In any of [1] to [7], the source electrode may be connected to the first region and the second region, in which case carriers can be easily supplied from the source electrode to the electric field buffer region via the first region and to the body region via the second region.

[0021] [9] In any of [1] to [8], the electric field relaxation region may be spaced apart from the bottom surface of the gate trench, which reduces on-resistance and makes it easier for on-current to flow.

[0022]

[10] In any of [1] to [9], a lower end of the gate trench may be located inside the electric field relaxation region when viewed in a plan view perpendicular to the first main surface, which facilitates relaxation of electric field concentration at the lower end of the gate trench.

[0023]

[11] In

[10] , an upper end of the gate trench may be located inside the electric field relaxation region when viewed in a plan view perpendicular to the first main surface, which makes it easier to relax the electric field concentration at the lower end of the gate trench.

[0024]

[12] In any of [1] to

[11] , the side surface of the gate trench may include a {0-33-8} plane, which allows good mobility to be obtained on the side surface of the gate trench and reduces channel resistance.

[0025] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). FIGS. 1 and 2 are perspective cross-sectional views showing a configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a see-through view of a portion of the internal structure of the silicon carbide semiconductor device. FIG. 3 is a diagram showing a configuration of an interlayer insulating film and a first main surface of the silicon carbide semiconductor device according to an embodiment. FIG. 4 is a diagram showing a configuration of a first main surface of the silicon carbide semiconductor device according to an embodiment. FIGS. 5 to 8 are cross-sectional views showing a configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIGS. 3 and 4. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIGS. 3 and 4. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIGS. 3 and 4. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIGS. 3 and 4.

[0026] 1 to 8 , a MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type (first conductivity type).

[0027] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0028] The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, an electric field reduction region 16, a connection region 17, and a contact region .

[0029] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 mainly includes, for example, a third region 11C, a fourth region 11D, and a fifth region 11E.

[0030] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type (second conductivity type) conductivity. The effective concentration of the p-type impurities in the body region 12 is 5×10 17 cm -3 That's all. The short channel effect (punch-through) can occur when a depletion layer spreads from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. By increasing the effective concentration of p-type impurities in the body region 12, the spread of the depletion layer formed in the channel region can be reduced. The thickness of the body region 12 may be smaller than 0.7 μm, for example. The effective concentration of p-type impurities in the body region 12 may be, for example, 1×10 18 cm -3 That's about it.

[0031] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurities in the source region 13 may be higher than the effective concentration of the p-type impurities in the body region 12. The effective concentration of the n-type impurities in the source region 13 is, for example, 1×10 19 cm -3 That's about it.

[0032] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 constitutes the first main surface 1. The contact region 18 mainly includes, for example, a first region 18A and a second region 18B. The effective concentration of the p-type impurity in the contact region 18 is higher than, for example, the effective concentration of the p-type impurity in the body region 12 and the effective concentration of the p-type impurity in the connection region 17. The contact region 18 penetrates the source region 13 and contacts the body region 12 or the connection region 17. The effective concentration of the p-type impurity in the contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0033] The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 extends through the source region 13 and the body region 12 to reach the drift region 11. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0034] As shown in particular in FIGS. 3 and 4 , when viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 overlaps with an imaginary line L1 extending in a first direction parallel to the first main surface 1. When viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 is on the imaginary line L1. A plurality of gate trenches 5 are provided at regular intervals on the imaginary line L1. For example, a plurality of gate trenches 5 are provided at a first period F1 so as to overlap with the imaginary line L1. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are also provided at regular intervals in a second direction perpendicular to the first direction. The plurality of gate trenches 5 may be provided, for example, in an array.

[0035] The electric field relaxation region 16 contains p-type impurities such as Al and has p-type conductivity. The electric field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2. That is, the electric field relaxation region 16 is spaced apart from the bottom surface 4 of the gate trench 5. Like the gate trench 5, the electric field relaxation region 16 overlaps with the imaginary line L1 when viewed in a plan view perpendicular to the first main surface 1. When viewed in a plan view perpendicular to the first main surface 1, the electric field relaxation region 16 is located on the imaginary line L1. On the imaginary line L1, the electric field relaxation region 16 may be common to multiple gate trenches 5. Furthermore, when viewed in a plan view perpendicular to the first main surface 1, multiple electric field relaxation regions 16 are provided at regular intervals in the second direction. When viewed in a plan view perpendicular to the first main surface 1, a portion of the electric field relaxation region 16 and a portion of the second region 18B may overlap each other. Multiple electric field relaxation regions 16 may be provided in a striped pattern. The effective concentration of the p-type impurity in the electric field relaxation region 16 is, for example, 5×10 17 cm -3 5x10 or more 18 cm -3 The following is the result.

[0036] The fifth region 11E of the drift region 11 is located closer to the second main surface 2 than the electric field relaxation region 16. The fifth region 11E is in contact with the electric field relaxation region 16. The fifth region 11E is located closer to the first main surface 1 than the silicon carbide single crystal substrate 50. The fifth region 11E may be sandwiched between the electric field relaxation region 16 and the silicon carbide single crystal substrate 50. The fifth region 11E may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the fifth region 11E is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 The following is the result.

[0037] The fourth region 11D is closer to the first major surface 1 than the fifth region 11E. The fourth region 11D is continuous with the fifth region 11E. The fourth region 11D is in contact with the electric field relaxation region 16 in a direction parallel to the second major surface 2. The fourth region 11D and the electric field relaxation region 16 may be located on the same plane parallel to the second major surface 2. The effective concentration of n-type impurities in the fourth region 11D may be higher than the effective concentration of n-type impurities in the fifth region 11E. The effective concentration of n-type impurities in the fourth region 11D is, for example, 5×10 16 cm -3 5x10 or more 17 cm -3 The following is the result.

[0038] The third region 11C is located closer to the second major surface 2 than the body region 12 and closer to the first major surface 1 than the electric field relaxation region 16 and the fourth region 11D. The third region 11C is continuous with the fourth region 11D. The third region 11C is sandwiched between the body region 12 and the electric field relaxation region 16 and the fourth region 11D. The third region 11C is in contact with each of the body region 12, the electric field relaxation region 16, and the fourth region 11D. The upper end surface of the third region 11C includes, for example, the bottom surface 4 of the gate trench 5. The effective concentration of n-type impurities in the third region 11C may be lower than the effective concentration of n-type impurities in the fourth region 11D. The effective concentration of n-type impurities in the third region 11C is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 The following is the result.

[0039] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, a silicon dioxide film. Third area 11C The gate insulating film 81 is in contact with the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0040] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

[0041] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0042] The interlayer insulating film 83, like the gate trench 5 and the electric field reduction region 16, overlaps with the imaginary line L1 when viewed in a plan view from a direction perpendicular to the first main surface 1. On the imaginary line L1, the interlayer insulating film 83 may be provided commonly to a plurality of gate trenches 5. When viewed in a plan view from a direction perpendicular to the first main surface 1, contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. When viewed in a plan view from a direction perpendicular to the first main surface 1, the contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in the first direction. The source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 90.

[0043] 3 and 4 , the first region 18A of the contact region 18 extends in the second direction between adjacent gate trenches 5 in the first direction and intersects with the imaginary line L1. A portion of the first region 18A is covered with an interlayer insulating film 83 and a barrier metal film 84 between adjacent gate trenches 5 in the first direction, and the gate insulating film 81 and the gate electrode 82 may be sandwiched between the first region 18A and the interlayer insulating film 83 in the thickness direction. Another portion of the first region 18A is exposed from the interlayer insulating film 83 through the contact hole 90 between two adjacent imaginary lines L1 in the second direction.

[0044] The second region 18B is exposed from the interlayer insulating film 83 through the contact hole 90. The second region 18B is provided between adjacent gate trenches 5 in the second direction. The second region 18B is provided on both sides of the gate trench 5 in the second direction. A part (narrowed portion) of the source region 13 is sandwiched between the gate trench 5 and the second region 18B in the second direction. For example, the second region 18B may be provided away from the first region 18A in the first direction and near the middle of the adjacent first regions 18A in the first direction. The source region 13 is located between the first region 18A and the second region 18B. In other words, when viewed in a plan view from a direction perpendicular to the first main surface 1, the second region 18B is surrounded by the source region 13 provided between adjacent gate trenches 5 in the second direction.

[0045] 3 , the first region 18A, the second region 18B, and the source region 13 are exposed from the interlayer insulating film 83 through the contact hole 90. A portion (narrowed portion) of the source region 13 sandwiched between the gate trench 5 and the second region 18B is covered with the interlayer insulating film 83. That is, when viewed in a plan view from a direction perpendicular to the first main surface 1, the narrowed portion of the source region 13 is separated from the source electrode 60.

[0046] The connection region 17 contains p-type impurities such as Al and has p-type conductivity. The connection region 17 electrically connects the first region 18A of the contact region 18 and the electric field relaxation region 16. The connection region 17 is in contact with the electric field relaxation region 16 on the virtual line L1. The connection region 17 may extend in the second direction, similar to the first region 18A. The connection region 17 may be provided between adjacent gate trenches 5 in the first direction when viewed in a plan view perpendicular to the first main surface 1. The connection region 17 is in contact with the first region 18A or the body region 12. The connection region 17 may be in contact with both the body region 12 and the first region 18A. The connection region 17 may be in direct contact with the first region 18A. The body region 12 may be in direct contact with the first region 18A, and the connection region 17 may be in direct contact with the body region 12. The connection region 17 is located between the electric field relaxation region 16 and the first region 18A in the direction perpendicular to the second main surface 2. The connection region 17 is located closer to the second main surface 2 than the first region 18A. The connection region 17 is located closer to the first main surface 1 than the electric field relaxation region 16. For example, the connection region 17 may be in contact with both the first region 18A and the electric field relaxation region 16. If the connection region 17 is located between the electric field relaxation region 16 and the first region 18A in the direction perpendicular to the second main surface 2 and in contact with both the first region 18A and the electric field relaxation region 16, the series resistance between the first region 18A and the electric field relaxation region 16 is reduced. The effective concentration of the p-type impurity in the connection region 17 may be approximately the same as the effective concentration of the p-type impurity in the electric field relaxation region 16. The effective concentration of the p-type impurity in the connection region 17 may be, for example, 5×10 17 cm -3 5x10 or more 18 cm -3 The following is the result.

[0047] If the plurality of gate trenches 5 aligned in the first direction are considered to be one gate trench assembly, the gate trench assembly can be considered to be divided into a plurality of gate trenches 5 by the first region 18A and the connection region 17.

[0048] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with both the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0049] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the first region 18A and the second region 18B of the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is in ohmic contact with the source region 13 and the first region 18A and the second region 18B of the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, Al.

[0050] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

[0051] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing NiSi, for example. The drain electrode 70 may also be made of a material containing Ti, Al, and Si. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0052] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and fifth region 11E. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in fifth region 11E.

[0053] The effective concentration of impurities in each of the impurity regions can be measured, for example, by using a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS).

[0054] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. FIGS. 9 to 29 are cross-sectional views showing a method for manufacturing the MOSFET 100 according to the embodiment. FIGS. 9 to 12 show changes common to the cross section shown in FIG. 5 and the cross section shown in FIG. 6. FIGS. 13, 15, 18, 20, 22, 24, 26, and 28 show changes in the cross section shown in FIG. 6. FIGS. 14, 16, 17, 19, 21, 23, 25, 27, and 29 show changes in the cross section shown in FIG. 5.

[0055] First, as shown in FIG. 9, a step of preparing a silicon carbide single crystal substrate 50 is performed. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by a chemical vapor deposition (CVD) method using, for example, a mixed gas of silane (SiH) and propane (C3H8) as a source gas and hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0056] Next, as also shown in FIG. 9 , a step of forming first epitaxial layer 21 is performed. For example, first epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into first epitaxial layer 21. First epitaxial layer 21 has n-type conductivity. The effective concentration of the n-type impurity in first epitaxial layer 21 may be lower than the effective concentration of the n-type impurity in the buffer layer.

[0057] 10, a step of forming the electric field relaxation region 16 is performed. For example, a mask layer (not shown) having an opening is formed on the region where the electric field relaxation region 16 is to be formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the first epitaxial layer 21. As a result, the electric field relaxation region 16 is formed.

[0058] 11 , a step of forming fourth region 11D is performed. For example, a mask layer (not shown) having openings is formed in the region where fourth region 11D is to be formed, that is, on the side of electric field relaxation region 16 in the direction parallel to second main surface 2. Next, n-type impurity ions capable of imparting n-type conductivity, such as nitrogen, are implanted into first epitaxial layer 21. This forms fourth region 11D. A portion of first epitaxial layer 21 closer to silicon carbide single crystal substrate 50 than electric field relaxation region 16 and a portion closer to silicon carbide single crystal substrate 50 than fourth region 11D constitute fifth region 11E. The effective concentration of n-type impurities in fourth region 11D is higher than the effective concentration of n-type impurities in fifth region 11E.

[0059] Next, as shown in FIG. 12 , a step of forming a second epitaxial layer 22 is performed. For example, the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into the second epitaxial layer 22. The second epitaxial layer 22 has n-type conductivity. The thickness of the second epitaxial layer 22 is, for example, 0.8 μm or more and 1.2 μm or less. For example, the effective concentration of the n-type impurity in the second epitaxial layer 22 is set lower than the effective concentration of the n-type impurity in the fourth region 11D.

[0060] 13 and 14, a step of forming the connection region 17 is performed. For example, a mask layer (not shown) having an opening on the region where the connection region 17 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer 22. This forms the connection region 17.

[0061] 13 and 14, a step of forming the body region 12 is performed. P-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer 22. As a result, the body region 12 is formed.

[0062] 13 and 14, a step of forming the source region 13 is performed. For example, n-type impurity ions such as phosphorus that can impart n-type conductivity are implanted into the entire surface of the second epitaxial layer 22. As a result, the source region 13 is formed.

[0063] 15 and 16, a step of forming the contact region 18 is performed. For example, a mask layer (not shown) having an opening on the region where the contact region 18 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer 22. This forms the contact region 18. The contact region 18 includes a first region 18A and a second region 18B.

[0064] Next, activation annealing is performed to activate the impurity ions implanted into the silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0065] Next, as shown in FIG. 17, a step of forming a gate trench 5 is performed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1 including the source region 13 and the contact region 18. Using the mask layer, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF) or a mixed gas of SF and oxygen (O) can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0066] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask layer formed on the first main surface 1 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 800°C or higher and 900°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0067] By the thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is formed by the source region 13, the body region 12, and the drift region 11. The bottom surface 4 is formed by the drift region 11. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0068] Next, as shown in FIGS. 18 and 19 , a step of forming a gate insulating film 81 is performed. For example, by thermally oxidizing the silicon carbide substrate 10, the gate insulating film 81 is formed in contact with the source region 13, the body region 12, the drift region 11, the electric field relaxation region 16, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4. Note that, when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a portion of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. For this reason, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0069] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is maintained, for example, under conditions of 1100°C or higher and 1400°C or lower for about one hour. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0070] 20 and 21, a step of forming a gate electrode 82 is performed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.

[0071] 22 and 23, a step of forming an interlayer insulating film 83 is performed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0072] Next, as shown in FIGS. 24 and 25 , steps of forming a barrier metal film 84, a contact electrode 61, and a drain electrode 70 are performed. For example, etching is performed to form contact holes 90 in the interlayer insulating film 83 and the gate insulating film 81, thereby exposing the source region 13 and the contact region 18 through the contact holes 90 from the interlayer insulating film 83 and the gate insulating film 81. Next, a barrier metal film 84 is formed to cover the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is made of a material containing TiN, for example. The barrier metal film 84 is formed by film formation using a sputtering method and reactive ion etching (RIE), for example. Next, a metal film (not shown) for the contact electrode 61 is formed on the first main surface 1, in contact with the portions of the source region 13 and the contact region 18 exposed through the contact holes 90. The metal film for the contact electrode 61 is formed by a sputtering method, for example. The metal film for the contact electrode 61 is made of a material containing Ni, for example. Next, a metal film (not shown) for the drain electrode 70 is formed in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of, for example, a material containing Ni.

[0073] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are maintained at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 and at least a portion of the metal film for the drain electrode 70 reacts with silicon contained in the silicon carbide substrate 10 and becomes silicide. This forms the contact electrode 61 that forms an ohmic junction with the source region 13 and the contact region 18, and the drain electrode 70 that forms an ohmic junction with the silicon carbide single crystal substrate 50. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

[0074] 26 and 27, a step of forming a source wiring 62 is performed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed by film formation using a sputtering method and RIE, for example. The source wiring 62 is made of a material containing aluminum, for example. In this way, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0075] Next, as shown in FIGS. 28 and 29, a step of forming a passivation film 85 is performed. Specifically, the passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide. The passivation film 85 is formed by, for example, a coating method. The passivation film 85 may also be formed by a plasma CVD method.

[0076] In this way, the MOSFET 100 according to the embodiment is completed.

[0077] Next, the effects of the MOSFET according to this embodiment will be described. Fig. 30 is a diagram showing an example of a path of a short-circuit current.

[0078] 30 , in the MOSFET 100 according to this embodiment, when a short circuit occurs, part of the short-circuit current 9 flows from a portion of the source region 13 that is sandwiched between the gate trench 5 and the second region 18B in the second direction (the narrowed portion) along the side surface 3 of the gate trench 5 toward the drift region 11. When the short-circuit current 9 flows, heat is generated on the second main surface 2 side of the gate trench 5, and this heat increases the temperature in the vicinity of the first main surface 1. As a result, the electrical resistance increases, particularly in the narrowed portion, making it more difficult for the short-circuit current 9 to flow, thereby improving the short-circuit resistance.

[0079] A plurality of gate trenches 5 are provided at a first period F1 so as to overlap with the virtual line L1, and a connection region 17 is provided between adjacent gate trenches 5 in the first direction when viewed in a plan view from a direction perpendicular to the first main surface 1. Although the connection region 17 may be provided so as to overlap with the gate trench 5 when viewed in a plan view from a direction perpendicular to the first main surface 1, the volume of the connection region 17 can be increased and the electrical resistance in the connection region 17 can be reduced when the connection region 17 is provided between the gate trenches 5. Furthermore, if the source region 13, the body region 12, and the drift region 11 are present between the end of the gate trench 5 in the first direction and the first region 18A, a drain current can also flow in the region between the gate trench 5 and the first region 18A in the first direction.

[0080] Furthermore, when viewed in a plane from a direction perpendicular to the first main surface 1, the narrowed portion of the source region 13 is separated from the source electrode 60, which prevents direct contact between the source electrode 60 and the narrowed portion, making it easier to obtain the effect of improving short-circuit resistance due to an increase in the electrical resistance of the narrowed portion.

[0081] It is preferable that a portion of electric field relaxation region 16 and a portion of second region 18B overlap when viewed in a plan view perpendicular to first main surface 1. When a portion of electric field relaxation region 16 and a portion of second region 18B overlap, the path of the short-circuit current is further limited. This makes it easier to obtain the effect of improving short-circuit resistance by increasing the electrical resistance of the narrowed portion.

[0082] The second region 18B is provided on both sides of the gate trench 5 in the second direction. Therefore, the electrical resistance between the source electrode 60 and the electric field relaxation region 16 can be reduced compared to when the second region 18B is provided on only one side of the gate trench 5 in the second direction.

[0083] Since the first region 18A extends in the second direction, it is easy to connect the source electrode 60 and the first region 18A through the contact hole 90.

[0084] The source electrode 60 is connected to the first region 18A. Furthermore, the first region 18A and the electric field relaxation region 16 are electrically connected by the connection region 17. Therefore, the electric field relaxation region 16 is electrically connected to the source electrode 60. This allows carriers to be supplied from the source electrode 60 to the electric field relaxation region 16, thereby reducing feedback capacitance. The reduction in feedback capacitance reduces switching loss and improves switching speed. Furthermore, the source electrode 60 is connected to the second region 18B, and the second region 18B is connected to the body region 12. This allows carriers to be supplied from the source electrode 60 to the body region 12.

[0085] Since the electric field relaxation region 16 is located away from the bottom surface 4 of the gate trench 5, an on-current can easily flow between the source electrode 60 and the drain electrode 70.

[0086] When viewed in a plan view from a direction perpendicular to the first main surface 1, the lower end of the gate trench 5 is preferably located inside the electric field relaxation region 16. This is because it is easier to alleviate electric field concentration at the lower end of the gate trench 5. When viewed in a plan view from a direction perpendicular to the first main surface 1, it is more preferable that the upper end of the gate trench 5 is located inside the electric field relaxation region 16. This is because it is easier to alleviate electric field concentration at the lower end of the gate trench 5.

[0087] The first dimension W1 in the first direction of the second region 18B is preferably 0.20 to 0.50 times the first period F1. If the first dimension W1 is less than 0.20 times the first period F1, the narrowed portion may be small, making it difficult to improve short-circuit resistance. On the other hand, if the first dimension W1 is more than 0.50 times the first period F1, the source region 13 may be small, resulting in high on-resistance. The first dimension W1 is more preferably 0.22 to 0.48 times the first period F1, and even more preferably 0.25 to 0.45 times the first period F1.

[0088] [Variations] Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 31 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to the modified example of the embodiment. Fig. 31 shows a cross section similar to the cross section taken along line VV in Figs. 3 and 4.

[0089] 31 , in a MOSFET 110 according to the modification, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 may be 90°. The other configurations are the same as those of the embodiment.

[0090] Even with such a modification, the same effects as those of the embodiment can be obtained.

[0091] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0092] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 9 Short-circuit current 10 Silicon carbide substrate 11 Drift Region 11C Third area 11D 4th area 11E 5th area 12 Body Region 13 Source Region 16 Electric field relaxation region 17 Connection Area 18 Contact Area 18A 1st area 18B 2nd area 21 First epitaxial layer 22 Second epitaxial layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation Film 90 Contact Holes 100 MOSFET 110 MOSFET L1 Virtual line

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; a contact region provided on the body region and having the second conductivity type; and a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, and extending in a first direction parallel to the first main surface; a source electrode connected to the source region and the contact region; The silicon carbide substrate is an electric field relaxation region provided between the bottom surface and the second main surface, extending in the first direction, and having the second conductivity type; a connection region that electrically connects the contact region and the electric field reduction region and has the second conductivity type; and When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relief region are located on a virtual line extending in the first direction, the connection region is in contact with the electric field relaxation region on the virtual straight line, The contact region is a first region that is in contact with the connection region on the virtual straight line, that is provided between the gate trenches that are adjacent to each other in the first direction, and that is spaced apart from the gate trenches; a second region provided at a position sandwiching the source region between the second region and the gate trench in a second direction perpendicular to the first direction; and a silicon carbide semiconductor device, wherein a portion of the source region is located between the first region and the gate trench;

2. a plurality of the gate trenches are provided so as to overlap with the virtual straight line at a first period; The silicon carbide semiconductor device according to claim 1 , wherein the connection region is provided between the gate trenches adjacent to each other in the first direction when viewed in a plan view perpendicular to the first main surface.

3. The silicon carbide semiconductor device according to claim 2 , wherein a first dimension in said first direction of said second region is not less than 0.20 times and not more than 0.50 times said first period.

4. When viewed in a plan view from a direction perpendicular to the first main surface, The silicon carbide semiconductor device according to claim 1 , wherein a portion of the source region located between the gate trench and the second region in the second direction is spaced apart from the source electrode.

5. When viewed in a plan view from a direction perpendicular to the first main surface, The silicon carbide semiconductor device according to claim 1 , wherein a portion of the electric field relaxation region and a portion of the second region overlap with each other.

6. The silicon carbide semiconductor device according to claim 1 , wherein the contact region has the second region on both sides of the gate trench in the second direction.

7. The silicon carbide semiconductor device according to claim 1 , wherein the first region extends in the second direction.

8. The silicon carbide semiconductor device according to claim 1 , wherein the source electrode is connected to the first region and the second region.

9. The silicon carbide semiconductor device according to claim 1 , wherein the electric field relaxation region is spaced apart from the bottom surface of the gate trench.

10. When viewed in a plan view from a direction perpendicular to the first main surface, The silicon carbide semiconductor device according to claim 1 , wherein a lower end of the gate trench is located inside the electric field relaxation region.

11. When viewed in a plan view from a direction perpendicular to the first main surface, The silicon carbide semiconductor device according to claim 10 , wherein an upper end of the gate trench is located inside the electric field relaxation region.

12. 12. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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