Semiconductor Devices

Abstract

To provide a semiconductor device that facilitates extraction of a carrier when turned off.SOLUTION: A semiconductor device 100 comprises: a trench part including a gate trench part 40 and a dummy trench part 30; a drift region 18 of a first conductivity type; a base region 14 of a second conductivity type; a well region 13 of the second conductivity type provided from a top surface of a semiconductor substrate 10 to a posiiton deeper than the position of a p-n junction formed at a lower end of the base region; a collector region 22 of the second conductivity type provided on the reverse surface of the semiconductor substrate; and a reverse surface-side region 20 of the first conductivity type provided on the reverse surface of the semiconductor substrate. The reverse surface region is provided extending from the position of a side wall of one trench part to the position of a side wall of the other trench part below a mesa part 71 as a region of the semiconductor substrate sandwiched between the two trench parts, and the mesa part adjoins at least one dummy trench part.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, power semiconductor elements such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Document 1). In semiconductor elements such as IGBTs, the on-voltage can be reduced by accumulating carriers such as holes in the drift region. Patent Document 1: JP 2015-72950 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is desirable to facilitate the extraction of carriers when turning off a semiconductor device. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device provided with trenches including gate trenches and dummy trenches. The semiconductor device may include a first-conductivity-type drift region provided within a semiconductor substrate, a second-conductivity-type base region provided between an upper surface of the semiconductor substrate and the drift region in the depth direction, a second-conductivity-type well region provided from the upper surface of the semiconductor substrate to a depth deeper than a p-n junction formed at a lower end of the base region, a second-conductivity-type collector region provided on a rear surface of the semiconductor substrate, and a first-conductivity-type lower-surface-side region provided on the rear surface of the semiconductor substrate. Below a first mesa portion, which is a region of the semiconductor substrate sandwiched between two trenches, the lower-surface-side region may extend from one of the trenches to the other in the arrangement direction of the trenches. The first mesa portion may be adjacent to at least one of the dummy trenches. The semiconductor device may further include an accumulation region of the first conductivity type, which is provided between the base region and the drift region in the depth direction and has a doping concentration higher than that of the drift region, and at least a portion of the accumulation region may be provided below a lower end of the trench portion.

[0005] A second aspect of the present invention provides a semiconductor device provided with trench portions including gate trench portions and dummy trench portions. The semiconductor device may include: a drift region of a first conductivity type provided within a semiconductor substrate; a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region in the depth direction; an accumulation region of the first conductivity type provided between the base region and the drift region in the depth direction and having a doping concentration higher than that of the drift region; a well region of the second conductivity type provided from the upper surface of the semiconductor substrate to at least a depth position where the accumulation region is formed; a collector region of the second conductivity type provided on a back surface of the semiconductor substrate; and a lower surface region of the first conductivity type provided on the back surface of the semiconductor substrate. Below a first mesa portion, which is a region of the semiconductor substrate sandwiched between the two trench portions, the lower surface region may extend from one of the trench portions to the other of the trench portions in the arrangement direction of the trench portions. The first mesa portion may be adjacent to at least one of the dummy trench portions.

[0006] In any of the above semiconductor devices, the accumulation region may be provided in multiple stages in the depth direction.

[0007] In any of the above semiconductor devices, the first mesa portion may be a dummy mesa portion that is a region of the semiconductor substrate sandwiched between two of the dummy trench portions.

[0008] A third aspect of the present invention provides a semiconductor device provided with trench portions including a gate trench portion and a dummy trench portion. The semiconductor device may include: a first conductivity type drift region provided within a semiconductor substrate; a second conductivity type base region provided between an upper surface of the semiconductor substrate and the drift region in the depth direction; a second conductivity type well region provided from the upper surface of the semiconductor substrate to a depth deeper than a p-n junction formed at a lower end of the base region; a second conductivity type collector region provided on a back surface of the semiconductor substrate; and a first conductivity type lower surface region provided on the back surface of the semiconductor substrate. The lower surface region may be provided below a dummy mesa portion, which is a region of the semiconductor substrate sandwiched between two of the dummy trench portions.

[0009] In any of the above semiconductor devices, the collector region may be provided at least partially below the dummy mesa portion.

[0010] In any of the semiconductor devices described above, the trench portion may include a longitudinal portion extending in an extension direction, and the lower surface side region and the collector region may be alternately arranged along the extension direction below the dummy mesa portion.

[0011] In any of the above semiconductor devices, the collector region may be provided in at least a portion below a second mesa portion adjacent to at least one of the gate trench portions, within the region of the semiconductor substrate sandwiched between the trench portions.

[0012] In any of the above semiconductor devices, the concentration peak of the well region may be located at a position shallower than the lower end position of the trench portion.

[0013] In any of the above semiconductor devices, the well region may have a first concentration peak at a position deeper than the base region, and the first concentration peak may be higher than the concentration peak of the base region.

[0014] In any of the above semiconductor devices, the well region may have a first concentration peak at a position deeper than the base region, and the first concentration peak may be lower than the concentration peak of the base region.

[0015] In any of the above semiconductor devices, the base region may have a depth of 0.5 μm to 5.0 μm, and the well region may have a depth of 2.0 μm to 10 μm.

[0016] In any of the above semiconductor devices, the semiconductor device may be a semiconductor chip including a transistor that is an IGBT or a MOSFET.

[0017] The above summary of the invention does not list all of the features of the present invention. Subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a diagram showing an example of a cross section aa in FIG. [Figure 2B] FIG. 2 is a diagram showing an example of a cross section aa in FIG. [Figure 2C] FIG. 2 is a diagram showing an example of a cross section aa in FIG. [Figure 2D] 2B is an example of a distribution map of doping concentration when cutting the cc cross section and the dd cross section of FIG. 2A. [Figure 2E] 2B is another example of a distribution map of doping concentrations when cutting the cc cross section and the dd cross section of FIG. 2A. [Figure 3] 10 is a diagram showing another example of the top surface of the semiconductor device 100. FIG. [Figure 4A] FIG. 4 is a diagram showing an example of a cross section aa in FIG. 3. [Figure 4B] FIG. 4 is a diagram showing an example of a cross section aa in FIG. 3. [Figure 4C]4C is an example of a distribution map of doping concentration when cutting the cc cross section and the dd cross section of FIG. 4B. [Figure 4D] 4C is another example of a distribution map of doping concentrations when cutting the cc cross section and the dd cross section of FIG. 4B. [Figure 4E] FIG. 4 is a diagram showing an example of a cross section aa in FIG. 3. [Figure 5] 10 is a diagram showing another example of the top surface of the semiconductor device 100. FIG. [Figure 6] FIG. 6 is a diagram showing an example of a cross section aa in FIG. 5. [Figure 7] FIG. 6 is a diagram showing another example of the aa cross section in FIG. [Figure 8] FIG. 6 is a diagram showing another example of the aa cross section in FIG. [Figure 9] FIG. 4 is a diagram showing another example of the aa cross section in FIG. [Figure 10] FIG. 4 is a diagram showing another example of the aa cross section in FIG. [Figure 11] FIG. 2 is an enlarged cross-sectional view of the vicinity of a first well region 13. [Figure 12] 12 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. [Figure 13] 12 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. [Figure 14] 10A and 10B are diagrams showing other examples of the dummy trench portion 30 and the gate trench portion 40. FIG. [Figure 15] 10 is a diagram showing another example of the first well region 13. FIG. [Figure 16] 10 is a diagram showing another example of the aa cross section of the semiconductor device 100. FIG. [Figure 17] FIG. 4 is a diagram showing an example of the bb cross section shown in FIG. 3. [Figure 18] FIG. 2 is a view partially illustrating the top surface of a semiconductor device 200 according to another embodiment of the present invention. [Figure 19] FIG. 19 is a diagram showing an example of a cross section aa in FIG. 18. [Figure 20] FIG. 19 is a diagram showing another example of the aa cross section in FIG. [Figure 21] 10 is a diagram showing an example of the arrangement of the emitter region 12 and the contact region 15 on the upper surface of the first mesa portion 71-1 and the second mesa portion 71-2. FIG. [Figure 22] 10 is a diagram showing another example of the arrangement of the emitter regions 12 and the contact regions 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. FIG. [Figure 23] 10 is a diagram showing another example of the arrangement of the emitter regions 12 and the contact regions 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. FIG. [Figure 24] FIG. 2 is a diagram showing an example of the arrangement of the storage region 16. [Figure 25] 2A to 2C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which a semiconductor device is attached to a substrate or the like when mounted. In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The depth direction of the semiconductor substrate is the Z-axis. In this example, the orthogonal coordinate system is a so-called right-handed system.

[0021] Although the terms "emitter" and "collector" are used in this specification, the semiconductor device is not limited to an IGBT. The "source" and "drain" of a transistor such as a MOSFET may also be included in the scope of the terms "emitter" and "collector" in this specification.

[0022] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities. When comparing doping concentrations between regions in this specification, the peak concentration in each region may be used.

[0023] In this specification, the term "same" may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0024] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip including transistors such as IGBTs. In FIG. 1, the top surface of the chip around the edge portion is shown, and other regions are omitted.

[0025] 1 shows an active region of the semiconductor substrate of the semiconductor device 100, but the semiconductor device 100 may have an edge termination surrounding the active region. The active region refers to the region through which current flows when the semiconductor device 100 is controlled to an on-state. The edge termination relieves electric field concentration on the upper surface side of the semiconductor substrate. The edge termination may have a structure such as a guard ring, a field plate, a resurf, or a combination of these.

[0026] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a first well region 13, and a second well region 11, which are provided inside a semiconductor substrate. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate electrode 46, which are provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate electrode 46 are provided separately from each other.

[0027] An interlayer insulating film is provided between the emitter electrode 52 and the gate electrode 46 and the upper surface of the semiconductor substrate, but is not shown in Fig. 1. In this example, contact holes 54, 55, and 56 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0028] The emitter electrode 52 contacts the emitter region 12, contact region 15, base region 14, and first well region 13 on the upper surface of the semiconductor substrate through a contact hole 54. In this example, the contact holes 54 are provided between the respective trench portions. The emitter electrode 52 also connects to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 57 made of a conductive material such as impurity-doped polysilicon may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 57 is provided on the upper surface of the semiconductor substrate, with an insulating film such as a thermal oxide film sandwiched between them. In this example, the contact hole 56 is located at the tip of the dummy trench portion 30 in the X-axis direction.

[0029] The gate electrode 46 contacts the gate wiring 45 through the contact hole 55. The gate wiring 45 is formed of impurity-doped polysilicon or the like. An insulating film such as a thermal oxide film is provided between the gate wiring 45 and the semiconductor substrate. The gate wiring 45 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate wiring 45 is not connected to the dummy conductive portion in the dummy trench portion 30. In this example, the gate wiring 45 is provided from below the contact hole 55 to the tip portion 43 of the gate trench portion 40. At the tip portion 43 of the gate trench portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate and contacts the gate wiring 45.

[0030] The emitter electrode 52 and the gate electrode 46 are formed of a material containing metal. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0031] One or more gate trenches 40 and one or more dummy trenches 30 are arranged at predetermined intervals along a predetermined arrangement direction (short-side direction) on the upper surface of the semiconductor substrate, which is the Y-axis direction in FIG.

[0032] The gate trench portion 40 in this example may have two extension portions 41 extending linearly along an extension direction perpendicular to the arrangement direction (the longitudinal direction of the trench, in this example, the X-axis direction), and a tip portion 43 connecting the two extension portions 41 at their tips. At least a portion of the tip portion 43 is preferably formed in a curved shape on the upper surface of the semiconductor substrate. By connecting the tips of the two extension portions 41 of the gate trench portion 40 at the tip portion 43, electric field concentration at the end of the extension portion 41 can be alleviated. In this specification, the two extension portions 41 connected at the tip portion 43 may be treated as two gate trench portions 40.

[0033] One or more dummy trench portions 30 are provided between the extension portions 41 of each gate trench portion 40. Similar to the gate trench portion 40, the dummy trench portion 30 may have a tip portion 33 connecting the tips of the two extension portions 31. In this example, a dummy trench portion 30 having two extension portions 31 and a tip portion 33 is provided between the extension portions 41 of each gate trench portion 40. In other examples, the dummy trench portion 30 may be linear and not have a tip portion 33. The dummy trench portion 30 is provided in a position that does not overlap with the gate wiring 45. In this specification, two extension portions 31 connected by the tip portion 33 may be treated as two dummy trench portions 30.

[0034] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the first well region 13, the second well region 11, the emitter region 12, the base region 14, and the contact region 15. The second well region 11 is provided within a predetermined range away from the longitudinal end of the contact hole 54 in the direction toward the gate electrode 46. The diffusion depth of the second well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 46 side are provided in the second well region 11. The ends and the bottom of the tip portion of the dummy trench portion 30 in the extension direction may be covered by the second well region 11.

[0035] In this example, the region of the semiconductor substrate sandwiched between the trench portions is referred to as a mesa portion 71. However, the region of the semiconductor substrate sandwiched between two dummy trench portions 30 (or two extension portions 31) is referred to as a dummy mesa portion 72. The mesa portion 71 and the dummy mesa portion 72 are regions of the semiconductor substrate sandwiched between the trench portions that are above the deepest bottom of the trench portions.

[0036] A base region 14 is provided in the mesa portion 71. The second well region 11 is of the second conductivity type. The base region 14 is of P- type, which has a lower doping concentration than the second well region 11, and the second well region 11 is of P+ type.

[0037] A P+ type contact region 15 having a doping concentration higher than that of the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 71. The second well region 11 is provided away from the contact region 15 in the active region that is located at the end furthest in the extension direction of the trench portion, in the direction of the gate electrode 46. In addition, an N+ type emitter region 12 having a doping concentration higher than that of the semiconductor substrate is selectively formed on the upper surface of the base region 14.

[0038] The contact regions 15 and the emitter regions 12 are each provided from one adjacent trench portion to the other adjacent trench portion in the Y-axis direction. The contact regions 15 and the emitter regions 12 are provided alternately along the extension direction of the trench portions (the X-axis direction) so as to be exposed on the upper surface of the semiconductor substrate. The contact regions 15 and the emitter regions 12 may be provided on the upper surface of the mesa portion 71 in regions sandwiched between base regions 14 exposed at both ends in the X-axis direction.

[0039] In another example, the contact region 15 and the emitter region 12 may be provided in a stripe pattern along the extension direction (X-axis direction) in the mesa portion 71. For example, the emitter region 12 is provided in a region adjacent to the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0040] The dummy mesa portion 72 is provided with a first well region 13 of the second conductivity type having a doping concentration higher than that of the base region 14. In this example, the first well region 13 is of P+ type. The doping concentration of the first well region 13 may be the same as or different from that of the second well region 11. The doping concentration of the first well region 13 may be five or more times, or even ten or more times, the doping concentration of the base region 14.

[0041] The first well region 13 is provided and exposed on the upper surface of the dummy mesa portion 72. In this example, the first well region 13 is provided in a range facing the emitter region 12 and the contact region 15 of the adjacent mesa portion 71 in the Y-axis direction. The first well region 13 is provided continuously in the Y-axis direction on the upper surface of the dummy mesa portion 72 from a position where it contacts one dummy trench portion 30 to a position where it contacts the other dummy trench portion 30. The first well region 13 may be provided continuously in a region sandwiched between the base regions 14 exposed at both ends in the X-axis direction on the upper surface of the dummy mesa portion 72.

[0042] The contact hole 54 provided in the mesa portion 71 is provided above the contact region 15 and the emitter region 12. The contact hole 54 provided in the dummy mesa portion 72 is provided above the first well region 13. The contact hole 54 is not provided in the regions corresponding to the base region 14 and the second well region 11. An emitter region may not be provided on the upper surface of the dummy mesa portion 72. The contact region 15 may be provided on the upper surface of the dummy mesa portion 72 at least in the region where the contact hole 54 is formed.

[0043] FIG. 2A is a diagram showing an example of the a-a cross section in FIG. 1. The a-a cross section in this example is a YZ plane passing through the emitter region 12. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 58. The interlayer insulating film 26 is silicate glass doped with impurities such as boron and phosphorus. The interlayer insulating film 26 is selectively formed on the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the interlayer insulating film 26. The collector electrode 58 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 58 may be provided over the entire lower surface 23 of the semiconductor substrate 10.

[0044] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0045] An N-type drift region 18 is provided inside the semiconductor substrate 10. The drift region 18 in this cross section is a region of the semiconductor substrate 10 that remains without the emitter region 12, the base region 14, the first well region 13, the buffer region 20, and the collector region 22 being formed therein.

[0046] In a region of the semiconductor substrate 10 adjacent to one of the gate trench portions 40, a P-type base region is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. In this example, a P-type base region is provided in each mesa portion 71. The base region 14 may be formed by implanting P-type impurities such as boron from the upper surface of the semiconductor substrate 10.

[0047] In the mesa portion 71, an N+ type emitter region 12 is provided on the upper surface of the base region 14. The emitter region 12 may be formed by implanting N type impurities such as phosphorus or arsenic from the upper surface of the semiconductor substrate 10.

[0048] In a region of the semiconductor substrate 10 adjacent to any one of the dummy trench portions 30, a first well region 13 is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. The first well region 13 is provided from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the lower end of the dummy trench portion 30. In the cross section shown in FIG. 2A , the first well region 13 is provided in the entire dummy mesa portion 72 and in a region below the dummy mesa portion 72.

[0049] The lower end of the first well region 13 may be determined based on the doping concentration distribution in the depth direction (Z-axis direction) of the first well region 13 and the drift region 18. In this specification, the doping concentration refers to the concentration of impurities (dopants) that have become donors or acceptors. The lower end of the first well region 13 may be determined as the depth position at which the distribution of the difference in concentration between donors and acceptors (net doping concentration), measured by a spreading resistance (SR) method or the like, becomes a minimum.

[0050] The gate trench portion 40 is formed from the upper surface 21 of the semiconductor substrate 10 to the interior of the semiconductor substrate 10, and is in contact with the emitter region 12 and the base region 14 at its sidewall. The gate trench portion 40 of this example is not in contact with the first well region 13. The gate trench portion 40 of this example is provided from the upper surface 21 of the semiconductor substrate 10, penetrating through the emitter region 12 and the base region 14.

[0051] The dummy trench portion 30 is formed from the upper surface 21 of the semiconductor substrate 10 to the interior of the semiconductor substrate 10, and its sidewalls are in contact with the first well region 13. Of the sidewalls of the dummy trench portion 30, the sidewall facing the gate trench portion 40 may be in contact with the emitter region 12 and the base region 14. The gate trench portion 40 and the dummy trench portion 30 may be provided up to the same depth position Z1 in the Z-axis direction.

[0052] In this example, the bottom of the gate trench portion 40 is located within the drift region 18. The bottom of the dummy trench portion 30 may be located within the drift region 18, or may be covered by the first well region 13. Note that the trench portion penetrating each doping region is not limited to being manufactured in the order of forming the doping region and then the trench portion. A trench portion penetrating a doping region may also be formed in which the doping region is formed between the trench portions after the trench portions are formed.

[0053] The buffer region 20 is formed on the lower surface side of the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22. The P+ type collector region 22 is formed on the lower surface side of the buffer region 20.

[0054] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is covered by the gate insulating film 42 inside the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0055] The gate conductive portion 44 includes a region facing at least the adjacent base region 14 in the depth direction, with the gate insulating film 42 sandwiched therebetween. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0056] The dummy trench portion 30 of this example has a dummy insulating film 32 and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench portion 30 and is covered by the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44. The dummy trench portion 30 in the cross section is covered by the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0057] The width of the mesa portion 71 and the width of the dummy mesa portion 72 may be equal. The width of the mesa portion 71 is typically 1.0 μm, and may be 0.1 μm or more and 3.0 μm or less. The width W of the gate trench portion GT and the width W of the dummy trench portion 30 DTThe widths C of the mesa portion 71 and D of the dummy mesa portion 72 may be equal to each other or may be different from each other. In this example, they are equal to each other. Furthermore, the width C of the mesa portion 71 may be equal to the width D of the dummy mesa portion 72.

[0058] The width of the contact hole 54 in the Y-axis direction may be equal between the mesa portion 71 and the dummy mesa portion 72. The width of the contact hole 54 is typically 0.6 μm, and may be 0.05 μm or more and 2.0 μm or less, provided that it does not exceed the mesa width or the dummy mesa width.

[0059] The provision of the dummy trenches 30 can enhance the carrier accumulation effect, promote conductivity modulation, and reduce the on-state voltage. In addition, the switching speed of the semiconductor device 100 can be adjusted by adjusting the ratio of the dummy trenches 30 to the gate trenches 40.

[0060] When the semiconductor device 100 is turned off, carriers accumulated near the bottom of the trench in the drift region 18 are extracted to the emitter electrode 52 via the second conductivity type region. If the speed at which the carriers are extracted when the semiconductor device 100 is turned off is slow compared to the concentration of the accumulated carriers, the withstand voltage of the semiconductor device 100 will decrease. The carrier extraction speed refers to the amount of carriers, such as holes, extracted from the drift region 18 to the emitter electrode 52 or the like per unit time when the semiconductor device 100 is turned off.

[0061] In the semiconductor device 100, by providing the first well region 13 formed deeper than the dummy trench portion 30, carriers such as holes accumulated near the bottom of the trench can be efficiently extracted. This makes it easy to reduce the on-voltage of the semiconductor device 100 while maintaining the withstand voltage of the semiconductor device 100.

[0062] 2B is a diagram showing an example of the aa cross section in FIG. 1. In the semiconductor device 100 of this example, the contact width of the contact for connecting to the semiconductor substrate 10 is different from that in FIG. 2A. In this example, the contact width B of the contact formed on the first well region 13 is different from the contact width A of the contact formed on the emitter region 12. In this example, the contact width B may be larger or smaller than the contact width A. In this example, the contact width B is larger than the contact width A. In other words, by making the contact width B between the dummy trench portions 30 larger than the contact width A between the dummy trench portion 30 and the gate trench portion 40, the turn-off resistance of the semiconductor device 100 can be improved.

[0063] The ratio (A / B) of contact width A to contact width B may be 0.2 or more and 2.0 or less. When contact width B is larger than contact width A, the ratio (A / B) may be 0.2 or more and less than 1.0, or may be 0.4 or more and 0.7 or less. On the other hand, when contact width B is smaller than contact width A, the ratio (A / B) may be greater than 1.0 and 2.0 or less, or may be 1.3 or more and 1.7 or less.

[0064] 2C is a diagram showing an example of the cross section aa in FIG. 1. The semiconductor device 100 of this example differs from the case of FIG. 2A in that the width of the dummy mesa portion 72 in the Y-axis direction is different from the width of the mesa portion 71 in the Y-axis direction. In this example, the width D of the dummy mesa portion 72 is different from the width C of the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40. The width D of the dummy mesa portion 72 of this example may be larger than the width C of the mesa portion 71. By making the width D of the dummy mesa portion 72 larger than the width C of the other mesa portions 71, the turn-off resistance of the semiconductor device 100 can be improved.

[0065] The ratio (D / C) of the width C of the mesa portion 71 to the width D of the dummy mesa portion 72 may be greater than 0.2 and less than 5.0. When the width D of the dummy mesa portion 72 is smaller than the width C of the mesa portion 71, the ratio (D / C) may be greater than 0.2 and less than 1.0, or may be greater than 0.4 and less than 0.7. On the other hand, when the width D of the dummy mesa portion 72 is greater than the width C of the mesa portion 71, the ratio (D / C) may be greater than 1.0 and less than 5.0, or may be greater than 2.0 and less than 4.0.

[0066] 2D is an example of a distribution diagram of the doping concentration when cutting the cc cross section and the dd cross section of FIG. 2A. In the cc cross section, the emitter region 12, the base region 14, and the drift region 18 are arranged in this order from the top surface side of the semiconductor substrate 10. In the dd cross section, the doping concentration distribution of the first well region 13 may be a Gaussian distribution from the top surface of the semiconductor substrate 10. The Gaussian distribution is a profile when a dopant introduced into the top surface of the semiconductor substrate 10 diffuses by thermal diffusion.

[0067] The depth of the pn junction between the base region 14 and the drift region 18 from the upper surface, i.e., the depth of the base region 14, is deeper than the lower end position Z1 of the trench portion. On the other hand, the depth of the pn junction between the first well region 13 and the drift region 18, i.e., the depth of the first well region 13, may be deeper than the lower end position Z1 of the trench portion. The depth of the base region 14 is typically 3.0 μm and may be 0.5 μm or more and 5.0 μm or less. The depth of the first well region 13 is typically 7.0 μm and may be 2.0 μm or more and 10 μm or less.

[0068] FIG. 2E is another example of a doping concentration distribution diagram when cutting the cc cross section and the dd cross section of FIG. 2A. The doping concentration distribution in the cc cross section in this example is the same as the doping concentration distribution in the cc cross section in FIG. 2D. In this example, the doping concentration distribution in the dd cross section is different from that in FIG. 2D. In this example, the first well region 13 has four peaks, namely, first well region 13-1 to first well region 13-4. For example, in the dd cross section, the doping concentration distribution in first well region 13 consists of a first stage that reduces contact resistance, a second stage with a doping concentration distribution substantially the same as that in base region 14, a third stage with a concentration peak located deeper than base region 14, and a fourth stage with a concentration peak located even deeper than the third stage.

[0069] The number and depth of peak positions in first well region 13 are not limited to this example. The fourth step of first well region 13 contacts drift region 18 and has a pn junction. The minimum concentration in the valley between each concentration peak may be higher than the doping concentration of drift region 18. The peak concentrations of the third and fourth steps of first well region 13 in FIG. 2E may be higher than the peak concentration of base region 14, or may be lower than that of base region 14.

[0070] The third peak position may be deeper than the position of the pn junction between the base region 14 and the drift region 18. The fourth peak position may be shallower than the bottom end position Z1 of the trench portion.

[0071] 3 is a diagram showing another example of the top surface of the semiconductor device 100. In addition to the configuration of the semiconductor device 100 described in FIGS. 1 and 2A, the semiconductor device 100 of this example further includes an accumulation region 16. The accumulation region 16 is a region of the first conductivity type that has a higher doping concentration than the drift region 18. The accumulation region 16 of this example is of N+ type.

[0072] The accumulation region 16 is not exposed on the upper surface of the semiconductor substrate 10. The accumulation region 16 may be formed between the drift region 18 and the base region 14. In Fig. 3, the region in which the accumulation region 16 is provided in the XY plane parallel to the upper surface 21 of the semiconductor substrate 10 is indicated by a dashed line. In this example, a plurality of accumulation regions 16 separated from each other are provided in that plane.

[0073] An accumulation region 16 is provided in at least a portion of the mesa portion 71 sandwiched between two trench portions, at least one of which is a gate trench portion 40. In this example, the accumulation region 16 is provided at least below the emitter region 12. The accumulation region 16 may also be provided below the contact region 15. In this example, the accumulation region 16 is provided over the entire mesa portion 71 in the width direction (Y-axis direction). The accumulation region 16 does not have to be provided below the base region 14 exposed on the upper surface of the mesa portion 71. In contrast, the dummy mesa portion 72 does not have an accumulation region 16 with a doping concentration higher than that of the base region 14.

[0074] 4A is a diagram showing an example of the aa cross section in FIG. 3. The aa cross section in this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 of this example further includes an accumulation region 16 in addition to the configuration of the semiconductor device 100 shown in FIG. 2A. The accumulation region 16 is provided between the base region 14 and the drift region 18 in each mesa portion 71. The accumulation region 16 of this example is provided in each mesa portion 71 from a region adjacent to one trench portion to a region adjacent to the other trench portion.

[0075] The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. For example, the accumulation region 16 may be a region between the drift region 18 and the base region 14 that has a doping concentration that is 10 times or more the average doping concentration of the drift region 18. The doping concentration of the accumulation region 16 may be 50 times or more, or even 100 times or more, the doping concentration of the drift region 18. The accumulation region 16 may be formed by implanting N-type impurities such as phosphorus or protons from the upper surface 21 of the semiconductor substrate 10.

[0076] By providing the accumulation region 16, the concentration of carriers accumulated below the accumulation region 16 can be further increased. This makes it possible to reduce the on-voltage of the semiconductor device 100. Furthermore, by providing the first well region 13, the carriers accumulated by the accumulation region 16 can be efficiently extracted. This makes it possible to maintain the withstand capability of the semiconductor device 100 even when the accumulation region 16 is provided.

[0077] 4B is a diagram showing an example of a cross section taken along line aa in FIG. 3. The semiconductor device 100 of this example differs from the case of FIG. 4A in that it has an accumulation region 16 in the dummy mesa portion 72. The accumulation region 16 of this example includes an accumulation region 16-1 formed in the mesa portion 71 and an accumulation region 16-2 formed in the dummy mesa portion 72. The accumulation region 16-1 and the accumulation region 16-2 may be formed simultaneously by the same process. Alternatively, the accumulation region 16-1 and the accumulation region 16-2 may be formed by different processes with different dopant concentrations.

[0078] The accumulation region 16-2 is formed in the dummy mesa portion 72, sandwiched between the dummy trench portions 30. That is, the upper and lower ends of the accumulation region 16-2 are provided in contact with the first well region 13. The accumulation region 16-2 is a region of the first conductivity type that has a higher doping concentration than the drift region 18. By providing the accumulation region 16-2 in the dummy mesa portion 72, the semiconductor device 100 of this example can suppress the extraction of carriers via the P-type inversion layer at the bottom of the dummy trench portion 30 during turn-on, thereby reducing turn-on loss.

[0079] 4C is an example of a distribution diagram of the doping concentration when cutting the cc cross section and the dd cross section of FIG. 4B. In the cc cross section, the emitter region 12, the base region 14, and the drift region 18 are arranged in this order from the top surface side of the semiconductor substrate 10. In the dd cross section, the doping concentration distribution of the first well region 13 may be a Gaussian distribution from the top surface of the semiconductor substrate 10. The Gaussian distribution is a profile when a dopant introduced into the top surface of the semiconductor substrate 10 diffuses by thermal diffusion.

[0080] The depth from the upper surface of the semiconductor substrate 10 to the peak position of the doping concentration of the accumulation region 16 may be deeper than the depth from the peak position to the bottom end position Z1 of the trench portion. The peak position of the accumulation region 16 is typically 4.0 μm, and may be 1.0 μm or more and 6.0 μm or less.

[0081] FIG. 4D shows another example of the doping concentration distribution diagram when the cc cross section and the dd cross section of FIG. 4B are cut. The doping concentration distribution in the dd cross section is different from that in FIG. 2D. The first well region 13 in this example has three peaks: the first well region 13-1 to the first well region 13-3. For example, in the dd cross section, the doping concentration distribution is composed of a first stage of the first well region 13 that reduces contact resistance, a second stage of the first well region 13 that has a distribution similar to that of the base region 14, an accumulation region 16-2, and a third stage of the first well region 13 that has a concentration peak deeper than the accumulation region 16-2. The peak concentration in the third stage of the first well region 13 in FIG. 4D may be higher or lower than that of the accumulation region 16-2. In this example, the peak concentration in the third stage of the first well region 13 is higher than that of the accumulation region 16-2.

[0082] FIG. 4E is a diagram showing an example of the aa cross section in FIG. 3. The semiconductor device 100 of this example differs from the semiconductor device of FIG. 4A in that the thickness d1 of the dummy insulating film 32 and the thickness d2 of the gate insulating film 42 are different. The thickness d1 of the dummy insulating film 32 of this example is thicker than the thickness d2 of the gate insulating film 42. This suppresses carrier extraction via the P-type inversion layer at the bottom of the dummy trench portion 30 during turn-on, thereby reducing turn-on loss. The thickness d2 is typically 0.1 μm and may be 0.05 μm to 0.3 μm. The thickness d1 is typically 0.2 μm and may be 0.1 μm to 1.0 μm thicker than the thickness d2. This suppresses carrier extraction via the P-type inversion layer at the bottom of the dummy trench portion 30 during turn-on, thereby reducing turn-on loss.

[0083] In this example, the dummy trench portion 30 and the gate trench portion 40 have the same width in the Y-axis direction, and the thickness d1 of the dummy insulating film 32 is thicker, so the width in the Y-axis direction of the dummy conductive portion 34 is smaller than the width in the Y-axis direction of the gate conductive portion 44. Note that the width in the Y-axis direction of the dummy trench portion 30 may be made larger than the width in the Y-axis direction of the gate trench portion 40, thereby making the thickness d1 of the dummy insulating film 32 larger than the thickness d2 of the gate insulating film 42.

[0084] 5 is a diagram showing another example of the top surface of the semiconductor device 100. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in FIGS. 3 and 4A in the arrangement of the accumulation region 16. The other configuration is the same as that of the semiconductor device 100 shown in FIGS. 3 and 4A.

[0085] In this example, the accumulation region 16 is not provided in a region adjacent to at least one of the trench portions in at least some of the mesa portions 71. In the example of Fig. 5, the accumulation region 16 is in contact with the gate trench portion 40 in each mesa portion 71, but is not in contact with the dummy trench portion 30. In addition, the accumulation region 16 is not provided in the dummy mesa portion 72.

[0086] 6 is a diagram showing an example of the aa cross section in FIG. 5. The aa cross section in this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 in this example differs from the configuration of the semiconductor device 100 shown in FIG. 4A in the arrangement of the accumulation region 16. The other configurations are the same as those of the semiconductor device 100 shown in FIG. 4A.

[0087] The accumulation region 16 in this example is provided in a region adjacent to the gate trench portion 40 inside the semiconductor substrate 10. The accumulation region 16 may be provided in contact with the base region 14, or may be provided apart from the base region 14. However, it is preferable that the accumulation region 16 be provided inside the mesa portion 71 (i.e., the region from the upper surface 21 of the semiconductor substrate 10 to the lower end of the trench portion).

[0088] In each mesa portion 71, a region 17, which is adjacent to the dummy trench portion 30 inside the semiconductor substrate 10 and is at the same depth as the accumulation region 16, has a lower N-type doping concentration than the accumulation region 16. In this example, the region 17 has the same doping concentration as the drift region 18. The accumulation region 16 may be provided in a region that is equal to or less than half the width of the mesa portion 71 in the Y-axis direction, or may be provided in a region that is equal to or more than half the width of the mesa portion 71.

[0089] With this structure, carriers can be accumulated near the bottom end of the gate trench portion 40, and at turn-off, carriers such as holes can be extracted from the mesa portion 71. For example, carriers that pass near the dummy trench portion 30 pass through the base region 14 and the contact region 15 and are extracted to the emitter electrode 52.

[0090] Fig. 7 is a diagram showing another example of the cross section taken along the line aa in Fig. 5. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in Fig. 6 in the arrangement of the accumulation region 16 in the Z-axis direction. The other configurations are the same as those of the semiconductor device 100 shown in Fig. 6.

[0091] The accumulation region 16 in this example is disposed apart from the base region 14. A drift region 18 may be provided between the accumulation region 16 and the base region 14. The accumulation region 16 is in contact with the gate trench portion 40, but is not in contact with the dummy trench portion 30. A portion of the accumulation region 16 may be provided below the lower end of the gate trench portion 40.

[0092] In this example, the bottom of the gate trench 40 has a curved shape that is convex downward. The accumulation region 16 may cover part of the curved surface at the bottom of the gate trench 40. Even with this structure, carriers can be accumulated near the bottom end of the gate trench 40, and carriers such as holes can also be extracted from the mesa portion 71 during turn-off.

[0093] Fig. 8 is a diagram showing another example of the cross section taken along the line aa in Fig. 5. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in Fig. 6 in the arrangement of the accumulation region 16. The other configurations are the same as those of the semiconductor device 100 shown in Fig. 6.

[0094] The semiconductor device 100 of this example has a first accumulation region 16-1 and a second accumulation region 16-2 in each mesa portion 71. The first accumulation region 16-1 is the same as the accumulation region 16 shown in Figure 6, and the second accumulation region 16-2 is the same as the accumulation region 16 shown in Figure 7.

[0095] The first accumulation region 16-1 and the second accumulation region 16-2 may have the same doping concentration or different doping concentrations. When viewed from the Z-axis direction, at least a portion of the first accumulation region 16-1 and at least a portion of the second accumulation region 16-2 are arranged to overlap each other.

[0096] The first accumulation region 16-1 and the second accumulation region 16-2 may be provided apart from each other in the Z-axis direction. In this case, the drift region 18 may be provided between the first accumulation region 16-1 and the second accumulation region 16-2. The first accumulation region 16-1 and the second accumulation region 16-2 may be provided continuously in the Z-axis direction. In this case, the doping concentration distribution in the depth direction of the first accumulation region 16-1 and the second accumulation region 16-2 may have a peak within each of the first accumulation region 16-1 and the second accumulation region 16-2. The doping concentration between the peaks is greater than the doping concentration of the drift region 18.

[0097] With this structure, carriers can be accumulated near the bottom end of the gate trench portion 40, and carriers such as holes can also be extracted from the mesa portion 71 when the device is turned off.

[0098] Fig. 9 is a diagram showing another example of the cross section taken along the line aa in Fig. 3. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in Fig. 4A in the arrangement of the accumulation region 16. The other configurations are the same as those of the semiconductor device 100 shown in Fig. 4A.

[0099] The semiconductor device 100 of this example has a first accumulation region 16-1 and a second accumulation region 16-2 in each mesa portion 71. The first accumulation region 16-1 is the same as the accumulation region 16 shown in FIG. 4A. The second accumulation region 16-2 is provided below the first accumulation region 16-1 inside the mesa portion 71. The second accumulation region 16-2 may have the same doping concentration as the first accumulation region 16-1, or may have a different doping concentration. The semiconductor device 100 may have accumulation regions 16 provided in three or more stages in the depth direction inside the mesa portion 71.

[0100] Like the first accumulation region 16-1, the second accumulation region 16-2 is provided in the Y-axis direction from a region adjacent to one trench portion to a region adjacent to the other trench portion. The first accumulation region 16-1 and the second accumulation region 16-2 may be provided separately in the Z-axis direction or may be provided continuously. This structure can further enhance the carrier accumulation effect.

[0101] Furthermore, by providing the accumulation region 16 in multiple stages in the depth direction, when the base region 14 is turned on, the electron current that passes through the channel formed near the interface with the gate trench portion 40 is more likely to flow near the center of the mesa portion 71 in the Y-axis direction.

[0102] The main current in the initial stage of turn-on is electron current, not hole current. The initial stage refers to the period from just before the gate voltage Vge reaches the threshold voltage until the Miller period, during which Vge remains constant at approximately the threshold voltage. When Vge approaches the threshold voltage, the channel begins to open, and electrons begin to be injected into the drift region 18.

[0103] Electrons flowing downward from the channel may flow once in the first accumulation region 16-1 in the arrangement direction (the Y-axis direction, or the direction from the vicinity of the gate trench portion 40 toward the center of the mesa portion 71). If the second accumulation region 16-2 is not provided, in the drift region 18 below the first accumulation region 16-1, an electron accumulation layer has already been formed near the gate trench portion 40 (the threshold voltage at which the electron accumulation layer is formed in the N-type region is much lower than the threshold voltage of the inversion layer in the P-type region), and therefore the impedance is lower than that of the drift region 18. Therefore, the electron current mainly flows near the gate trench portion 40.

[0104] When the electrons reach the collector region 22 on the back surface, holes start to be injected from the collector region 22 into the buffer region 20 and the drift region 18. As a result, holes are accumulated near the bottom end of the trench portion. As an example, holes accumulate from near the bottom end of the gate trench portion 40 to the side of the dummy trench portion 30 below the first accumulation region 16 at a rate of 1.0×10 16 [cm -3 ] exists in the order of

[0105] Holes gather at the bottom end of the gate trench 40 and the bottom end of the dummy trench 30. In particular, because the dummy conductive portion 34 has the same potential as the emitter electrode 52, a hole inversion layer is likely to form on the sidewall of the dummy trench 30. Holes injected from the collector region 22 gather near this hole inversion layer. Holes are continuously distributed from the dummy trench 30 to the bottom end of the gate trench 40. Due to this hole distribution, a large displacement current may flow near the bottom end of the gate trench 40 when the device is turned on.

[0106] The semiconductor device 100 of this example further includes a second accumulation region 16-2. In this case, the impedance for electron current is lower along a path that flows directly from the first accumulation region 16-1 to the second accumulation region 16-2 than along a path that flows from near the center of the first accumulation region 16-1 back to near the gate trench portion 40 and then to the second accumulation region 16-2.

[0107] Of the areas below each accumulation region, holes tend to accumulate in the high-hole concentration region adjacent to the gate trench portion 40. In addition, the electron current flows near the center of the mesa portion 71 rather than near the gate trench portion 40, which promotes the accumulation of holes in the high-hole concentration region. This promotes the flow of the electron current near the center of the mesa portion 71.

[0108] By providing the accumulation region 16 in multiple stages in the depth direction, the electron current is more likely to flow downward near the center of the mesa portion 71. When the electron current flows near the center of the mesa portion 71, the hole distribution near the bottom of the mesa portion 71 is split by the electron current near the center of the mesa portion 71. Therefore, holes on the dummy trench portion 30 side of the electron current path do not flow toward the gate trench portion 40 side. This splitting of the hole distribution at the center of the mesa portion 71 suppresses the accumulation of holes at the bottom end of the gate trench portion 40. This reduces the displacement current. Since the displacement current can be reduced, the charging of the gate conductive portion 44 is also reduced, and the instantaneous increase in the gate electrode Vge is also suppressed. This also reduces the voltage decrease rate (dV / dt) of the collector-emitter voltage.

[0109] Figure 10 is a diagram showing another example of the aa cross section in Figure 3. The semiconductor device 100 of this example differs from the semiconductor device 100 of any of the aspects described with reference to Figures 1 to 9 in the shape of the first well region 13. The other configuration is the same as any of the semiconductor devices 100 described with reference to Figures 1 to 9. Figure 10 shows an example in which the shape of the first well region 13 in the semiconductor device 100 shown in Figure 9 is changed.

[0110] In this example, the first well region 13 has a recessed portion 73 in the YZ plane whose width in the Y-axis direction is minimal. The first well region 13 may also have a plurality of recessed portions 73 at different positions in the Z-axis direction. At least one recessed portion 73 may be provided below the lower end of the dummy trench portion 30. The first well region 13 has doping concentration peaks above and below the recessed portion 73.

[0111] In this example, the first well region 13 can be formed by implanting P-type impurities multiple times at different implantation depths. By varying the implantation depth of the impurities, the first well region 13 can be formed to a deeper position. In other words, it is easy to form a first well region 13 that has a relatively small width in the Y-axis direction and a large depth in the Z-axis direction. By forming the first well region 13 deep, carriers such as holes can be easily extracted.

[0112] For example, the first well region 13 may be formed 20% or more deeper than the dummy trench portion 30, or 50% or more deeper. The difference in depth between the first well region 13 and the dummy trench portion 30 may be larger than the width of the dummy mesa portion 72 in the Y-axis direction. The first well region 13 may be formed deeper than the second well region 11.

[0113] 11 is an enlarged cross-sectional view of the vicinity of the first well region 13. In this example, the dummy trench portion 30 has a first dummy sidewall 38, a second dummy sidewall 37, and a bottom 35 in the YZ plane. The first dummy sidewall 38 contacts the first well region 13. The second dummy sidewall 37 is a sidewall on the opposite side to the first dummy sidewall 38 in the YZ plane.

[0114] The first well region 13 in this example covers at least a portion of the bottom 35 of the dummy trench portion 30. The bottom 35 in this example has a curved shape that protrudes downward from the lower ends of the first dummy sidewall 38 and the second dummy sidewall 37. A lower end position Z2 of the first well region 13 is located lower than a lower end position Z1 of the dummy trench portion 30.

[0115] Of the sidewalls of the dummy trench portion 30, a region having the same slope as the portion in contact with the base region 14 may be referred to as the second dummy sidewall 37. The first dummy sidewall 38 is a sidewall on the opposite side to the second dummy sidewall 37 and has the same depth range as the second dummy sidewall 37. The bottom 35 may refer to a region having a smaller slope with respect to the top surface 21 of the semiconductor substrate 10 than the first dummy sidewall 38 and the second dummy sidewall 37. By covering at least a portion of the bottom 35 of the dummy trench portion 30 with the first well region 13, the carrier extraction speed can be further improved.

[0116] The first well region 13 covers at least a part of the region between the center Y1 in the width direction (Y-axis direction) and the first dummy sidewall 38 at the bottom 35 of the dummy trench portion 30. In other words, the position Y2 of the end 36 in the Y-axis direction of the first well region 13 covering the bottom 35 is located between the center Y1 of the bottom 35 and the first dummy sidewall 38. With this structure, the carrier extraction speed can be further improved.

[0117] 12 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. 11. In this example, the first well region 13 covers the bottom 35 from the center Y1 of the bottom 35 toward the second dummy sidewall 37. In other words, the position Y2 of the end 36 of the first well region 13 is located between the center Y1 of the bottom 35 and the second dummy sidewall 37. This structure can further improve the carrier extraction speed.

[0118] 13 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. 11. The first well region 13 in this example covers the entire bottom 35. In other words, the position Y2 of the end 36 of the first well region 13 is located closer to the center of the mesa portion 71 than the second dummy sidewall 37. In this case, the first well region 13 is extended to below the mesa portion 71. This structure can further improve the carrier extraction speed.

[0119] In the trench portion in contact with the mesa portion 71, the length from the trench portion sidewall on the mesa portion 71 side to Y2 may be shorter or longer than the length from the trench portion sidewall to Y1. In this example, in the trench portion in contact with the mesa portion 71, the length from the trench portion sidewall on the mesa portion 71 side to Y2 is shorter than the length from the trench portion sidewall to Y1.

[0120] 14 is a diagram showing another example of the dummy trench portion 30 and the gate trench portion 40. The dummy trench portion 30 in this example is formed deeper than the gate trench portion 40 when viewed from the upper surface 21 of the semiconductor substrate 10. In other words, the bottom end position Z3 of the dummy trench portion 30 is located lower than the bottom end position Z1 of the gate trench portion 40. When viewed from the upper surface 21 of the semiconductor substrate 10, the dummy trench portion 30 may be formed 10% or more deeper than the gate trench portion 40, or may be formed 20% or more deeper. This structure can further improve the carrier extraction speed.

[0121] 15 is a diagram showing another example of the first well region 13. In the semiconductor device 100 of this example, three or more dummy trench portions 30 are arranged continuously in the Y-axis direction. The three or more dummy trench portions 30 may be sandwiched between gate trench portions 40 in the Y-axis direction. In this example, the first well regions 13 provided in two or more dummy mesa portions 72 are connected to each other.

[0122] In this example, of the multiple dummy trenches 30 arranged continuously, the entire bottoms of the dummy trenches 30 other than the dummy trenches 30 arranged at both ends in the Y-axis direction may be covered by the first well region 13. The relationship between the dummy trenches 30 arranged at both ends in the Y-axis direction and the first well region 13 is the same as that described in any of the embodiments with reference to Figures 1 to 14. This structure can further improve the carrier extraction speed.

[0123] 16 is a diagram showing another example of the aa cross section of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 described with reference to FIGS. 1 to 15 in that it further includes a lower surface side region 28. The other configurations are the same as those of the semiconductor device 100 of any of the aspects described with reference to FIGS.

[0124] The lower side region 28 is provided at the same depth as the collector region 22 in at least a portion of a region below the dummy mesa portion 72. The lower side region 28 is an N-type region. The lower side region 28 may have a higher doping concentration than the drift region 18. The lower side region 28 may also have a higher doping concentration than the buffer region 20.

[0125] The lower surface side region 28 may have the same width in the Y-axis direction as the dummy mesa portion 72. The lower surface side region 28 may have a width in the Y-axis direction that is smaller or larger than that of the dummy mesa portion 72. The lower surface side region 28 may also be formed below the dummy trench portion 30, or may also be formed in a portion of the region below the mesa portion 71.

[0126] Providing the lower-surface-side region 28 can suppress the accumulation of second-conductivity-type carriers below the dummy mesa portion 72. The carrier concentration below the dummy mesa portion 72 has little effect on the on-voltage of the semiconductor device 100. Therefore, the on-voltage can be reduced while facilitating carrier extraction during turn-off and other times.

[0127] Fig. 17 is a diagram showing an example of the bb cross section shown in Fig. 3. However, the structure shown in Fig. 17 can also be applied to semiconductor devices 100 shown in other than those shown in Fig. 3. The bb cross section is an XZ plane passing through the contact hole 54 in the dummy mesa portion 72.

[0128] In the semiconductor device 100 of this example, the collector regions 22 and the lower surface side regions 28 are alternately arranged below the dummy mesa portion 72 along the longitudinal direction of the dummy trench portion 30. This structure makes it easy to adjust the area ratio between the collector regions 22 and the lower surface side regions 28. The width of one collector region 22 and the width of one lower surface side region 28 in the X-axis direction may be the same. In the X-axis direction, the width of one collector region 22 may be larger than the width of one lower surface side region 28, and the width of one lower surface side region 28 may be larger than the width of one collector region 22.

[0129] Furthermore, the range in the X-axis direction in which the collector region 22 is provided may at least partially overlap with the range in the X-axis direction in which the emitter region 12 is provided. The range in the X-axis direction in which the collector region 22 is provided may coincide with the range in the X-axis direction in which the emitter region 12 is provided. The range in the X-axis direction in which the collector region 22 is provided may be included in the range in the X-axis direction in which the emitter region 12 is provided, and the range in the X-axis direction in which the emitter region 12 is provided may be included in the range in the X-axis direction in which the collector region 22 is provided.

[0130] The length L in the X-axis direction of the collector region 22 sandwiched between the two lower surface side regions 28 in the X-axis direction p is the length L of the lower surface region 28 n The length L of the collector region 22 in the X-axis direction is equal to the length L of the collector region 22 in the X-axis direction. p The length L of the lower surface side region 28 is typically 10 μm, and may be 5 μm or more and 15 μm or less. n is typically 5 μm, and may be 5 μm or more and 15 μm or less.

[0131] 18 is a view partially illustrating the top surface of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 differs from the semiconductor device 100 described with reference to FIGS. 1 to 17 in the arrangement of the emitter region 12, the contact region 15, and the accumulation region 16. The other configuration may be the same as any of the semiconductor devices 100 described with reference to FIGS. 1 to 17.

[0132] In this example, the extending portion 41 of the gate trench portion 40 has a long side and a short side on the upper surface of the semiconductor substrate 10. In the example of Fig. 18, the extending portion 41 has a long side in the X-axis direction and a short side in the Y-axis direction.

[0133] The gate trench portion 40 has a first gate sidewall 74 along the longitudinal direction and a second gate sidewall 75 on the opposite side to the first gate sidewall 74. The first gate sidewall 74 and the second gate sidewall 75 are disposed opposite to each other inside the semiconductor substrate 10.

[0134] In this example, of the mesa portions 71, the mesa portion 71 adjacent to the first gate sidewall 74 is referred to as the first mesa portion 71-1, and the mesa portion 71 adjacent to the second gate sidewall 75 is referred to as the second mesa portion 71-2. In other words, one of the mesa portions 71 arranged on either side of the gate trench portion 40 is referred to as the first mesa portion 71-1, and the other mesa portion 71 is referred to as the second mesa portion 71-2.

[0135] On the upper surface of each of the first mesa portion 71-1 and the second mesa portion 71-2, emitter regions 12 and contact regions 15 are arranged so as to be exposed alternately along the X-axis direction. In the semiconductor device 100 of this example, at least a portion of at least one emitter region 12 in the first mesa portion 71-1 is arranged in a position facing a contact region 15 in the second mesa portion 71-2. In other words, at least a portion of the range in the X-axis direction in which at least one emitter region 12 in the first mesa portion 71-1 is provided overlaps with the range in the X-axis direction in which the contact region 15 in the second mesa portion 71-2 is provided.

[0136] 18, all of the emitter regions 12 in the first mesa portion 71-1 are disposed in their entirety in positions facing any of the contact regions 15 in the second mesa portion 71-2. The width in the X-axis direction of the emitter regions 12 in the first mesa portion 71-1 may be the same as the width in the X-axis direction of the contact regions 15 in the second mesa portion 71-2.

[0137] Furthermore, at least a portion of the at least one contact region 15 in the first mesa portion 71-1 is disposed in a position facing the emitter region 12 in the second mesa portion 71-2. In other words, at least a portion of the range in the X-axis direction in which the at least one contact region 15 in the first mesa portion 71-1 is provided overlaps with the range in the X-axis direction in which the emitter region 12 in the second mesa portion 71-2 is provided.

[0138] In the example of FIG. 18 , the entire contact region 15 in the first mesa portion 71-1 is disposed in a position facing one of the emitter regions 12 in the second mesa portion 71-2. The width of the contact region 15 in the first mesa portion 71-1 in the X-axis direction may be the same as the width of the emitter region 12 in the second mesa portion 71-2 in the X-axis direction. However, among the contact regions 15 in the first mesa portion 71-1, the contact regions 15 provided at both ends in the X-axis direction are disposed facing both the emitter region 12 and the contact region 15 in the second mesa portion 71-2. That is, in both the first mesa portion 71-1 and the second mesa portion 71-2, the contact regions 15 are disposed adjacent to the base regions 14 provided at both ends in the X-axis direction. This allows carriers below the base regions 14 provided at both ends in the X-axis direction to be efficiently extracted. The width of the contact region 15 in the first mesa portion 71-1 in the X-axis direction may be the same as the sum of the widths of the emitter region 12 and contact region 15 in the second mesa portion 71-2 in the X-axis direction.

[0139] In two mesa portions 71 adjacent to each other across the gate trench portion 40, the emitter regions 12 and the contact regions 15 are arranged to be offset in the X-axis direction, thereby distributing the contact regions 15 that contribute to the extraction of holes. This allows holes to be extracted evenly in the XY plane, improving the withstand capability of the semiconductor device 100 when it is turned off.

[0140] In the semiconductor device 200 of this example, the contact region 15 is exposed on the top surface of the dummy mesa portion 72. A base region 14 may be formed below the contact region 15. In addition, in the semiconductor device 200 of this example, an accumulation region 16 is formed in the mesa portion 71 and the dummy mesa portion 72.

[0141] Furthermore, in the first mesa portion 71-1 and the second mesa portion 71-2, in the regions where the emitter regions 12 or the contact regions 15 are formed, no trench portions extending in the short direction (Y-axis direction) of the gate trench portion 40 are formed. In other words, in the region where the emitter regions 12 and the contact regions 15 are regularly arranged, the gate trench portion 40 does not have any branch portions or forks extending into the inside of the mesa portion 71. Furthermore, no dummy trench portions 30 are provided in this region. With this structure, carriers such as holes can be effectively extracted via the dispersedly arranged contact regions 15 without being hindered by the trench portions.

[0142] Fig. 19 is a diagram showing an example of the aa cross section in Fig. 18. The aa cross section in this example is a YZ plane passing through the contact region 15 of the first mesa portion 71-1 and the emitter region 12 of the second mesa portion 71-2.

[0143] As described above, the contact region 15 of the first mesa portion 71-1 and the contact region 15 of the second mesa portion 71-2 are arranged so as to be offset in the X-axis direction. Therefore, in the cross section shown in Fig. 19, the contact region 15 is provided in the first mesa portion 71-1, and the emitter region 12 is provided in the second mesa portion 71-2. This arrangement allows holes to be extracted evenly.

[0144] In the dummy mesa portion 72 of this example, the contact region 15, the base region 14, and the accumulation region 16 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. In other examples, the accumulation region 16 may not be provided in the dummy mesa portion 72. Furthermore, similar to the semiconductor device 100 shown in FIGS. 1 and 2A, the accumulation region 16 may not be provided in the mesa portion 71 either.

[0145] FIG. 20 is a diagram showing another example of the aa cross section in FIG. 18. In the semiconductor device 200 of this example, the structure of the dummy mesa portion 72 is similar to that of the semiconductor device 100 described with reference to FIGS. 1 to 17. That is, the semiconductor device 200 of this example has a first well region 13 in the dummy mesa portion 72. This structure makes it possible to extract carriers more easily. The structure of the accumulation region 16 in the semiconductor device 200 may also be similar to that of the accumulation region 16 in the semiconductor device 100. The semiconductor device 200 may also include the lower surface region 28 shown in FIGS. 16 and 17.

[0146] 21 is a diagram showing an example of the arrangement of the emitter regions 12 and contact regions 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, the emitter regions 12 and contact regions 15 in each mesa portion 71 have the same length in the X-axis direction. The contact region 15 in the first mesa portion 71-1 is arranged in a position facing the emitter region 12 of the second mesa portion 71-2, and the emitter region 12 in the first mesa portion 71-1 is arranged in a position facing the contact region 15 of the second mesa portion 71-2.

[0147] 22 is a diagram showing another example of the arrangement of the emitter regions 12 and the contact regions 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, in the first mesa portion 71-1 and the second mesa portion 71-2, the contact regions 15 are formed to be longer in the X-axis direction than the emitter regions 12. The length of the contact regions 15 may be twice or more the length of the emitter regions 12.

[0148] The range in the X-axis direction in which the emitter region 12 of the first mesa portion 71-1 is provided is included in the range in the X-axis direction in which the contact region 15 of the second mesa portion 71-2 is provided. The range in the X-axis direction in which the emitter region 12 of the second mesa portion 71-2 is provided is included in the range in the X-axis direction in which the contact region 15 of the first mesa portion 71-1 is provided. This structure can improve the carrier extraction speed.

[0149] 23 is a diagram showing another example of the arrangement of the emitter regions 12 and the contact regions 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, in the first mesa portion 71-1 and the second mesa portion 71-2, the emitter regions 12 are formed to be longer in the X-axis direction than the contact regions 15. The length of the emitter regions 12 may be twice or more the length of the contact regions 15.

[0150] The range in the X-axis direction in which the contact region 15 of the first mesa portion 71-1 is provided is included in the range in the X-axis direction in which the emitter region 12 of the second mesa portion 71-2 is provided. The range in the X-axis direction in which the contact region 15 of the second mesa portion 71-2 is provided is included in the range in the X-axis direction in which the emitter region 12 of the first mesa portion 71-1 is provided. This structure can improve the channel density.

[0151] FIG. 24 is a diagram showing an example of the arrangement of the accumulation region 16. The accumulation region 16 in this example has an opening 92 in the XY plane. The drift region 18 may be provided inside the opening 92. The opening 92 may be arranged to overlap the contact region 15 in the first mesa portion 71-1 and the second mesa portion 71-2. With this structure, carriers can be extracted in the first mesa portion 71-1 and the second mesa portion 71-2. The area of ​​the opening 92 in the XY plane may be the same as or smaller than the area of ​​the contact region 15. The area of ​​the opening 92 may be half or less of the area of ​​the contact region 15.

[0152] 25 is a diagram showing an example of a method for manufacturing the semiconductor device 100. The semiconductor device 200 may also be manufactured by a similar method. In step S250, a base region 14 is formed in the semiconductor substrate 10 provided with the gate trench portion 40 and the dummy trench portion 30. The base region 14 may be formed by implanting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10.

[0153] In step S252, the accumulation region 16 is formed. The accumulation region 16 may be formed by injecting N-type impurities such as phosphorus from the upper surface side of the semiconductor substrate 10 using a mask such as photoresist.

[0154] In step S254, the first well region 13 is formed. The first well region 13 may be formed by implanting P-type impurities such as boron from the upper surface side of the semiconductor substrate 10 using a mask such as photoresist. The P-type impurities may be implanted to different depths in multiple steps by changing the acceleration voltage.

[0155] In step S256, the contact region 15 is formed. The contact region 15 may be formed by implanting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10 using a mask such as photoresist.

[0156] In step S258, a structure is formed on the lower surface side of the semiconductor substrate 10. For example, the collector region 22 is formed.

[0157] In step S260, the semiconductor substrate 10 is annealed under predetermined conditions, thereby converting the impurities implanted in steps S250 to S258 into donors or acceptors to form the respective regions.

[0158] In step S262, the emitter region 12 is formed. The emitter region 12 may be formed by implanting an N-type impurity such as arsenic from the upper surface side of the semiconductor substrate 10 using a mask such as photoresist.

[0159] In step S264, the semiconductor substrate 10 is annealed under predetermined conditions, thereby converting the impurities implanted in step S262 into donors, thereby forming the emitter regions 12.

[0160] After step S264, the interlayer insulating film 26, the contact hole 54, the emitter electrode 52, etc. are formed, thereby completing the manufacturing of the semiconductor device 100.

[0161] Note that step S254 may be performed after step S264. In this case, an annealing step may be performed after step S254. In this case, the number of annealing steps after forming first well region 13 can be reduced, and the depth of first well region 13 can be controlled with high precision.

[0162] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0163] It should be noted that the order of execution of each process in the methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that processes can be performed in any order unless the result of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the process must be performed in this order. [Explanation of symbols]

[0164] 10 semiconductor substrate, 11 second well region, 12 emitter region, 13 first well region, 14 base region, 15 contact region, 16 accumulation region, 17 region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 26 interlayer insulating film, 28 lower surface region, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 tip portion, 34 dummy conductive portion, 35 bottom portion, 36 end portion, 37 5. A semiconductor device comprising: a first dummy sidewall, a gate trench portion, an emitter electrode, a contact hole, a collector electrode, a mesa portion, a dummy mesa portion, a recess portion, a first gate sidewall, a first gate sidewall, a second gate sidewall, a gate insulating film, a gate conductive portion, a gate wiring, a gate electrode, a first dummy sidewall, a first dummy sidewall, a first gate trench portion, an extension portion, a gate insulating film, a tip portion, a gate conductive portion, a gate wiring, a gate electrode, a first dummy sidewall ...

Claims

1. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; a second conductivity type well region provided from the upper surface of the semiconductor substrate to a depth greater than the position of a pn junction formed at the lower end of the base region; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with below a first mesa portion, which is a region of the semiconductor substrate sandwiched between the two trench portions, the lower surface side region is provided to extend from one of the trench portions to the other of the trench portions in an arrangement direction of the trench portions; the first mesa portion is a dummy mesa portion that is a region of the semiconductor substrate sandwiched between two of the dummy trench portions, the well region is provided in the dummy mesa portion, The lower surface region is provided in at least a portion of the region below the dummy mesa portion. Semiconductor device.

2. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; a second conductivity type well region provided from the upper surface of the semiconductor substrate to a depth greater than the position of a pn junction formed at the lower end of the base region; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with below a first mesa portion, which is a region of the semiconductor substrate sandwiched between the two trench portions, the lower surface side region is provided to extend from one of the trench portions to the other of the trench portions in an arrangement direction of the trench portions; the first mesa portion is a dummy mesa portion that is a region of the semiconductor substrate sandwiched between two of the dummy trench portions, the trench portion includes a longitudinal portion extending in an extension direction, The lower surface side regions and the collector regions are alternately arranged along the extension direction below the dummy mesa portion. Semiconductor device.

3. an accumulation region of a first conductivity type provided between the base region and the drift region in the depth direction and having a doping concentration higher than that of the drift region; 3. The semiconductor device according to claim 1.

4. At least a part of the accumulation region is provided below the lower end of the gate trench portion. The semiconductor device according to claim 3 .

5. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; an accumulation region of a first conductivity type provided between the base region and the drift region in the depth direction and having a doping concentration higher than that of the drift region; a well region of a second conductivity type provided from the upper surface of the semiconductor substrate to at least a depth position where the accumulation region is to be formed; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with below a first mesa portion, which is a region of the semiconductor substrate sandwiched between the two trench portions, the lower surface side region is provided to extend from one of the trench portions to the other of the trench portions in an arrangement direction of the trench portions; the first mesa portion is a dummy mesa portion that is a region of the semiconductor substrate sandwiched between two of the dummy trench portions, the well region is provided in the dummy mesa portion, The lower surface region is provided in at least a portion of the region below the dummy mesa portion. Semiconductor device.

6. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; an accumulation region of a first conductivity type provided between the base region and the drift region in the depth direction and having a doping concentration higher than that of the drift region; a well region of a second conductivity type provided from the upper surface of the semiconductor substrate to at least a depth position where the accumulation region is to be formed; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with below a first mesa portion, which is a region of the semiconductor substrate sandwiched between the two trench portions, the lower surface side region is provided to extend from one of the trench portions to the other of the trench portions in an arrangement direction of the trench portions; the first mesa portion is a dummy mesa portion that is a region of the semiconductor substrate sandwiched between two of the dummy trench portions, the trench portion includes a longitudinal portion extending in an extension direction, The lower surface side regions and the collector regions are alternately arranged along the extension direction below the dummy mesa portion. Semiconductor device.

7. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, comprising: a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; a second conductivity type well region provided from the upper surface of the semiconductor substrate to a depth greater than the position of a pn junction formed at the lower end of the base region; an accumulation region of a first conductivity type provided between the base region and the drift region in the depth direction and having a doping concentration higher than that of the drift region; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with below a first mesa portion, which is a region of the semiconductor substrate sandwiched between the two trench portions, the lower surface side region is provided to extend from one of the trench portions to the other of the trench portions in an arrangement direction of the trench portions; the first mesa portion is a dummy mesa portion that is a region of the semiconductor substrate sandwiched between two of the dummy trench portions, The accumulation region is provided in multiple stages in the depth direction. Semiconductor device.

8. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, comprising: a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; a second conductivity type well region provided from the upper surface of the semiconductor substrate to a depth greater than the position of a pn junction formed at the lower end of the base region; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with the lower surface side region is provided in at least a part of a region below a dummy mesa portion, which is a region of the semiconductor substrate sandwiched between the two dummy trench portions, The well region is provided in the dummy mesa portion. Semiconductor device.

9. A semiconductor device provided with a trench portion including a gate trench portion and a dummy trench portion, a first conductivity type drift region provided inside a semiconductor substrate; a second conductivity type base region provided between the upper surface of the semiconductor substrate and the drift region in a depth direction; a second conductivity type well region provided from the upper surface of the semiconductor substrate to a depth greater than the position of a pn junction formed at the lower end of the base region; a collector region of a second conductivity type provided on a rear surface of the semiconductor substrate; a first conductivity type lower surface side region provided on a rear surface of the semiconductor substrate; Equipped with the lower surface side region is provided below a dummy mesa portion, which is a region of the semiconductor substrate sandwiched between the two dummy trench portions, the trench portion includes a longitudinal portion extending in an extension direction, The lower surface side regions and the collector regions are alternately arranged along the extension direction below the dummy mesa portion. Semiconductor device.

10. The collector region is provided at least partially below the dummy mesa portion. The semiconductor device according to claim 1 .

11. the trench portion includes a longitudinal portion extending in an extension direction, The lower surface side regions and the collector regions are alternately arranged along the extension direction below the dummy mesa portion.

9. The semiconductor device according to claim 1, 5 or 8.

12. The collector region is provided in at least a portion below a second mesa portion adjacent to at least one of the gate trench portions, in the region of the semiconductor substrate sandwiched between the trench portions. The semiconductor device according to claim 6 .

13. The concentration peak of the well region is located at a position shallower than the bottom end of the trench portion. The semiconductor device according to claim 1 .

14. the well region has a first concentration peak at a position deeper than the base region; the first concentration peak is higher than the concentration peak of the base region; The semiconductor device according to claim 1 .

15. the well region has a first concentration peak at a position deeper than the base region; the first concentration peak is lower than the concentration peak of the base region; The semiconductor device according to claim 1 .

16. the depth of the base region is 0.5 μm or more and 5.0 μm or less; The depth of the well region is 2.0 μm or more and 10 μm or less. The semiconductor device according to claim 1 .

17. The lower surface side region is provided at the same depth position as the collector region.

9. The semiconductor device according to claim 1, 5 or 8.

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