Solid-state imaging device, imaging device, and distance measuring imaging device

Abstract

This solid-state imaging device comprises a pixel circuit (3), a detection selection circuit (450), and an AD conversion circuit (26). The pixel circuit (3) outputs a plurality of pixel signals corresponding to gains or sensitivities that are different from each other. The detection selection circuit (450) generates a signal selection signal (407) which directs the selection of a pixel signal contained in the plurality of pixel signals by comparing one or more pixel signals among the plurality of pixel signals with a reference value. The detection selection circuit (450) has a sample hold circuit (412) which holds the plurality of pixel signals and, on the basis of the signal selection signal (407), selects one pixel signal from among the plurality of pixel signals held in the sample hold circuit (412). The detection selection circuit (450) is located in the front stage of the AD conversion circuit (26) which performs AD conversion on the selected pixel signal.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device, an imaging device, and a ranging imaging device. [Background technology]

[0002] Patent Document 1 discloses a method for achieving a wide dynamic range in a solid-state imaging device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3976754 Summary of the Invention [Problem to be solved by the invention]

[0004] The solid-state imaging device disclosed in Patent Document 1, which is a conventional technology, selectively reads one digital signal from among a plurality of digital signals obtained by AD-converting a plurality of pixel signals. However, since AD ​​conversion of a plurality of pixel signals is included, there is a problem that it is difficult to improve speed and power consumption.

[0005] Therefore, the present disclosure provides a solid-state imaging device, an imaging device, and a ranging imaging device that improves speed and power consumption while simultaneously expanding the dynamic range. [Means for solving the problem]

[0006] In order to solve the above problem, a solid-state imaging device according to one embodiment of the present disclosure includes a pixel circuit, a detection selection circuit, and an AD conversion circuit, wherein the pixel circuit outputs a plurality of pixel signals corresponding to different gains or sensitivities, the detection selection circuit generates a signal selection signal that instructs the selection of a pixel signal included in the plurality of pixel signals by comparing one or more of the plurality of pixel signals with a reference value, the detection selection circuit has a sample-and-hold circuit that holds the plurality of pixel signals, and selects one of the plurality of pixel signals held in the sample-and-hold circuit based on the signal selection signal, and the detection selection circuit is arranged in a stage preceding the AD conversion circuit that AD converts the selected pixel signal.

[0007] In addition, an imaging device according to one aspect of the present disclosure includes a solid-state imaging device according to the above aspect that captures an image of a subject, an imaging optical system that guides incident light from the subject to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device.

[0008] In addition, a distance measuring imaging device according to one aspect of the present disclosure includes a solid-state imaging device according to the above aspect that drives and controls a light source unit to irradiate pulsed light onto an object and capture the light reflected from the object, an imaging optical system that guides the reflected light from the object to the solid-state imaging device, and a signal processing unit that processes the output signal from the solid-state imaging device. [Effects of the Invention]

[0009] The solid-state imaging device, imaging device, and distance measuring imaging device of the present disclosure can improve speed and power consumption, and can widen the dynamic range. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device including pixel circuits and a column detection selection circuit according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a pixel circuit according to the first embodiment. [Figure 3]FIG. 3 is a diagram showing an example of a circuit of a main part including a pixel circuit and a sample-and-hold circuit SH10 according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of a pixel circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing an example of a circuit of a main part including a pixel circuit and a sample-and-hold circuit SH10 according to the first embodiment. [Figure 6A] FIG. 6A is a block diagram showing an example of a configuration including a detection selection circuit made up of a selection circuit and a first detection circuit. [Figure 6B] FIG. 6B is a diagram illustrating the operation of the first detection circuit. [Figure 6C] FIG. 6C is a diagram showing a modification of the selection circuit. [Figure 7] FIG. 7 is a block diagram showing an example of a configuration including a detection selection circuit made up of a selection circuit and a second detection circuit. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of the switch circuits SW15 and SW16 in the first detection circuit and the second detection circuit. [Figure 9] FIG. 9 is a diagram showing an example of the configuration of the sample-and-hold circuit SH430 associated with the selection circuit. [Figure 10] FIG. 10 is a diagram showing an example of combining the pixel circuit according to the first embodiment with one detection and selection circuit. [Figure 11] FIG. 11 is a diagram showing an example of joining a pixel circuit according to the first embodiment with two detection and selection circuits. [Figure 12] FIG. 12 is a block diagram showing an example of the configuration of the reference signal generating unit and the voltage comparator. [Figure 13A] FIG. 13A is a diagram showing an overview of how WDR is implemented within a pixel. [Figure 13B] FIG. 13B is a diagram showing an overview of how WDR is implemented within a pixel. [Figure 14A] FIG. 14A is a flowchart for determining a synthesis ratio at the boundary between HCG and MCG in WDR. [Figure 14B]FIG. 14B is a flowchart for determining the synthesis ratio at the boundary between MCG and LCG in WDR. [Figure 14C] FIG. 14C is a diagram showing an outline of a method for implementing the synthesis ratio of HCG, MCG, and LCG in WDR. [Figure 15] FIG. 15 is a diagram showing timings of reading from the pixel circuit to the sample-and-hold circuit SH412 and reading from the sample-and-hold circuit SH412 in the first embodiment. [Figure 16] FIG. 16 is a diagram showing the timing of reading from the pixel circuit to the sample and hold circuit SH10 in the first embodiment. [Figure 17] FIG. 17 is a continuation of the timing chart of FIG. 16, and shows the timing of reading from the sample and hold circuit SH10 to the sample and hold circuit SH412 and reading from the sample and hold circuit SH412 in the first embodiment. [Figure 18] FIG. 18 is a diagram showing timings between vertical signal lines and ADCs according to a conventional example. [Figure 19] FIG. 19 is a diagram illustrating timings between vertical signal lines and ADCs according to the first embodiment. [Figure 20] FIG. 20 is a diagram showing the effective area and the OB area in the pixel array section. [Figure 21] FIG. 21 is a diagram showing the effective area and the OB area in the pixel array section. [Figure 22] FIG. 22 is a block diagram illustrating an example of the configuration of a pixel array unit and a column detection and selection circuit according to the first embodiment. [Figure 23A] FIG. 23A is a block diagram showing an example of the configuration of a pixel array unit according to the first embodiment. [Figure 23B] FIG. 23B is a diagram illustrating an example of the configuration of the solid-state imaging device according to the first embodiment as a stacked image sensor. [Figure 24A] FIG. 24A is a block diagram showing a configuration example of a pixel array unit and a column detection and selection circuit according to the first embodiment. [Figure 24B]FIG. 24B is a diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment as a stacked image sensor. [Figure 25] FIG. 25 is a diagram illustrating an example of the configuration of a signal processing unit that performs WDR synthesis using three frames. [Figure 26] FIG. 26 is a diagram showing an example of a configuration in which the column detection selection circuit selects signals independently for each color. [Figure 27] FIG. 27 is a diagram showing an example of a configuration in which the column detection selection circuit selects the gain by giving priority to the maximum signal of each color in Bayer units. [Figure 28] FIG. 28 is a diagram showing an example of hysteresis of the reference values ​​REF1 and REF2 of the WDR. [Figure 29] FIG. 29 is a block diagram showing an example of the configuration of a solid-state imaging device including pixel circuits and a column detection selection circuit according to the second embodiment. [Figure 30] FIG. 30 is a diagram showing an example of combining a pixel circuit according to the second embodiment with one detection and selection circuit. [Figure 31] FIG. 31 is a diagram showing an example of joining a pixel circuit according to the second embodiment with two detection and selection circuits. [Figure 32] FIG. 32 is a diagram illustrating timings between vertical signal lines and ADCs according to the second embodiment. [Figure 33A] FIG. 33A is a block diagram showing a configuration example of a pixel array unit according to the second embodiment. [Figure 33B] FIG. 33B is a diagram illustrating a configuration example of the solid-state imaging device according to the second embodiment as a stacked image sensor. [Figure 34A] FIG. 34A is a block diagram showing an example of the configuration of a pixel array unit according to the second embodiment. [Figure 34B] FIG. 34B is a diagram illustrating a configuration example of the solid-state imaging device according to the second embodiment as a stacked image sensor. [Figure 35] FIG. 35 is a block diagram showing an example of a configuration with low power consumption according to the second embodiment. [Figure 36] FIG. 36 is a diagram illustrating an example of a camera system equipped with the imaging device according to the third embodiment. [Figure 37] FIG. 37 is a diagram illustrating an example of a distance measuring system equipped with a distance measuring imaging device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Findings that formed the basis of this disclosure) The present inventors have found that the solid-state imaging device described in the Background Art section has the following problems.

[0012] The solid-state imaging device disclosed in Patent Document 1 converts pixel signals into analog signals, performs redundant reading by reading all digital signals, and selectively reads one signal from among multiple signals. This poses a problem in that it is difficult to improve speed and power consumption in the preceding stages, including the AD converter.

[0013] Specifically, since the AD conversion circuit processes all of the multiple signals, it is difficult to improve speed and power consumption, and it is also difficult to improve the speed of the pixel array.

[0014] Furthermore, it is necessary to wait for convergence of the vertical signal lines for all of the multiple pixel signals, which also makes it difficult to improve speed and power consumption. In particular, as the pixel size or number of pixels increases, the parasitic resistance and capacitance of the vertical signal lines increase, making convergence a serious issue.

[0015] For this reason, a possible configuration is to divide the vertical signal lines of the pixel array section into groups of multiple rows or into the smallest unit of one row (one pixel), thereby minimizing the convergence time of the vertical signal lines, and then selectively read out one or two pixel signals from the multiple signals when they are output from the pixel circuit.

[0016] This further enables faster convergence times, and makes it possible to achieve higher speeds and lower power consumption in all areas of analog and digital processing, including the pixel array section and the AD conversion circuit, as well as an expanded dynamic range.

[0017] Therefore, the present disclosure provides a solid-state imaging device, an imaging device, and a ranging imaging device that can improve speed and power consumption and expand the dynamic range.

[0018] Hereinafter, a solid-state imaging device, an imaging device, and a distance measuring imaging device according to embodiments of the present disclosure will be described with reference to the drawings.

[0019] As outlined above, a solid-state imaging device according to one aspect of the present disclosure includes a pixel circuit, a detection selection circuit, and an AD conversion circuit. The pixel circuit outputs multiple pixel signals corresponding to different gains or sensitivities. The detection selection circuit generates a signal selection signal that instructs selection of a pixel signal included in the multiple pixel signals by comparing one or more pixel signals with a reference value. The detection selection circuit has a sample-and-hold circuit that holds the multiple pixel signals and selects one of the multiple pixel signals held in the sample-and-hold circuit based on the signal selection signal. The detection selection circuit is disposed upstream of the AD conversion circuit that AD converts the selected pixel signal. Note that the gain refers to the conversion ratio in the conversion from the original signal charge to a pixel signal voltage value within the pixel circuit. Furthermore, the sensitivity refers to the magnitude of the signal charge amount or pixel signal voltage value generated in the pixel circuit per unit amount of received light or unit exposure time.

[0020] This eliminates the redundant reading of all multiple signals by selectively reading at least one pixel signal from multiple pixel signals, thereby achieving faster and lower power consumption in the analog and digital processing stages, including the AD conversion circuit. For example, if N pixel signals are combined into one pixel signal, the speed increases by N times, or the power consumption decreases by 1 / N. Furthermore, the dynamic range can be maintained at the same level as when multiple pixel signals are used.

[0021] Here, the semiconductor device may include a first semiconductor chip having a pixel array including a plurality of the pixel circuits and vertical signal lines, and a second semiconductor chip having the detection selection circuit and stacked on the first semiconductor chip, wherein the pixel array and the vertical signal lines are divided into a plurality of parts, and the detection selection circuit is provided in each of the divided pixel arrays.

[0022] According to this, multiple detection selection circuits are arranged in a stage preceding the AD conversion circuit, and AD conversion and reading of at least one pixel signal from among the multiple pixel signals is avoided by performing redundant operations of AD converting and reading all of the multiple pixel signals. This provides high-speed and low-power analog and digital processing in subsequent stages including the AD conversion circuit. Furthermore, vertically dividing the vertical signal lines of the pixel array unit or the sample-and-hold circuit corresponding to the pixel array into multiple lines improves the convergence of the vertical signal lines and provides high speed. For example, dividing the vertical signal lines into M lines in the vertical direction can speed up the convergence time of the vertical signal lines by 1 / M times. For example, combining multiple N signals into one signal can speed up analog and digital processing by N times, or reduce power consumption by 1 / N times. In particular, the convergence times of the pixel signals on the vertical signal lines is reduced by 1 / N times, resulting in an N-fold increase in speed. Furthermore, the dynamic range can be maintained equivalent to that when multiple pixel signals are present.

[0023] Here, the plurality of pixel signals may include a first pixel signal for low illumination, a second pixel signal for medium illumination, and a third pixel signal for high illumination. The solid-state imaging device may further include a synthesis circuit that interpolates non-selected pixel signals based on selected pixel signals and synthesizes the selected pixel signals with other pixel signals obtained by the interpolation process. The reference values ​​in the detection selection circuit may include a first reference value and a second reference value. The first reference value may include a value corresponding to a level of the second pixel signal corresponding to a boundary level immediately before a saturation level of the first pixel signal, and the second reference value may correspond to a boundary level immediately before a saturation level of the second pixel signal. Hereinafter, the first pixel signal for low illumination may be referred to as an HCG (High Conversion Gain) signal or simply as HCG. Similarly, the second pixel signal for medium illumination may be referred to as an MCG (Middle Conversion Gain) signal or simply as MCG. The third pixel signal for high illuminance may be referred to as an LCG (Low Conversion Gain) signal, or simply as LCG.

[0024] This allows the selection of at least one pixel signal from multiple pixel signals for wide dynamic range (WDR) synthesis to be determined solely from the MCG signal. This eliminates the need to wait for the LCG signal to be read from the pixel circuit, eliminating the need for a sample-and-hold capacitor for the LCG in the sample-and-hold circuit and reducing the layout area. Furthermore, because the detection selection circuit only performs comparison operations for the LCG, the circuit can be downsized, reducing the layout area.

[0025] Here, the first reference value may include a value corresponding to a boundary level immediately before a saturation level of the first pixel signal.

[0026] According to this, when selecting at least one pixel signal from multiple pixel signals for wide dynamic range function (WDR function) synthesis, it can be determined from the HCG signal and the MCG signal. Therefore, since there is no need to wait for the LCG signal to be read from the pixel circuit, the LCG sample-and-hold capacitance element in the sample-and-hold circuit can be eliminated, and the layout area can be reduced.

[0027] Here, the sample and hold circuit may have a plurality of sample and hold elements that hold the plurality of pixel signals, and when the pixel signal specified by the signal selection signal is within a predetermined range including the reference value, the detection selection circuit mixes the pixel signal specified by the signal selection signal with another pixel signal at a mixing ratio of α to (1-α) (α is a real number greater than or equal to 0 and less than 1), and outputs the mixed signal as the pixel signal specified by the signal selection signal, where α is determined according to a difference between the pixel signal specified by the signal selection signal and the reference value, and a capacitance ratio of the plurality of sample and hold elements corresponding to the plurality of pixel signals may be an inverse ratio of a gain at which the original signal charges are converted into voltage values ​​within the pixel circuit for the plurality of pixel signals.

[0028] This makes it possible to mitigate sudden changes in SN at the boundary between HCG and MCG and at the boundary between MCG and LCG when combining with a wide dynamic range function (WDR function).

[0029] Here, the sample and hold circuit may include two sample and hold capacitance elements, one for a reset component and one for a signal component, corresponding to each of the plurality of pixel signals, and the detection selection circuit may compare the pixel signal level, obtained by subtracting the reset component from the signal component, with the reference value.

[0030] According to this, by performing analog CDS, it is possible to compare the pixel signal level, in which variations in the pixel circuit have been cancelled, with the reference value.

[0031] Here, the reference value may be determined according to a gain of AD conversion in the AD conversion circuit, and the gain of AD conversion may be adjusted according to the magnitude of the slope of a RAMP signal input to the AD conversion circuit.

[0032] This makes it possible to synthesize frames in a wide dynamic range even when the analog gain or digital gain is varied by AE (automatic exposure) control.

[0033] Here, the device may include a reference signal generation unit that simultaneously generates a plurality of RAMP signals corresponding to the plurality of pixel signals, and a selection switch that selects one of the plurality of RAMP signals and outputs the selected signal to the AD conversion circuit, and the selection switch may select one of the plurality of RAMP signals in accordance with a signal selection signal generated by the detection circuit.

[0034] According to this, when the RAMP signal is a single pixel signal, three RAMP signals (HCG, MCG, and LCG) are generated in time series, which makes it impossible to increase speed. Alternatively, if the gains are the same, noise increases and accuracy deteriorates. According to this aspect, three RAMP signals are generated simultaneously and analog gains are set for each, so it is possible to achieve both increased speed and reduced noise.

[0035] Here, the detection selection circuit may generate the same signal selection signal for pixels included in a unit of the color filter array.

[0036] This allows the gain to be the same for each color filter array, for example, a Bayer array consisting of four colors, eliminating coloration caused by deviations in the linearity of each color that may occur when the gains differ for each color.

[0037] Here, the detection selection circuit may include a detection circuit that generates the signal selection signal, and a selection circuit that has the sample and hold circuit and selects one of the plurality of pixel signals held in the sample and hold circuit based on the signal selection signal.

[0038] According to this, since the selection circuit has a sample-and-hold circuit, it is possible to more easily and flexibly control the operation of sampling pixel signals, the holding time, and the operation of selecting and outputting the pixel signals.

[0039] Here, a plurality of pairs of the selection circuit and the detection circuit may be provided for each pixel circuit, and the detection circuit of one pair and the selection circuit of another pair may operate in parallel in terms of time.

[0040] This allows one detection circuit to detect a signal while the other selection circuit selects and outputs it, thus enabling operations to be performed in parallel in time, thereby achieving high speed.

[0041] Here, the detection selection circuit includes a comparator, one input of which receives a reset component of the second pixel signal from the pixel circuit to perform auto-zero, and then one input of which receives a signal component of the second pixel signal from the pixel circuit, and the other input of which receives the first reference value or the second reference value, and the detection selection circuit may perform the comparison operation between the second pixel signal and the first reference value and the comparison operation between the second pixel signal and the second reference value in parallel using a plurality of the comparators, or may perform these operations sequentially using one of the comparators.

[0042] This allows analog CDS to be performed by implementing auto-zero, canceling noise and correctly extracting signal components. Furthermore, since at least one pixel signal can be detected during the period in which the second pixel signal (MCG) is being read out, readout and detection can be processed simultaneously, achieving high speed. Furthermore, the capacitance of the LCG can be reduced, thereby reducing the layout area. Furthermore, when comparing signals divided in time, only one comparator is required, further reducing the layout area.

[0043] Here, the detection selection circuit may generate a signal selection signal that instructs selection of two pixel signals.

[0044] This allows you to select two frames, one each of HCG and MCG, or one each of MCG and LCG. The signal processing unit can digitally mitigate the sudden change in signal-to-noise ratio (SN) at the frame boundary that occurs when combining frames in a wide dynamic range.

[0045] Here, the detection selection circuit may output the selected pixel signal to the AD conversion circuit via a vertical signal line, the detection selection circuit may generate a gain selection signal similar to the signal selection signal, and the vertical signal line may be used in a time-division manner for transmitting the gain selection signal from the detection selection circuit to the AD conversion circuit and for transmitting the gain selection signal from the detection selection circuit to the AD conversion circuit.

[0046] This allows the number of wirings for the gain selection signal to be reduced, thereby reducing the layout area. Also, the RAMP signal can be selected before the pixel signal is supplied to the AD conversion circuit.

[0047] Here, the first reference value and the second reference value may be adjusted according to the signal selection signal of the previous frame so as to have a hysteresis characteristic that makes it easier for a pixel signal having the same gain or sensitivity as the pixel signal indicated by the signal selection signal of the previous frame to be selected in the current frame.

[0048] This makes it possible to mitigate sudden changes in SN between frames that occur when compositing with the wide dynamic range function (WDR function) at the boundary between HCG and MCG, or at the boundary between MCG and LCG, when the pixel signal level is close to the reference value and a misjudgment occurs due to noise superposition or the like.

[0049] Here, a noise reduction ratio in a signal processing unit may be determined in accordance with a digital signal level of the second pixel signal or the first pixel signal within a first range including the first reference value, and digital noise reduction of the first pixel signal and the second pixel signal may be performed, and a noise reduction ratio in a signal processing unit may be determined in accordance with a digital signal level of the second pixel signal within a second range including the second reference value, and digital noise reduction of the second pixel signal and the third pixel signal may be performed.

[0050] According to this, when combining wide dynamic range functions (WDR functions), digital noise reduction can be performed to mitigate the sudden change in SN at the boundaries between HCG and MCG, and between MCG and LCG.

[0051] Here, the pixel circuit may have a first amplification transistor for outputting the plurality of pixel signals, the detection selection circuit may have a second amplification transistor for outputting a pixel signal indicated by the signal selection signal, and the area of ​​the second amplification transistor may be larger than the area of ​​the first amplification transistor.

[0052] This makes it possible to reduce device noise that occurs when a signal is read out from the selection circuit via the second amplification transistor.

[0053] Here, the vertical signal lines from the detection selection circuit may be arranged on a power supply wiring layer or a ground potential (GND) wiring layer.

[0054] This provides an electromagnetic shield against noise from the digital and analog circuits of the logic chip, and prevents noise from being superimposed on the vertical signal lines.

[0055] Here, the device may include a first semiconductor chip having a pixel array including a plurality of the pixel circuits and vertical signal lines, and a second semiconductor chip having the detection selection circuit and stacked on the first semiconductor chip, wherein the vertical signal lines are divided into vertical rows of the pixel array, and the detection selection circuit may be provided for each pixel circuit.

[0056] This further enables faster convergence times for vertical signal lines, and makes it possible to achieve faster and lower power consumption in analog and digital processing, including AD conversion circuits, without compromising the dynamic range.

[0057] In addition, an imaging device according to one aspect of the present disclosure includes a solid-state imaging device according to each of the above aspects that captures an image of a subject, an imaging optical system that guides incident light from the subject to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device.

[0058] This makes it possible to obtain the same effects as those of the above-described solid-state imaging device.

[0059] In addition, a distance measuring imaging device according to one aspect of the present disclosure includes a solid-state imaging device according to each of the above aspects, which drives and controls a light source unit to irradiate pulsed light onto an object and captures the light reflected from the object, an imaging optical system which guides the reflected light from the object to the solid-state imaging device, and a signal processing unit which processes the output signal from the solid-state imaging device.

[0060] This makes it possible to obtain the same effects as those of the above-described solid-state imaging device.

[0061] Hereinafter, a solid-state imaging device according to an embodiment of the present disclosure will be described with reference to the drawings.

[0062] (Embodiment 1) First, a configuration example of a solid-state imaging device according to the present embodiment will be described. In the first embodiment, a configuration example in which a detection selection circuit 450 is arranged in the preceding stage of the column AD circuit in the configuration example of FIG.

[0063] [Configuration example of solid-state imaging device 100] FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device 100 according to the first embodiment.

[0064] The solid-state imaging device 100 includes a pixel array section 1, a horizontal scanning circuit 12, a vertical scanning circuit 14, vertical signal lines 30A, vertical signal lines 19B, a timing control section 20, an AD conversion circuit 26, a reference signal generation section 22, a first detection circuit 401, a second detection circuit 402, a gain reference signal generation section 40, an output circuit 28, and signal processing sections 70 and 90. The solid-state imaging device 100 also includes an MCLK terminal for receiving an external master clock signal, a DATA terminal for transmitting and receiving commands or data to and from the outside, a D1 terminal for transmitting video data to the outside, and other terminals to which a power supply voltage and a ground voltage are supplied.

[0065] The pixel array section 1 has a plurality of pixel circuits 3a or 3b arranged in a matrix. Hereinafter, when there is no need to distinguish between the pixel circuits 3a and 3b, they will be referred to as pixel circuits 3. The plurality of pixel circuits 3 are arranged in n rows and m columns in FIG. 1. Each pixel circuit 3a includes a photodiode (PD), a charge storage section (FD0), a transfer transistor (TG) that transfers signal charge generated in the photodiode to the charge storage section (FD0), an amplifier transistor (amplification transistor SF1) that outputs a pixel signal corresponding to the signal charge in the charge storage section (FD0), and a reset transistor (RS) that resets the charge storage section (FD0).

[0066] The horizontal scanning circuit 12 sequentially scans the memories 256 in the plurality of column AD circuits 25, thereby outputting the AD-converted pixel signals to the signal processing units 70 and 80 via horizontal signal lines. This scanning may be performed in the same order as the arrangement of the column AD circuits 25.

[0067] The vertical scanning circuit 14 scans, row by row, horizontal scanning line groups (also referred to as row control line groups) 15 provided for each row of pixel circuits 3 in the pixel array unit 1. In this way, the vertical scanning circuit 14 selects pixel circuits 3 row by row and causes pixel circuits 3 belonging to the selected row to simultaneously output pixel signals to m vertical signal lines 19. The number of horizontal scanning line groups 15 provided is the same as the number of pixel circuit 3 rows.

[0068] In FIG. 1, a group of n horizontal scanning lines 15 (V1, V2, ..., Vn) is provided for pixel circuit 3a or pixel circuit 3b, and each includes a reset control line φRS, an accumulated charge transfer control line φTG, and a selection control line φSEL_RS.

[0069] In addition, n horizontal scanning line groups 16 (VSH1, VSH2, ..., VSHn) are provided for the sample and hold circuit SH10 and the sample and hold circuit SH412, and each includes a sample and hold switch control signal φSH, a read selection switch element control signal φSE, selection control lines φSEL_GS, φSEL_DET, and each switch element control signal φSW.

[0070] The detection selection circuit 450 is disposed between the AD conversion circuit 26 and the pixel array unit 1 at the previous stage.

[0071] The vertical signal line 30A is provided on a pixel chip or logic chip in the pixel array unit 1. A plurality of pixel signals output from the amplification transistor SF1 of the pixel circuit 3a or pixel circuit 3b, or from the amplification transistor SF2 of the sample-and-hold circuit SH10, are input to the detection selection circuit 450 via the vertical signal line 30A. At least one pixel signal is selected from the plurality of pixel signals based on reference values ​​(REF1, REF2, REF3) supplied from the gain reference signal generation unit 40. The selected signal is then connected to the vertical signal line 19B from the amplification transistor SF30 via the selection transistor SEL_DET. In this way, at least one pixel signal selected from the plurality of pixel signals output from the pixel circuit 3a or pixel circuit 3b is propagated to the column AD circuit 25.

[0072] 1, the plurality of vertical signal lines 19A and 19B are made up of m vertical signal lines (H1, . . . , Hm). The plurality of ADC input lines are made up of m ADC input lines (ADIN1, . . . , ADINm).

[0073] The timing control unit 20 generates various control signals to control the entire solid-state imaging device 100. The various control signals include control signals CN0, CN1, CN2, CN4, CN5, and CN8, and counter clock signals CK0 and CK1. For example, the timing control unit 20 receives a master clock MCLK via a terminal, generates various internal clocks, and controls the horizontal scanning circuit 12, the vertical scanning circuit 14, etc.

[0074] The gain reference signal generator 40 is controlled by the control signal CN0 and the counter clock signal CK1, and generates a first reference value and a second reference value. For example, by increasing the resolution using a DA circuit or the like, it can also accommodate characteristics that require precision, such as hysteresis characteristics.

[0075] The AD conversion circuit 26 includes a column AD circuit 25 provided for each column. Each column AD circuit 25 performs AD conversion on the pixel signal from the vertical signal line 19B, which is the output of the detection selection circuit 450.

[0076] Each of the column AD circuits 25 includes a voltage comparator 252 , a counter unit 254 , and a memory 256 .

[0077] The voltage comparator 252 compares the analog pixel signal from the vertical signal line 19B, which is the output of the detection selection circuit 450, with a reference signal RAMP, which includes a ramp waveform (i.e., a triangular wave), generated by the reference signal generation unit 22, and inverts the output signal indicating the comparison result when, for example, the former becomes larger than the latter.

[0078] Counter unit 254 counts the time from when the triangular wave in reference signal RAMP starts to change until the output signal of voltage comparator 252 inverts. The time until inversion is determined according to the value of the analog pixel signal, so the count value is the value of the digitized pixel signal.

[0079] The memory 256 stores the count value of the counter unit 254, that is, the digital pixel signal.

[0080] The reference signal generating unit 22 generates a reference signal RAMP including a triangular wave, and outputs the reference signal RAMP to the positive input terminal of the voltage comparator 252 in each column AD circuit 25.

[0081] The output circuit 28 outputs the digital pixel signal to the video data terminal D1.

[0082] The signal processing unit 90 has a frame memory 97 and a control unit 96, and has a function of providing hysteresis to the reference values ​​(REF1, REF2, REF3) of the previous frame and the current frame that are supplied to the detection selection circuit 450. The signal processing unit 90 stores the gain reference signal 403 of the previous frame supplied from the detection selection circuit 450 in the frame memory 97. The control unit 96 calculates the reference value of the current frame based on this information, and supplies a hysteresis selection signal 404 to the first detection circuit 401 or the second detection circuit 402 to control the reference value to be reflected in the current frame.

[0083] The signal processing unit 70 obtains the non-selected pixel signals by interpolation based on the selected pixel signals, and combines the selected pixel signals with the other pixel signals obtained by the interpolation.

[0084] This reduces multiple pixel signals to at least one pixel signal, thereby achieving higher speeds and lower power consumption in subsequent stages including the AD conversion circuit, and also achieving higher speeds and lower power consumption in the signal processing unit 70, while maintaining the same dynamic range as when there are multiple pixel signals.

[0085] The vertical scanning circuit 14, the reference signal generating section 22, and the gain reference signal generating section 40 may be collectively referred to as a driving section. The AD conversion circuit 26 and the horizontal scanning circuit 12 may be collectively referred to as a control section.

[0086] According to this, the detection selection circuit 450 is arranged in a stage preceding the AD conversion circuit 26 and selectively reads at least one pixel signal from among the multiple pixel signals without redundantly reading all of the multiple signals, thereby providing higher speed and lower power consumption in the analog processing and digital processing in the subsequent stages including the AD conversion circuit 26. For example, if N pixel signals are combined into one pixel signal, the speed increases by N times or the power consumption is reduced by 1 / N times. At the same time, the dynamic range can be maintained at the same level as when there are multiple pixel signals.

[0087] [Pixel configuration (horizontal OFD) example] 1 and 29 includes, as pixel circuits 3, a plurality of pixel circuits 3a shown in Fig. 2 arranged in a matrix in a pixel array section 1. This configuration is suitable for the rolling shutter method.

[0088] Similarly, the solid-state imaging device 100 can also include a sample-and-hold circuit SH10 connected to the pixel circuit 3a in Fig. 3. This configuration is suitable for the global shutter system.

[0089] The pixel signal has at least two components: a reset component and a signal component.

[0090] First, a configuration example of a horizontal OFD will be described. The configuration example of a horizontal OFD shows a configuration in which a storage circuit is provided in the horizontal direction.

[0091] The pixel circuit 3a includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, a transfer transistor TG, an amplifying transistor SF1, a reset transistor RS, and a first gain control transistor GC1. The rolling shutter type of FIG. 2 includes a selection transistor SEL_RS, but the global shutter type of FIG. 3 does not include a selection transistor SEL_RS. Furthermore, the positions of the first storage capacitor C1, the first gain control transistor GC1, the second storage capacitor C2, and the second gain control transistor GC2 are added laterally from the viewpoint of charge transfer.

[0092] The photodiode PD is a photoelectric conversion element that converts incident light into a signal charge.

[0093] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and holds the signal charge generated in the photodiode PD. In Figures 2 and 3, the storage capacitance element of the charge storage unit FD0 is denoted as C0.

[0094] The amplification transistor SF1 outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0 to the vertical signal line 30A via the selection transistor SEL_RS.

[0095] The selection transistor SEL_RS is a switch element that selects whether or not to output a pixel signal from the amplification transistor SF1 to the vertical signal line 30A.

[0096] The reset transistor RS can be reset in three ways by controlling the first gain control transistor GC1 and the second gain control transistor GC2: That is, the reset transistor RS can reset the charge storage unit FD0, the first charge storage unit FD1, and the second charge storage unit FD2.

[0097] When the transfer transistor TG is in the ON state, the charge overflowing from the charge storage unit FD0 is transferred to and held in the first storage capacitor element C1 as indicated by the dotted arrow A in FIGS.

[0098] The first gain control transistor GC1 is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitor element C1. The first gain control transistor GC1 acts as a switching element and is in an ON state and an OFF state.

[0099] The signal charge that overflows the photodiode PD during exposure is transferred to and held in the second storage capacitor element C2, as indicated by the dotted arrow B in Figures 2 and 3. Here, an overflow element OF is provided between the photodiode PD and the second storage capacitor element C2, and the signal charge that overflows from the photodiode PD is transferred to the second storage capacitor element C2 via the overflow element OF rather than being transferred to the first storage capacitor element C1 via the transfer transistor TG.

[0100] Furthermore, the signal charge that has overflowed the second storage capacitor element C2 is discharged to the power supply via the second gain control transistor GC2 and the reset transistor RS.

[0101] Furthermore, as indicated by the dotted arrow B, the signal charge overflowing from the photodiode PD is accumulated in the second storage capacitor element C2 without passing through the charge accumulation unit FD0, thereby reducing the influence of dark current components in the charge accumulation unit FD0. Furthermore, the presence of the overflow element OF makes it possible to control the level of overflow and the depth of the charge channel, thereby reducing the influence of dark current components generated in the surface layer.

[0102] The second gain control transistor GC2 is a transistor for gain control that controls the connection between the first storage capacitor element C1 and the second storage capacitor element C2. The second gain control transistor GC2 serves as a switching element and is in an ON state and an OFF state.

[0103] To hold the signal charge overflowing from the photodiode PD, an overflow storage circuit is provided, each consisting of a switch element and a storage capacitor element. The first-stage storage circuit is a pair of a first gain control transistor GC1 and a first storage capacitor element C1. The second-stage storage circuit is a pair of a second gain control transistor GC2 and a second storage capacitor element C2.

[0104] In this way, the first configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio.

[0105] In the rolling shutter method, as shown in FIG. 2, a plurality of pixel signals from the pixel circuits 3a are read out row by row in a rolling manner, and the plurality of pixel signals are supplied to the detection selection circuit 450 via the vertical signal lines 30A.

[0106] In the global shutter system, a sample-and-hold circuit SH10 connected to the pixel circuit 3a can also be provided, as shown in Figure 3. This is particularly suitable for the global shutter system, as it exposes all pixels simultaneously, then simultaneously reads out the signals from all pixels to the sample-and-hold circuit SH10, and holds the pixel signals until the next rolling readout is performed row by row. In this case, too, the multiple pixel signals from the sample-and-hold circuit SH10 are read out row by row in a rolling manner, and the multiple pixel signals are supplied to the detection selection circuit 450 via the vertical signal line 30A.

[0107] According to this, when the first pixel signal HCG, the second pixel signal MCG, and the third pixel signal LCG are synthesized by the WDR synthesis circuit 76 using three frames each of the HCG for low illumination, the MCG for medium illumination, and the LCG for high illumination, each frame is exposed simultaneously, so no blurring or coloring occurs between frames.

[0108] The sample-and-hold circuit SH10 will be described in detail later.

[0109] [Pixel configuration (vertical OFD) example] Next, an example of the configuration of a vertical OFD will be described. The vertical OFD configuration example shows a configuration in which the above-mentioned horizontal OFD storage circuits are connected in two stages in the vertical direction.

[0110] 1 and 29 includes, as pixel circuits 3, a plurality of pixel circuits 3b shown in Fig. 4 arranged in a matrix in a pixel array section 1. This configuration is suitable for the rolling shutter method.

[0111] Similarly, the solid-state imaging device 100 can also include a sample-and-hold circuit SH10 connected to the pixel circuit 3b in Fig. 5. This configuration is suitable for the global shutter system.

[0112] The pixel signal has at least two components: a reset component and a signal component.

[0113] The configuration example of the vertical OFD in Fig. 4 is different from the configuration example of the horizontal OFD in Fig. 2 in that the pixel circuit 3b is different. The sample-and-hold circuit SH10 is the same. The following description will focus on the differences.

[0114] The pixel circuit 3b includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, a transfer transistor TG, an amplifying transistor SF1, a reset transistor RS, a first storage capacitor element C1, a first gain control transistor GC1, a second storage capacitor element C2, and a second gain control transistor GC2. The pixel circuit 3b includes a selection transistor SEL_RS in the rolling shutter system of FIG. 4 but not in the global shutter system of FIG. 5.

[0115] The photodiode PD is a photoelectric conversion element that converts incident light into signal charge. The signal charge that overflows the photodiode PD during exposure is transferred to and held in the first storage capacitor element C1, as indicated by the dotted arrow D in Figures 4 and 5. Furthermore, the signal charge that overflows from the first storage capacitor element C1 is transferred to and held in the second storage capacitor element C2.

[0116] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and holds the signal charge generated in the photodiode PD. In Figures 4 and 5, the storage capacitance element of the charge storage unit FD0 is denoted by C0.

[0117] The amplification transistor SF1 outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0 to the vertical signal line 30A via the selection transistor SEL_RS.

[0118] The reset transistor RS resets the charge storage unit FD0. Specifically, the reset transistor RS can perform three types of resetting under the control of the first gain control transistor GC1 and the second gain control transistor GC2. That is, the reset transistor RS can reset the charge storage unit FD0, the first charge storage unit FD1, and the second charge storage unit FD2.

[0119] The first storage capacitor element C1 holds signal charges that overflow from the photodiode PD. For example, the first storage capacitor element C1 stores the signal charges that overflow from the photodiode PD during exposure via the transfer transistor TG and the first gain control transistor GC1.

[0120] The first gain control transistor GC1 is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitor element C1. The first gain control transistor GC1 acts as a switching element, taking an ON state and an OFF state. Note that the gate voltages of the transfer transistor TG and the first gain control transistor GC1 do not have to be completely OFF during exposure, and may be set so that signal charges overflowing from the photodiode PD can be transmitted from the transfer transistor TG to the first storage capacitor element C1 via the charge storage unit FD0 and the first gain control transistor GC1.

[0121] The second storage capacitor C2 holds the signal charge that has overflowed from the first storage capacitor C1. For example, the second storage capacitor C2 stores the signal charge that has overflowed from the first storage capacitor C1 via the second gain control transistor GC2.

[0122] The second gain control transistor GC2 is a gain control transistor that controls the connection between the first storage capacitor element C1 and the second storage capacitor element C2. The second gain control transistor GC2 acts as a switching element and is in an ON state and an OFF state. The gate voltage of the second gain control transistor GC2 does not have to be in a completely OFF state during exposure, and may be set so that signal charges overflowing from the first storage capacitor element C1 can be transmitted to the second storage capacitor element C2 via the second gain control transistor GC2.

[0123] In this way, the second configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the S / N ratio.

[0124] In the rolling shutter method, as shown in FIG. 4, a plurality of pixel signals from the pixel circuits 3b are read out row by row in a rolling manner, and the plurality of pixel signals are supplied to the detection selection circuit 450 via the vertical signal lines 30A.

[0125] In the global shutter system, a sample-and-hold circuit SH10 connected to the pixel circuit 3b can also be provided, as shown in Figure 5. This is particularly suitable for the global shutter system, as it exposes all pixels simultaneously, then simultaneously reads out the signals from all pixels to the sample-and-hold circuit SH10, and holds the pixel signals until the next rolling readout is performed for each row. In this case, too, the multiple pixel signals from the sample-and-hold circuit SH10 are read out for each row in a rolling readout, and the multiple pixel signals are supplied to the detection selection circuit 450 via the vertical signal line 30A.

[0126] According to this, when the first pixel signal HCG, the second pixel signal MCG, and the third pixel signal LCG are synthesized by the WDR synthesis circuit 76 using three frames each of the HCG for low illumination, the MCG for medium illumination, and the LCG for high illumination, each frame is exposed simultaneously, so no blurring or coloring occurs between frames.

[0127] The sample-and-hold circuit SH10 will be described in detail later.

[0128] [Example of sample and hold circuit configuration] An example of the sample-and-hold circuit SH10 will be described.

[0129] The sample-and-hold circuits SH10 are provided in a one-to-one correspondence with the pixel circuits 3a or 3b, and are primarily suitable for transferring multiple pixel signals from the pixel circuits 3a or 3b to all pixels simultaneously in a global shutter system.

[0130] In the sample-and-hold circuit SH10, the output of the amplification transistor SF1 of the pixel circuit 3a or 3b is connected to a vertical signal line 30B and further to sample-and-hold capacitance elements (C20, C21, C22, C23, C24, C25) via sample-and-hold switch elements (SH20, SH21, SH22, SH23, SH24, SH25), and is input to the gate of the amplification transistor SF2 via output selection switch elements (SE26, SE27, SE28, SE29, SE30, SE31).The output of the amplification transistor SF2 is connected to a vertical signal line 30A via a selection transistor SEL_GS.

[0131] The sample and hold switch elements SH (SH20, SH21, SH22, SH23, SH24, SH25) are switch transistors that are turned ON and OFF in response to a sample and hold switch control signal φSH. When the sample and hold switch control signal φSH is OFF, the sample and hold switch elements SH (SH20, SH21, SH22, SH23, SH24, SH25) hold pixel signals in the sample and hold capacitive elements C. In other words, the address selection when holding pixel signals in the sample and hold capacitive elements C is performed by the sample and hold switch control signal φSH.

[0132] The read selection switch elements SE (SE26, SE27, SE28, SE29, SE30, SE31) are switch transistors that are turned ON and OFF in response to a read selection switch element control signal φSE. When the read selection switch element control signal φSE is ON, the read selection switch elements SE (SE26, SE27, SE28, SE29, SE30, SE31) input the pixel signal held in the sample and hold capacitive element C to the gate of the amplifying transistor SF2. In other words, the address selection when reading out the pixel signal from the sample and hold capacitive element C is performed by the read selection switch element control signal φSE.

[0133] The selection transistor SEL_GS is a switch transistor that is turned on and off in response to a selection control signal φSEL_GS When the selection control signal φSEL_GS is at a high level, the selection transistor SEL_GS electrically connects the source of the amplification transistor SF2 to the vertical signal line 30A.

[0134] Here, the sample and hold capacitance element (C20) holds a signal of the reset component of HCG, while the sample and hold capacitance element (C21) holds a signal of the signal component of HCG.

[0135] The sample and hold capacitor (C22) holds the reset component signal of MCG, while the sample and hold capacitor (C23) holds the signal component signal of MCG.

[0136] The sample and hold capacitor (C24) holds the signal of the reset component of the LCG, while the sample and hold capacitor (C25) holds the signal of the signal component of the LCG.

[0137] Then, the reset component is subtracted from the signal component by the CDS of the AD conversion circuit, so that variations in the circuits such as the amplifier transistor SF1 and the amplifier transistor SF2 are cancelled out.

[0138] [Detection selection circuit configuration example] An example of the detection selection circuit 450 will be described.

[0139] The detection selection circuit 450 is composed of a selection circuit 400 that selects a signal from a plurality of pixel signals and has a sample-and-hold circuit SH412 that holds the plurality of pixel signals, and a first detection circuit 401 or a second detection circuit 402 that detects at least one pixel signal from the plurality of pixel signals.

[0140] First, a plurality of pixel signals from pixel circuit 3a or pixel circuit 3b, or sample and hold circuit SH10, are held in sample and hold circuit SH412.

[0141] First, an example of the sample-and-hold circuit SH412 will be described.

[0142] In the sample-and-hold circuit SH412, the output of the amplification transistor SF1 of the pixel circuit 3a or 3b, or the output of the amplification transistor SF2 of the sample-and-hold circuit SH10, is connected to the sample-and-hold capacitance elements (C30, C31, C32, C33, C34, C35) via the vertical signal line 30A by turning on the switch element SW0, and then input to the gate of the amplification transistor SF30 via the read selection switch elements (SE7, SE8, SE9, SE10, SE11, SE12). The output of the amplification transistor SF30 is connected to the vertical signal line 19B via the selection transistor SEL_DET.

[0143] The sample and hold switch elements (SH1, SH2, SH3, SH4, SH5, SH6) are switch transistors that are turned ON and OFF in response to a sample and hold switch control signal φSH. When the sample and hold switch control signal φSH is OFF, the sample and hold switch elements SH hold pixel signals in the sample and hold capacitive elements (C30, C31, C32, C33, C34, C35). In other words, the address selection when holding pixel signals in the sample and hold capacitive elements (C30, C31, C32, C33, C34, C35) is performed by the sample and hold switch control signal φSH.

[0144] The read selection switch elements (SE7, SE8, SE9, SE10, SE11, SE12) are switch transistors that are turned ON and OFF in response to a read selection switch element control signal φSE. When the read selection switch element control signal φSE is ON, the read selection switch element SE inputs pixel signals held in the sample and hold capacitance elements (C30, C31, C32, C33, C34, C35) to the gate of the amplification transistor SF30. In other words, the read selection switch element control signal φSE selects addresses when reading pixel signals from the sample and hold capacitance elements (C30, C31, C32, C33, C34, C35).

[0145] The selection transistor SEL_DET is a switch transistor that is turned on and off in response to a selection control signal φSEL_DET When the selection control signal φSEL_DET is at a high level, the selection transistor SEL_DET electrically connects the source of the amplification transistor SF30 to the vertical signal line 19B.

[0146] Here, the sample and hold capacitance element (C30) holds a signal of the reset component of HCG, while the sample and hold capacitance element (C31) holds a signal of the signal component of HCG.

[0147] The sample and hold capacitor (C32) holds the reset component signal of MCG, while the sample and hold capacitor (C33) holds the signal component signal of MCG.

[0148] The sample and hold capacitor (C34) holds the signal of the reset component of the LCG, while the sample and hold capacitor (C35) holds the signal of the signal component of the LCG.

[0149] Next, the first detection circuit 401 and the second detection circuit 402 compare the value obtained by subtracting the reset component (C32) from the MCG signal component (C33), which is the second pixel signal of the sample-and-hold circuit SH412, with the first reference value REF1 at the boundary between HCG and MCG and the second reference value REF2 at the boundary between MCG and LCG. This detects which gain the pixel signal belongs to: HCG, MCG, or LCG, and sends a signal selection signal 407 (φSE, φSH, φSW) to the selection circuit 400.

[0150] Next, in the selection circuit 400, the read selection switch element control signal φSE is controlled based on this signal selection signal 407 (φSE, φSH, φSW). For example, in the case of HCG, the read selection switch element SE7 is turned on to output the reset component to the vertical signal line 19B via the amplification transistor SF30 and the selection transistor SEL_DET, and similarly, the read selection switch element SE8 is turned on to output the signal component to the vertical signal line 19B.

[0151] Then, the reset component is subtracted from the signal component by the CDS of the AD conversion circuit, so that variations in the circuits of the amplifier transistor SF1, the amplifier transistor SF2, the amplifier transistor SF30, and the like are cancelled out.

[0152] This eliminates the redundant reading of all multiple signals, and instead selectively reads out at least one pixel signal from among multiple pixel signals, thereby providing higher speed and lower power consumption in subsequent stages including the AD converter.

[0153] [Configuration example of the first detection circuit] The first detection circuit 401 shown in Fig. 6A includes a comparator 411 and a comparator 419. Fig. 6B is a diagram illustrating the operation of the first detection circuit.

[0154] A first reference value (REF1) is input to one input terminal of the comparator 411 via the switch circuit SW15, and the reset component of the MCG signal, which is the second pixel signal, is first input to the other terminal to perform auto-zero (SW0, SH3, SW13, SW17, SW18 are turned ON), and then the reset component of the MCG signal, which is the second pixel signal, is input (SW0, SH4, SW14 are turned ON), and analog CDS is performed and compared.

[0155] At the same time, a second reference value (REF2) is input to one input terminal of the comparator 419 via the switch circuit SW16, and the reset component of the MCG signal, which is the second pixel signal, is first input to the other terminal to perform auto-zero (SW0, SH3, SW13, SW17, SW18 are turned ON), and then the signal component of the MCG signal, which is the second pixel signal, is input (SW0, SH4, SW14 are turned ON), and analog CDS is performed and compared.

[0156] When the second pixel signal (MCG signal) is smaller than the first reference value (REF1), the output of comparator 411 is L and the output of comparator 419 is H. As a result, the output of latch circuit 414 is H, the output of latch circuit 415 is L, and the output of latch circuit 416 is L. H signals of SE7 and SE8, which are output signals of latch circuit 414, are sent to selection circuit 400 as signal selection signals 407 (φSE, φSH, φSW) for selection. In other words, signal selection signals 407 (φSE, φSH, φSW) instruct selection circuit 400 to select the first pixel signal (HCG) held in sample-and-hold circuit SH.

[0157] When the second pixel signal (MCG signal) is between the first reference value (REF1) and the second reference value (REF2), the output of comparator 411 is H and the output of comparator 419 is H. As a result, the output of latch circuit 414 is L, the output of latch circuit 415 is H, and the output of latch circuit 416 is L. H signals of SE9 and SE10, which are output signals of latch circuit 415, are sent to selection circuit 400 as signal selection signals 407 (φSE, φSH, φSW) for selection. In other words, signal selection signals 407 (φSE, φSH, φSW) instruct selection circuit 400 to select the second pixel signal (MCG) held in sample-and-hold circuit SH.

[0158] When the second pixel signal (MCG signal) is greater than the second reference value (REF2), the output of comparator 411 is H and the output of comparator 419 is L. As a result, the output of latch circuit 414 is L, the output of latch circuit 415 is L, and the output of latch circuit 416 is H. H signals of SE11 and SE12, which are output signals of latch circuit 416, are sent to selection circuit 400 as signal selection signals 407 (φSE, φSH, φSW) and selected. In other words, signal selection signals 407 (φSE, φSH, φSW) instruct selection circuit 400 to select the third pixel signal (LCG) held in sample-and-hold circuit SH.

[0159] The signal selection signals 407 (φSE, φSH, φSW) are also sent as gain selection signals 403 to the voltage comparator 252 of the column AD circuit 25. Details will be described later.

[0160] According to this, one pixel signal can be detected using the MCG signal, which is the second pixel signal, and therefore the detection speed can be increased.

[0161] Furthermore, when detecting two signals, it will be HCG and MCG, or MCG and LCG. Therefore, the selection control circuit 410 always sends an H signal to SE9 and SE10 of MCG as the signal selection signal 407 (φSE, φSH, φSW) to select them. HCG and LCG are selected based on the above comparison results.

[0162] In addition, the gain selection signal 403 sent from the first detection circuit 401 to the AD conversion circuit 26 can also be used as the vertical signal line 19B from the selection circuit 400, and the gain selection signal 403 can be sent to the AD conversion circuit 26 before sending the selected pixel signal.

[0163] According to this, when selecting at least one pixel signal from multiple pixel signals for wide dynamic range function (WDR function) synthesis, it can be determined from the MCG signal alone. Therefore, there is no need to wait for the LCG signal to be read from the pixel circuit 3, so the LCG sample-and-hold capacitance elements (C34, C35) of the sample-and-hold circuit SH412 can be eliminated, and the layout area can be reduced. Furthermore, because the detection circuits (401, 402) perform comparison operations only for LCG, the circuit can be downsized, and the layout area can be reduced.

[0164] In addition, with a similar circuit configuration, it is also possible to detect one pixel signal by using the HCG signal, which is the first pixel signal, as the first reference value (REF3) and the MCG signal, which is the second pixel signal, as the second reference value (REF2).

[0165] According to this, when selecting at least one pixel signal from multiple pixel signals for wide dynamic range function (WDR function) synthesis, it can be determined from the HCG signal and the MCG signal. Therefore, since there is no need to wait for the LCG signal to be read from the pixel circuit 3, the LCG sample and hold capacitance elements (C34, C35) of the sample and hold circuit SH412 can be eliminated, and the layout area can be reduced.

[0166] Furthermore, when detecting two signals, the first detection circuit 401 detects two frames of HCG and MCG, or two frames of MCG and LCG. For this reason, the selection control circuit 410 should always select MCG, and the selection of HCG and LCG should be based on the above comparison results.

[0167] This allows the signal processing unit 70 to digitally mitigate the sudden change in signal-to-noise ratio (SN) at the frame boundary that occurs when combining frames in a wide dynamic range. The digital mitigation method is basically the same as the above-mentioned blending based on the WDR combination ratio.

[0168] Furthermore, when the gain selection signal 403 and the vertical signal line 19B are used together, the number of wires for the gain selection signal 403 can be reduced, and the layout area can be suppressed.

[0169] [Configuration example of the second detection circuit] 7 reduces the number of comparators to one and includes a comparator 421 and a latch circuit 423. The second detection circuit 402 inputs a first reference value (REF1) and a second reference value (REF2) to one input terminal of the comparator 421 while switching between them in time succession.

[0170] To the other end, first, the reset component of the MCG signal, which is the second pixel signal, is input in time order to perform auto-zero (SW0, SH3, SW13, SW17 are turned ON), and then the signal component of the MCG signal, which is the second pixel signal, is input (SW0, SH4, SW14 are turned ON), and analog CDS is performed and compared.

[0171] When the pixel signal is the first pixel signal (HCG), when the first reference value (REF1) is input, the output of the comparator 421 is L, the output of the latch circuit 423 is H, and the output of the INV circuit 424 is L. Next, when the second reference value (REF2) is input, the latch circuits 426 and 428 are reset, the output of the comparator 421 is L, the output of the latch circuit 423 holds H, and the output of the AND 425 is L. Therefore, the output of the latch circuit 426 is L, the output of the latch circuit 423 is H, and the output of the latch circuit 428 is L. The H signals of SE7 and SE8, which are output signals of the latch circuit 423, are sent to the selection circuit 400 as the signal selection signal 407 (φSE, φSH, φSW) and selected.

[0172] When the pixel signal is the second pixel signal (MCG), when the first reference value (REF1) is input, the output of the comparator 421 becomes H, the output of the latch circuit 423 becomes L, and the output of the INV circuit 424 becomes H. Next, when the second reference value (REF2) is input, the latch circuits 426 and 428 are reset, the output of the comparator 421 becomes L, the output of the latch circuit 423 holds L, and the output of the AND 425 becomes H. Therefore, the output of the latch circuit 426 becomes L, the output of the latch circuit 423 becomes L, and the output of the latch circuit 428 becomes H. The H signals of SE9 and SE10, which are output signals from the latch circuit 428, are sent to the selection circuit 400 as the signal selection signal 407 (φSE, φSH, φSW) and selected.

[0173] When the pixel signal is the third pixel signal (LCG), when the first reference value (REF1) is input, the output of the comparator 421 becomes H, the output of the latch circuit 423 becomes L, and the output of the INV circuit 424 becomes H. Next, when the second reference value (REF2) is input, the latch circuits 426 and 428 are reset, the output of the comparator 421 becomes H, the output of the latch circuit 423 holds L, and the output of the AND 425 becomes L. Therefore, the output of the latch circuit 426 becomes H, the output of the latch circuit 423 becomes L, and the output of the latch circuit 428 becomes L. The H signals of SE11 and SE12, which are output signals of the latch circuit 426, are sent to the selection circuit 400 as the signal selection signal 407 (φSE, φSH, φSW) and selected.

[0174] The signal selection signals 407 (φSE, φSH, φSW) are also sent as gain selection signals 403 to the voltage comparator 252 of the column AD circuit 25. Details will be described later.

[0175] According to this, one pixel signal can be detected using the MCG signal, which is the second pixel signal, and therefore the detection speed can be increased.

[0176] According to this, when selecting at least one pixel signal from multiple pixel signals for wide dynamic range function (WDR function) synthesis, it can be determined from the MCG signal alone. Therefore, there is no need to wait for the LCG signal to be read from the pixel circuit 3, so the LCG sample-and-hold capacitance elements (C34, C35) of the sample-and-hold circuit SH412 can be eliminated, and the layout area can be reduced. Furthermore, because the detection circuits (401, 402) perform comparison operations only for LCG, the circuit can be downsized, and the layout area can be reduced.

[0177] Furthermore, when detecting two signals, the same as in the above [Configuration example of second detection circuit] is used.

[0178] [Configuration example for speeding up the detection and selection circuit] A description will be given of an example of a configuration for increasing the speed of the detection and selection circuit 450. As described above, an example of the configuration and timing of the detection and selection circuit 450 made up of the selection circuit 400 and the detection circuit 401 has been explained, and an increase in speed will now be described.

[0179] In the above method, multiple pixel signals are held in the sample-and-hold circuit SH412, and these pixel signals are used for detection by the detection circuit 401. The signal selection signal 407 (φSE) selected by the selection control circuit 410 is used to perform a readout operation for each row in the selection circuit 400. Therefore, the "operation of holding multiple pixel signals," the "operation of detecting at least one pixel signal," and the "operation of reading out the selection signal" are performed in series in terms of time, which causes an increase in the time required.

[0180] As a countermeasure, although there is one detection selection circuit 450 in FIGS. 10 and 30, there are configuration examples in which two or more detection selection circuits are provided as shown in FIGS. 11 and 31, which are methods of increasing speed by performing "an operation of holding a plurality of pixel signals," "an operation of detecting at least one pixel signal," and "an operation of reading out a selected pixel signal" in parallel.

[0181] First, multiple pixel signals from a certain row are input from the vertical signal line 30A to the first of the multiple detection selection circuits 450 via the switch element SW0, which is turned OFF after input. Then, multiple pixel signals from the next row are input from the vertical signal line 30A to the second of the multiple detection selection circuits 450 via the switch element SW0, which is turned OFF after input. Then, as necessary, they are input to the third detection selection circuit 450 via the switch element SW0, which is turned OFF after input.

[0182] For these multiple input signals, each detection selection circuit 450 performs "an operation of holding multiple pixel signals," "an operation of detecting at least one pixel signal," and "an operation of reading out a selected pixel signal" in parallel, and outputs the selected pixel signal to the vertical signal line 19B via the amplification transistor SF30 and the switch element SEL_DET. This type of control can achieve high speed.

[0183] At this time, the switch elements SW0 that input pixel signals to the plurality of detection selection circuits 450 are turned ON / OFF exclusively.

[0184] This allows the first detection circuit 401 or the second detection circuit 402 to perform detection while the other selection circuit 400 is performing selection and output, thereby realizing faster operation in the detection selection circuit 450.

[0185] [Column AD circuit configuration example] An example of the configuration of the column AD circuit 25 will be described with reference to FIG.

[0186] The reference signal generating unit 22, which supplies a RAMP signal as a reference signal to the column AD circuit 25, simultaneously generates RAMP signals (RAMP1, RAMP2, RAMP3) having analog gains corresponding to HCG, MCG, and LCG.

[0187] Each RAMP signal is configured to be supplied to the voltage comparator 252 via a selection switch (SW260, SW261, SW262), and the selection switch element (SW260, SW261, 262) is selected according to the gain selection signal 403 from the first detection circuit 401 or the second detection circuit 402 and supplied to the voltage comparator 252.

[0188] For example, if there is only one RAMP signal line, three RAMP signals (HCG, MCG, and LCG) are generated in time series, which makes it impossible to increase speed. Alternatively, if the gains are the same, noise increases and accuracy deteriorates. In contrast, the reference signal generator 22 simultaneously generates three RAMP signals and sets analog gains for each, allowing for both increased speed and reduced noise.

[0189] [Expanded dynamic range] A feature of this embodiment is that the exposure control of the three frames of high-illuminance exposure, medium-illuminance exposure, and high-illuminance exposure that combine WDR is performed using the global shutter method and the rolling shutter method, with exposure occurring at exactly the same timing and using exactly the same pixels, eliminating false colors, coloring, and blurring.

[0190] For pixel signals in frames in low-light areas (low-light exposure), the in-pixel gain is set to high (HCG), for pixel signals in frames in medium-light areas (medium-light exposure), the in-pixel gain is set to medium (MCG), and for pixel signals in frames in high-light areas (high-light exposure), the in-pixel gain is set to low (LCG), thereby improving noise in low light and expanding the dynamic range in high light.

[0191] Figure 13A shows an overview of the WDR in-pixel synthesis method. Figure 25 shows an example of the configuration of a signal processing unit that performs WDR synthesis using three frames. For WDR, the low-illuminance exposure in Figure 13A is set by HCG and the signal charge is Q0, the medium-illuminance exposure is set by MCG and the signal charge is (Q0 + Q1), and the high-illuminance exposure is set by LCG and the signal charge is (Q0 + Q1 + Q2). The horizontal axes (1), (2), (3), and (4) in Figure 13A represent the product of illuminance and exposure time, illuminance for a fixed time, or exposure time at a fixed illuminance. On the vertical axis, (1) represents the charge accumulation level, (2) represents the signal potential of the pixel unit, (3) represents the value after AD conversion, and (4) represents the SN level.

[0192] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are shown in (3) and (4) of Figure 13A. The "illuminance vs. exposure time" at the boundary between low-illuminance exposure and medium-illuminance exposure corresponds to the charge Q0' immediately before the charge Q0 saturates in (1) and corresponds to the signal potential FDH of the pixel unit in (2). The "illuminance vs. exposure time" at the boundary between medium-illuminance exposure and high-illuminance exposure corresponds to the charge Q0+Q1' immediately before the charge Q0+Q1 saturates in (1) and corresponds to the signal potential FDM of the pixel unit in (2). Furthermore, the "illuminance vs. exposure time" at the maximum high-illuminance exposure corresponds to the charge Q0+Q1+Q2' immediately before the charge Q0+Q1+Q2 saturates in (1) and corresponds to the signal potential FDL of the pixel unit in (2).

[0193] According to this, the pixel signal of the first low-illuminance frame (low-illuminance exposure), the pixel signal of the second medium-illuminance frame (medium-illuminance exposure), and the pixel signal of the third high-illuminance frame (high-illuminance exposure) are combined to realize a wide dynamic range function (WDR function), i.e., the dynamic range is expanded.

[0194] The signal processing unit 70 in FIG. 25 includes a memory 77, an interpolation circuit 71, and a WDR synthesis circuit 76.

[0195] The memory 77 stores pre-measured data, such as gain ratios or sensitivity ratios of pixel values ​​of the HCG signal, MCG signal, and LCG signal corresponding to illuminance and exposure time. For example, the memory 77 stores Gain1 and Gain2 shown in (3) of FIG. 13A. Gain1 is the gain ratio between the MCG signal and the HCG signal. Gain2 is the gain ratio between the LCG signal and the HCG signal. The gain ratio between the LCG signal and the MCG signal may be calculated by Gain2 / Gain1, or a pre-measured value may be stored. In this way, once one value of the HCG signal, MCG signal, and LCG signal is identified, the other two values ​​can be calculated by interpolation using the above gain ratios. The memory 77 may store sensitivity ratios instead of gain ratios.

[0196] The interpolation circuit 71 uses interpolation processing to determine pixel values ​​of two pixel signals not selected from the three pixel signals, the HCG signal, the MCG signal, and the LCG signal, based on one pixel signal selected by the selection circuit 400. The pixel values ​​of the two pixel signals not selected by the selection circuit 400 are determined by interpolation processing in the interpolation circuit 71 and input to the WDR synthesis circuit 76. The interpolation processing here means interpolation or estimation.

[0197] The WDR synthesis circuit 76 synthesizes the three pixel signals linearly based on the pixel signal selected by the selection circuit 400 and the two pixel signals obtained by the interpolation process of the interpolation circuit 71, using the gain ratio or sensitivity ratio data in the memory 77.

[0198] For example, when the pixel value PH of the pixel signal surrounded by the HCG signal in the dashed-dotted line frame in FIG. 13B is selected, the MCG signal and the LCG signal are obtained by interpolation processing from the gain ratio or sensitivity ratio of the memory 77.

[0199] Similarly, when the pixel value PM of the pixel signal surrounded by the MCG signal in the dashed-dotted line frame in FIG. 13B is selected, the HCG signal and the LCG signal are obtained by interpolation processing from the gain ratio or sensitivity ratio of the memory 77.

[0200] Similarly, when the pixel value PL of the pixel signal surrounded by the LCG signal in the dashed-dotted frame in FIG. 13B is selected, the HCG signal and the MCG signal are obtained by interpolation processing from the gain ratio or sensitivity ratio of the memory 77.

[0201] Similarly, the interpolation circuit 71 can also determine the pixel value of one pixel signal that was not selected by interpolation processing based on two pixel signals selected by the selection circuit 400 out of the three pixel signals, namely, the HCG signal, the MCG signal, and the LCG signal.

[0202] In this way, the signal processing unit 70 obtains one of the pixel values ​​PH of the HCG signal, the pixel values ​​PM of the MCG signal, and the pixel values ​​PL of the LCG signal as the signal selected by the selection circuit 400. Furthermore, the signal processing unit 70 obtains two of the pixel values ​​PH of the HCG signal, the pixel values ​​PM of the MCG signal, and the pixel values ​​PL of the LCG signal by interpolation using the interpolation circuit 71. The signal processing unit 70 combines the three pixel values ​​obtained in this way so that they are linear, thereby obtaining a linear digital pixel signal of (3) in FIG. 13A corresponding to the mixed charge of (1) in FIG. 13A.

[0203] It is preferable to prevent the SN of the subject from changing suddenly near the boundary between low-illuminance exposure and medium-illuminance exposure, or the boundary between medium-illuminance exposure and high-illuminance exposure, as much as possible.

[0204] [Regarding the first and second standard values] The first reference value and the second reference value will be described while referring to FIG. 13A.

[0205] When synthesizing three frames consisting of the first pixel signal HCG (low illuminance exposure), the second pixel signal MCG (medium illuminance exposure), and the third pixel signal LCG (high illuminance exposure), the first reference values (REF1, REF3) of the first detection circuit 401 or the second detection circuit 402 are the values at the boundary between the first pixel signal HCG (low illuminance exposure) and the second pixel signal MCG (medium illuminance exposure). The second reference value (REF2) of the first detection circuit 401 or the second detection circuit 402 is the value at the boundary between the second pixel signal MCG (medium illuminance exposure) and the third pixel signal LCG (high illuminance exposure).

[0206] (i) The method for setting each of the first reference values (REF1, REF2) will be described.

[0207] The "illuminance · exposure time" at the boundary between low illuminance exposure and medium illuminance exposure is set as REF1', and the "illuminance · exposure time" at the boundary between medium illuminance exposure and high illuminance exposure is set as REF2'. These correspond to REF1 and REF2 of LCG in terms of the signal potential of the pixel portion in (2). The signal potential REF1 of LCG is indicated by the "A point" and corresponds to the charge Q0' immediately before the charge Q0 of the first pixel signal in (1) saturates. The signal potential REF2 of LCG is indicated by the "B point" and corresponds to the charge Q0 + Q1' immediately before the charge Q0 + Q1 of the second pixel signal in (1) saturates.

[0208] · When it is the first pixel signal HCG (low illuminance exposure), it is when "the signal potential of LCG < REF1 of LCG".

[0209] · When it is the second pixel signal MCG (medium illuminance exposure), it is when "REF1 of LCG < the signal potential of LCG < REF2 of LCG".

[0210] · When it is the third pixel signal LCG (high illuminance exposure), it is when "REF2 of LCG < the signal potential of LCG".

[0211] (ii) The method for setting each of the second reference values (REF3, REF2) will be described.

[0212] The "illuminance · exposure time" at the boundary between low illuminance exposure and medium illuminance exposure is set as REF1', and the "illuminance · exposure time" at the boundary between medium illuminance exposure and high illuminance exposure is set as REF2'. These correspond to REF3 and REF2 of LCG in terms of the signal potential of the pixel section in (2). The signal potential REF3 of HCG is indicated by the "C point" and corresponds to the charge Q0' immediately before the charge Q0 of the first pixel signal in (1) saturates. The signal potential REF2 of LCG is indicated by the "B point" and corresponds to the charge Q0 + Q1' immediately before the charge Q0 + Q1 of the second pixel signal in (1) saturates.

[0213] · When it is the first pixel signal, i.e., HCG (low illuminance exposure), it is when "the signal potential of HCG < REF3 of HCG".

[0214] · When it is the second pixel signal, i.e., MCG (medium illuminance exposure), it is when "REF3 of HCG < the signal potential of HCG" and "the signal potential of LCG < REF2 of LCG". <H

[0215] · When it is the third pixel signal, i.e., LCG (high illuminance exposure), it is when "REF2 of LCG < the signal potential of LCG".

[0216] According to this, the pixel signals of the first low illuminance frame (low illuminance exposure), the second medium illuminance frame (medium illuminance exposure), and the third high illuminance frame (high illuminance exposure) are combined to realize the wide dynamic range function (WDR function), that is, the dynamic range is expanded

[0217] [Regarding the hysteresis function of reference values] The temporal hysteresis function of each of the reference values REF1, REF2, REF3 shown in Fig. 13A will be described. Although Fig. 28 describes the case when the reference values REF1, REF2 are used, the concept is the same for the case when the reference values REF3, REF2 are used.

[0218] 28 shows an example in which disturbance noise is superimposed on the MCG signal. Conversely, there may be a case in which disturbance noise is superimposed on the reference value.

[0219] The reference values ​​REF1 and REF2 are boundary values ​​between low-light exposure frames (HCG), medium-light exposure frames (MCG), and high-light exposure frames (LCG). Therefore, if the reference values ​​REF1 and REF2 are always constant over time, as shown in the figure, the signal level may become high (signal A) or low (signal B) due to slight disturbance noise and shot noise superimposed on the MCG signal in the second or Nth frame, resulting in a possible misjudgment. In other words, what should be correctly judged as MCG may be erroneously judged as HCG or LCG. In this case, even though the subject is the same, the gain may be switched to one of these, resulting in images with different SN for each frame due to the influence of SN changes at the boundary.

[0220] For this reason, when the gains are the same, it is preferable to configure the reference values ​​REF1 and REF2 of the current frame to have hysteresis, with a different voltage from that of the previous frame. For example, as shown in the figure, if the previous frame is the 1st frame or the N-1th frame, then in the 2nd or Nth frame of the current frame, if temporal hysteresis is provided so that the first reference value REF1M is a voltage (signal B) slightly lower than REF1 and the second reference value REF2P is a voltage (signal A) slightly higher than REF2, erroneous determinations will be eliminated. In other words, what should correctly be determined as MCG will be correctly determined as LCG even in the presence of external noise.

[0221] In FIG. 8, the voltage supplied from the gain reference signal generating unit 40 is given first reference values ​​REF1, REF1P, REF1M and second reference values ​​REF2, REF2P, REF2M and is supplied to the switch circuit SW15 and switch circuit SW16 of the first detection circuit 401 or the second detection circuit 402, and the optimum reference value is selected by the hysteresis selection signal 404 described later.

[0222] In the signal processing unit 90, gain information for at least the previous frame for all pixels is stored in the frame memory 97 via a gain selection signal 403. Based on this information, the control unit 96 performs the following signal processing flow to select an optimal reference value for the current frame. This information is supplied to the first detection circuit 401 or the second detection circuit 402 via a hysteresis selection signal 404 as gain information for the current frame.

[0223] Next, we will explain the flow of signal processing in the control unit 96. The basic temporal hysteresis is a configuration in which the signal range of the same gain in the current frame is wider than the signal range in the previous frame.

[0224] First, REF1 at the boundary between HCG and MCG will be described. If the previous frame is HCG, the current frame will have a voltage REF1P that is slightly higher than REF1. If the previous frame is MCG, the current frame will have a voltage REF1M that is slightly lower than REF1.

[0225] Next, REF2 at the boundary between MCG and LCG will be described. If the previous frame is MCG, the voltage in the current frame is REF2P, which is slightly higher than REF2. If the previous frame is LCG, the voltage in the current frame is REF2M, which is slightly lower than REF2.

[0226] Furthermore, the signal that has been subjected to the above-mentioned control by the control unit 96 based on the frame memory 97 of the previous frame of all pixels is passed through the column AD circuit 25 and, using the hysteresis selection signal 404, selects the switch circuit SW15 (SW15A, SW15B, SW15C) and switch circuit SW16 (SW16A, SW16B, SW16C) of each pixel, so that hysteresis can be provided.

[0227] This makes it possible to mitigate sudden changes in signal-to-noise ratio between frames that occur when pixel signal levels at the boundaries between HCG and MCG, or between MCG and LCG, are close to the reference value due to noise superposition or the like, resulting in erroneous determination when combining with the wide dynamic range function (WDR function).

[0228] [Signal selection in units of color filter array] Signal selection in units of color filter arrays will be explained using a typical Bayer array of four colors (R·Gr·B·Gb) as an example.

[0229] First, each reference value (REF1, REF2, REF3) is configured to have a function of changing in conjunction with the analog gain or the digital gain.

[0230] This allows each frame to be composed over a wide dynamic range, even when the analog or digital gain of each color is varied by AE control. This is particularly important when adjusting the gain for each color when the white balance changes due to a change in the color temperature of the subject.

[0231] Next, the relationship between the first reference value REF1, the second reference value REF2, and the color filters will be described with reference to FIG. 13A.

[0232] First, for example, in the case of a Bayer array, the sensitivity differs among the four colors (R, Gr, B, Gb), with Gr or Gb having the greatest sensitivity and B and R having lower sensitivity. Therefore, the reference values ​​REF1' and REF2' for Gr or Gb are lower than those for B and R. In conjunction with this, the voltage levels of the reference values ​​REF1, REF2, and REF3 for each color change.

[0233] There are two ways to synthesize WDR.

[0234] (i) The first is a pattern in which, in the case of a Bayer array, three frames are synthesized using the maximum signal gain of the four colors (R, Gr, B, Gb) shown in the bold frame in Figure 27.

[0235] In this case, the detection and selection circuit 450 has four colors (R, Gr, B, Gb) and matches the color with the highest maximum signal level. For example, if the color with the highest maximum signal level is Gr and is detected as LCG, the other three colors (R, B, Gb) are also set to LCG. For example, if the color with the highest maximum signal level is R and is detected as MCG, the other three colors (Gr, B, Gb) are also set to MCG.

[0236] This means that the gain is the same for each color filter array, for example, a Bayer array consisting of four colors, so there is no coloring due to deviations in the linearity of each color that may occur when the gains differ for each color.Even if the gain of each color changes due to AE control, the reference values ​​REF1' and REF2' at the boundary always change in tandem using the maximum signal level of the four colors (R, Gr, B, Gb) at the SN level (4) in Figure 13A.Since the gains of each color (HCG, MCG, LCG) are the same before and after the WDR boundary, coloring due to deviations in the linearity of each color does not occur.

[0237] (ii) The second pattern is a Bayer array pattern in which three frames are individually synthesized using individual gains for the four color (R, Gr, B, Gb) signals shown in Figure 26. Even when the gain for each color changes due to AE operation, the reference values ​​REF1' and REF2' at the boundary between the four colors (R, Gr, B, Gb) always change independently at the SN level (4) in Figure 13A. In this case, there are detection selection circuits 450 for the four colors (R, Gr, B, Gb), and each detects HCG, MCG, and LCG at its respective signal level.

[0238] According to this, the merit of WDR is that it can maximize the reference values ​​REF1' and REF2' for each color, resulting in a good SN ratio.

[0239] [About exposure time] The photodiode PD, the first storage capacitor element C1, and the second storage capacitor element C2 store electric charges of which amounts Q0, Q1, and Q2, respectively, as they continue to be exposed for a desired exposure period.

[0240] (i) In the rolling shutter method, all pixels are scanned row by row, shuttered, and exposure begins. Since each exposure period is the same, the exposure time is T_Q0 = T_Q1 = T_Q2. Next, charge is read from the photodiodes by scanning row by row to the sample and hold capacitance elements (C30, C31, C32, C33, C34, C35) of the sample and hold circuit SH412 in the detection selection circuit 450, and is read out for the selected row. After that, the selected pixel signals are read out row by row in a rolling manner.

[0241] (ii) In the global shutter method, a global reset is performed on all pixels simultaneously, and exposure starts. Since each exposure period is the same, the exposure time is T_Q0 = T_Q1 = T_Q2. Next, the charge from the photodiode is read out to the sample and hold capacitance elements (C20, C21, C22, C23, C24, C25) simultaneously for all pixels. After that, the signal charge in the sample and hold capacitance elements (C20, C21, C22, C23, C24, C25) is read out row by row in a rolling manner.

[0242] Next, this signal charge is read out for the row selected by scanning row by row into the sample and hold capacitance elements (C30, C31, C32, C33, C34, C35) of the sample and hold circuit SH412 in the detection selection circuit 450. After that, the selected pixel signals are read out row by row in a rolling manner.

[0243] According to this, when the first pixel signal HCG, the second pixel signal MCG, and the third pixel signal LCG are synthesized by the WDR synthesis circuit 76 into three frames each of the HCG for low illumination, the MCG for medium illumination, and the LCG for high illumination, each frame is exposed simultaneously, so no blurring or coloring occurs between frames.

[0244] [WDR boundary blending] When one pixel signal is selected from multiple pixel signals, there is a large change in SN at the boundary between HCG and MCG and at the boundary between MCG and LCG, as shown by the SN level (4) in Fig. 13A. Therefore, even for the same subject, there is a possibility that the SN perception will change depending on which gain is selected.

[0245] One way to address this issue is to blend the HCG and MCG signals from just before the boundary between the HCG and MCG, and select this blended signal as a single pixel signal to mitigate the S / N noise at the boundary.A similar method can also be used to mitigate the S / N noise at the boundary between MCG and LCG.

[0246] 9 shows a configuration in which the sample and hold circuit SH430 provided in the selection circuit 400, which holds signals of each gain of the sample and hold circuit SH412, is provided with a plurality of sets of sample and hold elements (SH, C, SE). In this example, this does not apply only to the reset component of HCG, but shows that the sample and hold circuit SH430 is provided for six sets of signal components and reset components of all gains. Furthermore, the sample and hold circuit SH430 is provided with, for example, four times as many sets of each of the sample and hold switch elements (SH), sample and hold capacitance elements (C), and read selection switch elements (SE) that constitute the sample and hold circuit SH412.

[0247] Furthermore, with regard to the sample and hold capacitance elements (C), the ratio between HCG (C30, C31), MCG (C32, C33), and LCG (C34, C35) is set to the inverse ratio of the gain (FD conversion gain (μV / ele)) in the charge storage section (FD0). This is because the charge of the sample and hold capacitance elements is given by ΔQ = C x ΔV, and the signal voltage ΔV of each gain is determined by the FD conversion gain ratio. Therefore, if the capacitance value C is set to the inverse ratio of the FD conversion gain ratio, the charge Q will be equal, and they can be mixed equally, independent of the gains of HCG, MCG, and LCG.

[0248] First, the blending ratio of HCG and MCG in WDR will be explained using FIG. 14A. <s1>The reference value (voltage) at the boundary between HCG and MCG is changed to, for example, VREF1A, VREF1, and VREF1B, and the MCG voltage is monitored and latched. <s2>The blending ratio is determined according to the voltage of the MCG. <s3>Based on the above ratio, the charges of HCG and MCG are mixed in the sample-and-hold circuit SH412 which includes the sample-and-hold circuit SH430.

[0249] Next, the blending ratio of MCG and LCG in WDR will be described with reference to FIG. 14B. <s1>The reference value (voltage) at the boundary between MCG and LCG is changed to, for example, VREF2A, VREF2, and VREF2B, and the MCG voltage is monitored and latched. <s2>The blending ratio is determined according to the voltage of the MCG. <s3>Based on the above ratio, the charges of MCG and LCG are mixed in the sample-and-hold circuit SH412 which includes the sample-and-hold circuit SH430.

[0250] Next, a method for blending HCG and MCG will be described with reference to (2) and (4) of Figure 13A and Figure 14C.

[0251] For example, if REF1A' (REF1A) has a signal level lower than that of (2) and (4) in Figure 13A and the boundary portion REF1' (REF1) between HCG and MCG in Figure 14C, the signal components can be mixed by mixing C100+C101+C102+C103 of HCG without mixing the charge of MCG, and the combination ratio can be HCG:MCG = 4:0. Similarly, if the signal level is slightly lower than that of the boundary portion REF1' (REF1), the signal components can be mixed by mixing C100+C101+C102 of HCG and the charge of C100 of MCG, and the combination ratio can be HCG:MCG = 3:1. Similarly, at the boundary REF1' (REF1) between HCG and MCG, the signal components can be mixed at a combination ratio of HCG:MCG = 2:2 by mixing the charges of C100+C101 of HCG and C100+C101 of MCG. Similarly, at a signal level slightly higher than at the boundary REF1' (REF1), the signal components can be mixed at a combination ratio of HCG:MCG = 1:3 by mixing the charges of C100 of HCG and C100+C101+C102 of MCG. Similarly, at REF1B' (REF1B) (Q0 is almost at the saturation level), which is a signal level higher than at the boundary REF1' (REF1) between HCG and MCG, the signal components can be mixed at a combination ratio of HCG:MCG = 0:4 by mixing the charges of C100+C101+C102+C103 of MCG without mixing the charges of HCG.

[0252] Next, a method for blending MCG and LCG will be described with reference to (2) and (4) of Figure 13A and Figure 14C.

[0253] For example, at REF2A' (REF2A), which has a lower signal level than the boundary REF2' (REF2) between the MCG and LCG in (2) and (4) of FIG. 13A and FIG. 14C, the signal components can be mixed at a mixing ratio of MCG:LCG = 4:0 without mixing C100+C101+C102+C103 of the MCG and the charge of the MCG. Similarly, at a signal level slightly lower than the boundary REF1' (REF1), the signal components can be mixed at a mixing ratio of MCG:LCG = 3:1 by mixing the charge of C100+C101+C102 of the MCG and the charge of C100 of the LCG. Similarly, at the boundary REF2' (REF2) between the MCG and LCG, the signal components can be mixed at a mixing ratio of MCG:LCG = 2:2 by mixing the charge of C100+C101 of the MCG and the charge of C100+C101 of the LCG. Similarly, at a signal level slightly higher than that of the boundary REF2' (REF2), the signal component can mix the charges of C100 of the MCG and C100+C101+C102 of the LCG at a combination ratio of MCG:LCG = 1:3. Similarly, at REF2B' (REF2B) (Q0+Q1 is almost at a saturation level), which is a signal level higher than that of the boundary REF2' (REF2) between the MCG and LCG, the signal component can mix the charges of C100+C101+C102+C103 of the LCG without mixing any charges of the MCG, at a combination ratio of MCG:LCG = 0:4.

[0254] According to this, when combining wide dynamic range functions (WDR functions), the signals are gently mixed (blended) at the boundary between HCG and MCG, and at the boundary between MCG and LCG, and this mixed (blended) signal is selected as the pixel signal, thereby mitigating the S / N sensation at the boundary. Similarly, the reset component is mixed at the same ratio.

[0255] [Noise reduction at the borders of WDR] When one pixel signal is selected from multiple pixel signals, there is a large change in SN at the boundary between HCG and MCG and at the boundary between MCG and LCG, as shown by the SN level (4) in Fig. 13A. Therefore, a large change in SN sensation appears depending on which gain is selected.

[0256] To address this issue, the noise reduction ratio in the signal processing unit is determined according to the digital signal level of each MCG or HCG around the first reference value (REF1, REF3) in (3) of Figure 13A, and noise reduction is performed for the HCG and MCG.

[0257] Similarly, the noise reduction ratio in the signal processing unit is determined according to the digital signal level of the MCG around the second reference value (REF2) in FIG. 13A (3), and noise reduction is performed for the MCG and LCG.

[0258] According to this, when combining wide dynamic range functions (WDR functions), digital noise reduction is performed, thereby mitigating the sudden change in SN at the boundary between HCG and MCG, and at the boundary between MCG and LCG.

[0259] [Read operation example] Next, we will explain the HCG (High Conversion Gain) readout operation in the solid-state imaging device 100 of the pixel circuit 3 in Figure 1. The HCG readout operation uses only the charge storage unit FD0 to store signal charges and increases the conversion gain of the amplification transistor SF1. Therefore, the HCG operation is a high-sensitivity imaging operation that is suitable for imaging in low-illumination environments.

[0260] In the HCG readout operation, CDS (Correlated Double Sampling) reads out the kTC noise of the analog pixel signal, and then reads out the signal level. CDS calculates the difference between the kTC noise and the signal level.

[0261] [Explanation of timing chart (RS)] An example of the timing of the signal readout operation when multiple pixel signals are read out for each row using the rolling shutter method for pixel circuit 3a of the horizontal OFD in Fig. 2 and at least one pixel signal is selected for selection circuit 400 in detection selection circuit 450 in Fig. 6A and Fig. 7 will be described using Fig. 15. Here, two pixel signals (times t115 to t119 and time t119 to t123) are selected in Fig. 15, but one pixel signal may also be selected.

[0262] First, at time t100, the photodiodes PD, FD0, GC1, and GC2 are reset and exposure is started. Then, at time t101, the shutter is operated and exposure begins. At time t102, the exposure time ends.

[0263] Next, (1) at time t102, RS and GC1 are turned ON to reset FD0, entering the readout period for the reset component of MCG. At this time, auto-zero (SW0, SH3, SW13, SW17, and SW18 are ON) is performed while the reset component from pixel circuit 3 is directly input. Next, (2) at time t104, GC1 is turned OFF to enter the readout period for the reset component of HCG. Next, (3) at time t106, TG is turned ON to transfer the signal charge accumulated in the photodiode to FD0 using the transfer signal (TG), entering the readout period for the signal component (Q0) of HCG. Next, (4) at time t108, TG and GC1 are turned ON to transfer the signal charge overflowing from FD0 to storage capacitor C1 using GC1, entering the readout period for the signal component (Q0+Q1) of MCG. At this time, the MCG signal component from pixel circuit 3 is directly input to one input terminal of each of comparators 411 and 419 (SW0, SH4, and SW14 are ON), and simultaneously, a reference value (REF1) and a reference value (REF2) are input to the other input terminal of each of comparators 411 and 419 (SW15 and SW16 are ON). In first detection circuit 401, multiple comparators 411 and 419 input simultaneously and compare (time t109A), or in second detection circuit 402, a single comparator 421 inputs continuously and compares (times t109A and t109B). Next, (5) at time t110, TG, GC1, and GC2 are turned ON, and the charge in storage capacitor C2 is transferred to FD0 by GC2, entering the readout period of LCG signal component (Q0+Q1+Q2). Next, (6) at time t112, RS, GC1, and GC2 are turned ON to enter the read period of the reset component of LCG.

[0264] In this way, at times t103, t105, t107, t109, t111, and t113, the control signal φSH of the sample and hold switch elements (SH3, SH1, SH2, SH4, SH6, and SH5) is turned ON, thereby connecting the sample and hold capacitance elements (C32, C30, C31, C33, C35, and C34) to the vertical signal line 30A. As a result, the output signal of the pixel circuit 3a is held in the sample and hold capacitance elements (C32, C30, C31, C33, C35, and C34).

[0265] Here, the read selection switch element φSE is always in the OFF state.

[0266] The comparison result is then latched and sent to the selection circuit 400 via the selection control circuit 410, which selects one or two signals from the plurality of pixel signals (three signals in this example).

[0267] After the above (6), the operation of the detection selection circuit 450 may be started. The operation and timing of the first detection circuit 401 are described in [Configuration Example of the First Detection Circuit], and the second detection circuit 402 is described in [Configuration Example of the Second Detection Circuit].

[0268] Next, signal readout from the sample-and-hold circuit SH412 will be described. Here, SEA and SEC represent the read selection switch element control signal φSE of one of SE7, SE9, and SE11 selected for the reset component. SEB and SED represent the read selection switch element control signal φSE of one of SE8, SE10, and SE12 selected for the signal component. As a result, the sample-and-hold capacitance elements C30, C32, and C34 for the reset component are selected by the read selection switch element control signal φSE. Similarly, the sample-and-hold capacitance elements C31, C33, and C35 for the signal component are selected by the read selection switch element control signal φSE.

[0269] Although an example in which two pixel signals are selected is shown here, if one pixel signal is selected, the process is completed at time t119, and the steps from t119 to t123 are omitted.

[0270] First, the control signal φSE of the read selection switch element SEA is turned ON (21) at time t115, and the reset component held in the sample and hold capacitance element of the first signal of the selected pixel signal is read out and transferred via the amplification transistor SF30. The control signal φSE of the read selection switch element SEB is turned ON (22) at time t117, and the signal component held in the sample and hold capacitance element of the first signal of the selected pixel signal is read out and transferred via the amplification transistor SF30.

[0271] Next, the control signal φSE of the read selection switch element SEC is turned ON (23) at time t119, so that the reset component held in the sample and hold capacitance element of the second signal of the selected pixel signal is read out and transferred via the amplification transistor SF30, and the control signal φSE of the read selection switch element SED is turned ON (24) at time t121, so that the signal component held in the sample and hold capacitance element of the second signal of the selected pixel signal is read out and transferred via the amplification transistor SF30.

[0272] Here, at times t116, t118, t120, and t122, the charge accumulated in the parasitic capacitance of the gate of the amplification transistor SF30 may be discharged by the switch element SW21.

[0273] Here, regarding the readout order of signals from the sample-and-hold capacitance elements, there is no particular rule for the readout order of each gain, and any readout order is acceptable. Preferably, since CDS is performed, the order is reset component and signal component for each gain.

[0274] Here, among a plurality of pixel signals, one pixel signal refers to either HCG, MCG, or LCG, and two signals refers to either HCG and MCG, or MCG and LCG.

[0275] Then, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out each variation.

[0276] According to this, by performing auto-zero and analog CDS, it is possible to compare and determine the pixel signal level with the pixel signal level in which the variation in the sample-and-hold capacitance element (C) has been cancelled.

[0277] As described above, in this timing chart, at least one signal is detected during the period in which the reset component and signal component of the MCG are read from the pixel circuit 3, and readout and detection are processed simultaneously, thereby enabling higher speeds. Furthermore, since the pixel signal of the pixel circuit 3 is directly used for the comparison operation, rather than using the signal held in the sample-and-hold circuit SH412, the comparison operation can be performed with high accuracy without being affected by noise generated by the ON / OFF of the switch element, etc. Furthermore, the capacitance of the LCG can be reduced, thereby enabling a reduction in layout area. When comparing by dividing the time, only one comparator 421 is required, making it possible to further reduce the layout area.

[0278] [Explanation of timing chart (mixed mode)] As described above in [Regarding blending of WDR boundaries], when compositing a wide dynamic range function (WDR function), it is possible to mitigate changes in signal-to-noise ratio by blending HCG and MCG, and blending MCG and LCG at the boundaries between HCG and MCG, and between MCG and LCG.

[0279] An example of the timing of a signal read operation will be described with reference to FIG.

[0280] The period from time t100 to time t115 in FIG. 15 is the same as in [Explanation of the Timing Chart (RS)], so a description thereof will be omitted.

[0281] Next, signal readout from the sample-and-hold circuit SH412 will be described. Here, SEA and SEC represent the read selection switch element control signal φSE of one of SE7, SE9, and SE11 selected for the reset component. SEB and SED represent the read selection switch element control signal φSE of one of SE8, SE10, and SE12 selected for the signal component. As a result, the sample-and-hold capacitance elements C30, C32, and C34 for the reset component are selected by the read selection switch element control signal φSE. Similarly, the sample-and-hold capacitance elements C31, C33, and C35 for the signal component are selected by the read selection switch element control signal φSE.

[0282] Although an example in which two signals are selected is shown here, one signal is selected when blending is performed, so the process is completed at time t119, and the period from t119 to t123 is omitted.

[0283] This is because when HCG and MCG are mixed (blended), one mixed signal is selected, when MCG and LCG are mixed (blended), one mixed signal is selected, and when LCG is selected, the signal is not mixed and is one signal.

[0284] First, (21) based on the combination ratio determined at time t115, the control signal φSE of the read selection switch element SEA is turned ON to mix (blend), and the reset component held in the sample and hold capacitor element of the first signal of the selected pixel signal is read out and transferred via the amplification transistor SF30. Next, (22) based on the combination ratio determined at time t117, the control signal φSE of the read selection switch element SEB is turned ON to mix (blend), and the signal component held in the sample and hold capacitor element of the first signal of the selected pixel signal is read out and transferred via the amplification transistor SF30.

[0285] [Explanation of timing chart (GS)] 3, where pixel circuits 3a of the horizontal OFD are stacked one-to-one in relation to sample-and-hold circuits SH10, first, multiple pixel signals are read from pixel circuits 3a to sample-and-hold circuit SH10 using a global shutter method in which all pixels are read out simultaneously, or are read out row by row using a rolling shutter method, and then signals are read out row by row from sample-and-hold circuit SH10 using the rolling shutter method, and an example of the timing of the signal readout operation when at least one signal is selected by detection selection circuit 450 of FIG. 6A and FIG. 7 will be described using FIG. 16 and FIG. 17. Here, although two signals are selected in FIG. 16 and FIG. 17 (times t222 to t226 and time t226 to t230), one signal may also be selected.

[0286] Here, times t215 to t222 in FIG. 16 and FIG. 17 are the same.

[0287] First, at time t200, the photodiodes PD, FD0, GC1, and GC2 are reset to wait for the start of exposure. Then, at time t201, the shutter operates and exposure begins. At time t102, the exposure time ends.

[0288] Next, (1) at time t202, RS and GC1 are turned ON to reset FD0, entering the readout period for the reset component of MCG. Next, (2) at time t204, GC1 is turned OFF to enter the readout period for the reset component of HCG. Next, (3) at time t206, TG is turned ON to transfer the signal charge accumulated in the photodiode to FD0 via the transfer signal (TG), entering the readout period for the signal component (Q0) of HCG. Next, (4) at time t208, TG and GC1 are turned ON to transfer the signal charge overflowing from FD0 to the storage capacitor C1 via GC1, entering the readout period for the signal component (Q0+Q1) of MCG. Next, (5) at time t210, TG, GC1, and GC2 are turned ON to transfer the charge in storage capacitor C2 to FD0 via GC2, entering the readout period for the signal component (Q0+Q1+Q2) of LCG. Next, (6) at time t212, RS, GC1, and GC2 are turned ON to enter the read period of the reset component of LCG.

[0289] In this way, at times t203, t205, t207, t209, t211, and t213, the control signal φSH of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, and SH24) of the sample and hold circuit SH10 is turned ON, thereby connecting the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24) to the vertical signal line 30B. As a result, the output signal of the pixel circuit 3a is held in the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24).

[0290] Here, the read selection switch element φSE is always in the OFF state.

[0291] Next, the signal readout from the sample-and-hold circuit SH10 will be described. By turning on the selection control line φSEL_GS, the output of the amplification transistor SF2 is connected to the vertical signal line 30A via the selection transistor SEL_GS.

[0292] First, the reset component (sample and hold capacitance element C30) of the pixel signal of the HCG selected by turning on the control signal φSE of the read selection switch element SE26 (11) at time t216 is read out and transferred via the amplification transistor SF2. The signal component (sample and hold capacitance element C31) of the pixel signal of the HCG selected by turning on the control signal φSE of the read selection switch element SE27 (12) at time t217 is read out and transferred via the amplification transistor SF2.

[0293] Next, by turning on the control signal φSE of the read selection switch element SE28 (13) at time t218, the reset component of the MCG pixel signal (sample and hold capacitor C32) is read out and transferred via the amplification transistor SF2. At this time, auto-zero is performed (SW0, SH3, SW13, SW17, and SW18 are ON) while the reset component from the pixel circuit 3 is directly input. By turning on the control signal φSE of the read selection switch element SE29 (14) at time t219, the signal component of the MCG pixel signal (sample and hold capacitor C33) is read out and transferred via the amplification transistor SF2. At this time, the MCG signal component from the pixel circuit 3 is directly input to one input terminal of each of the comparators 411 and 419 (SW0, SH4, and SW14 are ON), and at the same time, the reference value (REF1) and reference value (REF2) are input to the other input terminals of the comparators 411 and 419 (SW15 and SW16 are ON). In the first detection circuit 401, multiple comparators 411 and 419 input and compare signals simultaneously (time t219A), or in the second detection circuit 402, a single comparator 421 inputs and compares signals continuously (times t219A and t219B).

[0294] Next, by turning on the control signal φSE of the read selection switch element SE30 at (15) time t220, the reset component of the pixel signal of MCG (sample and hold capacitance element C34) is read out and transferred via the amplification transistor SF30, and by turning on the control signal φSE of the read selection switch element SE31 at (16) time t221, the signal component of the pixel signal of MCG (sample and hold capacitance element C35) is read out and transferred via the amplification transistor SF2.

[0295] That is, at times t216, t217, t218, t219, t220, and t221 when the read selection switch element control signal φSE of the sample and hold circuit SH10 is turned ON, the control signal φSH of the sample and hold switch elements (SH20, SH31, SH32, SH33, SH34, and SH35) of the sample and hold circuit SH412 is turned ON, thereby connecting the sample and hold capacitance elements (C30, C31, C32, C33, C34, and C35) to the vertical signal line 30A. As a result, the output signal of the sample and hold circuit SH10 is held in the sample and hold capacitance elements (C30, C31, C32, C33, C34, and C35).

[0296] Here, the read selection switch element φSE is always in the OFF state.

[0297] In this timing chart, at least one signal is detected during the period in which the reset component and signal component of the MCG are read out from the pixel circuit 3, and reading and detection are processed simultaneously, thereby enabling speedup. The comparison result is then latched and sent to the selection circuit 400 via the selection control circuit 410, which selects one or two signals from the multiple pixel signals (three signals in this example).

[0298] It is also possible to proceed to the operation of the detection selection circuit 450 after the above (16) without simultaneously processing the readout and detection. The operation and timing of the first detection circuit 401 are as described in [Configuration Example of the First Detection Circuit], and the operation of the second detection circuit 402 are as described in [Configuration Example of the Second Detection Circuit].

[0299] Next, the signal readout from the sample-and-hold circuit SH412 will be explained. This is the same as [Explanation of the timing chart 1], so it will be omitted.

[0300] [Description of the timing chart (effect of embodiment 1)] A description will be given of an example of the timing of the signal readout operation by the detection selection circuit 450 in the first embodiment. Here, the timing when selecting one signal from a plurality of pixel signals will be described.

[0301] (i) An example of the timing of a signal readout operation in a conventional example (estimated from Patent Document 1) is shown in Figure 18. Specifically, it shows the convergence time of the vertical signal line 30A and the processing time of the AD conversion circuit 26. This is, as an example, the readout timing of a signal from the pixel circuit 3a in the rolling shutter system, and the basic concept remains the same when reading out a signal from the sample and hold circuit SH10 in the global shutter system, except that the readout order from the sample and hold capacitive elements changes.

[0302] First, for the reset component of the MCG, the convergence time of the vertical signal line 30A is from time t300 to t301, and then the processing time of the column AD circuit 25 is from time t301 to t302.

[0303] Next, for the reset component of HCG, the convergence time of the vertical signal line 30A is from time t302 to t303, and then the processing time of the column AD circuit 25 is from time t303 to t304.

[0304] Next, for the HCG signal component, the convergence time of the vertical signal line 30A is from time t304 to t305, and then the processing time of the column AD circuit 25 is from time t305 to t306.

[0305] Next, for the MCG signal component, the convergence time of the vertical signal line 30A is from time t306 to t307, and then the processing time of the column AD circuit 25 is from time t307 to t308.

[0306] Next, for the LCG signal component, the convergence time of the vertical signal line 30A is from time t308 to t309, and then the processing time of the column AD circuit 25 is from time t309 to t310.

[0307] Next, for the reset component of the LCG, the convergence time of the vertical signal line 30A is from time t310 to t311, and then the processing time of the column AD circuit 25 is from time t311 to t312.

[0308] (ii) An example of the timing of the signal readout operation in the first embodiment is shown in Fig. 19. Specifically, the timing shows the convergence time of the vertical signal line 30A and the processing time of the AD conversion circuit 26.

[0309] First, for the reset component of MCG, the convergence time of the vertical signal line 30A is required from time t320 to t321, and the pixel signal is held in the sample-and-hold circuit SH412.

[0310] Next, for the reset component of HCG, the convergence time of the vertical signal line 30A is required from time t321 to t322, and the pixel signal is held in the sample-and-hold circuit SH412.

[0311] Next, for the HCG signal component, the convergence time of the vertical signal line 30A is required from time t322 to t323, and the pixel signal is held in the sample-and-hold circuit SH412.

[0312] Next, for the MCG signal component, the convergence time of the vertical signal line 30A is required from time t323 to t324, and the pixel signal is held in the sample-and-hold circuit SH412.

[0313] Next, for the LCG signal component, the convergence time of the vertical signal line 30A is required from time t324 to t325, and the pixel signal is held in the sample-and-hold circuit SH412.

[0314] Next, for the reset component of LCG, the convergence time of the vertical signal line 30A is required from time t325 to t326, and the pixel signal is held in the sample-and-hold circuit SH412.

[0315] Next, the operation time required for the detection selection circuit 450 to select one signal from the plurality of pixel signals is from time t326 to t327.

[0316] Next, the processing time of the column AD circuit 25 for the reset component of this selected one signal is required from time t327 to time t328.

[0317] Next, the processing time of the column AD circuit 25 for the signal component of this selected one signal is from time t328 to time t329.

[0318] Here, the convergence time and ADC time when an HCG signal is selected are shown by solid lines for easy understanding, and the convergence time and ADC time when an MCG or LCG signal is selected are shown by dashed lines.

[0319] According to this, the detection selection circuit 450 is placed in the stage preceding the AD conversion circuit 26, and instead of redundantly reading all of the multiple signals, selectively reads one signal from three signals. This means that the number of convergence times for the vertical signal line 30A remains unchanged, but the analog and digital processing in the subsequent stages, including the AD conversion circuit 26, is faster and consumes less power. For example, if three signals are combined into one signal, the speed increases threefold, or the power consumption is reduced by one-third. Here, the presence of a reset component and a signal component reduces the number of times from six to two.

[0320] [Example of OB clamp] The OB clamp will be described with reference to FIGS.

[0321] The pixel array unit 1 is composed of an OB region 6 and an effective region 7. The OB region 6 has pixel circuits 3 that are identical to those in the light-shielded effective region 7. In both the first and second embodiments, a plurality of pixel signals in the OB region 6 are input to a detection selection circuit 450.

[0322] Here, in the OB region, the signal level is small and the HCG gain is always selected. For this reason, it is necessary to select fixed HCG, MCG, and LCG signals for each region in advance for the multiple pixel signals in the OB region 6.

[0323] Then, using the signals for HCG, MCG, and LCG in the OB area 6, the signals for HCG, MCG, and LCG in the effective area 7 are used after OB clamping.

[0324] In FIG. 20, multiple pixel signals in the effective area 7 are OB clamped using pixel signals of the sample-and-hold circuit SH412 corresponding to the vertically divided LCG signal (A10), MCG signal (A11), and HCG signal (A12) in the OB area 6.

[0325] In FIG. 21, multiple pixel signals in the effective area 7 are OB clamped using pixel signals of the sample-and-hold circuit SH412 corresponding to the horizontally divided LCG signal (A20), MCG signal (A21), and HCG signal (A22) in the OB area 6.

[0326] This allows the OB clamp to cancel fixed components that depend on the layout and driving of the sample-and-hold circuit SH412.

[0327] [Example of a stacked BSI configuration of pixel circuits and detection / selection circuits] An example of a configuration using a stacked BSI of pixel circuits and detection selection circuits in the first and second embodiments will be described.

[0328] 1, 22, 23A, 23B, 24A, and 24B are diagrams showing an example in which the solid-state imaging device according to embodiment 1 is configured as a stacked back-illuminated image sensor. The solid-state imaging device in these figures includes a first semiconductor chip and a second semiconductor chip or multiple semiconductor chips bonded together. The first semiconductor chip and the second semiconductor chip are bonded together on their respective wiring layer sides. In the figures, Pix denotes pixel circuits 3, and SH denotes a sample-and-hold circuit SH10.

[0329] The first semiconductor chip is referred to as a pixel chip in the figure and includes a main part of the solid-state imaging device 100 as a back-illuminated CMOS image sensor. The first semiconductor chip includes the photodiodes PD of the pixel circuits 3.

[0330] The second semiconductor chips are designated as logic chip A and logic chip B in the figure, and include main analog circuits and logic circuits, such as a signal processing unit 70. The second semiconductor chips may include a column detection selection circuit and a sample-and-hold circuit SH10.

[0331] In this solid-state imaging device 100, the pixel circuits 3 can be mounted on the pixel chip as a stacked BSI-type CIS, and the column detection selection circuit 27 can be mounted on the logic chip. In other words, a PD can be mounted on each pixel circuit 3 on the pixel chip, and the column detection selection circuit 27 can be configured on the logic chip. This allows pixel signals to be directly read out to the column detection selection circuit 27, making the logic chip comprised only analog and logic circuits, facilitating integration and reducing the layout area. Furthermore, the column detection selection circuit 27 selects at least one optimal signal from multiple pixel signals from the pixel array unit 1. This reduces the number of pixel signals converging on the vertical signal line 30A and the number of pixel signals to be AD converted, thereby reducing the convergence time, signal processing time, and power consumption, resulting in higher speed and lower power consumption. Specifically, the pixel chip and logic chip may be connected via junctions A and B, as shown in FIGS. 10 and 11.

[0332] 1 and 22 are diagrams showing an example of the solid-state imaging device according to the first embodiment configured as an image sensor (not a stacked type). In this case, a pixel array unit 1, a column detection selection circuit 27, and an AD conversion circuit 26 are mounted without using a stacked type. At least one optimal signal is selected from multiple pixel signals from the pixel array unit 1 by the column detection selection circuit 27, and AD conversion is performed by the AD conversion circuit 26. As a result, the number of pixel signals to be AD converted is reduced without using stacking, which reduces the time and power required for signal processing, thereby achieving higher speed and lower power consumption.

[0333] 1, 23A, and 23B are diagrams showing an example in which the solid-state imaging device according to the first embodiment is configured as a stacked back-illuminated image sensor. A stacked BSI CIS is used, and each pixel circuit 3 is mounted on a pixel chip, and a column detection selection circuit 27 and an AD conversion circuit 26 are mounted on a logic chip. The logic chip is composed only of analog and logic circuits, facilitating integration and reducing the layout area. At least one optimal signal is selected from multiple pixel signals from the pixel array unit 1 by the column detection selection circuit 27, and is then AD converted by the AD conversion circuit 26. Because the number of pixel signals to be AD converted is reduced, the time and power required for signal processing can be reduced, resulting in higher speeds and lower power consumption.

[0334] 1, 24A, and 24B are diagrams showing an example of a solid-state imaging device according to the first embodiment configured as a stacked back-illuminated image sensor. Each pixel on a pixel chip is mounted in a stacked BSI-type CIS, and a global shutter-type sample-and-hold circuit SH10 is mounted on a logic chip corresponding to each pixel circuit 3. A column detection selection circuit 27 and an AD conversion circuit 26 are mounted on the pixel chip or the logic chip. A sample-and-hold switch element SH and a readout selection switch element SE can be configured on the logic chip for each sample-and-hold circuit SH10, and the sample-and-hold circuit 10 corresponding to the pixel circuit 3 is directly connected, enabling high-speed readout of pixel signals to the sample-and-hold circuit 10. If the mounting area is limited, the sample-and-hold capacitance element C may be mounted separately on the pixel chip and the logic chip. Multiple pixel signals from the sample-and-hold circuit SH10 are read out row by row in a rolling manner, and at least one optimal signal is selected by the column detection selection circuit 27 and AD converted by the AD conversion circuit 26. Because the number of pixel signals that require AD conversion has been reduced, the time and power required for signal processing can be reduced, resulting in higher speeds and lower power consumption.

[0335] Regarding the bonding between the pixel chip and the logic chip, in FIG. 10, the vertical signal line 30A of each pixel array section 1 of the pixel chip is input to the detection selection circuit 450 via the bonding A, and the output is connected to the vertical signal line 19B and input to the column AD circuit 25.

[0336] 11, the vertical signal lines 30A of the pixel array units 1 of each pixel chip are input to two detection selection circuits 450 via junctions A and B, and the outputs are connected to vertical signal lines 19B and input to the column AD circuits 25. While one detection selection circuit 450 is performing detection using the first detection circuit 401, the other selection circuit selects a signal and reads it out row by row in a rolling manner, thereby achieving high speeds.

[0337] [Note] In the sample and hold circuit SH412 of Fig. 6A, the output terminals of the sample and hold switch elements (SH1 to SH6) are connected to the sample and hold capacitance elements (C30 to C35) and the read selection switch elements (SE7 to SE12). Also, the output terminals of the sample and hold switch elements (SH1 to SH6) are connected to the gate node of the amplification transistor SF30 via the read selection switch elements (SE7 to SE12). The sample and hold circuit SH412 may have the following configuration.

[0338] That is, like the configuration of the sample and hold circuit SH412 in Fig. 6C, the read selection switch elements (SE7 to SE12) may be omitted, and one of the two terminals of the sample and hold switch elements (SH1 to SH6) may be connected to the node of the gate of the amplification transistor SF30, and the other terminal of the sample and hold switch elements (SH1 to SH6) may be connected to the sample and hold capacitance elements (C30 to C35). As a result, the sample and hold switch elements (SH1 to SH6) in Fig. 6C have both the function of the sample and hold switch elements (SH1 to SH6) in Fig. 6A and the function of the read selection switch elements (SE7 to SE12).

[0339] In this case, in the operation and timing diagram of the detection selection circuit 450, the timing of the read selection switch element control signal φSE (each of SE7 to SE12) can be read as the timing of the sample and hold switch control signal φSH (each of SH1 to SH6). When reading out the signals of the sample and hold capacitive elements (each of C30 to C35), the switch element SW0 must be turned OFF. At this time, the parasitic capacitance value of the floating wiring is negligible compared to the capacitance value of the sample and hold capacitive elements (each of C30 to C35), and does not affect the holding voltage of the sample and hold capacitive elements (each of C30 to C35).

[0340] This configuration has the advantages of reducing the area by reducing the number of elements, and simplifying the control signals by reducing the number of control signals.

[0341] Note that while the vertical signal line 19B was conventionally mounted on the pixel chip and was less susceptible to noise, according to this embodiment, it passes through the analog circuit of the logic chip and may therefore be more susceptible to noise. For this reason, in the logic chip, power supply or GND wiring layers may be disposed above or below the wiring layer of the vertical signal line 19B to serve as an electromagnetic shield. This provides an electromagnetic shielding effect against noise from the digital and analog circuits of the logic chip, and can prevent noise from being superimposed on the vertical signal line 19B.

[0342] The amplification transistor SF30 of the detection selection circuit 450 has device noise (thermal noise, 1 / f noise, RTS noise), etc., and in order to suppress these, it is effective to make the transistor area as large as possible in order to reduce device noise, and it is preferable to make it larger than the amplification transistor SF1 of the pixel circuit 3. This makes it possible to reduce device noise that occurs when a signal is read out from the selection circuit 400 via the amplification transistor SF30.

[0343] The amplifying transistor SF2 of the sample-and-hold circuit SH10 has device noise (thermal noise, 1 / f noise, RTS noise), etc., and in order to suppress these, it is effective to make the transistor area as large as possible in order to reduce the device noise, and it is preferable to make it larger than the amplifying transistor SF1 of the pixel circuit 3a and the pixel circuit 3b.

[0344] Note that signal selection in units of color filter arrays has been explained using the typical Bayer array of four colors (R, Gr, B, Gb) as an example, but the color filters may be complementary colors, and the array may be a different unit than four pixels.

[0345] The sample and hold capacitor is composed of an MIM capacitor, a MOS capacitor, or the like, and is required to have low leakage characteristics and high density capacitance characteristics. It is preferable to provide a light-shielding layer at the substrate contact portion to suppress parasitic sensitivity.

[0346] In the pixel circuit 3a (horizontal OFD) and pixel circuit 3b (vertical OFD) in this embodiment, the photodiode PD is composed of one element, the storage capacitance element is composed of three elements, and the charge storage section is composed of three elements, and it has been described that three signals, HCG, MCG, and LCG, are generated, but if more elements are provided for each element, it is also possible to generate multiple signals of three or more signals and expand the dynamic range.

[0347] For example, by providing multiple photodiodes PD with different sensitivities in the pixel circuits 3a and 3b and further increasing the number of storage capacitor elements, the signal charges can be combined to further increase the number of pixel signals, thereby increasing the number of frames for WDR and further expanding the dynamic range.

[0348] It should be noted that the current source I0 can be turned on only when the pixel signals of the pixel circuits 3a and 3b are read out to the sample-and-hold circuit SH10, thereby reducing power consumption.

[0349] The technology of the detection selection circuit 450, which selects at least one pixel signal from multiple pixel signals, can be applied not only to global shutter imaging devices but also to TOF (Time of Flight) distance measuring devices. Naturally, it can also be extended to rolling shutter systems in addition to global shutter systems. This allows it to be installed in imaging devices that capture images of subjects and distance measuring imaging devices.

[0350] (Embodiment 2) First, a configuration example of a solid-state imaging device according to the present embodiment will be described. In the configuration example of Embodiment 2, in the configuration example of Fig. 29, the vertical signal line 30A of the pixel array unit 1 is divided into multiple parts in the vertical direction, and a detection selection circuit 450 is provided for each of the vertical signal lines 30A and 30A, and the detection selection circuit 450 is arranged in a stage preceding the column AD circuit 25.

[0351] 29 shows an example in which the pixel array unit 1 is mounted on a pixel chip, and the detection selection circuit 450 is mounted on logic chip A or logic chip B. In FIG. 29, the pixel array unit 1 is depicted as being divided in the vertical direction, but in reality, the pixel circuits 3 are arranged at equal pitches and are not physically divided, and this diagram simply shows the electrical connection relationships in an easy-to-understand manner.

[0352] The following description will focus on the differences from the first embodiment.

[0353] [Configuration example of solid-state imaging device 100] FIG. 29 is a block diagram showing an example of the configuration of the solid-state imaging device 100 according to the first embodiment.

[0354] The following mainly describes the differences from the first embodiment.

[0355] The pixel array section 1 has a plurality of pixel circuits 3a or pixel circuits 3b arranged in a matrix. In FIG. 1, the plurality of pixel circuits 3 are arranged in n rows and m columns. However, unlike the first embodiment, the pixel array section 1 divides the vertical signal line 30A into a plurality of parts in the vertical direction, which significantly reduces parasitic resistance and parasitic capacitance and speeds up the convergence time. For example, if the vertical signal line 30A is divided into M parts in the vertical direction, the convergence time of the vertical signal line 30A will be 1 / M times faster.

[0356] A plurality of detection selection circuits 450 are arranged on the logic chip so as to correspond to the pixel array sections 1 into which the vertical signal lines 30A are divided in the vertical direction (arranged in front of the AD conversion circuit 26). The vertical signal line 30A is provided on a pixel chip in the pixel array unit 1, and multiple pixel signals output from the amplification transistor SF1 of the pixel circuit 3a or pixel circuit 3b are input to a detection selection circuit 450 on the logic chip via the vertical signal line 30A. At least one pixel signal is selected from the multiple pixel signals based on reference values ​​(REF1, REF2, REF3) supplied from the gain reference signal generation unit 40. The selected signal is then connected to the vertical signal line 19B via the amplification transistor SF30 and the selection transistor SEL_DET. In this manner, at least one pixel signal selected from the multiple pixel signals output from the pixel circuit 3a or pixel circuit 3b is propagated to the column AD circuit 25. Here, in the conventional embodiment, the vertical signal line 19B required multiple convergence times corresponding to the multiple pixel signals. However, according to the second embodiment, the convergence time can be significantly reduced because only one selected pixel signal is output.

[0357] The signal processing unit 90 has a frame memory 97 and a control unit 96, and has a function of providing hysteresis to the reference values ​​(REF1, REF2, REF3) of the previous frame and the current frame that are supplied to the detection selection circuit 450. The signal processing unit 90 is configured to calculate the reference value of the current frame based on the gain selection signal 403 of the previous frame supplied from the detection selection circuit 450, and to supply a hysteresis selection signal 404 to the detection selection circuit 450 to control the reflection of the result on the current frame.

[0358] The signal processing unit 70 obtains the non-selected pixel signals by interpolation based on the selected pixel signals, and combines the selected pixel signals with the other pixel signals obtained by the interpolation.

[0359] According to this configuration, multiple detection selection circuits 450 are stacked corresponding to the pixel array unit 1 and arranged in front of the AD conversion circuit 26. Instead of redundantly reading all of the multiple signals, the detection selection circuits 450 selectively read at least one pixel signal from the multiple signals, thereby achieving high-speed and low-power analog and digital processing in the subsequent stages, including the AD conversion circuit 26. Furthermore, vertically dividing the vertical signal line 30A of the pixel array unit 1 into multiple lines improves the convergence of the vertical signal line 30A, thereby achieving high speed in the pixel array unit. For example, if N pixel signals are combined into one pixel signal, the speed of analog and digital processing with the vertical signal line 19B is increased by N times, or power consumption is reduced by 1 / N times. Furthermore, vertically dividing the vertical signal line 30A into M lines increases the convergence speed by M times. Increasing the number of divisions M makes the convergence time of the vertical signal line 30A almost negligible.

[0360] This makes it possible to achieve high speeds in all areas, including the pixel array section, analog processing section, and digital processing section, while maintaining the same dynamic range as when there are multiple pixel signals.

[0361] 3 and 5, which are suitable configurations for the global shutter system, as shown in Fig. 34B, the sample and hold circuit SH10 is located on logic chip A, and therefore the vertical signal lines 30A are divided vertically in the array section of the sample and hold circuit SH10, not in the pixel array section 1. A detection selection circuit 450 is provided corresponding to each line, thereby achieving high speeds in the same manner as above.

[0362] [Description of the timing chart (effect of embodiment 2)] A description will now be given of an example of the timing of the signal readout operation by the detection selection circuit 450 in Embodiment 2. Here, the timing when selecting one pixel signal from a plurality of pixel signals will be described.

[0363] 32 shows an example of the timing of the signal readout operation in the second embodiment. Specifically, the timing shows the convergence time of the vertical signal line 30A and the processing time of the AD conversion circuit 26.

[0364] 30, the vertical signal line 30A of the pixel array unit 1 is divided into four in the vertical direction, and each is provided with a detection selection circuit 450. As a result, the parasitic resistance and capacitance of the vertical signal line 30A are 1 / 4 times that of the first embodiment, and the convergence time is 1 / 4 times faster. Furthermore, as described in [Configuration Example for High-Speed ​​Detection Selection Circuit], multiple detection selection circuits 450 are provided as shown in FIG. 31, and the time required by the detection selection circuit 450 is zero.

[0365] First, for the reset component of MCG, the convergence time of the vertical signal line 30A is required from time t340 to t341, and the pixel signal is held in the sample-and-hold circuit SH412.

[0366] Next, for the reset component of HCG, the convergence time of the vertical signal line 30A is required from time t341 to t342, and the pixel signal is held in the sample-and-hold circuit SH412.

[0367] Next, for the HCG signal component, the convergence time of the vertical signal line 30A is required from time t342 to t343, and the pixel signal is held in the sample-and-hold circuit SH412.

[0368] Next, for the MCG signal component, the convergence time of the vertical signal line 30A is required from time t343 to time t344, and the pixel signal is held in the sample-and-hold circuit SH412.

[0369] Next, for the LCG signal component, the convergence time of the vertical signal line 30A is required from time t344 to t345, and the pixel signal is held in the sample-and-hold circuit SH412.

[0370] Next, for the reset component of LCG, the convergence time of the vertical signal line 30A is required from time t345 to t346, and the pixel signal is held in the sample-and-hold circuit SH412.

[0371] Next, as described above, the detection selection circuit 450 does not require any operation time to select one pixel signal from a plurality of pixel signals.

[0372] Next, for the reset signal component of this selected pixel signal, the convergence time of the vertical signal line 30A is required from time t346 to time t347.

[0373] Next, for the reset signal component of this selected pixel signal, the convergence time of the vertical signal line 30A is required from time t347 to time t348.

[0374] Next, the processing time of the column AD circuit 25 for the reset component of this selected pixel signal is from time t348 to time t349.

[0375] Next, the processing time of the column AD circuit 25 for the signal component of this selected pixel signal is from time t349 to t350.

[0376] Here, the convergence time and ADC time when HCG is selected are shown by solid lines for easy understanding, and the convergence time and ADC time when MCG or LCG is selected are shown by dashed lines.

[0377] According to this, the number of convergence times of the vertical signal line 30A remains unchanged, but the wiring length of the vertical signal line 30A is reduced to 1 / 4, and each convergence time is reduced to 1 / 4, resulting in a total speed increase of 1 / 4. Also, by converting the three signals (HCG, MCG, and LCG) into one pixel signal, the processing time of each column AD circuit 25 can be reduced from six times to two times if the signal component and reset component are combined, resulting in a speed increase of 1 / 3. Furthermore, the analog processing and digital processing in subsequent stages including the column AD circuit 25 can also be reduced to 1 / 3.

[0378] Furthermore, the vertical signal lines 30A of the pixel array section 1 may be divided into rows, and a selection circuit 400 and a first detection circuit 401 or a second detection circuit 402 may be provided for each pixel, thereby minimizing the convergence time of the vertical signal lines 30A. Then, one or two signals may be selectively read out from the plurality of pixel signals at the stage when they are output from the pixel circuit 3.

[0379] This makes it possible to achieve high speeds in all areas, including the pixel array section, analog processing section, and digital processing section, while maintaining the same dynamic range as when there are multiple pixel signals.

[0380] [Low power consumption] The reduction in power consumption in the second embodiment will be described with reference to Figure 35. Taking the case where the vertical signal line 30A of the pixel array section 1 is divided into four in the vertical direction as an example, (a) the time dependency of the vertical address, (b) an example of operation when the detection selection circuit 450 is always ON, and (c) an example of operation when the detection selection circuit 450 is ON only while processing a plurality of pixel signals corresponding to the pixel array section 1 are shown. The solid line in (a) indicates the readout timing for each row.

[0381] This makes it possible to realize low power consumption by the operation (c) without the need to keep the detection selection circuit 450 always ON. Note that this can be implemented with both the rolling shutter method and the global shutter method.

[0382] [Example of a stacked BSI configuration for pixel circuits and detection selection circuits] An example of a configuration using stacked BSI of pixel circuits and detection selection circuits in the first and second embodiments will be described.

[0383] 29, 33A, 33B, 34A, and 34B are diagrams showing an example of a solid-state imaging device according to embodiment 2 configured as a stacked back-illuminated image sensor. The solid-state imaging device in these figures includes a first semiconductor chip and a second semiconductor chip or multiple semiconductor chips bonded together. The first semiconductor chip and the second semiconductor chip are bonded together on their respective wiring layer sides. In the figures, Pix denotes pixel circuits 3, and SH denotes a sample-and-hold circuit SH10.

[0384] The first semiconductor chip is referred to as a pixel chip in the figure, and includes a main part of the solid-state imaging device 100 as a back-illuminated CMOS image sensor. The first semiconductor chip includes the photodiodes PD of the pixel circuits 3.

[0385] The second semiconductor chips are designated as logic chip A and logic chip B in the figure, and include main analog circuits and logic circuits, such as a signal processing unit 70. The second semiconductor chips may include a column detection selection circuit and a sample-and-hold circuit SH10.

[0386] In this solid-state imaging device 100, the pixel circuits 3 can be mounted on the pixel chip as a stacked BSI-type CIS, and the column detection selection circuit 27 can be mounted on the logic chip. That is, a PD can be mounted on each pixel circuit 3 on the pixel chip, and the column detection selection circuit 27 can be configured on the logic chip. Pixel signals can be directly read out to the column detection selection circuit 27. In particular, in the second embodiment, the vertical signal line 30A of the pixel array unit 1 is divided into multiple lines in the vertical direction, significantly reducing the parasitic resistance and parasitic capacitance of the vertical signal line 30A and speeding up the convergence time. Furthermore, the column detection selection circuit 27 selects at least one optimal pixel signal from the multiple pixel signals from the pixel array unit 1. This reduces the number of pixel signals that converge on the vertical signal line 30A and the number of pixel signals that undergo AD conversion, thereby reducing the convergence time, the time and power required for signal processing, and achieving higher speeds and lower power consumption. Specifically, the pixel chip and logic chip may be connected via junctions A and B shown in FIGS. 30 and 31.

[0387] 29, 33A, 33B, 34A, and 34B are diagrams showing an example in which the solid-state imaging device according to Embodiment 2 is configured as a stacked back-illuminated image sensor. A stacked BSI CIS is used, and each pixel of a pixel chip is mounted thereon. The vertical signal line 30A of the pixel array section 1 is divided into multiple sections in the vertical direction, and a column detection selection circuit 27 is mounted on a logic chip so as to correspond to the divided pixel array sections 1. An AD conversion circuit 26 is then mounted on the pixel chip or the logic chip.

[0388] 29, 34A, and 34B are diagrams showing an example in which the solid-state imaging device according to Embodiment 2 is configured as a stacked back-illuminated image sensor. A stacked BSI CIS is used, and each pixel of a pixel chip is mounted thereon. Vertical signal lines 30A of a pixel array section 1 are divided into multiple lines in the vertical direction. Column detection selection circuits 27 are mounted on logic chip B so as to correspond to the divided pixel array sections 1. A sample and hold circuit 10 is mounted on logic chip A between the pixel array section 1 and the column detection selection circuit 27. An AD conversion circuit 26 is mounted on the pixel chip, logic chip A, or logic chip B.

[0389] A PD can be mounted on each pixel circuit 3 on the pixel chip, and a column detection selection circuit 27 can be configured on the logic chip. As shown in FIG. 29, by dividing the vertical signal line 30A of the pixel array unit 1 into multiple lines in the vertical direction, the parasitic resistance and parasitic capacitance of the vertical signal line 30A can be significantly reduced by physically shortening its length. Therefore, for example, by dividing the vertical signal line 30A into four lines in the vertical direction as shown in FIGS. 30 and 31, the pixel signal readout time and convergence time can be shortened to one-fourth. Furthermore, since these pixel signals can be directly read out to the detection selection circuit 450, at least one optimal pixel signal can be selected from the multiple pixel signals from the pixel array unit 1 by the column detection selection circuit 27.

[0390] Therefore, in the past, in the case of multiple pixel signals, the vertical signal line 19B required multiple convergence times, and multiple AD conversion signal processing times were required in the AD conversion circuit 26. However, according to the second embodiment, by selecting at least one pixel signal from multiple pixel signals, the convergence time of the vertical signal line 19B can be reduced to at least one convergence time, and the AD conversion signal processing time in the AD conversion circuit 26 can also be reduced to at least one convergence time. This makes it possible to achieve higher speeds and lower power consumption.

[0391] Regarding the bonding between the pixel chip and the logic chip, in FIG. 29, the vertical signal line 30A of each divided pixel array section 1 of the pixel chip is input to the detection selection circuit 450 via the bonding A, and the output is connected to the vertical signal line 19B and input to the column AD circuit 25.

[0392] 30, the vertical signal lines 30A of each pixel array unit 1 divided from the pixel chip are input to two detection selection circuits 450 via junctions A and B, and the outputs are connected to vertical signal lines 19B and input to the column AD circuits 25. While one detection selection circuit 450 is performing detection using the first detection circuit 401, the other selection circuit selects a signal and reads it out row by row in a rolling manner, thereby achieving high speed.

[0393] (Embodiment 3A) 36 is a diagram showing a configuration example of an imaging device 200 to which the solid-state imaging device 100 according to Embodiments 1 and 2 is applied. The imaging device in the figure is a camera system, and includes the solid-state imaging device 100, an imaging optical system 202 including a lens, a signal processing unit 203, a drive circuit 204, and a system control unit 205.

[0394] In the imaging device 200, the solid-state imaging device 100 according to the first and second embodiments is used.

[0395] Furthermore, the drive circuit 204 receives a control signal corresponding to the drive mode from the system control unit 205 and supplies a drive mode signal to the solid-state imaging device 100. Upon receiving the drive mode signal, the solid-state imaging device 100 generates drive pulses corresponding to the drive mode signal and supplies them to each block within the solid-state imaging device 100.

[0396] Furthermore, the signal processing unit 203 receives the image signal output from the solid-state imaging device 100 and performs various signal processing on the image signal.

[0397] As such, the imaging device in this embodiment comprises the above-mentioned solid-state imaging device 100, an imaging optical system 202 that guides incident light from a subject to the solid-state imaging device 100, and a signal processing unit 203 that processes output signals from the solid-state imaging device 100.

[0398] (Embodiment 3B) 37 is a block diagram showing an example of the configuration of a distance measuring imaging device 300 according to embodiment 3B.

[0399] The distance measuring imaging device 300 includes a light source driver 150, a light source unit 160, an optical lens 170, a signal processing circuit 180, and the solid-state imaging device 100.

[0400] In the distance measuring imaging device 300, the solid-state imaging device 100 according to the first and second embodiments is used.

[0401] The light source driver 150 supplies a drive signal to the light source unit 160 in accordance with a signal from the solid-state imaging device 100 instructing it to emit light.

[0402] The light source unit 160 generates pulsed light for distance measurement in accordance with a drive signal from the light source driver 150 .

[0403] The lens 170 is a lens for collecting pulsed light reflected by the object 190 corresponding to the pulsed light from the light source unit 160 .

[0404] The signal processing circuit 180 calculates the distance to the object 190 based on the signal received from the solid-state imaging device 100 .

[0405] In the solid-state imaging device 100, near-infrared light is irradiated from the light source unit 160 onto an object 190 in the presence of background light. The light reflected from the object 190 is incident on the pixel array unit 10 via an optical lens 170. The reflected light incident on the pixel array unit 10 forms an image, and the formed optical image is converted into a pixel signal. The output of the solid-state imaging device 100 is converted into distance data by the signal processing circuit 180, and may also be converted into a visible distance image or brightness image depending on the application. [Industrial Applicability]

[0406] The present disclosure relates to a solid-state imaging device, and a photographing device or a distance measuring imaging device that uses the solid-state imaging device as an imaging device, and is suitable for, for example, a video camera, a digital camera, a distance measuring system, and the like. [Explanation of symbols]

[0407] 26 AD conversion circuit 3, 3a, 3b pixel circuit 450 detection selection circuit 400 selection circuit 401 first detection circuit 402 Second detection circuit 411, 419, 421 Comparators 19B Vertical signal line 30A vertical signal line 70 Signal Processing Section 76 WDR synthesis circuit C0 storage capacitance element C1 First storage capacitor element C2 Second storage capacitor element GC1 First gain control transistor GC2 Second gain control transistor FD0, FD1, FD2 charge storage units OF Overflow element PD photodiode RS Reset transistor SF1 First amplifying transistor SF2 Second amplifier transistor SH10, SH412, SH430 sample and hold circuit TG transfer transistor

Claims

1. A pixel circuit; a detection and selection circuit; an AD conversion circuit, the pixel circuit outputs a plurality of pixel signals corresponding to different gains or sensitivities; the detection selection circuit generates a signal selection signal that instructs selection of a pixel signal included in the plurality of pixel signals by comparing one or more pixel signals among the plurality of pixel signals with a reference value; the detection selection circuit has a sample-and-hold circuit that holds the plurality of pixel signals, and selects one of the plurality of pixel signals held in the sample-and-hold circuit based on the signal selection signal; the detection selection circuit is disposed in a stage preceding the AD conversion circuit that performs AD conversion on the selected pixel signal; Solid-state imaging device.

2. a first semiconductor chip having a pixel array including a plurality of the pixel circuits and vertical signal lines; a second semiconductor chip having the detection and selection circuit and stacked on the first semiconductor chip; the pixel array and the vertical signal line are divided into a plurality of sections; the detection selection circuit is provided for each of the divided pixel arrays; The solid-state imaging device according to claim 1 .

3. the plurality of pixel signals include a first pixel signal for low illuminance, a second pixel signal for medium illuminance, and a third pixel signal for high illuminance; the solid-state imaging device further comprises a synthesis circuit that determines non-selected pixel signals by interpolation processing based on the selected pixel signals, and synthesizes the selected pixel signals with other pixel signals determined by the interpolation processing; the reference values ​​in the detection selection circuit include a first reference value and a second reference value; the first reference value includes a value corresponding to a level of the second pixel signal corresponding to a level of a boundary portion immediately before a saturation level of the first pixel signal; the second reference value corresponds to a boundary level immediately before a saturation level of the second pixel signal. The solid-state imaging device according to claim 1 .

4. the first reference value includes a value corresponding to a boundary level immediately before a saturation level of the first pixel signal. The solid-state imaging device according to claim 3 .

5. a plurality of sample-and-hold elements for holding the plurality of pixel signals of the sample-and-hold circuit; when the pixel signal designated by the signal selection signal is within a predetermined range including the reference value, the detection selection circuit mixes the pixel signal designated by the signal selection signal with other pixel signals at a mixing ratio of α to (1-α) (α is a real number between 0 and 1), and outputs the mixed signal as the pixel signal designated by the signal selection signal; the value α is determined according to a difference between the level of the pixel signal designated by the signal selection signal and the reference value; a capacitance ratio of the plurality of sample and hold elements corresponding to the plurality of pixel signals is an inverse ratio of a gain at which the original signal charges are converted into voltage values ​​in the pixel circuit for the plurality of pixel signals; 5. The solid-state imaging device according to claim 1.

6. The sample and hold circuit two sample-and-hold capacitance elements for a reset component and a signal component corresponding to each of the plurality of pixel signals; the detection selection circuit compares a pixel signal level obtained by subtracting a reset component from a signal component with the reference value; 5. The solid-state imaging device according to claim 1.

7. the reference value is determined according to a gain of AD conversion in the AD conversion circuit; 5. The solid-state imaging device according to claim 1.

8. a reference signal generator that simultaneously generates a plurality of RAMP signals corresponding to the plurality of pixel signals; a selection switch that selects one of the plurality of RAMP signals and outputs it to the AD conversion circuit; The selection switch selects one of the plurality of RAMP signals in response to the signal selection signal.

5. The solid-state imaging device according to claim 1.

9. the detection selection circuit generates the same signal selection signal for pixels included in a unit of the color filter array; 5. The solid-state imaging device according to claim 1.

10. The detection selection circuit a detection circuit for generating the signal selection signal; a selection circuit that includes the sample-and-hold circuit and selects one of the pixel signals from the plurality of pixel signals held in the sample-and-hold circuit based on the signal selection signal; 5. The solid-state imaging device according to claim 1.

11. a plurality of pairs of the selection circuit and the detection circuit are provided for each of the pixel circuits; The detection circuit of one set and the selection circuit of the other set operate in parallel in time. The solid-state imaging device according to claim 10.

12. the detection selection circuit includes a comparator; a reset component of the second pixel signal from a pixel circuit is input to one input terminal of the comparator to perform auto-zero; Next, a signal component of the second pixel signal from the pixel circuit is input to one input terminal of the comparator, the first reference value or the second reference value is input to the other input terminal of the comparator; The detection selection circuit the comparison operation between the second pixel signal and the first reference value and the comparison operation between the second pixel signal and the second reference value are performed in parallel by a plurality of the comparators, or are performed sequentially by one of the comparators.

5. The solid-state imaging device according to claim 3.

13. the detection selection circuit generates a signal selection signal that instructs selection of two pixel signals; 5. The solid-state imaging device according to claim 1.

14. the detection selection circuit outputs the selected pixel signal to the AD conversion circuit via a vertical signal line; the detection selection circuit generates a gain selection signal having the same meaning as the signal selection signal; the vertical signal line is used in a time-division manner for transmitting the gain selection signal from the detection selection circuit to the AD conversion circuit and for transmitting the pixel signal from the detection selection circuit to the AD conversion circuit; 5. The solid-state imaging device according to claim 1.

15. the first reference value and the second reference value are adjusted in accordance with the signal selection signal of the previous frame so as to have a hysteresis characteristic that makes it easier to select in the current frame a pixel signal having the same gain or sensitivity as a pixel signal indicated by the signal selection signal of the previous frame; 5. The solid-state imaging device according to claim 3.

16. the pixel circuit has a first amplification transistor for outputting the plurality of pixel signals; the detection selection circuit has a second amplification transistor that outputs a pixel signal designated by the signal selection signal; an area of ​​the second amplification transistor is larger than an area of ​​the first amplification transistor; 5. The solid-state imaging device according to claim 1.

17. The vertical signal lines from the detection selection circuit are arranged on a power supply wiring layer or a ground potential wiring layer.

5. The solid-state imaging device according to claim 1.

18. a first semiconductor chip having a pixel array including a plurality of the pixel circuits and vertical signal lines; a second semiconductor chip having the detection and selection circuit and stacked on the first semiconductor chip; the vertical signal lines are divided into vertical rows of the pixel array, the detection selection circuit is provided for each of the pixel circuits, 5. The solid-state imaging device according to claim 1.

19. a solid-state imaging device according to any one of claims 1 to 4 for imaging a subject; an imaging optical system that guides incident light from the subject to the solid-state imaging device; a signal processing unit that processes an output signal from the solid-state imaging device, Imaging device.

20. a solid-state imaging device according to any one of claims 1 to 4, which drives and controls a light source unit to irradiate a target with pulsed light and capture an image of reflected light from the target; an imaging optical system that guides the reflected light from the object to the solid-state imaging device; a signal processing unit that processes an output signal from the solid-state imaging device, Ranging imaging device.

Images