Solar cell and its manufacturing method, photovoltaic module

Abstract

To provide a solar cell, a manufacturing method for the same, and a photovoltaic module, pertaining to the field of photovoltaic power.SOLUTION: The solar cell includes a substrate, a dielectric layer, a doping conductive layer, a passivation layer, and a plurality of electrodes sequentially arranged along a first direction. The substrate is provided with an electrode region and a non-electrode region which are alternately disposed along the first direction, with the non-electrode region including a plurality of first regions and a second region disposed in proximity to the first regions. Assuming that the substrate surface in the first regions is a first surface, the substrate surface in the second region is a second surface, and the substrate surface in the electrode region is a third surface, the dielectric layer covers the third surface and the second surface. The doping conductive layer is located on the side of the dielectric layer away from the substrate, the passivation layer is located on the first surface and the surface of the doping conductive layer, and each electrode is located in the electrode region, with the electrodes melting down the passivation layer and being electrically contacted with the doping conductive layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to the field of photovoltaics, and more particularly to solar cells and methods of fabricating same, and photovoltaic modules. [Background technology]

[0002] Currently, with the gradual depletion of fossil energy, solar cells are being used more and more widely as a new alternative energy source. A solar cell is a device that converts solar light energy into electrical energy. Solar cells use the principle of photovoltaic power to generate carriers, and then use electrodes to extract the carriers, which helps to effectively utilize electrical energy.

[0003] Current solar cells mainly include IBC (Interdigitated Back Contact) cells, TOPCON (Tunnel Oxide Passivated Contact) cells, PERC (Passivated Emitter and Real Cell) cells, and heterojunction solar cells. The installation and functional limitations of different film layers reduce light loss and reduce the recombination of photogenerated carriers on the surface and inside the silicon substrate, thereby improving the photoelectric conversion efficiency of solar cells.

[0004] However, the photoelectric conversion efficiency of current solar cells is still poor. Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments of the present invention provide a solar cell, a manufacturing method thereof, and a photovoltaic module that are advantageous in improving at least the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0006] According to some embodiments of the present application, in one aspect of the embodiments of the present application, there is provided a solar cell, the solar cell including: a substrate; a dielectric layer; a doped conductive layer; a passivation layer; and a plurality of electrodes arranged sequentially along a first direction, the substrate including electrode regions and non-electrode regions arranged alternately along the first direction, the non-electrode regions including a plurality of first regions and second regions arranged adjacent to the first regions, the substrate surface of the first regions being the first surface, the substrate surface of the second regions being the second surface, and the substrate surface of the electrode regions being the third surface, the dielectric layer covering the third surface and the second surface, the doped conductive layer being located on a side of the dielectric layer away from the substrate, the passivation layer being located on the first surface and on a surface of the doped conductive layer, and each electrode being located in the electrode region, the electrode being in electrical contact with the doped conductive layer by burning through the passivation layer.

[0007] In some embodiments, the substrate has first and second oppositely disposed surfaces, the first surface including a first surface, a second surface, and a third surface, and along a direction from the first surface to the second surface, the substrate in the first region has at least one groove recessed toward the second surface, and the passivation layer is located in the groove.

[0008] In some embodiments, a surface of the trench away from the second side is a fourth surface, a surface of the substrate excluding the fourth surface from the first surface is a fifth surface, and a passivation layer is located on the fifth surface.

[0009] In some embodiments, the roughness of the fifth surface is greater than or equal to the roughness of the second surface.

[0010] In some embodiments, the ratio of the total area of ​​the fourth surface to the total area of ​​the fifth surface ranges from 1:10 to 15:1.

[0011] In some embodiments, the shape of the groove comprises an inverted pyramid, an inverted truncated pyramid, an oval sphere, a rectangular parallelepiped, or a circular truncated pyramid.

[0012] In some embodiments, the groove size range includes 0.1 μm to 50 μm.

[0013] In some embodiments, the depth range of the grooves along the direction from the first surface to the second surface includes 0.2 μm to 5 μm.

[0014] In some embodiments, the range of the ratio of the total area of ​​the substrate in the first region to the total area of ​​the substrate in the non-electrode region includes 1:6 to 20:21.

[0015] In some embodiments, the ratio of the total area of ​​the substrate in the first region to the total area of ​​the substrate in the second region ranges from 1:2 to 20:1.

[0016] In some embodiments, the first side is a side of the doped conductive layer facing the first region along a direction from the second region to the first region, and the angle between the first side and the second surface is 90° or less.

[0017] In some embodiments, the first side comprises a flat surface or a textured surface.

[0018] In some embodiments, at least one of the second surface or the third surface comprises a flat or textured surface.

[0019] In some embodiments, the material of the dielectric layer includes silicon oxide, silicon carbide, amorphous silicon, microcrystalline silicon, and the like.

[0020] In some embodiments, the doped conductive layer includes a first doped conductive layer and a second doped conductive layer, the first doped conductive layer comprising one of an N-type doping element or a P-type doping element, and the second doped conductive layer comprising the other of an N-type doping element or a P-type doping element, the first doped conductive layer and the second doped conductive layer being respectively located on the surface of the dielectric layer, and the plurality of electrodes include first electrodes and second electrodes alternately arranged, the first electrode penetrating the passivation layer and in electrical contact with the first doped conductive layer, and the second electrode penetrating the passivation layer and in electrical contact with the second doped conductive layer.

[0021] In some embodiments, the doped conductive layer includes multiple layers of sub-doped conductive layers stacked in sequence, where there is an interface layer between two adjacent sub-doped conductive layers of a set.

[0022] According to some embodiments of the present application, in another aspect of the embodiments of the present application, there is further provided a method for manufacturing a solar cell, the method for manufacturing a solar cell including: providing a substrate having alternating electrode regions and non-electrode regions, wherein the non-electrode regions include a plurality of first regions and second regions arranged adjacent to the first regions; defining a substrate surface of the first regions as a first surface, a substrate surface of the second regions as a second surface, and a substrate surface of the electrode regions as a third surface; forming a dielectric layer covering the third surface and the second surface; forming a doped conductive layer located on a side of the dielectric layer away from the substrate; forming a passivation layer located on the first surface and on a surface of the doped conductive layer; and forming a plurality of electrodes arranged sequentially along a first direction, wherein each electrode is located in an electrode region and the electrode burns through the passivation layer to be in electrical contact with the doped conductive layer.

[0023] In some embodiments, the process steps of providing a substrate, forming a dielectric layer, and forming a doped conductive layer include: providing a base including an electrode region and a non-electrode region; sequentially forming an initial passivation film and a doped conductive film on a surface of the base; performing a shaping process on the initial passivation film, the doped conductive film, and the base in the non-electrode region, where the shaping process removes a portion of the initial passivation film and the doped conductive film in the non-electrode region, and forms a first surface on the base not covered by the initial passivation film and the doped conductive film, wherein the portion of the base having the first surface is a first region, the remaining non-electrode region is a second region, the remaining initial passivation film is a dielectric layer, the remaining doped conductive film is a doped conductive layer, and the remaining base is a substrate.

[0024] In some embodiments, the shaping process comprises a wet etching process.

[0025] In some embodiments, the process parameters for the wet etching process include a reaction solution comprising an acid solution and a reaction time of 50 to 550 seconds.

[0026] In some embodiments, the method further includes forming a mask layer on the surface of the base in the electrode region before shaping the initial passivation film, the doped conductive film, and the base in the non-electrode region.

[0027] According to some embodiments of the present application, in another aspect of the present application, there is further provided a photovoltaic module, the photovoltaic module including a cell string formed by connecting a plurality of solar cells according to any of the above embodiments or a plurality of solar cells manufactured by the method for manufacturing a solar cell according to any of the above embodiments, an encapsulation film for covering a surface of the cell string, and a cover plate for covering a surface of the encapsulation film away from the cell string. [Effects of the Invention]

[0028] The technical ideas provided in the embodiments of the present application have at least the following advantages:

[0029] In the solar cell provided in the present embodiment, the non-electrode region includes a plurality of first regions and a second region located adjacent to the first regions, a dielectric layer covering the third and second surfaces, and a passivation layer located on the first surface and the surface of the doped conductive layer. Compared to conventional dielectric layers and doped conductive layers covering the entire substrate surface, the present invention provides a first region partially uncovered by the dielectric layer and doped conductive layer, thereby reducing parasitic absorption in the doped conductive layer in the non-electrode region, improving light utilization efficiency, and contributing to improving the short-circuit current of the solar cell. Compared to the absence of a doped conductive layer in the non-electrode region, the second regions are distributed adjacent to the first regions, minimizing the coverage area and ensuring low parasitic absorption while maximizing lateral transport, thereby achieving the goals of improving lateral transport throughout the region. [Brief explanation of the drawings]

[0030] One or more embodiments are illustratively described in the accompanying drawings, but these illustrative descriptions are not intended to limit the embodiments, and parts denoted by the same reference numerals in the accompanying drawings are similar parts, and unless otherwise specified, the figures in the accompanying drawings are not limited to scale. In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without any creative effort. [Figure 1] FIG. 1 is a diagram showing the structure of a solar cell provided in the first embodiment of the present application. [Figure 2] FIG. 2 is an enlarged view of a portion C of the solar cell in FIG. [Figure 3] FIG. 3 is a diagram showing a first type cross-sectional structure along the A1-A2 cross section of FIG. [Figure 4] FIG. 4 is a diagram showing a first type cross-sectional structure along the B1-B2 cross section of FIG. [Figure 5] FIG. 5 is a diagram showing a first type cross-sectional structure along the E1-E2 cross section of FIG. [Figure 6] FIG. 6 is a locally enlarged view of the non-electrode region of the solar cell corresponding to FIGS. [Figure 7] FIG. 7 is a diagram showing a second type cross-sectional structure along the A1-A2 cross section of FIG. [Figure 8] FIG. 8 is an enlarged view of part F in FIG. [Figure 9] FIG. 9 is an enlarged view of part H in FIG. [Figure 10] FIG. 10 is a diagram showing a second type cross-sectional structure along the E1-E2 cross section of FIG. [Figure 11] FIG. 11 is a first scanning electron microscope photograph of a substrate in a non-electrode region of a solar cell provided in one example of the present application. [Figure 12] FIG. 12 is a second type of scanning electron microscope photograph of the substrate in the non-electrode region of the solar cell provided in one example of the present application. [Figure 13] FIG. 13 is a diagram showing a first cross-sectional structure of a solar cell provided in a second embodiment of the present invention. [Figure 14] FIG. 14 is a diagram showing a second cross-sectional structure of a solar cell provided in a second embodiment of the present invention. [Figure 15] FIG. 15 is a diagram showing a first cross-sectional structure of a solar cell provided in a third embodiment of the present invention. [Figure 16] FIG. 16 is a diagram showing a second cross-sectional structure of the solar cell provided in the third embodiment of the present application. [Figure 17] FIG. 17 is a diagram showing the local structure of the doped conductive layer and the electrode in the solar cell provided in the fourth embodiment of the present application. [Figure 18] FIG. 18 is a diagram showing a first cross-sectional structure of a solar cell provided in a fifth embodiment of the present application. [Figure 19] FIG. 19 is a diagram showing a second cross-sectional structure of a solar cell provided in a fifth embodiment of the present invention. [Figure 20] FIG. 20 is a diagram showing the structure of a solar cell provided in the sixth embodiment of the present application. [Figure 21] FIG. 21 is a diagram showing a cross-sectional structure along the A3-A4 cross section of FIG. [Figure 22] FIG. 22 is a diagram showing a cross-sectional structure along the B3-B4 cross section of FIG. [Figure 23] FIG. 23 is a diagram showing the structure of a solar cell provided in the seventh embodiment of the present application. [Figure 24] FIG. 24 is a diagram showing a cross-sectional structure along the A5-A6 cross section of FIG. [Figure 25] FIG. 25 is a diagram showing a cross-sectional structure along the B5-B6 cross section of FIG. [Figure 26] FIG. 26 is a diagram showing the structure of a photovoltaic module provided in the eighth embodiment of the present application. [Figure 27] FIG. 27 is a diagram showing a cross-sectional structure along the M1-M2 cross section of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0031] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0032] The present invention provides a solar cell, a manufacturing method thereof, and a photovoltaic module. In the solar cell, the non-electrode region includes a plurality of first regions and a second region located adjacent to the first regions, a dielectric layer covering the third and second surfaces, and a passivation layer located on the first surface and the surface of the doped conductive layer. Compared to conventional methods in which the dielectric layer and the doped conductive layer cover the entire substrate surface, the present invention provides a first region partially uncovered by the dielectric layer and the doped conductive layer, thereby reducing parasitic absorption in the doped conductive layer in the non-electrode region, improving light utilization efficiency, and contributing to improving the short-circuit current of the solar cell. Compared to the absence of a doped conductive layer in the non-electrode region, the second regions are distributed adjacent to the first regions, minimizing the coverage area and ensuring low parasitic absorption while maximizing lateral transport, thereby achieving the goals of improving lateral transport throughout the region.

[0033] Hereinafter, each embodiment of the present application will be described in detail with reference to the accompanying drawings. However, as will be understood by those skilled in the art, although many technical details are proposed in each embodiment of the present application to help readers better understand the present application, the technical solution claimed for protection by the present application can be realized without these technical details and various changes and modifications based on the following embodiments.

[0034] In the accompanying drawings, in all cross-sectional views of the solar cell, the upper surface is referred to as the front surface and the lower surface is referred to as the back surface in order to explain the relationship between the front surface and the back surface of the substrate.

[0035] Fig. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application, Fig. 2 is an enlarged view of portion C in Fig. 1, Fig. 3 is a diagram showing a first cross-sectional structure along the A1-A2 cross section of Fig. 2, Fig. 4 is a diagram showing the first cross-sectional structure along the B1-B2 cross section of Fig. 2, Fig. 5 is a diagram showing the first cross-sectional structure along the E1-E2 cross section of Fig. 2, and Fig. 6 is a locally enlarged view of a non-electrode region of the solar cell corresponding to Figs. 3 to 5. Here, for the sake of illustration, Fig. 3 shows only one first region in each non-electrode region, but in an actual solar cell, a cross section along the A1-A2 direction can cut out multiple first regions.

[0036] According to some embodiments of the present application, Example 1 of the present application provides a solar cell, as shown in Figure 3. The solar cell includes a substrate 100 having electrode regions 10 and non-electrode regions 11 alternately arranged along a first direction X.

[0037] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material may be composed of a single element, such as silicon or germanium. Here, the elemental semiconductor material may be in a single crystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (i.e., a state having both a single crystalline state and an amorphous state), and for example, silicon may be at least one of single crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0038] In some embodiments, the material of substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallide, perovskites, cadmium telluride, copper indium selenium, etc. Substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0039] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. An N-type semiconductor substrate is doped with an N-type doping element, which may be any of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). A P-type semiconductor substrate is doped with a P-type doping element, which may be any of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0040] In some embodiments, electrode region 10 can be understood to refer to the area of ​​substrate 100 directly facing electrode 108 in the thickness direction of substrate 100, or to refer to the area corresponding to the orthogonal projection of electrode 108 on substrate 100. Conversely, the area of ​​substrate 100 not directly facing electrode 108 is non-electrode region 11. By making the area of ​​electrode region 10 equal to or greater than the area of ​​the orthogonal projection of electrode 108 on substrate 100, it is ensured that all contact areas between electrode 108 and the substrate are electrode region 10.

[0041] It should be noted that the above definitions of electrode region 10 and non-electrode region 11 are intended for non-IBC cells, i.e., the two conductive electrodes of the solar cell with different polarities are not located on the same side of the substrate 100, but on corresponding opposite sides of the substrate 100. If the solar cell is an IBC cell or if the two conductive electrodes with different polarities are located on the same side of the substrate 100, the electrode region 10 refers to the region in the substrate where the conductive electrodes of one polarity face each other and the conductive electrodes of the other polarity face each other, and the non-electrode region 11 refers to the region in the substrate where the conductive electrodes of the two polarities do not face each other.

[0042] In some embodiments, the non-electrode region 11 includes a plurality of first regions 111 and a second region 112 disposed adjacent to the first regions 111. As shown in Figure 6, there is no absolute positional relationship between the first regions 111 and the second regions 112, and they are distinguished by the absence of a dielectric layer and a doped conductive layer in the first regions 111 and the presence of a dielectric layer and a doped conductive layer in the second regions 112. In other words, as shown in Figure 6, the positional relationship between the first regions 111 and the second regions 112 is such that the second regions 112 are adjacent to the first regions 111 and surround the first regions 111, thereby increasing the transport paths between the substrate and the electrode and improving the carrier collection speed and collection efficiency.

[0043] In some embodiments, the second region 112 may be located on one side of the first region 111 and may not surround the first region 111. The second region 112 may partially surround the first region 111. All of these positional relationships are within the scope of protection of the embodiments of the present application. In addition, the shape of the first region may be a rectangular region or an elliptical region as shown in FIG. 6, and the first region may have any shape and is not limited to the shape shown in FIG. 6.

[0044] In some embodiments, the ratio of the total surface area of ​​the portion of the substrate 100 corresponding to the first region 111 to the total surface area of ​​the portion of the substrate 100 corresponding to the non-electrode region 11 ranges from 1:6 to 20:21. This ratio may be in the range of 1:6 to 1:5.3, 1:5.3 to 1:4.9, 1:4.9 to 1:4.3, 1:4.3 to 1:3.5, 1:3.5 to 1:2.8, 1:2.8 to 1:2.1, 1:2.1 to 1:1.6, 1:1.6 to 1:1.3, or 1:1.3 to 20:21. As long as the ratio of the total surface area of ​​the substrate 100 in the first region 111 to the total surface area of ​​the substrate 100 in the first region 111 falls within any of the above ranges, the proportion of the doped conductive layer in the non-electrode region 11 is appropriate. This reduces parasitic absorption due to the large amount of the doped conductive layer itself in the non-electrode region 11, and reduces light absorption in the non-electrode region 11. At the same time, the doped conductive layers can establish transport paths with each other, improve the lateral transport ability between adjacent electrode regions 10, and enhance the cell performance of the solar cell.

[0045] In some embodiments, the ratio of the total surface area of ​​the first region 111 of the substrate 100 to the total surface area of ​​the second region 112 of the substrate 100 in each non-electrode region can range from 1:2 to 20:1. This ratio can be in the range of 1:2 to 1:1.3, 1:1.3 to 1.2:1, 1.2:1 to 2:1, 2:1 to 3.5:1, 3.5:1 to 5:1, 5:1 to 6.8:1, 6.8:1 to 11:1, 11:1 to 15:1, 15:1 to 18.3:1, or 18.3:1 to 20:1. By balancing the area of ​​the substrate 100 in the first region 111 and the area of ​​the substrate 100 in the second region 112, the area of ​​the doped conductive layer in the non-electrode region 11 can be balanced. This reduces the parasitic absorption of the doped conductive layer in the non-electrode region 11, and the doped conductive layer improves the lateral transport capability of the cell, thereby increasing the photoelectric conversion efficiency of the solar cell.

[0046] Fig. 7 is a diagram showing a second cross-sectional structure along the A1-A2 cross section of Fig. 2, Fig. 8 is an enlarged view of portion F of Fig. 7, Fig. 9 is an enlarged view of portion H of Fig. 7, Fig. 10 is a diagram showing a second cross-sectional structure along the E1-E2 cross section of Fig. 2, Fig. 11 is a first scanning electron microscope photograph of a substrate in a non-electrode region of a solar cell provided in one example of the present application, and Fig. 12 is a second scanning electron microscope photograph of a substrate in a non-electrode region of a solar cell provided in one example of the present application. Here, the view showing the second cross-sectional structure along the B1-B2 cross section of the solar cell corresponding to Fig. 7 is the same as Fig. 4.

[0047] 7, the first region 111 of the substrate 100 has at least one groove 113 recessed toward the second surface 14 along the direction from the first surface 13 to the second surface 14. The groove 113 can enhance the internal reflection of incident light, strengthen the capture and utilization of the incident light, increase the utilization rate of the incident light, reduce light loss, and contribute to the formation of a rear surface reflective structure, which in turn enhances the short-circuit current of the solar cell device and improves the photoelectric conversion efficiency.

[0048] When the ratio of the total area of ​​the substrate 100 in the first region 111 to the total area of ​​the substrate 100 in the non-electrode region 11 is 1:6 to 20:21, that is, the number and ratio of the grooves 113 are appropriate, this can improve the capture of incident light in the solar cell and increase the photoelectric conversion efficiency of the solar cell.

[0049] Furthermore, compared to a texture structure including a typical regular pyramid structure, the grooves 113 are recessed toward the center of the substrate 100, allowing the grooves 113 to capture more incident light and provide superior optical performance. Furthermore, because the dimensions of the regular pyramid structures are large, steps are likely to occur between regular pyramid structures of different crystal orientations, which could lead to electrical leakage. Conversely, the grooves 113 have a simple manufacturing process, no leakage current between crystal orientations, and good electrical performance.

[0050] In some embodiments, the shape of the groove 113 may be an inverted pyramid, an inverted truncated pyramid, an oval sphere, a rectangular parallelepiped, or a circular truncated pyramid, as shown in Figure 7. Here, to exemplarily illustrate the groove 113, the groove in Figure 7 is an inverted pyramid, but the shape of the groove may be any of the above shapes.

[0051] In some embodiments, the dimension of the groove 113 ranges from 0.1 μm to 50 μm. The dimension of the groove 113 may be from 0.1 μm to 0.8 μm, from 0.8 μm to 2.1 μm, from 2.1 μm to 5.6 μm, from 5.6 μm to 7.3 μm, from 7.3 μm to 9.3 μm, from 9.3 μm to 28.9 μm, from 28.9 μm to 38.8 μm, from 38.8 μm to 44.3 μm, or from 44.3 μm to 50 μm. The dimension of the groove 113 within any of the above ranges can provide a certain spatial region for capturing and utilizing incident light, can reduce the difficulty of the manufacturing process for forming the groove 113, and can avoid significant damage to the first surface 13 of the substrate 100 and reduce defects on the first surface 13.

[0052] In some embodiments, the depth of the grooves 113 along the direction from the first surface to the second surface ranges from 0.2 μm to 5 μm. The depth of the grooves 113 may range from 0.2 μm to 0.9 μm, 0.9 μm to 1.6 μm, 1.6 μm to 2.6 μm, 2.6 μm to 3.3 μm, 3.3 μm to 4.1 μm, 4.1 μm to 4.6 μm, or 4.6 μm to 5 μm. The depth of the grooves 113 within any of these ranges can improve the utilization rate and internal reflectance of incident light, thereby enhancing the photoelectric conversion efficiency of the solar cell. The depth range of the grooves 113 ensures that the film thickness of the passivation layer deposited therein is appropriate, providing a good passivation effect on the surface of the substrate 100 and reducing recombination defects in the substrate 100.

[0053] Furthermore, the depth range of the groove 113 indicates that the difference in height between the groove 113 and the surface of the second region 112 of the substrate 100 is small, the step is low, and there is less of a problem with leakage current due to the step, thereby improving the electrical performance of the substrate 100.

[0054] Here, the definition of the dimensions of the grooves 113 is to specify an arbitrary region within the surface of the substrate 100, detect the one-dimensional dimensions of the bottom of each groove 113 within this region, and finally take the average value. According to this, the range of dimensions of the grooves 113 refers to the range of average values ​​of the dimensions of the grooves 113 within a certain region (i.e., the average one-dimensional dimension), and it can be seen that it does not refer to the entire range of dimensions of all grooves 113 within the substrate 100, and that the entire range of dimensions of the grooves 113 is generally larger than the range of the average values. For example, the shapes of the grooves 113 in Figures 7 to 8 and 10 are the same, and the dimensions are equal to the average one-dimensional dimension.

[0055] The one-dimensional dimension refers to the distance between two diagonal corners of the groove 113. In some embodiments, the one-dimensional dimension may be the distance between two opposing sides of the groove 113. The depth of the groove 113 refers to the perpendicular distance in the direction from the first surface 13 to the second surface 14 between the apex of the groove 113 closest to the second surface 14 and the side surface of the groove 113 away from the second surface 14.

[0056] In some embodiments, as shown in FIG. 7, the side of the groove 113 away from the second surface 14 is the fourth surface, the surface of the substrate 100 excluding the fourth surface is the fifth surface, and the passivation layer is located on the fifth surface.

[0057] In some embodiments, the roughness of the fifth surface is equal to or greater than the roughness of the second surface. If the roughness of the fifth surface is greater than the roughness of the second surface, a subsequently formed passivation layer can cover the fifth surface, enhancing the passivation effect of the fifth surface and reducing surface recombination defects in the substrate 100. When a dielectric layer and a doped conductive layer are deposited on the second surface, the low roughness of the second surface, i.e., the high flatness of the second surface, ensures that the film layers of the dielectric layer and the doped conductive layer deposited thereon have good performance, such as compactness, and provide a good tunnel passivation effect for the substrate 100, effectively preventing the migration of minority carriers and promoting the migration of majority carriers, thereby increasing the carrier migration speed.

[0058] The difference in roughness here is due to the fact that the height of the texture structure on the fifth surface is greater than that of the texture structure on the second surface, or the degree of unevenness on the fifth surface is greater than that of the second surface. Roughness refers to the arithmetic mean of the absolute values ​​of the vertical deviation of each point on the surface from a reference mean line over one sampling length. Roughness can be measured by the comparison method, light section method, interferometry, and probe scanning method.

[0059] In some embodiments, the ratio of the total area of ​​the fourth surface to the total area of ​​the fifth surface ranges from 1:10 to 15:1, including 1:10 to 1:5.8, 1:5.8 to 1:1.9, 1:1.9 to 1:1, 1:1 to 2:1, 2:1 to 3.5:1, 3.5:1 to 5:1, 5:1 to 6.8:1, 6.8:1 to 10:1, 10:1 to 13.1:1, or 13:1 to 15:1. Limiting the total area of ​​the fourth surface and the total area of ​​the fifth surface can reduce the area of ​​the fifth surface and enhance the passivation effect of the solar cell. Increasing the total area of ​​the fourth surface can improve the utilization rate of incident light and enhance cell efficiency.

[0060] In some embodiments, the surface of the first region 111 of the substrate 100 is the first surface, the surface of the second region 112 of the substrate 100 is the second surface, and the surface of the substrate 100 in the electrode region 10 is the third surface.

[0061] In some embodiments, at least one of the second surface or the third surface comprises a flat surface or a textured surface. A flat surface comprises a polished surface.

[0062] The term "polished surface" refers to a flat surface formed by removing the surface texture using a polishing solution or laser etching. After polishing, the surface flatness of the substrate 100 is increased, the reflection of long-wavelength light is increased, secondary absorption of incident light is promoted, and the short-circuit current is improved. In addition, the specific surface area of ​​the surface of the substrate 100 is reduced, which reduces surface recombination on the substrate 100 and improves the surface passivation effect of the substrate 100.

[0063] In some cases, a flat surface refers to a relatively flat surface rather than an absolutely flat surface, and generally, a surface with a roughness of -5 μm or more and 5 μm or less is considered to be flat. A surface with a roughness smaller than that of an uneven surface can also be considered to be flat.

[0064] In some embodiments, substrate 100 comprises oppositely disposed first and second sides 13, 14, with first side 13 including a first surface, a second surface, and a third surface.

[0065] In some embodiments, the first surface 13 of the substrate 100 may be the front surface and the second surface 14 may be the back surface, or the first surface 13 of the substrate 100 may be the back surface and the second surface 14 may be the front surface. That is, the solar cell may be a single-sided cell, with the front surface used as a light-receiving surface to receive incident light and the back surface used as a backlight surface. In some embodiments, the solar cell may be a double-sided cell, with both the first surface 13 and the second surface 14 of the substrate 100 used as light-receiving surfaces to receive incident light.

[0066] In the solar cells shown in Figures 3 and 7, the first surface of the substrate is the front surface and the second surface of the substrate is the back surface, i.e., by improving the front surface of the solar cell, the parasitic absorption on the front surface of the solar cell is reduced.

[0067] In some embodiments, as shown in FIG. 3, the solar cell includes a dielectric layer 121 covering the third surface and the second surface, and a doped conductive layer 122 located on the side of the dielectric layer 121 away from the substrate 100.

[0068] In some embodiments, the material of the dielectric layer 121 includes silicon oxide, silicon carbide, amorphous silicon, microcrystalline silicon, and the like.

[0069] In some embodiments, the dielectric layer 121 includes a tunnel dielectric layer, forming a passivation contact structure between the tunnel dielectric layer and the doped conductive layer 122, and the doped conductive layer 122 can form a band bending at the surface of the substrate 100. The tunnel dielectric layer generates an asymmetric offset in the bands at the surface of the substrate 100, so that the potential barrier for majority carriers among the carriers is lower than the potential barrier for minority carriers among the carriers. Therefore, majority carriers can easily perform quantum tunneling by tunneling through the dielectric layer, but minority carriers have difficulty tunneling through the dielectric layer, thereby realizing selective transport of carriers.

[0070] The dielectric layer also exhibits a chemical passivation effect. Specifically, the presence of interface state defects at the interface between the substrate 100 and the tunnel dielectric layer increases the interface state density on the back surface of the substrate 100. The increase in interface state density promotes the recombination of photogenerated carriers, increases the backing factor, short-circuit current, and open-circuit voltage of the solar cell, and improves the photoelectric conversion efficiency of the solar cell. By positioning the tunnel dielectric layer on the first surface 13 of the substrate 100, the tunnel dielectric layer exhibits a chemical passivation effect on the front surface of the substrate 100. Specifically, by saturating the dangling bonds of the substrate 100, the interface state density of the substrate 100 is reduced, reducing the number of recombination centers in the substrate 100 and slowing the carrier recombination rate.

[0071] In some embodiments, the material of the tunnel dielectric layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0072] The doped conductive layer 122 can exert a field passivation effect, specifically, by forming an electrostatic field on the surface of the substrate 100 directed toward the inside of the substrate 100, which causes minority carriers to escape from the interface, thereby reducing the minority carrier concentration and the carrier recombination rate at the interface of the substrate 100, thereby increasing the open circuit voltage, short circuit current, and backing factor of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0073] The material of the doped conductive layer 122 may include at least one of amorphous silicon, polycrystalline silicon, or silicon carbide.

[0074] The doped conductive layer 122 may be doped with the same type of doping element as the substrate 100. For example, if the type of doping element in the substrate 100 is P-type, the type of doping element in the doped conductive layer 122 may be P-type; if the type of doping element in the substrate 100 is N-type, the type of doping element in the doped conductive layer 122 may be N-type.

[0075] The doping element concentration in the doped conductive layer 122 is greater than the doping element concentration in the substrate 100, so that a sufficiently high potential barrier is formed on the back surface of the substrate 100, allowing majority carriers in the substrate 100 to move to the doped conductive layer 122 through the tunnel dielectric layer.

[0076] In some embodiments, the thickness of the tunnel dielectric layer is 0.5 nm to 5 nm. For example, the thickness of the tunnel dielectric layer may be in the range of 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. When the tunnel dielectric layer is within any of the above ranges, the thickness of the dielectric layer is thin, allowing majority carriers to easily quantum tunnel through the dielectric layer, but minority carriers have difficulty passing through the dielectric layer, thereby achieving selective carrier transport.

[0077] In some embodiments, the dielectric layer 121 may include an intrinsic dielectric layer, forming a heterojunction structure between the intrinsic dielectric layer and the substrate, where the intrinsic dielectric layer has a good passivation effect on the substrate surface, greatly reducing carrier recombination, improving the minority carrier lifetime, and achieving a high open circuit voltage.

[0078] In some embodiments, the material of the intrinsic dielectric layer may be intrinsic amorphous silicon, intrinsic microcrystalline silicon, intrinsic silicon oxide, intrinsic silicon nitride, nanocrystalline silicon, or intrinsic silicon carbide. The thickness of the intrinsic dielectric layer can be selected from a range of 2 μm to 10 μm, preferably 5 μm. In some cases, the intrinsic dielectric layer may contain a small amount of doping elements due to the influence of the conditions of the diffusion or doping process of other film layers to be fabricated later.

[0079] In some embodiments, the doped conductive layer comprises a recombination thin film layer deposited with one or more of N-type doped or P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, hydrogenated microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide, or polycrystalline silicon semiconductor thin film, and the thickness of the doped conductive layer ranges from 4 to 30 nm.

[0080] Here, when hydrogenated microcrystalline silicon is used, it can have a larger band gap and a narrower absorption spectrum range, which can effectively increase the photoelectric conversion efficiency of the battery. In addition, as the crystallinity increases, the series resistance decreases and the backing factor increases, which improves the battery output current and effectively extends the battery life.

[0081] In some embodiments, the solar cell further includes a first transparent conductive layer located on a surface of the doped conductive layer away from the substrate, the first transparent conductive layer including at least one of tin-doped indium oxide (ITO), aluminum-doped zinc oxide (AZO), cerium-doped indium oxide, and tungsten-doped indium oxide.

[0082] In some embodiments, as shown in FIG. 9 , a side surface of the doped conductive layer 122 facing the first region 111 along the direction from the second region 112 toward the first region 111 is defined as a first side surface 123, and the angle between the first side surface 123 and the second surface is 90° or less. Thus, the first side surface 123, as a slope, can improve the internal reflectance of incident light and enhance the photoelectric conversion efficiency of the solar cell. Furthermore, the first side surface 123 can improve the deposition of the passivation layer and densify the passivation layer deposited on the first surface, contributing to the formation of a good passivation effect for the substrate 100.

[0083] In some embodiments, first side 123 comprises a flat surface or a textured surface.

[0084] In some embodiments, the surface of doped conductive layer 122 away from dielectric layer 121 comprises a flat surface.

[0085] In some embodiments, the solar cell includes a passivation layer 104. The passivation layer 104 is located on the first surface and on a surface of the doped conductive layer 122 facing away from the substrate. The passivation layer is located in the groove 113.

[0086] Here, when the solar cell includes a first transparent conductive layer, the passivation layer is located on the surface of the first transparent conductive layer that faces away from the substrate.

[0087] In some embodiments, the passivation layer 104 may be a single layer structure or a multilayer structure, and the material of the passivation layer 104 may be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0088] In some embodiments, the solar cell includes a plurality of electrodes 108 arranged sequentially along a first direction X. Each electrode 108 is located in an electrode region 10. The electrodes 108 burn through the passivation layer 104 to make electrical contact with the doped conductive layer 122.

[0089] Here, if the solar cell includes a first transparent conductive layer, the electrode 108 burns through the passivation layer and comes into contact with the first transparent conductive layer.

[0090] In some embodiments, the pitch range in the first direction X between the electrodes 108 is 0.5 mm to 2 mm. For example, the pitch range in the first direction X between the electrodes 108 may be 0.5 mm to 0.8 mm, 0.8 mm to 1.15 mm, 1.15 mm to 1.28 mm, 1.28 mm to 1.46 mm, 1.46 mm to 1.68 mm, 1.68 mm to 1.84 mm, or 1.84 mm to 2 mm.

[0091] In some embodiments, the width range of the electrode 108 in the first direction X is 5 μm to 50 μm. For example, the width range of the electrode 108 in the first direction X may be 5 μm to 9 μm, 9 μm to 14 μm, 14 μm to 23 μm, 23 μm to 34 μm, 34 μm to 42 μm, 42 μm to 45 μm, 45 μm to 48 μm, or 48 μm to 50 μm.

[0092] In some embodiments, the electrode 108 can be formed by sintering a burn-through paste. A method for forming the electrode 108 includes printing a metal paste on a surface of a portion of the passivation layer 104 or the anti-reflective layer using a screen printing process. The metal paste can include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. The metal paste is then subjected to a sintering process. In some embodiments, the metal paste contains a highly corrosive component, such as glass powder. During sintering, the corrosive component corrodes the passivation layer 104 or the anti-reflective layer, and the metal paste penetrates the passivation layer 104 or the anti-reflective layer to make electrical contact with the doped conductive layer 122.

[0093] In some embodiments, as shown in FIG. 3 , the solar cell further includes a first passivation layer 105 located on the second surface 14 and a third doped conductive layer 106 located on a side of the first passivation layer 105 away from the substrate 100, wherein the doped conductive layer 122 comprises one of an N-type doping element or a P-type doping element, and the third doped conductive layer 106 comprises the other of an N-type doping element or a P-type doping element.

[0094] In some embodiments, the first passivation layer 105 is an intrinsic passivation layer, and a heterojunction structure is formed between the intrinsic passivation layer and the substrate 100. Due to the heterojunction structure, the contact interface between the intrinsic passivation layer and the substrate 100 forms a high open circuit voltage and can achieve a better passivation effect, which makes it easier to improve the conversion efficiency.

[0095] In some embodiments, the solar cell includes a second transparent conductive layer 107, a second passivation layer 114, and a third electrode 109, which are sequentially stacked, with the second transparent conductive layer 107 located on the surface of the third doped conductive layer 106, and the third electrode 109 passing through the second passivation layer 114 and electrically contacting the second transparent conductive layer 107.

[0096] In some embodiments, the material of the first passivation layer 105 includes intrinsic amorphous silicon, intrinsic microcrystalline silicon, intrinsic silicon oxide, intrinsic nanocrystalline silicon, or intrinsic silicon carbide. The thickness of the first passivation layer 105 can be selected from a range of 2 μm to 10 μm, preferably 5 μm. In some cases, the first passivation layer 105 may contain a small amount of doping elements due to the influence of the conditions of the diffusion or doping process of other film layers to be fabricated later.

[0097] In some embodiments, the third doped conductive layer 106 comprises a recombination thin film layer stacked with one or more of N-type or P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, hydrogenated microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide, or polycrystalline silicon semiconductor thin film, and the thickness of the third doped conductive layer 106 ranges from 4 to 30 nm.

[0098] In some embodiments, the second transparent conductive layer 107 can include at least one of tin-doped indium oxide (ITO), aluminum-doped zinc oxide (AZO), cerium-doped indium oxide, and tungsten-doped indium oxide.

[0099] In some embodiments, a PN junction is formed between the third doped conductive layer 106 and the substrate 100. A first passivation layer 105 is inserted between the PN junction as a buffer layer, and the first passivation layer 105 has a good passivation effect on the surface of the substrate 100, which can significantly reduce carrier recombination and achieve a high minority carrier lifetime and open circuit voltage.

[0100] In the solar cell shown in FIG. 3 , in some embodiments, the substrate 100 contains either an N-type doping element or a P-type doping element, and the doped conductive layer 122 contains either an N-type doping element or a P-type doping element. In this way, a PN junction is formed between the substrate 100 and the doped conductive layer 122. When sunlight shines on the PN junction, new hole-electron pairs are formed. Under the action of the built-in electric field of the pn junction, the photo-generated holes flow to the p-region and the photo-generated electrons flow to the n-region, generating a current when the circuit is turned on. For example, if the substrate 100 is n-doped, the substrate 100 is an n-region, and if the doped conductive layer 122 is p-doped, the doped conductive layer 122 is a p-region. The P-type semiconductor has one hole (the P-type semiconductor can be considered to have one more positive charge due to the loss of one negatively charged electron) and generates electricity by utilizing the potential difference resulting from the one more free electron than the N-type semiconductor. When sunlight shines on the silicon, the light energy triggers the electrons in the silicon atoms (photovoltaic effect), causing the convection of electrons and holes. These electrons and holes are both influenced by the built-in potential and gather in the N-region and P-region, respectively. In this case, by connecting the outside with electrodes, a circuit can be formed and an electric current can be generated.

[0101] In some embodiments, the conductivity type of the third doping element in the substrate 100 is the same as the conductivity type of the first doping element in the doped conductive layer 122. A passivation contact structure and a high-low junction are formed between the substrate 100 and the doped conductive layer 122, so that carriers in the substrate 100 can be transported to the doped conductive layer 122 by the built-in electric field and then absorbed by the electrode 108, which helps improve cell efficiency. A PN junction is formed between the third doped conductive layer 106 and the substrate 100.

[0102] In the solar cell provided in the embodiment of the present application, the non-electrode region 11 includes a plurality of first regions 111 and second regions 112 disposed adjacent to the first regions 111, a dielectric layer 121 covering the third and second surfaces, and a passivation layer 104 located on the first surface and the surface of the doped conductive layer 122. Compared to conventional dielectric layers and doped conductive layers covering the entire substrate surface, the present invention provides the first regions 111 that are not covered by the dielectric layer 121 and the doped conductive layer 122, thereby reducing parasitic absorption in the doped conductive layer 122 in the non-electrode region 11, improving light utilization efficiency, and contributing to improving the short-circuit current of the solar cell. Compared to the absence of a doped conductive layer in the non-electrode region, the second regions 112 are distributed adjacent to the first regions 111, minimizing the coverage area and ensuring low parasitic absorption while ensuring lateral transport throughout the region.

[0103] FIG. 13 is a diagram showing a first cross-sectional structure of a solar cell provided in another embodiment of the present application, and FIG. 14 is a diagram showing a second cross-sectional structure of a solar cell provided in another embodiment of the present application.

[0104] In addition, another embodiment of the present application provides a solar cell, which is substantially the same as the solar cell provided in the above embodiment, except that the first passivation layer on the second surface in the above embodiment is an intrinsic passivation layer, while the first passivation layer on the second surface in the other embodiment is a second tunnel dielectric layer. Technical features that are the same as or correspond to those in the above embodiment will not be described here.

[0105] As shown in FIGS. 13 and 14 , the solar cell includes a substrate 200, a dielectric layer 221, a doped conductive layer 222, a passivation layer 204, and a plurality of electrodes 208 sequentially arranged along a first direction X. The substrate 200 includes electrode regions 20 and non-electrode regions 21 alternately arranged along the first direction X, and each non-electrode region 21 includes a first region 211 and at least one second region 212 arranged adjacent to the first region 211. The surface of the first region 211 of the substrate 200 is defined as a first region 211. a surface of the second region 212 of the substrate 200 as the first surface, a surface of the electrode region 20 of the substrate 200 as the second surface, a dielectric layer 221 covering the third surface and the second surface, a doped conductive layer 222 located on the side of the dielectric layer 221 away from the substrate 200, a passivation layer 204 located on the first surface and the surface of the doped conductive layer 222, and each electrode 208 located in the electrode region 20, the electrode 208 burning through the passivation layer 204 to be in electrical contact with the doped conductive layer 222.

[0106] In some embodiments, the substrate 200 has oppositely disposed first and second surfaces 23, 24, where the first surface 23 includes a first surface, a second surface, and a third surface.

[0107] In the solar cell shown in Figure 13, the first side of the substrate is the front side and the second side of the substrate is the back side, i.e., the improvements are made to the front side of the solar cell to reduce parasitic absorption on the front side of the solar cell. The back side of the solar cell is a TOPCon structure.

[0108] In addition, the substrate 200, electrode region 20, non-electrode region 21, dielectric layer 221, doped conductive layer 222, passivation layer 204, and electrode 208 in another embodiment can refer to the substrate 100, electrode region 10, non-electrode region 11, dielectric layer 121, doped conductive layer 122, passivation layer 104, and electrode 108 in the above embodiment, and their explanation will be omitted here.

[0109] In some embodiments, the solar cell further includes a first passivation layer 205 located on the second surface 24, a third doped conductive layer 206 located on the side of the first passivation layer 205 facing away from the substrate 200, and a second passivation layer 214 covering the surface of the third doped conductive layer 206 facing away from the substrate, wherein the doped conductive layer 222 comprises one of an N-type doping element or a P-type doping element, and the third doped conductive layer 206 comprises the other of an N-type doping element or a P-type doping element.

[0110] In some embodiments, the first passivation layer 205 is a second tunnel dielectric layer, and the second tunnel dielectric layer and the third doped conductive layer 206 form a passivation contact structure. The solar cell further includes a third electrode 209, which penetrates the second passivation layer 214 and electrically contacts the third doped conductive layer 206. The role, material, and thickness of the second tunnel dielectric layer may refer to the role, material, and thickness of the tunnel dielectric layer 121 in the above embodiment, but the description thereof will be omitted here. Similarly, the role, material, and thickness of the third doped conductive layer 206 may refer to the role, material, and thickness of the doped conductive layer 122 in the above embodiment. For example, the material of the second tunnel dielectric layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and magnesium fluoride.

[0111] By forming a local passivation contact structure on the second surface, the passivation effect of the solar cell can be improved, the surface defects on the second surface of the substrate can be reduced, and the cell efficiency of the solar cell can be increased.

[0112] FIG. 15 is a diagram showing a first cross-sectional structure of a solar cell provided in another embodiment of the present application, and FIG. 16 is a diagram showing a second cross-sectional structure of a solar cell provided in another embodiment of the present application.

[0113] In addition, in another embodiment of the present application, a solar cell is provided, which is almost the same as the solar cell provided in the above embodiment, except that the surface of the doped conductive layer away from the dielectric layer in the above embodiment is a flat surface, while the surface of the doped conductive layer away from the dielectric layer in the other embodiment is an uneven surface, and therefore, a description of the same or corresponding technical features as the above embodiment will be omitted here.

[0114] 15 and 16, the solar cell includes a substrate 300, a dielectric layer 321, a doped conductive layer 322, a passivation layer 304, and a plurality of electrodes 308 sequentially arranged along a first direction X. The substrate 300 includes electrode regions 30 and non-electrode regions 31 alternately arranged along the first direction X. The non-electrode regions 31 include a plurality of first regions 311 and second regions 312 arranged adjacent to the first regions 311. The surface of the substrate 300 in the first regions 311 is referred to as the first surface. a surface of the substrate 300 in the second region 312 is the second surface, a surface of the substrate 300 in the electrode region 30 is the third surface, a dielectric layer 321 covers the third surface and the second surface, a doped conductive layer 322 is located on the side of the dielectric layer 321 away from the substrate 300, a passivation layer 304 is located on the first surface and the surface of the doped conductive layer 322, each electrode 308 is located in the electrode region 30, and the electrode 308 burns through the passivation layer 304 to make electrical contact with the doped conductive layer 322.

[0115] The substrate 300 has a first surface 33 and a second surface 34 disposed opposite each other, and the first surface 33 includes a first surface, a second surface, and a third surface. In the solar cell shown in Figure 15, the first surface of the substrate is the front surface, and the second surface of the substrate is the back surface.

[0116] 15, the side of doped conductive layer 322 away from dielectric layer 321 has a micro-textured structure 320, forming a roughened surface. Micro-textured structure 320 includes a plurality of micro-protrusion structures, and the roughness of micro-textured structure 320 is greater than the roughness of the third surface. The greater roughness of micro-textured structure 320 improves the contact performance between electrode 308 and doped conductive layer 322, resulting in a higher soldering tensile strength between electrode 308 and doped conductive layer 322, and can improve the yield of solar cells.

[0117] In some embodiments, the shape of the micro-projection structures includes pyramidal, sinusoidal, or parabolic shapes.

[0118] In some embodiments, the dimensions of the micro-protrusion structures are less than 1 μm. The dimensions of the micro-protrusion structures are less than 890 nm. The dimensions of the micro-protrusion structures are less than 760 nm. The dimensions of the micro-protrusion structures are less than 620 nm. The dimensions of the micro-protrusion structures are less than 500 nm. The dimensions of the micro-protrusion structures are less than 320 nm. Thus, the dimensions of the micro-protrusion structures may be within any of the above ranges, and a smaller dimension of the micro-protrusion structures may reduce the etching time and etching extent of the doped conductive layer 322, thereby preventing significant etching loss in the doped conductive layer 322 and ensuring that the doped conductive layer 322 has a good passivation effect.

[0119] Here, the definition of the dimensions of the micro-protrusion structures is to randomly select a region within the surface of the doped conductive layer, measure the one-dimensional dimensions of the base of each micro-protrusion structure within that region, and finally calculate the average value. This means that the dimensions of the micro-protrusion structures are not the full range of the dimensions of all the micro-protrusion structures within the doped conductive layer, but the average range of the dimensions of a region, and the full range of the dimensions of the micro-protrusion structures is generally larger than the average range. For example, the shapes of each micro-protrusion structure in FIG. 15 are the same, and the dimensions are equal to the average one-dimensional dimension.

[0120] The one-dimensional dimension refers to the distance between two diagonal corners of the bottom surface pattern of the micro-protrusion structure. In some embodiments, the one-dimensional dimension may be the distance between two side surfaces of the bottom surface pattern. Here, the micro-protrusion structures can be fitted closely to the surface of the second surface 34 to construct a virtual surface as the bottom surface. In other words, the bottom surface is a pseudo-appearing surface that does not exist in an actual battery. For example, whether the surface of some micro-protrusion structures near the second surface 34 is flush with the bottom surface or whether the surface of some micro-protrusion structures near the second surface 34 is higher or lower than the bottom surface is also included in the micro-protrusion structures of the present application.

[0121] In some embodiments, the height of the micro-protrusion structure is less than 1 μm. The height of the micro-protrusion structure is less than 910 nm. The height of the micro-protrusion structure is less than 810 nm. The height of the micro-protrusion structure is less than 590 nm. The height of the micro-protrusion structure is less than 430 nm. The height of the micro-protrusion structure is less than 220 nm. Thus, when the height of the micro-protrusion structure is within any of the above ranges, the surface roughness of the doped conductive layer is reduced, and the passivation layer 304 is located not only in the recesses of the micro-protrusion structure but also in the protrusions of the micro-protrusion structure, i.e., the passivation structure is located on the entire surface of the micro-textured structure, thereby effectively achieving interface recombination. Here, the height of the micro-protrusion structure refers to the vertical distance between the highest point and the bottom surface of the micro-protrusion structure, which is farther from the third surface.

[0122] Furthermore, when the height and dimensions of the fine-protrusion structure are within the above ranges, the fine-protrusion structure has a large aspect ratio, and the slopes of the fine-protrusion structure reflect incident light multiple times, thereby increasing the light utilization rate.

[0123] In addition, the substrate 300, electrode region 30, non-electrode region 31, dielectric layer 321, doped conductive layer 322, passivation layer 304, electrode 308, first passivation layer 305, third doped conductive layer 306 and second passivation layer 314 in another embodiment can refer to the substrate 200, electrode region 20, non-electrode region 21, dielectric layer 221, doped conductive layer 222, passivation layer 204, electrode 208, first passivation layer 205, third doped conductive layer 206 and second passivation layer 214 in the above embodiment, and description thereof will be omitted here.

[0124] FIG. 17 is a diagram showing the local structure of the doped conductive layer and electrodes in a solar cell provided in another embodiment of the present application.

[0125] In addition, another embodiment of the present application provides a solar cell, which is substantially the same as the solar cell provided in the above embodiment, except that the doped conductive layer in the above embodiment is a single film layer, while the doped conductive layer in the other embodiment comprises multiple sub-doped conductive layers, and an interface layer is provided between adjacent sub-doped conductive layers. The same or corresponding technical features as those in the above embodiment will not be described here.

[0126] In some embodiments, the solar cell includes a substrate, a dielectric layer 421, a doped conductive layer 422, a passivation layer, and a plurality of electrodes 408 arranged sequentially along a first direction, the substrate having electrode regions and non-electrode regions arranged alternately along the first direction, each non-electrode region including a first region and a second region arranged adjacent to the first region, the substrate surface of the first region being the first surface, the substrate surface of the second region being the second surface, and the substrate surface of the electrode region being the third surface, the dielectric layer 421 covering the third surface and the second surface, the doped conductive layer 422 being located on a side of the dielectric layer 421 away from the substrate, the passivation layer being located on the first surface and on the surface of the doped conductive layer, each electrode 408 being located in the electrode region, and the electrode 408 being in electrical contact with the doped conductive layer 422 by burning through the passivation layer.

[0127] The substrate 400 has a first surface and a second surface disposed opposite to each other, and the first surface includes a first front surface, a second surface, and a third surface. In the solar cell shown in Figure 17, the first surface of the substrate is the front surface, and the second surface of the substrate is the back surface.

[0128] In some embodiments, as shown in FIG. 17, the doped conductive layer 422 includes multiple layers of sub-doped conductive layers stacked in sequence, where an interface layer 4223 is present between two adjacent sub-doped conductive layers of a set.

[0129] In some embodiments, there may be an interface layer between two adjacent sub-doped conductive layers. In some embodiments, there is no interface layer between two adjacent sub-doped conductive layers, i.e., the two sub-doped conductive layers are in contact with each other. In some embodiments, there may be multiple interface layers between two adjacent sub-doped conductive layers.

[0130] In some embodiments, the sub-doped conductive layer includes at least a first sub-doped conductive layer 4221 and a second sub-doped conductive layer 4222.

[0131] In some embodiments, the material of at least one of the first sub-doped conductive layer 4221 and the second sub-doped conductive layer 4222 includes at least one of amorphous silicon, polycrystalline silicon, or silicon carbide.

[0132] In some embodiments, the material of interface layer 4223 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0133] In another embodiment of the solar cell provided in the present application, the doped conductive layer is configured to include multiple sub-doped conductive layers, thereby reducing the thickness of each sub-doped conductive layer, reducing the parasitic absorption of the sub-doped conductive layers, and lowering the light loss of the solar cell. Furthermore, the use of multiple sub-doped conductive layers can avoid the problem of the silver paste material of the electrode burning through the dielectric layer, ensure the tunneling function of the dielectric layer, and improve the passivation effect of the solar cell.

[0134] FIG. 18 is a diagram showing a first cross-sectional structure of a solar cell provided in another embodiment of the present application, and FIG. 19 is a diagram showing a second cross-sectional structure of a solar cell provided in another embodiment of the present application.

[0135] In addition, another embodiment of the present application provides a solar cell, which is substantially the same as the solar cell provided in the above embodiment, except that the second surface in the above embodiment is flat, while the second surface in the other embodiment has a textured structure and an emitter. Technical features that are the same as or correspond to those in the above embodiment will not be described here.

[0136] 18 and 19, the solar cell includes a substrate 500, a dielectric layer 521, a doped conductive layer 522, a passivation layer 504, and a plurality of electrodes 508 sequentially arranged along a first direction X. The substrate 500 includes electrode regions 50 and non-electrode regions 51 alternately arranged along the first direction X. Each non-electrode region 51 includes a first region 511 and a second region 512 arranged adjacent to the first region 511. The surface of the substrate 500 in the first region 511 is referred to as a first surface. The surface of the substrate 500 in the second region 512 is the second surface, the surface of the substrate 500 in the electrode region 50 is the third surface, a dielectric layer 521 covers the third and second surfaces, a doped conductive layer 522 is located on the side of the dielectric layer 521 away from the substrate 500, a passivation layer 504 is located on the first surface and the surface of the doped conductive layer 522, each electrode 508 is located in the electrode region 50, and the electrode 508 burns through the passivation layer 504 to make electrical contact with the doped conductive layer 522.

[0137] Substrate 500 has first and second surfaces 53 and 54 disposed opposite to each other, and first surface 53 includes a first front surface, a second front surface, and a third front surface. In the solar cell shown in Figure 18, the first surface of the substrate is the back surface, and the second surface of the substrate is the front surface.

[0138] In some embodiments, the roughness of the second surface 54 is greater than the roughness of the first surface 53, i.e., the second surface 54 may be a surface with a textured structure, which can increase the internal reflection of incident light, thereby improving the light utilization rate of the solar cell and increasing the photoelectric conversion efficiency of the cell.

[0139] In some embodiments, the second surface 54 includes a textured structure 530, which includes a plurality of protruding structures. The shapes of the protruding structures include pyramidal, parabolic, or ellipsoidal shapes.

[0140] In some embodiments, the solar cell further includes an emitter 502, the emitter 502 being located in the electrode region 50 and the non-electrode region 51, the emitter 502 being located on a second surface of the substrate 500, and a PN junction being formed between the emitter 502 and the substrate 100.

[0141] In some embodiments, the material of the emitter 502 is the same as the material of the substrate 500, and the emitter 502 and the substrate 500 can each be fabricated using a diffusion process on the same base.

[0142] The substrate 500, electrode region 50, non-electrode region 51, dielectric layer 521, doped conductive layer 522, passivation layer 504, electrode 508, second passivation layer 514 and groove 513 in the fifth embodiment can refer to the substrate 200, electrode region 20, non-electrode region 21, dielectric layer 221, doped conductive layer 222, passivation layer 204, electrode 208, second passivation layer 214 and groove 113 in the above embodiment, and a description thereof will be omitted here.

[0143] FIG. 20 is a diagram showing the structure of a solar cell provided in another embodiment of the present application, FIG. 21 is a diagram showing the cross-sectional structure along the A3-A4 section of FIG. 20, and FIG. 22 is a diagram showing the cross-sectional structure along the B3-B4 section of FIG. 20.

[0144] In addition, another embodiment of the present application provides a solar cell, which is almost the same as the solar cell provided in the above embodiment, except that the solar cell in the above embodiment includes an electrode, while the solar cell in the other embodiment includes an electrode and a main grid, and the same or corresponding technical features as those in the above embodiment will not be described here.

[0145] As shown in FIGS. 21 and 22, the solar cell includes a substrate 600, a dielectric layer 621, a doped conductive layer 622, a passivation layer 604, and a plurality of electrodes 608 sequentially arranged along a first direction X. The substrate 600 has electrode regions 60 and non-electrode regions 61 alternately arranged along the first direction X. Each non-electrode region 61 includes a first region 611 and a second region 612 arranged adjacent to the first region 611. The surface of the substrate 600 in the first region 611 is referred to as a first surface. The surface of the substrate 600 in the second region 612 is the second surface, the surface of the substrate 600 in the electrode region 60 is the third surface, a dielectric layer 621 covers the third and second surfaces, a doped conductive layer 622 is located on the side of the dielectric layer 621 away from the substrate 600, a passivation layer 604 is located on the first surface and the surface of the doped conductive layer 622, each electrode 608 is located in the electrode region 60, and the electrode 608 burns through the passivation layer 604 to make electrical contact with the doped conductive layer 622.

[0146] The substrate 600 has a first surface 63 and a second surface 64 disposed opposite to each other, and the first surface 63 includes a first front surface, a second surface, and a third surface. In the solar cell shown in Figure 21, the first surface of the substrate is the front surface, and the second surface of the substrate is the back surface.

[0147] In some embodiments, the solar cell further includes a first main grid 631, which is sequentially arranged along the second direction Y and is in electrical contact with a plurality of electrodes arranged along the first direction. The solar cell further includes a second main grid 632, which is sequentially arranged along the second direction Y and is in electrical contact with a plurality of third electrodes arranged along the first direction.

[0148] In some embodiments, at least one of the first main grid 631 and the second main grid 632 is used to collect the current of the electrode and the third electrode, transport it to the PV ribbon, and ultimately collect it. The first main grid and the second main grid can be manufactured using a non-burn-through paste. When the non-burn-through paste is printed to directly contact the electrode or the third electrode, the non-burn-through paste causes less damage to the passivation layer 604. That is, the non-burn-through paste does not contain excess glass powder that can damage the p-n junction, effectively reducing metal recombination, improving the open-circuit voltage of the solar cell, and increasing the conversion efficiency of the solar cell.

[0149] Here, the conventional paste contains a mixture of metal powder, glass powder, and an organic carrier. The non-burn-through paste refers to a paste that contains less glass powder than the conventional paste and has weak burn-through ability during the sintering process, so that the passivation layer does not need to be burned through or cannot be burned through. The burn-through paste refers to a paste that has strong burn-through ability during the sintering process and can be burned through the passivation layer.

[0150] In addition, the substrate 600, electrode region 60, non-electrode region 61, dielectric layer 621, doped conductive layer 622, passivation layer 604, electrode 608, second passivation layer 614 and groove 613 in another embodiment can refer to the substrate 100, electrode region 10, non-electrode region 11, dielectric layer 121, doped conductive layer 122, passivation layer 104, electrode 108, first passivation layer 105, third doped conductive layer 106, second transparent conductive layer 107, second passivation layer 114 and groove 113 in the above embodiment, and description thereof will be omitted here.

[0151] FIG. 23 is a diagram showing the structure of a solar cell provided in another embodiment of the present application, FIG. 24 is a diagram showing the cross-sectional structure along the A5-A6 section of FIG. 23, and FIG. 25 is a diagram showing the cross-sectional structure along the B5-B6 section of FIG. 23.

[0152] In addition, another embodiment of the present application provides a solar cell, which is substantially the same as the solar cell provided in the above embodiment, except that the electrode and the third electrode in the above embodiment are located on both sides of the substrate, while the first electrode and the second electrode in the other embodiment are located on the same side of the substrate. Technical features that are the same as or correspond to those of the above embodiment will not be described here.

[0153] As shown in FIGS. 24 and 25 , the solar cell includes a substrate 700, a dielectric layer 721, a doped conductive layer, a passivation layer 704, and a plurality of electrodes 708 sequentially arranged along a first direction X. The substrate 700 has electrode regions 70 and non-electrode regions 71 alternately arranged along the first direction X. Each non-electrode region 71 includes a first region 711 and a second region 712 arranged adjacent to the first region 711. The surface of the substrate 700 in the first region 711 is referred to as a first surface. a surface of the substrate 700 in the second region 712 as a first surface, a surface of the substrate 700 in the electrode region 70 as a third surface, a dielectric layer 721 covering the third and second surfaces, a doped conductive layer located on the side of the dielectric layer 721 away from the substrate 700, a passivation layer 704 located on the first surface and on the surface of the doped conductive layer, and each electrode 708 located in the electrode region 70, the electrode 708 burning through the passivation layer 704 to make electrical contact with the doped conductive layer.

[0154] The substrate 700 has a first surface 73 and a second surface 74 disposed opposite to each other, and the first surface 73 includes a first front surface, a second surface, and a third surface. In the solar cell shown in Figure 24, the first surface of the substrate is the back surface, and the second surface of the substrate is the front surface.

[0155] In some embodiments, the doped conductive layer includes a first doped conductive layer 7226 and a second doped conductive layer 7227, where the first doped conductive layer 7226 comprises one of an N-type doping element or a P-type doping element, and the second doped conductive layer 7227 comprises the other of an N-type doping element or a P-type doping element, the first doped conductive layer 7226 and the second doped conductive layer 7227 are respectively located on the surface of the dielectric layer 721, and the multiple electrodes 708 include alternating first electrodes 7081 and second electrodes 7082, where the first electrode 7081 penetrates the passivation layer 704 and is in electrical contact with the first doped conductive layer 7226, and the second electrode 7082 penetrates the passivation layer 704 and is in electrical contact with the second doped conductive layer 7227.

[0156] Here, the material and thickness settings of the first doped conductive layer 7226 and the second doped conductive layer 7227 can refer to the material and thickness settings of the doped conductive layer 122 in the above embodiment, and it is only necessary that the first doped conductive layer is doped with either an N-type doping element or a P-type doping element, and the second doped conductive layer is doped with the other of an N-type doping element or a P-type doping element.

[0157] Similarly, the dielectric layer 721 can be set with reference to the material and thickness of the dielectric layer 121 in the above embodiment, and the first electrode 7081 and the second electrode 7082 can be set with reference to the material and thickness of the electrode 108 in the above embodiment.

[0158] Thus, the solar cell can be a TBC (TOPCon-BC) cell or an HBC (HJT-BC) cell. By changing the selective carrier contact passivation material of the TOPCon cell, the recombination current of the cell can be minimized and the conversion efficiency of the crystalline silicon cell can be increased to approach its theoretical limit. Furthermore, the TBC and HBC cells can be applied to stacked cells, and the cell efficiency can be improved by combining low-resistance tunnel layer technology in the interlayer between the top and bottom cells, conformal deposition technology on the crystalline silicon texture of the top cell, and spectral distribution and metallization technology in the top and bottom cells.

[0159] In addition, the substrate 700, electrode region 70, non-electrode region 71, dielectric layer 721, doped conductive layer, passivation layer 704, electrode 708, second passivation layer 714, and groove 713 in another embodiment can refer to the substrate 500, electrode region 50, non-electrode region 51, dielectric layer 521, doped conductive layer 522, passivation layer 504, electrode 508, second passivation layer 514, and groove 513 in the above embodiment, and a description thereof will be omitted here.

[0160] In addition, according to some embodiments of the present application, another embodiment of the present application further provides a solar cell manufacturing method for manufacturing the solar cell provided in the above embodiment, and the same or corresponding technical features as those of the above embodiment will not be described here.

[0161] A method for manufacturing a solar cell includes providing a substrate having alternating electrode and non-electrode regions, the non-electrode regions including a plurality of first regions and second regions adjacent to the first regions, the substrate surface of the first regions being a first surface, the substrate surface of the second regions being a second surface, and the substrate surface of the electrode regions being a third surface, forming a dielectric layer covering the third and second surfaces, forming a doped conductive layer located on a side of the dielectric layer away from the substrate, forming a passivation layer located on the first surface and on the surface of the doped conductive layer, and forming a plurality of electrodes sequentially arranged along a first direction, each electrode located in an electrode region and electrically contacting the doped conductive layer by burning through the passivation layer. The method will be described in detail below.

[0162] A method for manufacturing a solar cell includes providing a base, the surface of which has an initial surface structure, the base including alternating electrode and non-electrode regions.

[0163] In some embodiments, the base includes a first surface and a second surface, the first surface comprising an initial surface structure, the initial surface structure comprising an abrasive surface.

[0164] The method for manufacturing a solar cell includes sequentially forming an initial passivation film and a doped conductive film on the surface of a base, the initial passivation film covering the initial surface structure, and the doped conductive film covering the surface of the initial passivation film.

[0165] When forming the solar cell of Figure 15, the manufacturing method includes performing an etching process on the doped conductive film so that the surface of the doped conductive film away from the initial passivation film has a microtexture structure including at least one microprotrusion structure.

[0166] In some embodiments, the etching process includes a solution etching process and a laser etching process.

[0167] A method for manufacturing a solar cell includes performing a shaping process on the initial passivation film, the doped conductive film, and the base in the non-electrode region, in which the shaping process removes a portion of the initial passivation film and the doped conductive film in the non-electrode region, and defines the base not covered by the initial passivation film and the doped conductive film as the first surface (i.e., the surface of the remaining non-electrode region as the second surface), where the portion of the base having the first surface is the first region, the remaining non-electrode region is the second region, the remaining initial passivation film is the dielectric layer, the remaining doped conductive film is the doped conductive layer, and the base after the shaping process is the substrate.

[0168] In some embodiments, the shaping process comprises a wet etching process.

[0169] In some embodiments, the process parameters for the wet etching process include a reaction solution comprising an acid solution and a reaction time of 50 to 550 seconds.

[0170] In some embodiments, the wet etching process includes the following steps: (1) using a mixed acid solution containing HF, HNO3, and H2SO4, with mass concentrations of 10-25%, 5-10%, and 2-4%, respectively, and patterning the surface of the non-metallic region by screen printing, with an application volume of 0.05-0.8 mL / cm 2 The treatment time is 50 to 550 seconds, and (2) after treatment, the substrate is washed twice alternately with deionized water, low-concentration alkaline solution (0.5 to 1% NaOH), and low-concentration HCl (2.5 to 3.5%).

[0171] In some embodiments, the method further includes forming a mask layer on the surface of the base in the electrode region before shaping the initial passivation film, the doped conductive film, and the base in the non-electrode region, where the material of the mask layer includes organic wax, metal, or silicon dioxide mask.

[0172] In some embodiments, a printing process is used to form the mask layer.

[0173] The method for manufacturing a solar cell includes removing the mask layer.

[0174] A method for manufacturing a solar cell includes forming a passivation layer overlying a surface of the substrate and a surface of the doped conductive layer in a first region of the non-electrode region.

[0175] A method for manufacturing a solar cell includes forming a plurality of electrodes arranged sequentially along a first direction, each electrode being located in an electrode region, and the electrode burning through a passivation layer to electrically contact a doped conductive layer.

[0176] The method for manufacturing a solar cell further includes forming a first passivation layer, a third doped conductive layer, and a third electrode.

[0177] In some embodiments, the process step of providing a substrate includes providing a base, the base having a textured structure on a surface thereof, the base having alternating electrode regions and non-electrode regions; defining the textured structure of the electrode regions as a third surface, removing the textured structure of the non-electrode regions, and etching some of the non-electrode regions, defining the etched regions as first regions and the non-etched non-electrode regions as second regions, and defining the surface of the base in the first regions after etching as the first surface and the surface of the base in the second regions as the second surface.

[0178] FIG. 26 is a diagram showing the structure of a photovoltaic module provided in another embodiment of the present application, and FIG. 27 is a diagram showing the cross-sectional structure along the M1-M2 cross section of FIG.

[0179] Also, according to some embodiments of the present application, another embodiment of the present application further provides a photovoltaic module. As shown in Figures 26 and 27, the photovoltaic module includes a cell string formed by connecting a plurality of solar cells 8 according to any of the above embodiments or a plurality of solar cells 8 manufactured by the method for manufacturing a solar cell according to any of the above embodiments, a sealing film 840 for covering the surface of the cell string, and a cover plate 850 for covering the surface of the sealing film 840 away from the cell string.

[0180] Specifically, in some embodiments, the multiple cell strings are electrically connected by conductive bands 818, and the conductive bands 818 are soldered to the electrodes 808 on the battery cells. Figure 26 shows only one type of solar cell configuration, i.e., the electrodes of the battery cells with the same polarity are arranged in the same direction, or the positive electrodes of each battery cell are arranged on the same side, and a conductive band connects the opposite sides of two adjacent battery cells. In some embodiments, the battery cells can be arranged so that the opposite polarity electrodes of adjacent battery cells face the same side, i.e., the polarities of the electrodes of adjacent battery cells facing the same side can be arranged in the order of first polarity, second polarity, first polarity, and the conductive bands connect the opposite sides of two adjacent battery cells.

[0181] In some embodiments, there is no space between the battery cells, i.e., the battery cells overlap.

[0182] In some embodiments, the encapsulating film 840 includes a first encapsulating layer covering one of the front and back surfaces of the solar cell 60, and a second encapsulating layer covering the other of the front and back surfaces of the solar cell 60. Specifically, at least one of the first encapsulating layer and the second encapsulating layer may be an organic encapsulating film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0183] As can be seen, there is a boundary between the first and second sealing layers before lamination, but when forming the photovoltaic module after the lamination process, there is no concept of the first and second sealing layers, i.e., the first and second sealing layers form an integrated sealing film 840.

[0184] In some embodiments, the cover plate 850 may be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 850 facing the sealing film 840 may be textured to improve the utilization efficiency of incident light. The cover plate 850 includes a first cover plate and a second cover plate, where the first cover plate faces the first sealing layer and the second cover plate faces the second sealing layer.

[0185] Although the present application has been disclosed as above in preferred embodiments, it does not limit the scope of the claims, and a person skilled in the art can make some possible variations and modifications without departing from the idea of ​​the present application, so the scope of protection of the present application should be in accordance with the scope defined by the claims of the present application. In addition, the embodiments and drawings in the present specification are merely examples, and do not cover the entire scope protected by the claims of the present application.

[0186] Those skilled in the art will understand that the above embodiments are specific examples of realizing the present application, but that various changes in form and details are possible in practice without departing from the spirit and scope of the present application. Since anyone skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, the scope of protection of the present application should be based on the scope limited by the claims.

Claims

1. The semiconductor device includes a substrate, a dielectric layer, a doped conductive layer, a passivation layer, and a plurality of electrodes sequentially arranged along a first direction; the substrate includes electrode regions and non-electrode regions that are alternately arranged along the first direction, the non-electrode regions include a first region and a second region that is arranged adjacent to the first region, the substrate surface of the first region is defined as a first surface, the substrate surface of the second region is defined as a second surface, and the substrate surface of the electrode region is defined as a third surface; the dielectric layer covers only the third surface and the second surface; the doped conductive layer covers only the surfaces of the dielectric layer located at the third surface and the second surface; the passivation layer covers only the first surface and a surface of the doped conductive layer; Each of the electrodes is located in the electrode region, and the electrodes burn through the passivation layer to make electrical contact with the doped conductive layer; the substrate has a first surface and a second surface disposed opposite to each other, the first surface including a first surface, a second surface, and a third surface, and along a direction from the first surface toward the second surface, each of the first regions has at least one groove recessed toward the second surface, the passivation layer is located in the groove, and the groove is formed only in the first region; a surface of each of the grooves away from the second surface is defined as a fourth surface, a surface of the substrate excluding the fourth surface from the first surface is defined as a fifth surface, and the passivation layer is further located on the fifth surface; the roughness of the fifth surface is greater than the roughness of the second surface; The groove size ranges from 0.1 μm to 50 μm; The depth of the groove is in the range of 0.2 μm to 5 μm along the direction from the first surface to the second surface. A solar cell characterized by:

2. the ratio of the total area of ​​the fourth surface to the total area of ​​the fifth surface is in the range of 1:10 to 15:1; The solar cell according to claim 1 .

3. The shape of the groove includes an inverted pyramid, an inverted truncated pyramid, an oval sphere, a rectangular parallelepiped, or a circular truncated pyramid. The solar cell according to claim 1 .

4. a ratio of a total area of ​​the first surfaces of all the first regions of the substrate to a total area of ​​the surfaces of all the non-electrode regions of the substrate is in the range of 1:6 to 20:21; The solar cell according to claim 1 .

5. In each non-electrode region, the ratio of the total area of ​​the first surface of the first region to the total area of ​​the second surface of the second region of the substrate is in the range of 1:2 to 20:

1. The solar cell according to claim 1 .

6. a side surface of the doped conductive layer facing the first region along a direction from the second region toward the first region is defined as a first side surface, and an angle between the first side surface and the second surface is 90° or less; The solar cell according to claim 1 .

7. The first side surface includes a flat surface or an uneven surface. The solar cell according to claim 6 .

8. At least one of the second surface and the third surface includes a flat surface or an uneven surface. The solar cell according to claim 1 .

9. the material of the dielectric layer is any one of silicon oxide, silicon carbide, amorphous silicon, and microcrystalline silicon; The solar cell according to claim 1 .

10. the doped conductive layer includes a first doped conductive layer and a second doped conductive layer, the first doped conductive layer comprises one of an N-type doping element or a P-type doping element, and the second doped conductive layer comprises the other of an N-type doping element or a P-type doping element, the first doped conductive layer and the second doped conductive layer are respectively located on the surface of the dielectric layer, the plurality of electrodes include first electrodes and second electrodes alternately arranged, the first electrode penetrates the passivation layer and is in electrical contact with the first doped conductive layer, and the second electrode penetrates the passivation layer and is in electrical contact with the second doped conductive layer; The solar cell according to claim 1 .

11. the doped conductive layer includes a plurality of sub-doped conductive layers sequentially stacked along a direction from the second surface to the first surface, and an interface layer is present between two adjacent sub-doped conductive layers of one set; The solar cell according to claim 1 .

12. providing a substrate having alternating electrode regions and non-electrode regions, wherein the non-electrode regions include a plurality of first regions and second regions disposed adjacent to the first regions, the substrate surfaces of the first regions being defined as a first surface, the substrate surfaces of the second regions being defined as a second surface, and the substrate surfaces of the electrode regions being defined as a third surface; forming a dielectric layer covering only the third surface and the second surface; forming a doped conductive layer covering only the surfaces of the dielectric layer located at the third surface and the second surface; forming a passivation layer covering only the first surface and a surface of the doped conductive layer; forming a plurality of electrodes sequentially arranged along a first direction, each of the electrodes being located in the electrode region, and the electrode being electrically contacted with the doped conductive layer by burning through the passivation layer; the substrate has a first surface and a second surface disposed opposite to each other, the first surface including a first surface, a second surface, and a third surface, and along a direction from the first surface toward the second surface, each of the first regions has at least one groove recessed toward the second surface, the passivation layer is located in the groove, and the groove is formed only in the first region; a surface of each of the grooves away from the second surface is defined as a fourth surface, a surface of the substrate excluding the fourth surface from the first surface is defined as a fifth surface, and the passivation layer is further located on the fifth surface; the roughness of the fifth surface is greater than the roughness of the second surface; The groove size ranges from 0.1 μm to 50 μm; The depth of the groove is in the range of 0.2 μm to 5 μm along the direction from the first surface to the second surface. A method for manufacturing a solar cell comprising the steps of:

13. The process steps of providing a substrate, forming a dielectric layer and forming a doped conductive layer include: providing a base including the electrode region and the non-electrode region; Sequentially forming an initial passivation film and a doped conductive film on the surface of the base; performing a shaping process on the initial passivation film, the doped conductive film and the base in the non-electrode regions, the shaping process removing a portion of the initial passivation film and the doped conductive film in each of the non-electrode regions, and defining the base not covered by the initial passivation film and the doped conductive film as a first surface, wherein the portion of the base having the first surface is defined as a first region, the remaining non-electrode region is defined as a second region, the remaining initial passivation film is defined as the dielectric layer, the remaining doped conductive film is defined as the doped conductive layer, and the remaining base is defined as the substrate; The method for manufacturing a solar cell according to claim 12 .

14. The shaping process includes a wet etching process. The method for manufacturing a solar cell according to claim 13 .

15. The process parameters of the wet etching process include: a reaction solution including an acid solution; and a reaction time of 50 to 550 seconds. The method for manufacturing a solar cell according to claim 14 .

16. and forming a mask layer on the surface of the base in the electrode region before shaping the initial passivation film, the doped conductive film, and the base in the non-electrode region. The method for manufacturing a solar cell according to claim 13 .

17. a cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 11; a sealing film for covering a surface of the cell string; a cover plate for covering a surface of the sealing film away from the cell string, A photovoltaic module characterized by:

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