Image sensor and image pickup device

Abstract

To materialize high quality of an image generated from a signal output from a pixel.SOLUTION: An imaging device comprises: a plurality of pixel blocks each of which has a plurality of pixels including photoelectric conversion units performing photo-electric conversion of light thereby generating electric charges and arranged in a first direction and a second direction intersecting with the first direction; and a plurality of control lines which are electrically connected to one pixel of the plurality of pixel blocks, being a part of the plurality of pixel blocks, and supply a control signal to the plurality of pixels. The plurality of pixels to which one control line of the plurality of control lines is connected, include pixels each of which has a first spectral responsivity and a second spectral responsivity different from the first spectral responsivity.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an imaging device. [Background technology]

[0002] There is known an imaging element in which one control line for transfer control is provided in common for a plurality of pixels that generate signals of the same color (for example, Patent Document 1). Conventionally, there has been a demand for improving the quality of images generated from output signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-143730 Summary of the Invention

[0004] According to the first aspect, the image sensor detects light transmitted through a first filter having a first spectral characteristic. light to the charge conversion The first Photoelectric conversion unit a first photoelectric conversion unit that converts light transmitted through a second filter having a second spectral characteristic different from the first spectral characteristic into electric charges and that is disposed adjacent to the first photoelectric conversion unit; a first transfer unit that transfers the electric charges converted by the first photoelectric conversion unit; and a second transfer unit that transfers the electric charges converted by the second photoelectric conversion unit. A pixel block; a second pixel block including a third photoelectric conversion unit that converts light that has passed through a third filter having the first spectral characteristic into electric charges, a fourth photoelectric conversion unit that converts light that has passed through a fourth filter having the second spectral characteristic into electric charges and that is disposed adjacent to the third photoelectric conversion unit, a third transfer unit that transfers the electric charges converted by the third photoelectric conversion unit, and a fourth transfer unit that transfers the electric charges converted by the fourth photoelectric conversion unit; and a first transfer circuit that is electrically connected to the first transfer unit and the fourth transfer unit and outputs a first transfer control signal for controlling the first transfer unit and the fourth transfer unit. A control line; a second transfer control line electrically connected to the second transfer unit and the third transfer unit, and through which a second transfer control signal for controlling the second transfer unit and the third transfer unit is output; Equipped with R . According to a second aspect, the imaging element includes a first pixel block including: a first photoelectric conversion unit that converts light that has passed through a first filter having a first spectral characteristic into an electric charge; a second photoelectric conversion unit that converts light that has passed through a second filter having a second spectral characteristic different from the first spectral characteristic and that is disposed adjacent to the first photoelectric conversion unit; a first reset unit that resets a voltage of a first accumulation unit to which the electric charge converted by the first photoelectric conversion unit is transferred; and a second reset unit that resets a voltage of a second accumulation unit to which the electric charge converted by the second photoelectric conversion unit is transferred; a second pixel block including a third photoelectric conversion unit that converts light that has passed through a third filter having the first spectral characteristic into electric charges; a fourth photoelectric conversion unit that converts light that has passed through a fourth filter having the second spectral characteristic into electric charges and that is arranged adjacent to the third photoelectric conversion unit; a third reset unit that resets the voltage of a third accumulation unit to which the electric charges converted by the third photoelectric conversion unit are transferred; and a fourth reset unit that resets the voltage of a fourth accumulation unit to which the electric charges converted by the fourth photoelectric conversion unit are transferred; a first reset control line that is electrically connected to the first reset unit and the fourth reset unit and that outputs a first reset control signal for controlling the first reset unit and the fourth reset unit; and a second reset control line that is electrically connected to the second reset unit and the third reset unit and that outputs a second reset control signal for controlling the second reset unit and the third reset unit. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating a configuration of an imaging device. [Figure 2] FIG. 2 is an overall plan view of the imaging element as viewed from the imaging surface side. [Figure 3] FIG. 3 is an enlarged view of a part of the imaging element shown in FIG. 2. [Figure 4] FIG. 2 is a circuit diagram of a pixel and a readout circuit of the image sensor. [Figure 5] FIG. 2 is a cross-sectional view of an imaging element. [Figure 6] FIG. 10 is a circuit diagram of a pixel and a readout circuit of an image sensor according to Modification 1. [Figure 7] FIG. 10 is a circuit diagram of a pixel and a readout circuit of an image sensor according to Modification 2. DETAILED DESCRIPTION OF THE INVENTION

[0006] An imaging device and an imaging element included in the imaging device according to an embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an imaging device according to an embodiment. FIG. 1 shows an example configuration of an electronic camera 1 (hereinafter referred to as camera 1), which is an example of an imaging device according to an embodiment. For convenience of explanation, a Cartesian coordinate system consisting of x, y, and z axes is provided as shown. In FIG. 1, the z axis is set along the optical axis O of the imaging optical system 2, and the y axis is set perpendicular to the z axis and parallel to the vertical direction of the paper on which FIG. 1 is drawn. The x axis is set along a direction perpendicular to the y and z axes. The camera 1 comprises an imaging optical system (imaging optical system) 2, an imaging element 3, a control unit 4, a memory 5, and an operation unit 7. The imaging optical system 2 has a plurality of lenses including a focus adjustment lens (focus lens) and an aperture, and forms an image of a subject on the imaging element 3. The imaging optical system 2 may be detachable from the camera 1.

[0007] The imaging element 3 is, for example, a CMOS image sensor. The imaging element 3 receives a light beam that has passed through the imaging optical system 2 and captures an image of a subject. As will be described in detail later, the imaging element 3 has a plurality of pixels, each of which has a microlens and a photoelectric conversion unit, arranged two-dimensionally (in a row direction and a column direction intersecting the row direction). The photoelectric conversion unit is formed, for example, by a photodiode (PD). The imaging element 3 has imaging pixels and AF pixels (focus detection pixels). The imaging pixels photoelectrically convert incident light and output a signal (image signal) used for image generation. The AF pixels photoelectrically convert incident light and output a signal (focus detection signal) used for focus detection. The signals (image signal, focus detection signal) generated by the imaging element 3 are output to the control unit 4.

[0008] The memory 5 is a recording medium such as a memory card. Image data and the like are recorded in the memory 5. Writing data to the memory 5 and reading data from the memory 5 are performed by the control unit 4. The operation unit 7 includes various setting switches such as a release button and a power switch, and outputs operation signals to the control unit 4 in response to each operation.

[0009] The control unit 4 is composed of a CPU, ROM, RAM, etc., and controls each unit of the camera 1 based on a control program. The control unit 4 has, as one of its functions, an image data generation unit 4a. The image data generation unit 4a generates image data by performing various image processes on the image signal output from the image sensor 3. The image processes include well-known image processes such as tone conversion, color interpolation, and edge enhancement.

[0010] The imaging element 3 included in the camera 1 of this embodiment will now be described in detail. Fig. 2 is a diagram showing a schematic view of the overall configuration of the image sensor 3 when viewed from the imaging surface side, i.e., from the +z side of Fig. 1. The image sensor 3 has a plurality of pixels 30 arranged in the x and y directions of Fig. 2. Although some of the pixels 30 are omitted in Fig. 2, a large number of pixels 30, for example, 1000 or more, may be arranged in each of the x and y directions. A horizontal control unit HC is provided at the left end of the region (imaging region) in which a plurality of pixels 30 are arranged, and a vertical control unit VC is provided at the top end of the region in the figure.

[0011] The imaging element 3 has a plurality of pixel blocks BC. In FIG. 2, one pixel block BC has a plurality of pixels 30 arranged in the x and y directions and surrounded by a boundary line BB indicated by a dashed line. As will be described later, the output units of the plurality of pixels 30 in each pixel block BC are connected to a single output line and to a single readout unit. Note that the plurality of pixels 30 in each pixel block BC may also be connected to a plurality of output lines and to a plurality of readout units.

[0012] 2, for ease of explanation, the portion corresponding to one pixel block BC is hatched, but each area surrounded by each boundary line BB indicated by a dashed line is a pixel block BC. In the example shown in FIG. 2, a total of 16 pixels 30, four arranged in the x direction and four arranged in the y direction, make up one pixel block BC. The number of pixels arranged in the x and y directions in one pixel block BC is not limited to four, and may be other numbers such as six or eight. The number of pixels arranged in the x and y directions may be different. 2, the contour shape of the pixel block BC is not limited to the rectangle shown in Fig. 2, but may be any shape that encompasses multiple pixels 30. In this case, the shape of the boundary line BB is not a simple straight line, but rather a shape made up of multiple straight lines that are bent and connected.

[0013] FIG. 3 is an enlarged view of some pixel blocks BC (i.e., two pixel blocks BC1 and BC2 adjacent in the x-direction) among the pixels 30 shown in FIG. 2. As shown in FIG. 3, each of the pixels 30 is provided with one of three color filters having different spectral characteristics, e.g., R (red), G (green), or B (blue). The R color filter mainly transmits light in the red wavelength range, the G color filter mainly transmits light in the green wavelength range, and the B color filter mainly transmits light in the blue wavelength range. The pixels have different spectral characteristics depending on the color filters arranged. The pixels 30 include pixels sensitive to red (R) light (hereinafter referred to as R pixels 30R), pixels sensitive to green (G) light (hereinafter referred to as G pixels 30Gr or G pixels 30Gb), and pixels sensitive to blue (B) light (hereinafter referred to as B pixels 30B). These pixels 30 are arranged in a so-called Bayer array. The G pixel 30Gb is a G pixel arranged in the same x direction as the B pixel 30B, and the G pixel 30Gr is a G pixel arranged in the same x direction as the R pixel 30R.

[0014] Pixel block BC1 has four G pixels 30Gb1, four G pixels 30Gr1, four R pixels 30R1, and four B pixels 30B1 arranged in a Bayer array. Pixel block BC2 has four G pixels 30Gb2, four G pixels 30Gr2, four R pixels 30R2, and four B pixels 30B2 arranged in a Bayer array. These pixels 30 are all imaging pixels Gb, Gr, R, and B used to capture an optical image formed on the imaging surface of the image sensor 3.

[0015] 2, vertical selection lines VS1 to VS8 (collectively referred to as vertical selection lines VS) extend in the y direction and are connected to later-described vertical selection transistors TV (see FIG. 4) of each pixel 30. From the horizontal control unit HC, horizontal control lines HS1 to HS4 (collectively referred to as horizontal control lines HS) extend in the x direction and are connected to later-described transfer transistors TX (see FIG. 4) of the pixels 30 that function as transfer units of the pixels 30 for each row, and horizontal selection lines HD extend in the x direction and are connected to later-described horizontal selection transistors TH (see FIG. 4) of the pixels 30.

[0016] As shown in FIG. 3, each of the vertical selection lines VS1 to VS8 is shared by a plurality of pixels 30 aligned in the y direction, and the horizontal selection line HD is shared by a plurality of pixels 30 aligned in the x direction. In the present embodiment, the pixels 30 connected to one of the horizontal control lines HS1 to HS4 include pixels 30 having a first spectral sensitivity and pixels 30 having a second spectral sensitivity different from the first spectral sensitivity. Specifically, the spectral sensitivity of the pixels 30 connected to the horizontal control line HS1 in pixel block BC1 is different from the spectral sensitivity of the pixels 30 connected to the horizontal control line HS1 in pixel block BC2.

[0017] Fig. 4 is a diagram showing an outline of the electrical circuits of the pixels 30 constituting the pixel blocks BC1 and BC2 shown in Fig. 3. Note that Fig. 4 shows the electrical circuits of the pixels 30 in the nth row and the (n+1)th row shown in Fig. 3 as representatives. As shown in Figure 4, horizontal control line HS1 is connected to R pixel 30R1a of pixel block BC1 and G pixel 30Gr2a of pixel block BC2. Similarly, horizontal control line HS2 is connected to G pixel 30Gr1a of pixel block BC1 and R pixel 30R2a of pixel block BC2. Horizontal control line HS3 is connected to R pixel 30R1b of pixel block BC1 and G pixel 30Gr2b of pixel block BC2. Horizontal control line HS4 is connected to G pixel 30Gr1a of pixel block BC1 and R pixel 30R2b of pixel block BC2.

[0018] In each pixel 30 (Gr, R), the photodiode PD, which is a photoelectric conversion unit, photoelectrically converts incident light to generate electric charges and temporarily stores the generated electric charges. The transfer transistor TX is a transfer unit that transfers the electric charges stored in the photodiode PD to a floating diffusion (FD) region FD based on a control signal sent to its gate from a horizontal control line HS. The FD region FD is a storage unit in which a capacitance CC is formed and which stores the electric charges generated in the photodiode. The amplification transistor TA outputs a signal corresponding to the electric charges generated in the photodiode PD when a voltage generated in the FD region FD by the transferred electric charges is applied to its gate.

[0019] A power supply voltage VDD is applied to the input side (drain) of the amplification transistor TA. The reset transistor TR is a reset unit that resets the voltage of the FD region FD to the power supply voltage VDD by discharging the charge in the FD region FD to the power supply voltage VDD side. The output side (source side) of the amplification transistor TA of each pixel 30 is connected to the input side of the vertical selection transistor TV. The gate of the vertical selection transistor TV is connected to a vertical selection line VS, and the vertical selection transistor TV is made conductive or non-conductive by a control signal from the vertical selection unit VC shown in Figure 2.

[0020] The output side of the vertical selection transistor TV is connected to the input side of the horizontal selection transistor TH. The gate of the horizontal selection transistor TH is connected to a horizontal selection line HD, and the horizontal selection transistor TH is rendered conductive or non-conductive by a control signal sent from the horizontal control unit HC shown in FIG. 2. The output side of the horizontal selection transistor TH is connected to an output line RW, which serves as an output unit that outputs a signal based on charges generated by photoelectric conversion to the output line RW, which is a signal line. The output line RW is connected to a readout unit 100 that reads out signals from the pixels 30. The readout unit 100 has, for example, an AD conversion unit that converts analog signals output from the pixels 30 into digital signals, and is provided for each pixel block BC.

[0021] The imaging operation, including the reset operation of the pixels 30 of the image sensor 3 of this embodiment, is substantially the same as that of a conventional CMOS image sensor. That is, prior to an exposure operation for imaging or focus detection, the reset transistor TR and transfer transistor TX are brought into conduction with the power supply voltage VDD, and the FD region FD and photodiode PD are reset to the power supply voltage VDD. Thereafter, the transfer transistor TX is made non-conductive, and exposure for imaging or focus detection is performed with the photodiode PD.

[0022] Next, reading of signals from the pixels 30 of the image sensor 3 will be described. The vertical control unit VC sends signals to the vertical selection line VS1 connected to the R pixel 30R1a in the nth row of the pixel block BC1 and the vertical selection line VS6 connected to the G pixel 30Gr2a in the nth row of the pixel block BC2 shown in Figures 3 and 4, thereby turning on the vertical selection transistor TV of the R pixel 30R1a and the vertical selection transistor TV of the G pixel 30Gr2a.The horizontal control unit HC then sends a control signal to the horizontal control line HS1, thereby turning on the transfer transistor TX of the R pixel 30R1a and the transfer transistor TX of the G pixel 30Gr2a.The horizontal control unit HC then sends a signal to the horizontal selection line HD, thereby turning on the horizontal selection transistors TH of the R pixel 30R1a and the G pixel 30Gr2a. Through the above control, the signal (R signal) of the R pixel 30R1a in pixel block BC1 is output to RW1, and the signal (G signal) of the G pixel 30Gr2a in pixel block BC2 is output to RW6. As a result, the readout unit 100 connected to pixel block BC1 can read out the signal (R signal) of the R pixel 30R1a, and the readout unit 100 connected to pixel block BC2 can read out the signal (G signal) of the G pixel 30Gr2a. After that, the vertical control unit VC sends a signal to the vertical selection line VS1 and the vertical selection line VS6 to make the vertical selection transistor TV non-conductive, and the horizontal control unit HC sends a signal to the horizontal control line HS1 to make the transfer transistor TX non-conductive.

[0023] The vertical control unit VC sends a signal to the vertical selection line VS2 connected to the G pixel 30Gr1a in pixel block BC1 and to the vertical selection line VS5 connected to the R pixel 30R2a in pixel block BC2, thereby turning on the vertical selection transistor TV of the G pixel 30Gr1a and the vertical selection transistor TV of the R pixel 30R2a. The horizontal control unit HC sends a control signal to the horizontal control line HS2, thereby turning on the transfer transistor TX of the G pixel 30Gr1a in pixel block BC1 and the transfer transistor TX of the R pixel 30R2a in pixel block BC2. The horizontal control unit HC then sends a signal to the horizontal selection line HD, thereby turning on the horizontal selection transistors TH of the G pixel 30Gr1a and the R pixel 30R2a. Through the above control, the signal (G signal) of the G pixel 30Gr1a in the pixel block BC1 is output to RW2, and the signal (R signal) of the R pixel 30R2a in the pixel block BC2 is output to RW5. As a result, the readout unit 100 can read out the G signal and the R signal. After that, the vertical control unit VC sends a signal to the vertical selection line VS2 and the vertical selection line VS5 to make the vertical selection transistor TV non-conductive, and the horizontal control unit HC sends a signal to the horizontal control line HS2 to make the transfer transistor TX non-conductive.

[0024] The vertical control unit VC sends a signal to the vertical selection line VS3 connected to the R pixel 30R1b in the pixel block BC1 and to the vertical selection line VS4 connected to the G pixel 30Gr2b in the pixel block BC2, thereby turning on the vertical selection transistor TV of the R pixel 30R1b and the vertical selection transistor TV of the G pixel 30Gr2b. The horizontal control unit HC sends a control signal to the horizontal control line HS3, thereby turning on the transfer transistor TX of the R pixel 30R1b in the pixel block BC1 and the transfer transistor TX of the G pixel 30Gr2b in the pixel block BC2. The horizontal control unit HC then sends a signal to the horizontal selection line HD, thereby turning on the horizontal selection transistors TH of the R pixel 30R1b and the G pixel 30Gr2b. Through the above control, the signal of the R pixel 30R1b in pixel block BC1 is output to RW3, and the signal of the G pixel 30Gr2b in pixel block BC2 is output to RW8. As a result, the readout unit 100 connected to pixel block BC1 can read out the signal of the R pixel 30R1b (R signal), and the readout unit 100 connected to pixel block BC2 can read out the signal of the G pixel 30Gr2b (G signal). Then, the vertical control unit VC sends a signal to the vertical selection line VS3 and the vertical selection line VS8 to make the vertical selection transistor TV non-conductive, and the horizontal control unit HC sends a signal to the horizontal control line HS3 to make the transfer transistor TX non-conductive.

[0025] The vertical control unit VC sends a signal to the vertical selection line VS4 connected to the G pixel 30Gr1b of pixel block BC1 and the vertical selection line VS7 connected to the R pixel 30R2b of pixel block BC2, thereby turning on the vertical selection transistor TV of the G pixel 30Gr1b and the vertical selection transistor TV of the R pixel 30R2b. The horizontal control unit HC sends a control signal to the horizontal control line HS4, thereby turning on the transfer transistor TX of the G pixel 30Gr1b of pixel block BC1 and the transfer transistor TX of the R pixel 30R2b of pixel block BC2. The horizontal control unit HC then sends a signal to the horizontal selection line HD, thereby turning on the horizontal selection transistors TH of the G pixel 30Gr1b and the R pixel 30R2b. Through the above control, the signal from the G pixel 30Gr1b in pixel block BC1 is output to RW4, and the signal from the R pixel 30R2b in pixel block BC2 is output to RW7. As a result, the readout unit 100 connected to pixel block BC1 can read out the signal from the G pixel 30Gr1b (G signal), and the readout unit 100 connected to pixel block BC2 can read out the signal from the R pixel 30R2b (R signal). After that, the vertical control unit VC sends a signal to the vertical selection line VS4 and the vertical selection line VS7 to make the vertical selection transistor TV non-conductive, and the horizontal control unit HC sends a signal to the horizontal control line HS4 to make the transfer transistor TX non-conductive.

[0026] The same processing as that performed for the nth row is performed for the nth row and onward. As a result, signals from the B pixels 30B (B signals) and signals from the G pixels 30Gb (G signals) can be read out from the nth row. The above has described the reading of signals from the pixels 30 in the pixel blocks BC1 and BC2, but this also applies to the other pixel blocks BC. The signals from each pixel 30 in each pixel block BC are output to an output line RW provided in that pixel block BC and read out by the readout unit 100. The vertical selection line VS may be shared by multiple pixel blocks BC. For example, the vertical selection lines VS1 to VS8 may be connected to each pixel 30 in other pixel blocks BC aligned in the y direction with respect to the pixel block BC. The signals read out by the readout unit 100 of each pixel block BC are output from the image sensor 3 via an output circuit (not shown).

[0027] The image data generator 4a rearranges the signals output from the imaging element 3 into an order corresponding to the arrangement of the pixels 30. In this case, the image data generator 4a rearranges the signals output in the order of the Gr signal from the G pixel 30Gr2a, the R signal from the R pixel 30R2a, the Gr signal from the G pixel 30Gr2b, and the R signal from the R pixel 30R2b by making the horizontal control line HS1, horizontal control line HS2, horizontal control line HS3, and horizontal control line HS4 conductive in this order, into the arrangement order of the pixels 30 in the x direction of the nth row. That is, the image data generator 4a rearranges the signals output in the above order into the order of the R signal from the R pixel 30R2a, the Gr signal from the G pixel 30Gr2a, the R signal from the R pixel 30R2b, and the Gr signal from the G pixel 30Gr2b. The image data generator 4a similarly rearranges the signals from the pixels 30 in the (n+1)th row and beyond into an order corresponding to the arrangement of the pixels 30. After the above processing, the image data generating unit 4a performs various image processing on the signal output from the imaging element 3 to generate image data.

[0028] FIG. 5 is a diagram showing a cross section of a pixel 30 portion of the image sensor 3 of this embodiment. Note that FIG. 5 shows only a partial cross section of the entire image sensor 3. The x and z directions shown in FIG. 5 are the same as those shown in FIG. 1. The image sensor 3 is a so-called back-illuminated image sensor. The image sensor 3 photoelectrically converts light incident from above on the page. The image sensor 3 includes a first semiconductor substrate 7 and a second semiconductor substrate 8.

[0029] As described above, the imaging element 3 has a plurality of pixels 30. Each pixel 30 includes an upper pixel portion 30x provided on the first semiconductor substrate 7 and a lower pixel portion 30y provided on the second semiconductor substrate 8. Each upper pixel portion 30x includes one microlens 74, one color filter 73, one light receiving portion 31 of a photodiode PD, and the like.

[0030] The first semiconductor substrate 7 includes a light receiving layer 71 including the light receiving portion 31 of the photodiode PD included in the pixel upper portion 30x, and a wiring layer 72 in which transistors such as a transfer transistor TX and an amplifying transistor TA are formed. The light receiving layer 71 is arranged on the opposite side (back side) of the first semiconductor substrate 7 to the wiring layer 72. In the light receiving layer 71, a plurality of light receiving portions 31 are arranged two-dimensionally.

[0031] On the second semiconductor substrate 8, the vertical selection transistor TV, horizontal selection transistor TH, vertical selection line VS, horizontal control line HS, readout section 100, current source CS, and the like, which are included in the pixel lower portion 30y, are arranged. A plurality of bumps 75 are arranged on the surface of the wiring layer 72. A plurality of bumps 76 corresponding to the plurality of bumps 75 are arranged on the surface of the second semiconductor substrate 8 facing the wiring layer 72. The plurality of bumps 75 and the plurality of bumps 76 are bonded to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the plurality of bumps 75 and the plurality of bumps 76.

[0032] The above-described configuration of the circuit elements disposed on the first semiconductor substrate 7 and the second semiconductor substrate 8 is an example, and some of these components may be disposed on either the first semiconductor substrate 7 or the second semiconductor substrate 8. For example, the light receiving layer 71 including the light receiving portion 31 of the photodiode PD, the transfer transistor TX, the amplifying transistor TA, and the vertical selection transistor TV may be formed on the first semiconductor substrate 7, and the horizontal selection transistor TH, the horizontal control line HS, the readout section 100, and the current source CS may be disposed on the second semiconductor substrate 8.

[0033] The light receiving layer 71 including the light receiving portion 31 of the photodiode PD, the transfer transistor TX, the amplifying transistor TA, the vertical selection transistor TV, the horizontal selection transistor TH, and the horizontal control line HS may be formed on the first semiconductor substrate 7, and the readout portion 100 and the current source CS may be disposed on the second semiconductor substrate 8. The vertical control section VC and the horizontal control section HC may be disposed on either the first semiconductor substrate 7 or the second semiconductor substrate 8. Furthermore, the pixel 30 is not limited to a laminated structure having the first semiconductor substrate 7 and the second semiconductor substrate 8, and the above components may be arranged on a single semiconductor substrate.

[0034] However, if many circuit elements are placed on the first semiconductor substrate 7, it will be impossible to secure sufficient area or volume for placing the light receiving unit 31 on the first semiconductor substrate 7, so it is preferable to place the readout unit 100 and the current source CS on the second semiconductor substrate 8. The color filter 73 of each pixel 30 is arranged with a color filter that matches the spectral sensitivity characteristics of the pixel.

[0035] In the above-described embodiments of the image sensor, the arrangement of the pixels 30 is not necessarily limited to the Bayer arrangement. Furthermore, the horizontal control lines HS may extend in the short side direction (y direction) of the image sensor 3 rather than in the long side direction (x direction), and the vertical selection lines VS may extend in the long side direction (x direction) of the image sensor 3 rather than in the short side direction (y direction). Furthermore, the horizontal control lines HS and vertical selection lines VS that control the signal output of each pixel 30 do not have to extend in the horizontal direction (x direction) and vertical direction (y direction).

[0036] According to the above-described embodiment, the following effects can be obtained. (1) The image sensor 3 includes a plurality of pixel blocks BC and a plurality of horizontal control lines HS. Each of the plurality of pixel blocks BC includes a photodiode PD, which is a photoelectric conversion unit that photoelectrically converts light to generate electric charges, and includes a plurality of pixels 30 arranged in a first direction (x direction) and a second direction (y direction) intersecting the first direction. The plurality of horizontal control lines HS are part of the plurality of pixel blocks BC and are electrically connected to one pixel 30 in each of the plurality of pixel blocks BC, and supply a control signal to the plurality of pixels 30. The plurality of 30 pixels to which one of the plurality of horizontal control lines HS is connected include a pixel 30 having a first spectral sensitivity and a pixel 30 having a second spectral sensitivity different from the first spectral sensitivity. In the case of conventional technology, when one control line for transfer control is provided in common for multiple pixels that generate signals of the same color, if there is an abnormality in the wiring, it becomes impossible to output signals of the specified color from pixels arranged in the same row. In contrast, in the present embodiment, by having the above-described configuration, when an abnormality occurs in any of the horizontal control lines HS, it is possible to prevent signals from being obtained from pixels 30 in the same row that are provided with color filters of the same color, and to prevent characteristic colors from becoming defective in the generated image. Furthermore, even when an abnormality occurs in any of the horizontal control lines HS and a signal of a certain color cannot be obtained, it is possible to perform interpolation processing using signals from other pixels 30 in the same row that are provided with color filters of the same color.

[0037] (2) The pixel 30 of the image sensor 3 includes a transfer transistor TX that transfers electric charges generated in a photodiode PD, which is a photoelectric conversion unit, and at least one of the horizontal control lines HS is connected to the transfer transistor TX. As a result, the circuit configuration of the image sensor 3 of the embodiment can be realized simply by changing the connection destination of the horizontal control line HS in the circuit configuration of a conventional image sensor.

[0038] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment. (Variation 1) The electrical circuit of each pixel 30 is not limited to the example shown in FIG. Fig. 6 is a diagram showing an outline of the electrical circuits of the pixels 30 that make up the pixel blocks BC1 and BC2 in Modification 1. Note that Fig. 6 also shows the circuit configurations of the pixels 30 in the nth and (n+1)th rows as representatives. In the first modification, the image sensor 3 has a configuration in which an FD region FD, which is an accumulation section, is shared by multiple pixels 30 included in a pixel block BC. That is, each pixel 30 in the pixel blocks BC1 and BC2 includes a photodiode PD and a transfer transistor TX, and each pixel 30 in the pixel blocks BC1 and BC2 shares a reset transistor TR, an amplification transistor TA, and a horizontal selection transistor TH.

[0039] In the first modification, as in the embodiment, the pixels 30 connected to one of the horizontal control lines HS1 to HS4 include a pixel 30 having a first spectral sensitivity and a pixel 30 having a second spectral sensitivity different from the first spectral sensitivity. Specifically, the horizontal control line HS1 connects the transfer transistor TX of the R pixel 30R1a in the pixel block BC1 and the transfer transistor TX of the G pixel 30Gr2a in the pixel block BC2. The horizontal control line HS2 connects the transfer transistor TX of the G pixel 30Gr1a in the pixel block BC1 and the transfer transistor TX of the R pixel 30R2a in the pixel block BC2. The horizontal control line HS3 connects the transfer transistor TX of the R pixel 30R1b in the pixel block BC1 and the transfer transistor TX of the G pixel 30Gr2b in the pixel block BC2. The horizontal control line HS4 connects the transfer transistor TX of the G pixel 30Gr1a in the pixel block BC1 and the transfer transistor TX of the R pixel 30R2b in the pixel block BC2. Even with the configuration of the electric circuit of the imaging element 3 of the first modification, the same effects as the effects (1) and (2) obtained by the above-described embodiment can be obtained.

[0040] (Variation 2) Instead of rearranging the signals output from the pixels 30 in the image data generation unit 4a in an order corresponding to the arrangement of the pixels 30, the image sensor 3 may output the signals from the pixels 30 in an order corresponding to the arrangement of the pixels 30. FIG. 7 shows an overview of the electrical circuits of the pixels 30 constituting pixel blocks BC1 and BC2 of Modification 2. FIG. 7 also shows the circuit configuration of the pixels 30 arranged in the nth row and the (n+1)th row as representatives. The image sensor 3 has a memory (storage unit) 101 for each pixel block BC. Other configurations are similar to the configuration of the charge circuit of the pixel 30 shown in FIG.

[0041] As described in the embodiment, in pixel block BC2, signals are output in the following order: Gr signal from G pixel 30Gr2a, R signal from R pixel 30R2a, Gr signal from G pixel 30Gr2b, and R signal from R pixel 30R2b. The signals output in this order are converted into digital signals by readout unit 100 and temporarily stored in memory 101 provided in pixel block BC2. The signals are output from memory 101 in the following order: R signal from R pixel 30R2a, Gr signal from G pixel 30Gr2a, R signal from R pixel 30R2b, and Gr signal from G pixel 30Gr2b, and input to image data generator 4a of control unit 4. In other words, even if horizontal control lines HS are connected to each pixel 30 as in the embodiment, signals can be output from the image sensor 3 in an order corresponding to the arrangement of the pixels 30.

[0042] (Variation 3) At least one of the horizontal control lines HS may be connected to a reset transistor TR, which is a reset unit. At least one of the horizontal control lines HS may be connected to a vertical selection transistor TV, which is an output unit. At least one of the horizontal control lines HS may be connected to a transfer transistor TX, at least one to a reset transistor TR, and at least one to a vertical selection transistor TV. Even when the horizontal control lines HS are connected as described above, the same effect as effect (1) obtained by the above-described embodiment can be obtained.

[0043] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0044] 1: Imaging device, 3: image sensor, 4a: image data generation unit, 7: first semiconductor substrate, 8: second semiconductor substrate, 30:pixels, 100: Reading section, 101: Memory, BC, BC1, BC2: pixel block, HS, HS1, HS2, HS3, HS4: Horizontal control lines PD: photodiode, TX: transfer transistor, TR: Reset transistor, TA: Amplifying transistor

Claims

1. A first pixel block including a first photoelectric conversion unit that converts light that has passed through a first filter having a first spectral characteristic into an electric charge, a second photoelectric conversion unit that converts light that has passed through a second filter having a second spectral characteristic different from the first spectral characteristic into an electric charge and that is arranged next to the first photoelectric conversion unit, a first transfer unit that transfers the electric charge converted by the first photoelectric conversion unit, and a second transfer unit that transfers the electric charge converted by the second photoelectric conversion unit; a second pixel block including: a third photoelectric conversion unit that converts light that has passed through a third filter having the first spectral characteristic into electric charges; a fourth photoelectric conversion unit that converts light that has passed through a fourth filter having the second spectral characteristic into electric charges and that is disposed adjacent to the third photoelectric conversion unit; a third transfer unit that transfers the electric charges converted by the third photoelectric conversion unit; and a fourth transfer unit that transfers the electric charges converted by the fourth photoelectric conversion unit; a first transfer control line electrically connected to the first transfer unit and the fourth transfer unit, and outputting a first transfer control signal for controlling the first transfer unit and the fourth transfer unit; a second transfer control line electrically connected to the second transfer unit and the third transfer unit, and through which a second transfer control signal for controlling the second transfer unit and the third transfer unit is output; An imaging element comprising:

2. A first pixel block including a first photoelectric conversion unit that converts light that has passed through a first filter having a first spectral characteristic into an electric charge, a second photoelectric conversion unit that converts light that has passed through a second filter having a second spectral characteristic different from the first spectral characteristic and that is arranged next to the first photoelectric conversion unit, a first reset unit that resets the voltage of a first storage unit to which the electric charge converted by the first photoelectric conversion unit is transferred, and a second reset unit that resets the voltage of a second storage unit to which the electric charge converted by the second photoelectric conversion unit is transferred; a second pixel block including: a third photoelectric conversion unit that converts light that has passed through a third filter having the first spectral characteristic into an electric charge; a fourth photoelectric conversion unit that converts light that has passed through a fourth filter having the second spectral characteristic into an electric charge and that is disposed adjacent to the third photoelectric conversion unit; a third reset unit that resets a voltage of a third accumulation unit to which the electric charge converted by the third photoelectric conversion unit is transferred; and a fourth reset unit that resets a voltage of a fourth accumulation unit to which the electric charge converted by the fourth photoelectric conversion unit is transferred; a first reset control line electrically connected to the first reset unit and the fourth reset unit, through which a first reset control signal for controlling the first reset unit and the fourth reset unit is output; a second reset control line electrically connected to the second reset unit and the third reset unit, through which a second reset control signal for controlling the second reset unit and the third reset unit is output; An imaging element comprising:

3. 3. The imaging device according to claim 1, the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit are arranged in the row direction in this order: the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit. Image sensor.

4. In the imaging element according to any one of claims 1 to 3, a first conversion unit that converts a first signal based on the charges converted by the first photoelectric conversion unit and a second signal based on the charges converted by the second photoelectric conversion unit into digital signals; a second conversion unit that converts a third signal based on the charges converted by the third photoelectric conversion unit and a fourth signal based on the charges converted by the fourth photoelectric conversion unit into digital signals; An imaging element comprising:

5. The imaging element according to claim 4, a first signal line through which the first signal and the second signal are output; a second signal line through which the third signal and the fourth signal are output; Equipped with the first conversion unit converts the first signal output to the first signal line and the second signal output to the first signal line into digital signals; the second conversion unit converts the third signal output to the second signal line and the fourth signal output to the second signal line into digital signals. Image sensor.

6. The imaging element according to claim 4 or claim 5, the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, and the fourth photoelectric conversion unit are disposed on a first semiconductor substrate; the first conversion unit and the second conversion unit are disposed on a second semiconductor substrate stacked together with the first semiconductor substrate; Image sensor.

7. The imaging element according to any one of claims 1 to 6, an imaging element comprising a third pixel block including a fifth photoelectric conversion unit that converts light that has passed through a fifth filter having the first spectral characteristic into an electric charge, and a sixth photoelectric conversion unit that converts light that has passed through a sixth filter having the second spectral characteristic into an electric charge, the sixth photoelectric conversion unit being disposed adjacent to the fifth photoelectric conversion unit.

8. The imaging element according to claim 7, the third pixel block includes a fifth transfer unit that transfers the charges converted by the fifth photoelectric conversion unit and a sixth transfer unit that transfers the charges converted by the sixth photoelectric conversion unit; Image sensor.

9. The imaging element according to claim 8, the third pixel block includes a fifth reset unit that resets a voltage of a fifth accumulation unit to which the electric charges converted by the fifth photoelectric conversion unit are transferred, and a sixth reset unit that resets a voltage of a sixth accumulation unit to which the electric charges converted by the sixth photoelectric conversion unit are transferred, Image sensor.

10. 10. The imaging device according to claim 7, An imaging element comprising a third conversion unit that converts a fifth signal based on the electric charges converted by the fifth photoelectric conversion unit and a sixth signal based on the electric charges converted by the sixth photoelectric conversion unit into digital signals.

11. The imaging element according to claim 10, a third signal line through which the fifth signal and the sixth signal are output, the third conversion unit converts the fifth signal output to the third signal line and the sixth signal output to the third signal line into digital signals. Image sensor.

12. An imaging device comprising an imaging element described in any one of claims 1 to 11.

13. The imaging device according to claim 12, an imaging device comprising a generation unit electrically connected to the imaging element and configured to generate image data;

14. In the imaging device according to claim 12 or claim 13, An imaging device equipped with an optical system that emits light to the imaging element.

Images