Semiconductor Devices

Abstract

To provide a semiconductor device which can increase to a latch-up resistance amount.SOLUTION: A semiconductor device according to an embodiment includes: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a gate electrode; a third semiconductor region of a first conductivity type; a fourth semiconductor region of a second conductivity type; a second electrode; and a fifth semiconductor region of a second conductivity type. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The gate electrode faces the second semiconductor region across a gate insulation layer in a second direction. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is lined with the third semiconductor region in a third direction. The second electrode includes a contact part which is lined with the third semiconductor region and the fourth semiconductor region in the second direction. The fifth semiconductor region is located between the second semiconductor region and the contact part in a first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. There is a demand for improved latch-up resistance in semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6605870 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving the latch-up resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a gate electrode, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a second electrode, and a fifth semiconductor region of the second conductivity type. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on the second semiconductor region and is aligned with the third semiconductor region in a third direction perpendicular to the first and second directions. The fourth semiconductor region has a higher impurity concentration of the second conductivity type than the second semiconductor region. The second electrode includes a contact portion aligned with the third and fourth semiconductor regions in the second direction. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. The fifth semiconductor region is provided between the second semiconductor region and the contact portion in the first direction, and has a higher impurity concentration of the second conductivity type than the second semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a perspective cross-sectional view showing a part of a semiconductor device according to a reference example. [Figure 3] FIG. 3 is a perspective cross-sectional view showing a part of the semiconductor device according to the embodiment. [Figure 4] 4(a) and 4(b) are cross-sectional views showing a part of the semiconductor device according to the embodiment. [Figure 5] 5(a) and 5(b) are cross-sectional views showing a part of the semiconductor device according to the embodiment. [Figure 6] 6(a) and 6(b) are plan views showing a part of the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a perspective cross-sectional view showing a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In addition, in the present specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to an embodiment. The semiconductor device 100 shown in Fig. 1 is an IGBT. - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + emitter region 3 (third semiconductor region), p + contact region 4 (fourth semiconductor region), p + contact region 5 (fifth semiconductor region), p +The semiconductor device includes a collector region 6 (sixth semiconductor region), a gate electrode 10, a collector electrode 21 (first electrode), an emitter electrode 22 (second electrode), and an insulating layer 25. In FIG. 1, the emitter electrode 22 is indicated by a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction toward the drift region 1 is called "up" and the opposite direction is called "down." These directions are the direction of the collector electrode 21 and the n - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] The collector electrode 21 is provided on the bottom surface of the semiconductor device 100. + The collector region 6 is provided on the collector electrode 21 and is electrically connected to the collector electrode 21. - The drift region 1 is p + The collector region 6 is provided on the substrate.

[0011] The p-type base region 2 is - The n-type drift region 1 is provided on the n-type drift region 1. + emitter region 3 and p + The p-type contact region 4 is provided on the p-type base region 2. + The contact region 4 has an n-type + The emitter region 3 is aligned with the n + Shape emitter region 3 and p + The contact regions 4 are in contact with each other in the Y direction.

[0012] The gate electrode 10 faces the p-type base region 2 in the X direction via the gate insulating layer 11. In the illustrated example, the gate electrode 10 further includes an n - Shape drift region 1, n +emitter region 3, and p + The gate insulating layer 11 faces each of the contact regions 4 through a gate insulating layer 11 .

[0013] The emitter electrode 22 is connected to the p-type base region 2, + Shape emitter region 3, p + The emitter electrode 22 is provided on the p-type contact region 4 and the gate electrode 10 via an insulating layer 25. The emitter electrode 22 includes a contact portion 22a extending toward the p-type base region 2. The contact portion 22a penetrates the insulating layer 25 in the Z direction and is + emitter region 3 and p + The contact area 4 is aligned with the contact area 4 .

[0014] p + The p-type contact region 5 is provided between the p-type base region 2 and the contact portion 22a in the Z direction. + The contact region 5 is an n + It is located below the emitter region 3. + Contact region 4 and p + The p-type impurity concentration of each of the p-type contact regions 5 is higher than the p-type impurity concentration of the p-type base region 2.

[0015] The contact portion 22a is + Shape emitter region 3, p + contact region 4, and p + The p-type base region 2 and the n-type contact region 5 are in contact with each other. + Shape emitter region 3, p + shaped contact region 4, and p + The contact region 5 is electrically connected to the emitter electrode 22. The gate electrode 10 and the emitter electrode 22 are electrically isolated from each other by an insulating layer 25.

[0016] p-type base region 2, n + Shape emitter region 3, p + Shape contact area 4, p +A plurality of p-type contact regions 5 and a plurality of gate electrodes 10 are provided in the X direction. + The contact region 5 and each gate electrode 10 extend in the Y direction. + Shape emitter region 3 and p + The contact regions 4 are alternately arranged in the Y direction.

[0017] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the collector electrode 21 relative to the emitter electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 2. Electrons pass through the channel from the emitter electrode 22 to form the n - In response to the injection of electrons, holes are injected into the n-type drift region 1, and the semiconductor device 100 is turned on. - The injected electrons and holes cause conductivity modulation, resulting in n - The electrical resistance of the p-type drift region 1 decreases. When a potential lower than the threshold is then applied to the gate electrode 10, the channel in the p-type base region 2 disappears, and the semiconductor device 100 enters an off state.

[0018] When the semiconductor device 100 is turned off, n - The electrons stored in the drift region 1 are p + The electrons are discharged through the collector region 6 to the collector electrode 21. - The holes accumulated in the p-type drift region 1 pass through the vicinity of the gate insulating layer 11 and the p-type base region 2, and + Shape contact area 4 or p + The electrons are discharged from the contact region 5 to the emitter electrode 22 .

[0019] An example of the material of each component will be described. n - p-type drift region 1, p-type base region 2, n + Shape emitter region 3, p + Shape contact area 4, p + shaped contact region 5, and p+ The collector region 6 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 25 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The collector electrode 21 and the emitter electrode 22 include a metal such as titanium, tungsten, or aluminum. The contact portion 22a also includes the metal. For example, the emitter electrode 22 including the contact portion 22a has a layered structure of titanium, titanium nitride, and aluminum.

[0020] The impurity concentration of each semiconductor region can be set, for example, as follows: - The n-type impurity concentration of the drift region 1 is 1.0×10 13 ~1.0×10 15 atom / cm 3 The p-type impurity concentration of the p-type base region 2 is 1.0×10 16 ~1.0×10 18 atom / cm 3 n + The n-type impurity concentration of the emitter region 3 is 1.0×10 17 ~1.0×10 21 atom / cm 3 p + Shape contact area 4, p + shaped contact region 5, and p + The p-type impurity concentration of each of the p-type collector regions 6 is 1.0×10 17 ~1.0×10 21 atom / cm 3 is.

[0021] As shown in Figure 1, - The drift region 1 may include a buffer region 1a, a barrier region 1b, and an intermediate region 1c.

[0022] The buffer area 1a is p +When the semiconductor device 100 is switched to the off state, n - The depletion layer spreads from the pn junction between the p-type drift region 1 and the p-type base region 2. The buffer region 1a prevents the depletion layer from spreading, and the depletion layer + Therefore, the electrons can be prevented from reaching the collector region 6.

[0023] The barrier region 1b is provided between the intermediate region 1c and the p-type base region 2, and is located between the gate electrodes 10. By providing the barrier region 1b, it is possible to increase the electrical resistance to holes. As a result, when the semiconductor device 100 is in the on state, holes accumulated in the intermediate region 1c are less likely to be discharged to the emitter electrode 22, and the carrier concentration in the intermediate region 1c can be increased. As a result, the on-resistance of the semiconductor device 100 can be reduced.

[0024] The n-type impurity concentration of each of the buffer region 1a and the barrier region 1b is higher than the n-type impurity concentration of the intermediate region 1c. For example, the n-type impurity concentration of each of the buffer region 1a and the barrier region 1b is 1.0×10 15 ~1.0×10 18 atom / cm 3 The n-type impurity concentration of the intermediate region 1c is 1.0×10 13 ~1.0×10 15 atom / cm 3 is.

[0025] The advantages of the embodiment will be described. The semiconductor device 100 is + shaped collector region 6, n - a p-type drift region 1, a p-type base region 2, and an n + It includes a parasitic thyristor consisting of an emitter region 3. - When holes are discharged from the p-type drift region 1, n +If the potential in the vicinity of the p-type emitter region 3 rises, a parasitic thyristor may operate. If the parasitic thyristor operates, a large current flows in the semiconductor device 100, destroying the semiconductor device 100. For this reason, when holes are discharged, the n-type + It is desirable that the rise in potential in the vicinity of the emitter region 3 be small.

[0026] FIG. 2 is a perspective cross-sectional view showing a part of a semiconductor device according to a reference example. The semiconductor device 100r according to the reference example shown in FIG. + When the semiconductor device 100r is turned off, holes h pass through the vicinity of the gate insulating layer 11 and the p-type base region 2 and are discharged to the emitter electrode 22. FIG. 2 shows an example of a part of the path of the holes h at this time. In path A1, the holes h reach the p-type base region 2 and then pass through the p + In the path A2, the holes h flow through the p-type base region 2 along the gate insulating layer 11 and then pass through the n-type contact region 5. + In the path A3, the holes h pass near the bottom surface of the emitter region 3. After flowing along the gate insulating layer 11, the holes h + The electrons pass near the side surfaces of the emitter region 3. The side surfaces are the end surfaces in the Y direction. In the path A2 or A3, the electrons pass through the n + The electrons pass near the emitter region 3. Therefore, if there are many holes h flowing through the path A2 or A3, a parasitic thyristor may operate.

[0027] FIG. 3 is a perspective cross-sectional view showing a part of the semiconductor device according to the embodiment. In the semiconductor device 100 according to the embodiment, n + The p-type emitter region 3 and the contact portion 22a are adjacent to each other. + 3 illustrates some of the paths of holes h in the semiconductor device 100. In the path A4 or A5, the holes h flow along the gate insulating layer 11 and then pass through the p +2 does not exist in the semiconductor device 100. In addition, the number of holes h passing through the path A2 can be reduced. Therefore, according to the embodiment, the number of holes h passing through the path A2 is reduced compared to the semiconductor device 100r. + This can suppress a rise in potential near the emitter region 3. In the semiconductor device 100, the possibility of the parasitic thyristor operating can be reduced, and the latch-up resistance can be improved.

[0028] Figures 4(a), 4(b), 5(a), and 5(b) are cross-sectional views showing a portion of a semiconductor device according to an embodiment. Figures 4(a) and 4(b) show a portion of a YZ cross section of the semiconductor device 100. Figures 5(a) and 5(b) show a portion of an XZ cross section of the semiconductor device 100. As shown in Figure 4(a), p + The bottom end of the contact region 4 is + 4(a), the amount of holes h flowing through the path A2 or A3 shown in FIG. 2 can be reduced compared to the semiconductor device 100r. Therefore, the latch-up resistance can be improved compared to the semiconductor device 100r.

[0029] p + The position of the lower end of the contact region 4 in the Z direction is determined, for example, by the following method. + The maximum p-type impurity concentration in the p-type contact region 4 is calculated. + Contact region 4 and p + The p-type impurity concentration at a position away from the p-type contact region 5 is calculated. + Between the p-type contact region 4, a set of points having an intermediate value of the two p-type impurity concentrations is + This corresponds to the lower surface of the contact region 4. The point located at the lowest point on the lower surface is the bottom end.

[0030] As shown in Figure 4(b), p + The bottom end of the contact region 4 is +The height may be the same as the lower end of the emitter region 3. The structure shown in FIG. 4(b) does not include the path A3 shown in FIG. 2, which further improves the latch-up resistance. Note that the "height" corresponds to the position in the Z direction.

[0031] As shown in Figure 5(a), p + The bottom end of the contact region 4 is p + It may be located at the same height as part of the contact region 5. + The contact region 4 is p + In the illustrated example, the p + The lower end of the contact region 4 is p + The contact area 5 is located at the same height as the lower end of the contact area 5 .

[0032] As shown in Figure 5(b), p + The bottom end of the contact region 4 is p + It may be located below the lower end of the contact region 5. As shown in FIG. 5(a) or 5(b), + The deeper the bottom end of the contact region 4 is, the more holes that have flowed near the gate insulating layer 11 are attracted to the p + It becomes easier for the electrons to flow to the contact region 4. + The amount of holes flowing near the emitter region 3 can be further reduced, and the latch-up resistance of the semiconductor device 100 can be further improved.

[0033] p + The position of the lower end of the contact region 5 in the Z direction is determined, for example, by the following method. + The maximum p-type impurity concentration in the p-type contact region 5 is calculated. + Contact region 4 and p + The p-type impurity concentration at a position away from the p-type contact region 5 is calculated. + Below the p-type contact region 5, a set of points having an intermediate value of the two p-type impurity concentrations is + This corresponds to the lower surface of the contact region 5. The point located at the lowest point on the lower surface is the bottom end.

[0034] p + The p-type impurity concentration of the p-type contact region 4 is + The p-type impurity concentration may be the same as that of the p-type contact region 5. + The p-type impurity concentration of the p-type contact region 4 is + The p-type impurity concentration may be higher than that of the p-type contact region 5. + This allows holes to flow more easily into the contact region 4. This further improves the latch-up resistance of the semiconductor device 100. + The p-type impurity concentration of the p-type contact region 4 is + The impurity concentration of the n-type contact region 5 may be lower than that of the p-type contact region 5. - The device has a built-in diode consisting of a p-type drift region 1 and a p-type base region 2. + When the p-type impurity concentration of the p-type contact region 4 is low, the p + This can suppress the injection of holes through the contact region 4. This can reduce the amount of carriers emitted when the built-in diode is turned off, and can reduce the switching loss of the semiconductor device 100.

[0035] 6(a) and 6(b) are plan views showing a part of the semiconductor device according to the embodiment. For example, as shown in Figure 6(a), n + Shape emitter region 3 and p + The contact regions 4 are alternately arranged in the Y direction. + The length L2 of the contact region 4 in the Y direction is n + The length L2 is longer than the length L1 of the emitter region 3 in the Y direction. + The distance between the emitter regions 3 in the Y direction is equal to the distance between the emitter regions 3 in the Y direction. + This allows holes to flow more easily into the contact region 4. This further improves the latch-up resistance of the semiconductor device 100.

[0036] As shown in FIG. 6(b), a pair of p + A contact region 4 is provided, and an n+ The emitter region 3 is a pair of p + The p-type contact region 4 may be provided between the p-type contact region 4. + The length L2 of the contact region 4 is n + The length L1 of the emitter region 3 may be shorter than the length L1 of the emitter region 3. + emitter region 3 and a pair of p + A plurality of sets S including the p-type contact region 4 are provided in the Y direction. A part of the p-type base region 2 is located between the sets S adjacent to each other in the Y direction. When the length L2 is shorter than the length L1, the p + This can suppress the injection of holes through the contact region 4. As a result, the switching loss of the semiconductor device 100 can be reduced.

[0037] (Variation) FIG. 7 is a perspective cross-sectional view showing a semiconductor device according to a modified example of the embodiment. The semiconductor device 110 according to the modification shown in Fig. 7 is a MOSFET. Compared with the semiconductor device 100, the semiconductor device 110 has a p + Instead of the collector region 6, + The semiconductor device 110 has an n-type drain region 7. + Instead of the emitter region 3, the collector electrode 21, and the emitter electrode 22, + A source region 3S, a drain electrode 21D (first electrode), and a source electrode 22S (second electrode) are provided. - The drift region 1 does not include a buffer region 1a and a barrier region 1b.

[0038] n + The structures of the source region 3S, the drain electrode 21D, and the source electrode 22S are each + The structure of the emitter region 3, the collector electrode 21, and the emitter electrode 22 is applicable. + The drain region 7 is connected to the drain electrode 21D and the n - The n-shaped drift region 1 is provided between the n-shaped drift region 1 and the n-shaped drift region 2. + The drain region 7 comprises a semiconductor material. +The n-type impurity concentration of the n-type drain region 7 is - The n-type impurity concentration of the n-type drift region 1 is higher than that of the n-type drift region 2.

[0039] When a voltage equal to or greater than the threshold is applied to the gate electrode 10 while a positive voltage is applied to the drain electrode 21D relative to the source electrode 22S, the semiconductor device 110 is turned on. Electrons flow from the source electrode 22S to the drain electrode 21D through the channel. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 110 is turned off.

[0040] When the semiconductor device 110 is switched to the off state, the voltage applied to the semiconductor device 110 temporarily increases significantly, which may cause avalanche breakdown. At this time, a large number of carriers (electrons and holes) are generated. The electrons are + The electrons pass through the p-type drain region 7 and are discharged from the drain electrode 21D. The holes pass through the p-type base region 2 and are discharged from the source electrode 22S.

[0041] The semiconductor device 110 is - a p-type drift region 1, a p-type base region 2, and an n + Therefore, when the semiconductor device 110 is turned off, the p-type base region 2 includes a parasitic bipolar transistor formed of an n-type source region 3S. + It is desirable that the rise in potential near the source region 3S is small.

[0042] In the semiconductor device 110, p + Therefore, similar to the semiconductor device 100, the n-type contact region 4 is provided. + The number of holes passing through the vicinity of the source region 3S can be reduced. According to this modification, the possibility of a parasitic bipolar transistor operating in the semiconductor device 110 can be reduced, and the latch-up resistance can be improved.

[0043] Embodiments may include the following features. (Appendix 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a fourth semiconductor region of a second conductivity type provided on the second semiconductor region, aligned with the third semiconductor region in a third direction perpendicular to the first direction and the second direction, and having a higher impurity concentration of the second conductivity type than the second semiconductor region; a second electrode including a contact portion aligned with the third semiconductor region and the fourth semiconductor region in the second direction, the second electrode being provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the contact portion in the first direction and having a higher impurity concentration of the second conductivity type than the second semiconductor region; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device according to claim 1, wherein a lower end of the fourth semiconductor region is located at the same height as a lower end of the third semiconductor region or lower than the lower end of the third semiconductor region. (Appendix 3) 2. The semiconductor device according to claim 1, wherein a lower end of the fourth semiconductor region is located at the same height as a lower end of the fifth semiconductor region or lower than the lower end of the fifth semiconductor region. (Appendix 4) 4. The semiconductor device according to claim 3, wherein the fourth semiconductor region is in contact with the fifth semiconductor region. (Appendix 5) a pair of the fourth semiconductor regions spaced apart from each other in the third direction, 5. The semiconductor device according to claim 1, wherein the third semiconductor region is located between the pair of fourth semiconductor regions. (Appendix 6) a plurality of pairs each including the third semiconductor region and the pair of fourth semiconductor regions are provided in the third direction; 6. The semiconductor device according to claim 5, wherein a portion of the second semiconductor region is provided between the pairs adjacent to each other in the third direction. (Appendix 7) 5. The semiconductor device according to any one of claims 1 to 4, wherein the length of the fourth semiconductor region in the third direction is longer than the length of the third semiconductor region in the third direction. (Appendix 8) 8. The semiconductor device according to claim 7, wherein a plurality of the third semiconductor regions and a plurality of the fourth semiconductor regions are provided alternately in the third direction. (Appendix 9) 9. The semiconductor device according to any one of appendices 1 to 8, further comprising a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region.

[0044] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, SIMS (secondary ion mass spectrometry).

[0045] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0046] 1:n - 1a: p-type drift region; 1b: barrier region; 1c: intermediate region; 2: p-type base region; 3: n + Shape emitter region, 3S:n + Shape source area, 4,5:p + Shape contact area, 6:p + Shape collector area, 7:n + Drain region, 10: gate electrode, 11: gate insulating layer, 21: collector electrode, 21D: drain electrode, 22: emitter electrode, 22S: source electrode, 22a: contact portion, 25: insulating layer, 100, 100r, 110: semiconductor device

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a fourth semiconductor region of a second conductivity type provided on the second semiconductor region, aligned with the third semiconductor region in a third direction perpendicular to the first direction and the second direction, and having a higher impurity concentration of the second conductivity type than the second semiconductor region; a second electrode including a contact portion aligned with the third semiconductor region and the fourth semiconductor region in the second direction, the second electrode being provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the contact portion in the first direction and having a higher impurity concentration of the second conductivity type than the second semiconductor region; Equipped with a lower end of the fourth semiconductor region is located at the same height as a lower end of the fifth semiconductor region or lower than the lower end of the fifth semiconductor region, A semiconductor device, wherein a lower end of the third semiconductor region is located above a lower end of the contact portion.

2. 2. The semiconductor device according to claim 1, wherein a lower end of said fourth semiconductor region is located at the same height as a lower end of said third semiconductor region or lower than said lower end of said third semiconductor region.

3. The semiconductor device according to claim 1 , wherein said fourth semiconductor region is in contact with said fifth semiconductor region.

4. a pair of the fourth semiconductor regions spaced apart from each other in the third direction; 4. The semiconductor device according to claim 1, wherein said third semiconductor region is located between said pair of fourth semiconductor regions.

5. a plurality of pairs each including the third semiconductor region and the pair of fourth semiconductor regions are provided in the third direction; The semiconductor device according to claim 4 , wherein a part of said second semiconductor region is provided between said pairs adjacent to each other in said third direction.

6. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a pair of second conductivity type fourth semiconductor regions provided on the second semiconductor region, having a higher impurity concentration of the second conductivity type than the second semiconductor region, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; a third semiconductor region of the first conductivity type provided on the second semiconductor region and positioned between the pair of fourth semiconductor regions; a second electrode including a contact portion aligned with the third semiconductor region and the fourth semiconductor region in the second direction, the second electrode being provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the contact portion in the first direction and having a higher impurity concentration of the second conductivity type than the second semiconductor region; Equipped with a lower end of each of the pair of fourth semiconductor regions is located at the same height as a lower end of the fifth semiconductor region or lower than the lower end of the fifth semiconductor region, a plurality of pairs each including the third semiconductor region and the pair of fourth semiconductor regions are provided in the third direction; a part of the second semiconductor region is provided between the pairs adjacent to each other in the third direction; a length of each of the pair of fourth semiconductor regions in the third direction being shorter than a length of the third semiconductor region in the third direction;

7. 4. The semiconductor device according to claim 1, wherein the length of said fourth semiconductor region in said third direction is longer than the length of said third semiconductor region in said third direction.

8. 8. The semiconductor device according to claim 7, wherein a plurality of said third semiconductor regions and a plurality of said fourth semiconductor regions are provided alternately in said third direction.

9. 4. The semiconductor device according to claim 1, further comprising a sixth semiconductor region of the second conductivity type provided between said first electrode and said first semiconductor region.

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