Insulated gate semiconductor device

Abstract

Provided is a semiconductor device comprising a p-type body region 11, an n-type inversion layer 15, an n-type source region 12, an n-type drain region 13, an insulated gate electrode 16, and a drift region 100. The drift region 100 comprises: an n-type first low-concentration layer 21n, a second low-concentration layer 22, and a third low-concentration layer 23 composed of a first semiconductor material; an n-type carrier formation layer 30 positioned in one of gaps therebetween; and a p-type carrier formation layer 40 positioned in the other of the gaps. The n-type carrier formation layer 30 has a two-dimensional electron layer 31e formed at a hetero-interface formed between the first semiconductor material and the second semiconductor material. The p-type carrier formation layer 40 is formed of a doping layer of the first semiconductor material. One end of the n-type carrier formation layer 30 is electrically connected to the n-type drain region 13, and the other end thereof is electrically connected to the n-type source region 12 via the n-type inversion layer 15. Further, the p-type carrier formation layer 40 is electrically connected to the p-type body region 11.

Description

[Technical Field]

[0001] This specification discloses a technique relating to an insulated gate semiconductor device. [Background technology]

[0002] A lateral insulated gate semiconductor device such as that disclosed in Non-Patent Document 1 has been known. FIGS. 42 and 43 are diagrams illustrating an example of its structure. This insulated gate semiconductor device has an offset gate structure for an n-channel insulated gate semiconductor device, and includes a p-type body region 11 formed in a low-concentration n-type drift layer 2 on a low-concentration p-type semiconductor substrate 1, a gate electrode 16 with a field plate formed on the p-type body region 11 via a gate insulating film 14, a high-concentration n-type source region 12 formed at one end of the gate electrode 16 in the p-type body region 11, a high-concentration n-type drain region 13 formed at a position spaced apart from the other end of the gate electrode 16, a drift region 100 extending between the drain and gate, and a thick insulating film 17 formed on this drift region 100. In this structure, a depletion layer from the pn junction between the high-resistance p-type semiconductor substrate 1 and the low-concentration n-type drift layer 2 extends to the surface of the low-concentration n-type drift layer 2, reducing the electric field at the surface and achieving a high breakdown voltage. For this reason, this structure is called a RESURF (REduced SURface Field) structure.

[0003] 44 to 46 show an example of a multilayer structure called an SJ (Super Junction) lateral SOI (Silicon On Insulator) insulated gate semiconductor device, which is another conventional structure. Fig. 44 is a plan view of the SJ structure lateral SOI insulated gate semiconductor device, Fig. 45 is a cross-sectional view taken along line BB in Fig. 44, and Fig. 46 is a cross-sectional view taken along line CC in Fig. 44. A similar structure is disclosed in Patent Document 1.

[0004] The SOI insulated gate semiconductor device of this example has a structure including a p-type body region 11 formed in a semiconductor substrate 2, a trench gate electrode 16a formed on the sidewall of the p-type body region 11 with a gate insulating film 14 interposed therebetween, a heavily doped n-type source region 12 formed along the upper edge of the trench gate electrode 16a, a heavily doped n-type drain region 13 formed at a position spaced apart from the trench gate electrode 16a, a drift region 100 extending between the drain and gate, and a thick insulating film 17 formed on the drift region 100.

[0005] The drift region 100 in this example has a layered structure in which plate-shaped n-type drift layers 30 and plate-shaped low-concentration p-type layers 40 are alternately stacked, with approximately the same doping surface density. A lower p-type drift layer 40b is formed directly below the lowest n-type drift layer 30, and an upper p-type drift layer 40a is also formed on the uppermost n-type drift layer 30. The doping surface density of the upper p-type drift region 40a and the lower p-type drift region 40b is approximately half that of the central p-type drift region 40. One end of each of the multiple n-type drift layers 30 forms a pn junction with the p-type body region 11, and the other end is connected to the n-type high-concentration drain region 13. Branching out from the n-type high-concentration drain region 13 side forms multiple n-type drift layers 30 (drift regions 100) connected in parallel. In addition, one end of each of the multiple p-type drift layers 40, 40a, and 40b is connected to the p-type body region 11, and the other ends thereof form a pn junction with the n-type heavily doped drain region 13 side, branching from the p-type body region 11 and being connected in parallel.

[0006] When the insulated gate semiconductor device is in the on state, carriers (electrons) flow from the n-type heavily doped source regions 12 into the multiple n-type drift layers 30 through the inversion layer 15 directly below the gate insulating film 14, and a drift current flows due to the electric field generated by the drain-source voltage. On the other hand, when the device is in the off state, the inversion layer 15 directly below the gate insulating film 14 disappears. If the thicknesses of the n-type drift layer 30 and the p-type drift layer 40 are sufficiently thin, a depletion layer extending from the pn junction between the n-type drift layer 30 and the p-type drift layer 40 depletes both the n-type drift layer 30 and the p-type drift layer 40 while the drain-source voltage is low (several volts), causing the entire drift region 100 to become depleted, effectively forming a high-resistance i-type region, equivalent to a lateral pin diode with a very long i-type region. Therefore, even if the drain-source voltage subsequently becomes as high as several hundred volts, the electric field is applied to the long i-type region, achieving high breakdown voltage. On the other hand, the concentration of the n-type drift layer 30 can be several orders of magnitude higher than that of the i-type region, so low resistance can be achieved in the on state, and this structure makes it possible to achieve both low resistance and high breakdown voltage to a certain extent. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-100783 [Non-patent literature]

[0008] [Non-Patent Document 1] AW Ludikhuize, “A review of RESURF technology”, Proceedings of 12th International Symposium on Power Semiconductor Devices and ICs, (France), 2000, p.12-18 [Non-patent document 2] C. Rindfleisch, et al., “The On-Chip Lateral Super-Junction IGBT in Integrated High-Voltage Low-Power Converters”, Proceedings of 33rd International Symposium on Power Semiconductor Devices and ICs, (Sun), 2021, p.51-54 Summary of the Invention [Problem to be solved by the invention]

[0009] The following two common problems exist in both the RESURF (REduced SURface Field) structure shown in FIGS. 42 and 43, which are examples of conventional structures, and the SJ (Super Junction) structure shown in FIGS.

[0010] To reduce the resistance, it is necessary to increase the concentration of the first-conductivity-type (n-type) low-concentration drift region. Furthermore, as shown in Figures 42-43 and 44-46, the second-conductivity-type (p-type) body region, which determines the threshold voltage of the insulated gate transistor, is formed with a concentration higher than that of the first-conductivity-type (n-type) drift layer after its formation. Furthermore, because the threshold voltage of the insulated gate transistor typically needs to be less than a dozen volts due to usage constraints, there is a limit to how high the concentration of the second-conductivity-type (p-type) body region can be. Therefore, there is a limit to how high the concentration of the first-conductivity-type (n-type) drift layer can be, and therefore, there is a limit to how low the resistance of the drift region can be.

[0011] Furthermore, it is known that increasing the concentration of the first conductivity type (n-type) drift region to reduce resistance reduces carrier mobility due to scattering by the doped impurities. Therefore, the resistance, which is proportional to the product of carrier concentration and mobility, does not decrease as rapidly as the concentration is increased. In other words, there is a limit to the trade-off relationship between drift region concentration and drift region mobility in conventional structures, and therefore there is a limit to how much the resistance of the drift region can be reduced.

[0012] In view of the above, an object of the present invention is to provide a high-voltage insulated gate semiconductor device that can reduce the on-state resistance while suppressing an increase in threshold voltage and a decrease in mobility. [Means for solving the problem]

[0013] In order to solve the above problems, the technology disclosed in this specification is embodied in the following insulated gate semiconductor device: That is, the insulated gate semiconductor device includes a second conductivity type body region made of a first semiconductor material, a first conductivity type high concentration source region, and a first conductivity type high concentration drain region, and has a gate electrode in contact with the drift region and the second conductivity type body region via a gate insulating film, the drift region passing a drift current in an on state and being depleted in an off state, and also has a first conductivity type inversion layer (two-dimensional carrier layer) generated at the interface between the second conductivity type body region and the gate insulating film in the on state, and the second conductivity type body region is electrically connected to the first conductivity type high concentration source region, The drift region includes first, second, and third low concentration layers made of the first semiconductor material, a first conductivity type carrier formation layer located either between the first low concentration layer and the second low concentration layer or between the second low concentration layer and the third low concentration layer, and a second conductivity type inversion layer located on the other side. and a conductive type carrier formation layer, wherein the first conductive type carrier formation layer has one or more heterogeneous material layers made of a second semiconductor material having a band gap different from that of the first semiconductor material, and a first conductive type two-dimensional carrier layer is formed in the first conductive type carrier formation layer at each of the heterointerfaces with the one or more heterogeneous material layers, separated from the doping impurities, one end of the first conductive type carrier formation layer in the drift region is electrically connected to the first conductive type drain region, and the other end of the first conductive type carrier formation layer in the drift region is electrically connected to the first conductive type source region via the first conductive type inversion layer, and in the second conductive type carrier formation layer, a second conductive type carrier layer is generated in the first semiconductor material by one or more doping layers, and is electrically connected to the second conductive type body region.

[0014] In the semiconductor device described above, by adjusting the voltage applied to the gate electrode, a drift current can be passed through the drift region in the on-state and the drift region can be depleted in the off-state. Specifically, in the on-state (when the absolute value of the voltage applied to the gate electrode is equal to or greater than the absolute value of the threshold voltage), a first-conductivity-type inversion layer is generated at the interface between the second-conductivity-type body region and the gate insulating film, and first-conductivity-type carriers are injected into the first-conductivity-type carrier formation layer. The first-conductivity-type source region and the first-conductivity-type drain electrode are electrically connected via the first-conductivity-type inversion layer and the first-conductivity-type carrier formation layer. Therefore, the p-n junction between the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer has approximately the same potential, and first-conductivity-type carriers and second-conductivity-type carriers are formed in the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer, respectively. In particular, the first-conductivity-type carrier formation layer has at least one pair (i.e., an even number of two or more) of heterointerfaces, and first-conductivity-type two-dimensional carriers permeate along each heterointerface. This creates an electrical connection between the source electrode and the drain electrode with relatively low resistance. Meanwhile, in the off state (when the absolute value of the voltage applied to the gate electrode is less than or equal to the threshold voltage), the first-conductivity-type inversion layer at the interface between the second-conductivity-type body region and the gate insulating film is eliminated, cutting off the carrier supply to the first-conductivity-type carrier formation layer. The source-drain voltage is then applied as a reverse bias to the pn junction formed by the first-conductivity-type carrier layer and the second-conductivity-type carrier layer, depleting the first-conductivity-type carrier layer and the second-conductivity-type carrier layer. At the same time, the entire drift region, including the first low-concentration layer, the second low-concentration layer, and the third low-concentration layer, is depleted, allowing a high voltage to be applied between the source and drain.

[0015] In the above structure, the second-conductivity-type body region is formed in one of the first low-concentration layer, second low-concentration layer, or third low-concentration layer, which is independent of the concentration of the first-conductivity-type carrier-formation layer. Therefore, increasing the concentration of the first-conductivity-type carrier-formation layer does not affect the threshold voltage, which depends on the concentration of the second-conductivity-type body region. Furthermore, in the first-conductivity-type carrier-formation layer, the first-conductivity-type two-dimensional carrier layer that contributes to the main current is formed in a region separate from the doping impurity layer across the heterointerface. Therefore, increasing the concentration of the first-conductivity-type doping impurity does not decrease the mobility of the first-conductivity-type two-dimensional carrier layer. In other words, the structure of the present invention provides an insulated gate semiconductor device that can reduce on-state resistance while suppressing an increase in threshold voltage and a decrease in mobility. [Brief explanation of the drawings]

[0016] [Figure 1] 3 is a plan view taken along line AA in FIG. 2, and schematically shows the planar structure of an insulated gate semiconductor device 10A according to the first embodiment. [Figure 2] 2 is a cross-sectional view taken along line BB in FIG. 1, and schematically shows the cross-sectional structure of insulated gate semiconductor device 10A according to Example 1. FIG. [Figure 3] 2 is a cross-sectional view taken along line CC in FIG. 1, and schematically shows the cross-sectional structure of insulated gate semiconductor device 10A according to Example 1. FIG. [Figure 4] FIG. 6 is a plan view taken along line AA in FIG. 5, and schematically shows the planar structure of an insulated gate semiconductor device 10B according to a second embodiment. [Figure 5] 5 is a cross-sectional view taken along line BB in FIG. 4, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10B according to a second embodiment. [Figure 6] 5 is a cross-sectional view taken along line CC in FIG. 4, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10C according to a second embodiment. [Figure 7] FIG. 9 is a plan view taken along line AA in FIG. 8, and schematically shows the planar structure of an insulated gate semiconductor device 10C according to a third embodiment. [Figure 8]FIG. 8 is a cross-sectional view taken along line BB in FIG. 7, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10C according to a third embodiment. [Figure 9] FIG. 11 is a plan view taken along line AA in FIG. 10, and schematically shows the planar structure of an insulated gate semiconductor device 10D according to a fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line BB in FIG. 9, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10D according to a fourth embodiment. [Figure 11] FIG. 10 is a cross-sectional view taken along line CC in FIG. 9, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10D according to a fourth embodiment. [Figure 12] FIG. 14 is a plan view taken along line AA in FIG. 13, and schematically shows the planar structure of an insulated gate semiconductor device 10Da according to Example 4. [Figure 13] FIG. 13 is a cross-sectional view taken along line BB in FIG. 12, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10Da according to a fourth embodiment. [Figure 14] FIG. 13 is a cross-sectional view taken along line CC in FIG. 12, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10Da according to a fourth embodiment. [Figure 15] FIG. 17 is a plan view taken along line AA in FIG. 16, and schematically shows the planar structure of an insulated gate semiconductor device 10E according to a fifth embodiment. [Figure 16] FIG. 16 is a cross-sectional view taken along line BB in FIG. 15, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10E according to a fifth embodiment. [Figure 17] 16 is a cross-sectional view taken along line CC in FIG. 15, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10E according to a fifth embodiment. [Figure 18] 20 is a plan view taken along line AA in FIG. 19, and schematically shows the planar structure of an insulated gate semiconductor device 10F according to Example 6. FIG. [Figure 19] 19 is a cross-sectional view taken along line BB in FIG. 18, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10F according to a sixth embodiment. [Figure 20]19 is a cross-sectional view taken along line CC in FIG. 18, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10F according to a sixth embodiment. [Figure 21] 23 is a plan view taken along line AA in FIG. 22, and schematically illustrates the planar structure of an insulated gate semiconductor device 10G according to Example 7. FIG. [Figure 22] 22 is a cross-sectional view taken along line BB in FIG. 21, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10G according to Example 7. FIG. [Figure 23] 22 is a cross-sectional view taken along line CC in FIG. 21, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10G according to Example 7. FIG. [Figure 24] 26 is a plan view taken along line AA in FIG. 25, and schematically illustrates the planar structure of an insulated gate semiconductor device 10Ga according to Example 7. FIG. [Figure 25] 25 is a cross-sectional view taken along line BB in FIG. 24, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10Ga according to Example 7. FIG. [Figure 26] 25 is a cross-sectional view taken along line CC in FIG. 24, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10Ga in accordance with Example 7. FIG. [Figure 27] FIG. 31 is a plan view taken along line AA in FIG. 30, and schematically shows the planar structure of an insulated gate semiconductor device 10H according to an eighth embodiment. [Figure 28] FIG. 28 is a cross-sectional view taken along line BB in FIG. 27, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10H according to an eighth embodiment. [Figure 29] FIG. 28 is a cross-sectional view taken along line CC in FIG. 27, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10H according to an eighth embodiment. [Figure 30] FIG. 28 is a cross-sectional view taken along line DD in FIG. 27, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10H according to an eighth embodiment. [Figure 31] 33 is a plan view taken along line AA in FIG. 32, and schematically shows the planar structure of an insulated gate semiconductor device 10I according to Example 9. FIG. [Figure 32]32 is a cross-sectional view taken along line BB in FIG. 31, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10I according to Example 9. FIG. [Figure 33] 32 is a cross-sectional view taken along line CC in FIG. 31, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10I according to Example 9. FIG. [Figure 34] 36 is a plan view taken along line AA in FIG. 35, and schematically shows the planar structure of an insulated gate semiconductor device 10J in accordance with Example 10. FIG. [Figure 35] 35 is a cross-sectional view taken along line BB in FIG. 34, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10J according to a tenth embodiment. [Figure 36] 35 is a cross-sectional view taken along line CC in FIG. 34, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10J in accordance with Example 10. FIG. [Figure 37] 39 is a plan view taken along line AA in FIG. 38, and schematically shows the planar structure of an insulated gate semiconductor device 10K in accordance with an eleventh embodiment. [Figure 38] 38 is a cross-sectional view taken along line BB in FIG. 37, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10K in accordance with an eleventh embodiment. [Figure 39] 38 is a cross-sectional view taken along line CC in FIG. 37, and schematically shows the cross-sectional structure of an insulated gate semiconductor device 10K in accordance with an eleventh embodiment. [Figure 40] 12 is a schematic diagram showing a cross-sectional structure of an insulated gate semiconductor device 10L according to a twelfth embodiment. [Figure 41] 13A and 13B are schematic diagrams illustrating a cross-sectional structure of an insulated gate semiconductor device 10M according to a thirteenth embodiment. [Figure 42] FIG. 44 is a plan view taken along line AA in FIG. 43, and schematically shows the planar structure of a conventional horizontal insulated gate semiconductor device. [Figure 43] FIG. 43 is a cross-sectional view taken along line BB in FIG. 42, and schematically shows the cross-sectional structure of a conventional horizontal insulated gate semiconductor device. [Figure 44] FIG. 46 is a plan view taken along the line AA in FIG. 45, and schematically shows the planar structure of a conventional SJ structure lateral SOI insulated gate semiconductor device. [Figure 45] 45 is a cross-sectional view taken along line BB in FIG. 44, and schematically shows the cross-sectional structure of a conventional SJ-structure lateral SOI insulated gate semiconductor device. [Figure 46] 45 is a cross-sectional view taken along the line CC in FIG. 44, and schematically shows the cross-sectional structure of a conventional SJ-structure lateral SOI insulated gate semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0017] In one embodiment of the present technology, the semiconductor substrate may be composed of a stack of a first low-concentration layer, a first-conductivity-type carrier formation layer, a second low-concentration layer, a second-conductivity-type carrier formation layer, and a third low-concentration layer, or a stack of a first low-concentration layer, a second-conductivity-type carrier formation layer, a second low-concentration layer, a first-conductivity-type carrier formation layer, and a third low-concentration layer, and the concentrations of the first low-concentration layer, the second low-concentration layer, and the third low-concentration layer may be equal to or lower than the concentration of the second-conductivity-type body region. Furthermore, the first low-concentration layer, the second low-concentration layer, and the third low-concentration layer may be a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, or an intrinsic-type semiconductor layer. With this configuration, the second-conductivity-type body region can be formed in the first low-concentration layer, the second low-concentration layer, and the third low-concentration layer, which are regions separate from the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer. Therefore, even if the concentrations of the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer are increased, the concentration of the second-conductivity-type body region can be set low. This makes it possible to set low the threshold value of the gate voltage (i.e., threshold voltage) for forming a first-conductivity-type inversion layer between the second-conductivity-type body region and the gate insulating film.

[0018] In one embodiment of the present technology, the first-conductivity-type carrier formation layer may have a first-conductivity-type (i.e., one of n-type and p-type) impurity introduced along one or more heterointerfaces formed between the first semiconductor material and the second semiconductor material. Additionally, the second-conductivity-type carrier formation layer may have a second-conductivity-type (i.e., the other of n-type and p-type) impurity introduced. With this configuration, a carrier layer (electron layer or hole layer) can be formed in the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer.

[0019] In one embodiment of the present technology, the first conductivity type carrier formation layer may be provided with one or more heterogeneous material layers, and since the first and second semiconductor materials constituting the heterointerface have different constituent elements or constituent element ratios and have a step in their conduction band minimum Ec or valence band maximum Ev, impurities may be doped into the material with the higher conduction band minimum Ec or the semiconductor material with the lower valence band maximum Ev to generate a two-dimensional carrier layer (two-dimensional electron layer or two-dimensional hole layer) in the semiconductor material with the lower conduction band minimum Ec or the semiconductor material with the higher valence band maximum Ev. With this configuration, the two-dimensional carrier layer is formed in a region separate from the doped impurity layers across each heterointerface, thereby preventing a decrease in mobility due to impurities impeding the movement of two-dimensional carriers.

[0020] In one embodiment of the present technology, one end of the first-conductivity-type carrier formation layer in the drift region may be electrically connected to the drain electrode via a first-conductivity-type heavily doped drain region, and the other end of the first-conductivity-type carrier formation layer in the drift region may be electrically connected to the source electrode via a first-conductivity-type inversion layer and a first-conductivity-type heavily doped source region. With this configuration, the first-conductivity-type inversion layer can be controlled by a gate voltage to turn on and off the current in the drift region. The first-conductivity-type heavily doped drain region may be replaced with a second-conductivity-type heavily doped drain region.

[0021] In one embodiment of the present technology, a first-conductivity-type second heavily doped drain region having a higher concentration than the second-conductivity-type carrier formation layer may be provided to electrically connect the other end of the first-conductivity-type carrier formation layer in the drift region to the first-conductivity-type inversion layer. With this configuration, the resistance between the other end of the first-conductivity-type carrier formation layer and the first-conductivity-type inversion layer can be reduced.

[0022] In the above-described embodiment, a second-conductivity-type high-concentration body region having a higher concentration than the first-conductivity-type carrier formation layer may be provided to electrically connect the second-conductivity-type carrier formation layer and the second-conductivity-type body region. With this configuration, the second-conductivity-type carrier formation layer is electrically connected to the high-concentration source electrode, allowing carriers from the second-conductivity-type carrier formation layer to be more efficiently delivered to the source electrode, thereby enabling faster switching. Alternatively, a second-conductivity-type high-concentration body region may be provided between the first-conductivity-type high-concentration drain region and the first-conductivity-type second high-concentration drain region. The gate electrode may be positioned to function as both the second-conductivity-type high-concentration body region and the second-conductivity-type high-concentration body region. With this configuration, the electric field near the first-conductivity-type second high-concentration drain region can be alleviated.

[0023] In one embodiment of the present technology, a first low-concentration layer of the first conductivity type may be provided to electrically connect the other end of the first conductivity type carrier formation layer in the drift region to the first conductivity type inversion layer. Alternatively, a trench gate may be provided to directly connect the first conductivity type carrier formation layer to the first conductivity type inversion layer. These configurations enable electrical connection between the other end of the first conductivity type carrier formation layer and the first conductivity type inversion layer without providing a first conductivity type second high-concentration drain region.

[0024] In the above-described embodiment, a second-conductivity-type high-concentration body region having a higher concentration than the first-conductivity-type carrier formation layer may be provided to electrically connect the second-conductivity-type carrier formation layer and the second-conductivity-type body region. With this configuration, the second-conductivity-type carrier formation layer is electrically connected to the high-concentration source electrode, allowing carriers in the second-conductivity-type carrier formation layer to be more efficiently delivered to the source electrode, enabling faster switching. Furthermore, in this embodiment, a first-conductivity-type second high-concentration drain region is not provided, and therefore a second-conductivity-type second high-concentration body region is not required.

[0025] In one embodiment of the present technology, a spacer layer (non-doped layer) may be provided between the two-dimensional carrier layer and the doped impurity layer. With this configuration, the influence of the doped impurity layer on the two-dimensional carrier layer can be further reduced, thereby further reducing the decrease in mobility. In particular, the thickness of the spacer layer may be approximately 10 nm or less, and in this case, the decrease in mobility can be further reduced.

[0026] In one embodiment of the present technology, a non-doped layer may be provided between the plurality of doped impurity layers in the first conductive type carrier formation layer and the second conductive type carrier formation layer, which increases the degree of freedom in designing each carrier formation layer.

[0027] In one embodiment of the present technology, the difference between the areal density of the first-conductivity-type carriers and the areal density of the second-conductivity-type carriers may be small in the total carrier areal density of the entire semiconductor substrate 2, including the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer in the drift region. With this configuration, the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer are more easily depleted, making it possible to achieve a higher breakdown voltage. In particular, the difference may be approximately 10% or less. In this case, a high breakdown voltage with less variation is possible.

[0028] In one embodiment of the present technology, the thickness of each second semiconductor material layer in the first conductivity type carrier formation layer in the drift region may be smaller than the thickness of the low-concentration layer of the first semiconductor material. This configuration allows the overall thickness of the epitaxially grown layer to be thin, and also reduces crystal distortion, making manufacturing easier. In particular, the thickness may be approximately 3 nm to 50 nm. In this case, it is easy to achieve both a high two-dimensional carrier layer surface density and a reduced thickness of the heterogeneous material layer.

[0029] In one embodiment of the present technology, the carrier areal densities of the first low-concentration layer, the second low-concentration layer, and the third low-concentration layer may be smaller than the areal densities of the second-conductivity-type body region, the first-conductivity-type carrier formation layer, and the second-conductivity-type carrier formation layer. This configuration reduces the influence of the carrier areal density of the low-concentration layer, making it easier to adjust the balance of the areal densities of the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer. In particular, the difference may be approximately 10% or less. In this case, a high breakdown voltage with less variation is possible.

[0030] In one embodiment of the present technology, a stack of a first low-concentration layer, a first-conductivity-type carrier formation layer, a second low-concentration layer, a second-conductivity-type carrier formation layer, and a third low-concentration layer, or a stack of a first low-concentration layer, a second-conductivity-type carrier formation layer, a second low-concentration layer, a first-conductivity-type carrier formation layer, and a third low-concentration layer, may be repeatedly stacked. With such a configuration, the number of main current (drift current) paths increases, thereby enabling further reduction in resistance.

[0031] In the above-described embodiments, the first conductivity type inversion layer (i.e., the second conductivity type body region) may be formed in any of the first low concentration layer, the second low concentration layer, or the third low concentration layer. This configuration increases the degree of freedom in the structure and facilitates design. Furthermore, the low concentration layer in which the first conductivity type inversion layer is not formed may be omitted. This configuration allows the semiconductor substrate to be made thinner, facilitating manufacturing.

[0032] In one embodiment of the present technology, the support substrate of the insulated gate semiconductor device may be a p-type, n-type, or i-type high-resistance (or semi-insulating) semiconductor substrate, an insulator such as SiO2, or a combination thereof (such as a partial SOI substrate).

[0033] In one embodiment of the present technology, the combination of the first semiconductor material and the second semiconductor material, that is, the combination of dissimilar material layers forming a heterointerface, may be two of Si, SiGe, and SiGeC, or two of GaAs, InGaAs, AlGaAs, and InAlGaAs, or any other combination of semiconductors that can form a heterointerface. [Example]

[0034] 1 to 3, an insulated gate semiconductor device 10A of Example 1 will be described. The insulated gate semiconductor device 10A of this Example includes a support substrate 1 and a semiconductor substrate 2 provided on the support substrate 1. The semiconductor substrate 2 includes a second conductivity type (p-type) body region 11, a first conductivity type (n-type) heavily doped source region 12, and a first conductivity type (n-type) heavily doped drain region 13. As an example, the first conductivity type (n-type) heavily doped source region 12 and the first conductivity type (n-type) heavily doped drain region 13 may be made of, for example, n-type heavily doped Si, and the second conductivity type (p-type) body region 11 may be made of, for example, p-type heavily doped Si. The semiconductor substrate 2 also has a drift region 100 that passes a drift current in the on state and is depleted in the off state, and a gate electrode 16 that contacts the second conductivity type (p type) body region 11 via a gate insulating film 14. The semiconductor substrate 2 also has a first conductivity type (n type) inversion layer 15 (two-dimensional electron layer) that is generated at the interface between the second conductivity type (p type) body region 11 and the gate insulating film 14 in the on state, and the second conductivity type (p type) body region 11 may be electrically connected to the first conductivity type (n type) high-concentration source region 12 (via a source electrode 18).

[0035] The semiconductor substrate 2 includes a first low-concentration layer 21, a second low-concentration layer 22, and a third low-concentration layer 23, which are low-concentration Si semiconductor layers; a first conductivity type (n-type) carrier formation region 30 located between the first low-concentration layer 21 and the second low-concentration layer 22; and a second conductivity type (p-type) carrier formation layer 40 located between the second low-concentration layer 22 and the third low-concentration layer 23. The first low-concentration layer 21, the second low-concentration layer 22, and the third low-concentration layer 23 are made of a first semiconductor material and may be p-type, n-type, or i-type. The thicknesses of the first low-concentration layer 21, the second low-concentration layer 22, and the third low-concentration layer 23 are not particularly limited, but may be approximately 0 nm to 1 μm. The support substrate 1 below the semiconductor substrate 2 may be a p-type high-resistance semiconductor substrate, an n-type high-resistance semiconductor substrate, an i-type high-resistance semiconductor substrate, a semi-insulating substrate, an insulating substrate, or a partially insulating substrate.

[0036] The first conductivity type (n-type) carrier formation layer 30 has one or more second semiconductor material layers 32. For example, there is a step at the conduction band minimum Ec (and valence band maximum Ev) of the first semiconductor material Si and the second semiconductor material SiGe, forming a heterointerface. The second semiconductor material layer 32 is in contact with each of the first low-concentration layer 21 and the second low-concentration layer 22, and a pair of heterointerfaces is formed on both sides of the second semiconductor material layer 32. The thickness of the second semiconductor material layer 32 may be approximately the same as the thicknesses of the first low-concentration layer 21, the second low-concentration layer 22, and the third low-concentration layer 23, or may be sufficiently smaller than these thicknesses, for example, approximately 3 nm to 50 nm.

[0037] Since there is a step in the conduction band minimum Ec or valence band maximum Ev of the first and second semiconductor materials constituting the heterointerface, impurities may be doped into the semiconductor material with the higher conduction band minimum Ec (or the lower valence band maximum Ev) to generate two-dimensional electrons (or two-dimensional holes) in the semiconductor material with the lower conduction band minimum Ec (or the higher valence band maximum Ev). For example, if the first semiconductor material is Si and the second semiconductor material is SiGe, a heterointerface is formed at the interface between the spacer layer (non-doped SiGe layer) 32s and the low-concentration Si layer 21. When an n-type doped SiGe region 32d is formed by doping an n-type impurity (e.g., As) to a thickness of about 10 nm or less (preferably about 1 nm to 6 nm) from the heterointerface at the upper end on the second semiconductor material SiGe (high conduction band minimum Ec) side through a spacer layer (non-doped SiGe layer) 32s having a thickness of about 10 nm or less (preferably about 1 nm to 3 nm), a two-dimensional electron layer 31e is formed on the first semiconductor material Si (low conduction band minimum Ec) side of the heterointerface. Therefore, because the two-dimensional electron layer formed on the Si side is separated from the doped impurity layer on the SiGe side by the heterointerface and the spacer layer (non-doped SiGe layer) 32s, even if the doped impurity concentration increases, the mobility of the two-dimensional electron layer 31e formed on the Si side does not decrease, and therefore a lower resistance than conventional structures can be achieved. The spacer layer (non-doped SiGe layer) 32s is inserted for the purpose of suppressing a decrease in mobility, but is not essential and may be omitted.

[0038] One end of the first conductivity type (n type) carrier formation layer 30 in the drift region 100 may be electrically connected to the first conductivity type (n type) heavily doped drain region 13, and the other end of the n type carrier formation layer in the drift region 100 may be electrically connected to the first conductivity type (n type) source region 12 via the first conductivity type (n type) second heavily doped drain region 13a and the first conductivity type (n type) inversion layer 15. Also, the first conductivity type (n type) heavily doped drain region 13 may be replaced with a second conductivity type (p type) heavily doped drain region.

[0039] The combination of the first semiconductor material and the second semiconductor material is not particularly limited and may be two of Si, SiGe, and SiGeC, or two of GaAs, AlGaAs, InAlGaAs, and InGaAs, or any other combination of semiconductors that can form a heterointerface.

[0040] The second conductivity type (p-type) carrier formation layer 40 may have an impurity-doped layer 40d made of one or more first semiconductor materials. The thickness of the impurity-doped layer may be approximately the same as the thicknesses of the first low-concentration layer 21, the second low-concentration layer 22, and the third low-concentration layer 23, or may be significantly smaller than these, for example, 3 nm to 50 nm (100 nm). The second conductivity type (p-type) carrier formation layer 40 may be located between the second low-concentration layer 22 and the third low-concentration layer 23, and one or more layers may be doped with p-type impurities (e.g., B) to form one or more second conductivity type (p-type) carrier layers.

[0041] The second conductivity type (p-type) carrier formation layer 40 may be electrically connected to the second conductivity type (p-type) body region 11. This electrical connection may be made, for example, by a deep-diffused second conductivity type (p-type) high-concentration body region 10, as shown in FIGS.

[0042] With the above configuration, in the semiconductor device 10A of this embodiment, by adjusting the voltage applied to the gate electrode 16, it is possible to cause a drift current to flow laterally in the drift region 100 in the on state and to deplete the drift region 100 in the off state. That is, in the on state (a state in which the voltage applied to the gate electrode is equal to or higher than the threshold voltage), a first conductivity type inversion layer 15 is generated at the interface between the second conductivity type (p type) body region 11 and the gate insulating film 14, and further, first conductivity type carriers (electrons) are injected into the first conductivity type (n type) carrier formation layer, and the first conductivity type (n type) high concentration source region and the first conductivity type (n type) high concentration drain region are electrically connected via the first conductivity type inversion layer and the first conductivity type carrier formation layer. Therefore, the pn junction between the first conductivity type (n type) carrier formation layer 30 and the second conductivity type (p type) carrier formation layer 40 has approximately the same potential, and a first conductivity type (n type) carrier layer (electron layer) and a second conductivity type (p type) carrier layer (hole layer) are formed in the first conductivity type (n type) carrier formation layer 30 and the second conductivity type (p type) carrier formation layer 40, respectively. In particular, the first conductivity type (n-type) carrier formation layer has one or more heterointerfaces, and a first conductivity type (n-type) two-dimensional carrier layer (two-dimensional electron layer) 31e is formed along the heterointerfaces. This provides an electrical connection between the source electrode 18 and the drain electrode 19 with relatively low resistance. On the other hand, in the off state (a state in which the voltage applied to the gate electrode is equal to or lower than the threshold voltage), when the first conductivity type inversion layer 15 at the interface between the second conductivity type (p-type) body region 11 and the gate insulating film 14 is eliminated, the supply of carriers to the first conductivity type (n-type) carrier formation layer 30 is cut off. As a result, the source-drain voltage is applied as a reverse bias to the pn junction formed by the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40, so that the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40 are depleted, and the entire drift region 100, including the first low-concentration layer 21, the second low-concentration layer 22, and the third low-concentration layer 23, is depleted, and the source-drain voltage can be applied to the entire drift region 100.

[0043] In the above configuration, it is desirable that the difference between the first conductivity type (n type) carrier surface density and the second conductivity type (p type) carrier surface density in the total carrier surface density of the entire semiconductor substrate 2 including the first conductivity type (n type) carrier formation layer 30 and the second conductivity type (p type) carrier formation layer 40 is small (particularly, within about 10%).In that case, similar to a so-called superjunction structure, the electric field strength throughout the drift region 100 becomes uniform, and therefore the insulated gate semiconductor device 10A and the insulated gate semiconductor device 10Aa can achieve a high off-state breakdown voltage.

[0044] Furthermore, in the semiconductor device 10A of this embodiment, it is desirable that the concentrations of the first low concentration layer 21, the second low concentration layer 22, and the third low concentration layer 23 are smaller than the areal densities of the second conductivity type body region 11, the first conductivity type (n-type) carrier formation layer 30, and the second conductivity type (p-type) carrier formation layer 40 (particularly, approximately 10% or less is desirable).In this case, the influence of the difference between the first conductivity type (n-type) carrier areal density and the second conductivity type (p-type) carrier areal density on the total carrier areal density of the entire semiconductor substrate 2 including the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40 described above is reduced, making it easier to achieve a high breakdown voltage.

[0045] In addition, in the semiconductor device 10A of this embodiment, it is desirable that the heterogeneous material layer 32 made of SiGe be sufficiently thinner than the first low concentration layer 21, the second low concentration layer 22, and the third low concentration layer 23 made of Si (particularly 3 nm to 50 nm is desirable).In this case, even when two types of semiconductor materials are grown alternately as crystals, the accumulation of strain caused by the difference in lattice constants is suppressed, making it relatively easy to manufacture a multilayer Si / SiGe heterostructure.

[0046] 1 to 3, in order to alleviate electric field concentration near the first conductivity type (n type) second heavily doped drain region 13a, a second conductivity type (p type) second heavily doped body region 10a may be provided between the first conductivity type (n type) second heavily doped drain region 13a and the first conductivity type (n type) heavily doped drain region 13, and electrically connected to the source electrode 18. With such a configuration, a higher off-state breakdown voltage can be achieved. [Example]

[0047] 4 to 6, an (insulated gate) semiconductor device 10B of Example 2 will be described. Unlike Example 1, the semiconductor device 10B of this Example includes a buried second conductivity type (p-type) high-concentration body region 10b. The following mainly describes the differences from Example 1, and the same reference numerals are used to denote components common to Example 1, thereby omitting redundant description.

[0048] As shown in FIGS. 4 to 6, unlike in the first embodiment, the second conductivity type (p type) carrier formation layer 40 may be electrically connected to the second conductivity type (p type) body region 11 by a buried second conductivity type (p type) high concentration body region 10b instead of the deep diffusion second conductivity type (p type) high concentration body region 10. [Example]

[0049] 7 and 8, an insulated gate semiconductor device 10C of Example 3 will be described. Unlike Example 1, the semiconductor device 10C of this Example has a structure in which the first conductivity type (n-type) second heavily doped drain region 13a and the second conductivity type (p-type) second heavily doped body region 10a can be omitted. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be denoted by the same reference numerals to avoid redundant description.

[0050] As shown in this embodiment, a first conductivity type (n-type) first low-concentration layer 21n may be provided to electrically connect the other end of the first conductivity type (n-type) carrier formation layer 30 in the drift region 100 to the first conductivity type (n-type) inversion layer 15. This configuration enables electrical connection between the other end of the first conductivity type (n-type) carrier formation layer 30 and the first conductivity type (n-type) inversion layer 15 without providing a first conductivity type (n-type) second high-concentration drain region 13a. Furthermore, the depth of the first conductivity type (n-type) high-concentration drain region 13 does not need to be as deep as in FIG. 8 , and may be approximately the same as the first conductivity type (n-type) high-concentration source region 12.

[0051] 1 to 3, in order to reduce electric field concentration near the first-conductivity-type (n-type) second heavily doped drain region 13a, a second-conductivity-type (p-type) second heavily doped body region 10a is provided between the first-conductivity-type (n-type) second heavily doped drain region 13a and the first-conductivity-type (n-type) heavily doped drain region 13a, and is electrically connected to the source electrode 18, thereby achieving a higher off-state breakdown voltage. However, as shown in FIGS. 7 and 8, if the first-conductivity-type (n-type) second heavily doped drain region 13a is not present, the second-conductivity-type (p-type) second body region may not be present. In FIGS. 7 to 8, the second-conductivity-type (p-type) carrier formation layer 40 may be electrically connected to the source electrode 18 via the second-conductivity-type (p-type) body region 10. [Example]

[0052] 9 to 11, an insulated gate semiconductor device 10D of Example 4 will be described. An insulated gate semiconductor device 10C of this Example differs from Example 1 in the configuration of the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40. The following mainly describes the differences from Example 1, and the same reference numerals are used to denote configurations common to Example 1, and redundant description will be omitted.

[0053] As shown in this embodiment, two or more heterointerfaces and doped regions may be provided in the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40. Figures 9 to 11 show an example having four heterointerfaces and doped layers, but without a spacer layer (non-doped SiGe layer) 32s for simplicity. When n-type doped SiGe regions 32d are formed at the four heterointerfaces in the first conductivity type (n-type) carrier formation layer 30, first conductivity type (n-type) carrier layers (two-dimensional electron layers) 31e and 33e are formed on the first semiconductor material Si (lower conduction band minimum Ec) side of the four heterointerfaces.

[0054] Additionally, four second-conductivity-type (p-type) doped regions 40d may be formed in the second-conductivity-type (p-type) carrier formation layer 40. Forming four second-conductivity-type (p-type) doped regions 40d in the second-conductivity-type (p-type) carrier formation layer 40 results in four second-conductivity-type (p-type) carrier layers 40. Furthermore, in the drift region 100, if the total p-type and n-type carrier areal densities of the entire semiconductor substrate 2 including the first-conductivity-type (n-type) carrier formation layer 30 and the second-conductivity-type (p-type) carrier formation layer 40 are approximately the same, a high breakdown voltage can be achieved similarly to the first embodiment.

[0055] In the insulated gate semiconductor device 10D of this embodiment, there are four first conductivity type (n-type) carrier layers (two-dimensional electron layers), which increases the number of main current paths between the source and drain, thereby making it possible to further reduce the resistance between the source and drain.

[0056] Note that all low-concentration layers other than the uppermost first low-concentration layer in which the non-doped SiGe region 32nd, non-doped Si region 30nd, non-doped Si region 40nd, and inversion layer 15 are formed may be omitted, as shown in Figures 12 to 14, for example, insulated gate semiconductor device 10Da. In this case, the thickness of the heterogeneous material layers can be reduced, thereby reducing strain between the heterogeneous material layers. Note that although Figures 12 to 14 omit all low-concentration layers other than the uppermost first low-concentration layer in which the inversion layer is formed, and all non-doped layers, any of these layers may be formed as appropriate.

[0057] 12 to 14, the boundaries of the homogeneous layers are left, but since the boundaries of the homogeneous layers have no practical meaning, the embodiments of FIGS. 12 to 14 can also be regarded as incorporating three first conductivity type (n-type) carrier layers (two-dimensional electron layers) and one second conductivity type (p-type) carrier layer 40, and if the total carrier surface densities of the p-type and n-type layers are approximately the same, a high breakdown voltage can be achieved as in Example 1. [Example]

[0058] 15 to 17, an insulated gate semiconductor device 10E of Example 5 will be described. Semiconductor device 10E of this example differs from Example 1 in the low concentration layer forming inversion layer 15. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be denoted by the same reference numerals to avoid redundant description.

[0059] As shown in this embodiment, the second conductivity type (p-type) body region 11, the first conductivity type (n-type) high-concentration source region 12, the gate insulating film 14, the gate electrode 16, and the first conductivity type (n-type) second high-concentration drain region 13a may be formed to reach the second low-concentration layer, and a first conductivity type (n-type) inversion layer 15 may be formed at the interface with the gate insulating film 14 in contact with the second conductivity type (p-type) body region 11 provided in the second low-concentration layer. For simplicity of illustration, Figures 15 to 17 show an example in which the spacer layer (non-doped SiGe layer) 32s, the non-doped SiGe layer 32nd, and the non-doped Si layer 40nd are not provided, but some or all of these layers may be provided.

[0060] In this embodiment, one end of the first conductivity type (n type) carrier formation layer 30 in the drift region 100 may be (electrically) connected to the first conductivity type (n type) high-concentration drain region 13, and the other end of the first conductivity type (n type) carrier formation layer 30 in the drift region 100 may be electrically connected to the first conductivity type (n type) source region 12 via the first conductivity type (n type) second high-concentration drain region 13 a and the first conductivity type (n type) inversion layer 15.

[0061] In this embodiment, both or one of the first and third low concentration layers, which are low concentration layers that do not form the inversion layer 15, may be omitted. [Example]

[0062] 18 to 20, an insulated gate semiconductor device 10F of Example 6 will be described. The semiconductor device 10F of this Example differs from Example 1 in the low concentration layer forming inversion layer 15. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be denoted by the same reference numerals to avoid redundant description.

[0063] As shown in this embodiment, the second conductivity type (p-type) body region 11, the first conductivity type (n-type) source region 12, the gate insulating film 14, the gate electrode 16, and the first conductivity type (n-type) second drain region 13a are formed to reach the third low-concentration layer, and a first conductivity type (n-type) inversion layer 15 may be formed at the interface with the gate insulating film 14 in contact with the second conductivity type (p-type) body region 11 provided in the third low-concentration layer. Note that, for simplification of the drawings, Figures 18 to 20 show an example in which the spacer layer (non-doped SiGe layer) 32s, the non-doped SiGe layer 32nd, and the non-doped Si layer 40nd are not provided, but some or all of these layers may be provided.

[0064] In addition, in this embodiment, one end of the first conductivity type (n type) carrier formation layer 30 in the drift region 100 may be (electrically) connected to the first conductivity type (n type) drain region 13, and the other end of the first conductivity type (n type) carrier formation layer 30 in the drift region 100 may be electrically connected to the first conductivity type (n type) source region 12 via the first conductivity type (n type) second drain region 13a and the first conductivity type (n type) inversion layer 15.

[0065] In this embodiment, both or one of the first low concentration layer and the second low concentration layer, which are low concentration layers in which the inversion layer 15 is not formed, may be omitted. [Example]

[0066] 21 to 23, an insulated gate semiconductor device 10G of Example 7 will be described. The semiconductor device 10G of this example differs from Example 1 in the configuration of the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be denoted by the same reference numerals to avoid redundant description.

[0067] 21 to 23, the stack of the first low-concentration layer 21, the first conductivity type (n-type) carrier formation layer 30, the second low-concentration layer 22, the second conductivity type (p-type) carrier formation layer 40, and the third low-concentration layer 23 may be repeated multiple times. While FIGS. 21 to 23 show an example in which the stack is repeated twice, it may be repeated three, four, or more times.

[0068] Additionally, in insulated gate semiconductor device 10G of this embodiment, the low concentration layers that do not form first conductivity type (n-type) inversion layer 15 do not need to be formed, and an example in which all low concentration layers other than uppermost low concentration layer 21 are omitted is shown in Figures 24 to 26 as insulated gate semiconductor device 10Ga. Note that, for the sake of simplicity, Figures 21 to 23 and 24 to 26 show an example in which spacer layer (non-doped SiGe layer) 32s, non-doped SiGe layer 32nd, and non-doped Si layer 40nd are not provided, but these layers may be provided.

[0069] In the insulated gate semiconductor device 10G and the insulated gate semiconductor device 10Ga of this embodiment, the presence of multiple n-type carrier formation layers 30 and multiple p-type carrier formation layers 40 increases the number of main current paths between the source and drain, thereby making it possible to further reduce the resistance between the source and drain. [Example]

[0070] 27 to 30, an insulated gate semiconductor device 10H of Example 8 will be described. Unlike Example 1, the semiconductor device 10H of this Example has a configuration in which the functions of the p-type high-concentration body region 10 and the p-type second high-concentration body region 10a are integrated. The following mainly describes the differences from Example 1, and components common to Example 1 are designated by the same reference numerals to avoid redundant description.

[0071] 27 to 30, the first conductivity type (n-type) heavily doped source region 12, the inversion layer 15, and the first conductivity type (n-type) second heavily doped drain region 13a may be disposed parallel to the first conductivity type (n-type) heavily doped drain region 13, instead of being disposed perpendicularly as in Example 1. Also, as shown in Figures 27 to 30, by disposing a p-type heavily doped body region 10 at the position of the p-type second heavily doped body region 10a in Example 1, the p-type heavily doped body region 10, the second conductivity type (p-type) heavily doped body region 11, and the first conductivity type (n-type) heavily doped source region 12 may be electrically connected by a source electrode 18. That is, the p-type high-concentration body region 10 in this embodiment electrically connects the source electrode and the second conductivity type (p-type) carrier formation layer 40, similar to the p-type high-concentration body region 10 in Example 1, and at the same time, relieves electric field concentration near the first conductivity type (n-type) second high-concentration drain region 13a, similar to the p-type second high-concentration body region 10a in Example 1. Note that, for the sake of simplicity, examples are shown in Figures 27 to 30 without the spacer layer (non-doped SiGe layer) 32s, the non-doped SiGe layer 32nd, and the non-doped Si layer 40nd, but these layers may be provided.

[0072] 27 to 30 show a structure in which a plurality of n-type carrier formation layers 30 and p-type carrier formation layers 40 are formed and low-concentration layers other than the non-doped SiGe layer 32nd, the non-doped Si layer 40nd, and the first low-concentration layer 21 are omitted, but the configuration of the semiconductor substrate 2 is not limited to this and may be any of the various embodiments described above. [Example]

[0073] 31 to 33, an insulated gate semiconductor device 10I of Example 9 will be described. The semiconductor device 10I of this example has a gate electrode structure different from that of Example 1, and is configured using a trench gate electrode structure. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be assigned the same reference numerals and redundant description will be omitted.

[0074] 31 to 33, the gate electrode structure in this embodiment is different from that in Example 1, and may be a trench gate electrode structure instead of a planar gate electrode structure. Also, it is possible to electrically connect a plurality of stacked first conductivity type (n-type) carrier formation layers 30 by using an inversion layer 15 formed by trench gate electrodes 16a. In such a case, the first conductivity type (n-type) second heavily doped drain region 13a shown in FIGS. 31 to 33 may be omitted.

[0075] 31 to 33, the first conductivity type (n-type) heavily doped source region 12, the inversion layer 15, and the first conductivity type (n-type) second heavily doped drain region 13a may be disposed parallel to the first conductivity type (n-type) heavily doped drain region 13, instead of being disposed perpendicularly as in Example 1. Also, as shown in FIGS. 31 to 33, by disposing a p-type heavily doped body region 10 at the position of the p-type second heavily doped body region 10a in Example 1, the p-type heavily doped body region 10, the second conductivity type (p-type) heavily doped body region 11, and the first conductivity type (n-type) heavily doped source region 12 may be electrically connected by a source electrode 18. That is, the p-type heavily doped body region 10 in this embodiment electrically connects the source electrode and the second conductivity type (p-type) carrier formation layer 40, similar to the p-type heavily doped body region 10 in Example 1, and at the same time, relieves electric field concentration near the first conductivity type (n-type) second heavily doped drain region 13a, similar to the p-type second heavily doped body region 10a in Example 1. Note that, for simplification of the drawings, Figures 31 to 33 show an example in which the spacer layer (non-doped SiGe layer) 32s, the non-doped SiGe layer 32nd, and the non-doped Si layer 40nd are not provided, but these layers may be provided.

[0076] 31 to 33 show a structure in which a plurality of n-type carrier formation layers 30 and p-type carrier formation layers 40 are formed and low-concentration layers other than the non-doped SiGe layer 32nd, the non-doped Si layer 40nd, and the first low-concentration layer 21 are omitted, but the configuration of the semiconductor substrate 2 is not limited to this and may be any of the various embodiments described above. [Example]

[0077] 34 to 36, an insulated gate semiconductor device 10J of Example 10 will be described. The semiconductor device 10J of this example differs from Example 1 in the positions of the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40. The following mainly describes the differences from Example 1, and the same reference numerals are used to denote components common to Example 1, and redundant description will be omitted.

[0078] As shown in this embodiment, the semiconductor substrate 2 does not have to be a laminate of the first low-concentration layer 21, the first conductivity type (n-type) carrier formation layer 30, the second low-concentration layer 22, the second conductivity type (p-type) carrier formation layer 40, and the third low-concentration layer 23 shown in Example 1, but may be a laminate of the first low-concentration layer 21, the second conductivity type (p-type) carrier formation layer 40, the second low-concentration layer 22, the first conductivity type (n-type) carrier formation layer 30, and the third low-concentration layer 23. In other words, the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40 may be upside down.

[0079] In addition, in the drift region 100, if the total p-type and n-type carrier areal densities of the entire semiconductor substrate 2, including the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40, are approximately the same, a high breakdown voltage can be achieved as in Example 1. In all of the other examples described above, the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40 may also be arranged in the up-down positions reversed. [Example]

[0080] 37 to 39, an insulated gate semiconductor device 10K of Example 11 will be described. The semiconductor device 10K of this example differs from Example 1 in the arrangement of the first conductivity type (n-type) and the second conductivity type (p-type). Below, differences from Example 1 will be mainly described, and configurations common to Example 1 will be denoted by the same reference numerals to avoid redundant description.

[0081] As shown in this example, a structure in which the polarities of all regions, including the polarities of the first-conductivity-type carrier formation layer and the second-conductivity-type carrier formation layer, are reversed may be used. That is, in this example, the first-conductivity-type carrier formation layer including the heterointerface may be the p-type carrier formation layer 40, and the second-conductivity-type carrier formation layer not including the heterointerface may be the n-type carrier formation layer 30. In this case, too, a high breakdown voltage can be achieved as in Example 1 as long as the difference between the first-conductivity-type (p-type) carrier areal density and the second-conductivity-type (n-type) carrier areal density in the total carrier areal density of the entire semiconductor substrate 2 including the first-conductivity-type (p-type) carrier formation layer 40 and the second-conductivity-type (n-type) carrier formation layer 30 is small. In all other examples described above, a structure in which the polarities of all regions other than the first-conductivity-type (p-type) and second-conductivity-type (n-type) carrier formation layer 40 and the second-conductivity-type (n-type) carrier formation layer 30 are reversed may be used, as in this example shown in Figures 37 to 39.

[0082] 37 to 39, in this embodiment, there is a step in the valence band upper end Ev of the first semiconductor material Si and the second semiconductor material SiGe, and a heterointerface may be formed at the interface between the spacer layer (non-doped Si layer) 41s and the non-doped SiGe layer 42. Because there is a step in the valence band upper end Ev of the spacer layer (non-doped Si layer) 41s and the non-doped SiGe layer 42 that constitute this heterointerface, a p-type doped Si region 41d may be formed by doping a p-type impurity on the semiconductor material side with a lower valence band upper end Ev, or a two-dimensional hole layer 42h may be generated in the SiGe region 42 on the semiconductor material side with a higher valence band upper end Ev.

[0083] As shown in FIGS. 37 to 39, the second conductivity type (n-type) carrier formation layer 30 may be formed by doping the first semiconductor material Si with an n-type impurity, for example, As. [Example]

[0084] An insulated gate semiconductor device 10L of Example 12 will be described with reference to Figure 40. The semiconductor device 10L of this example differs from Example 1 in the configuration of the support substrate. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be denoted by the same reference numerals to avoid redundant description.

[0085] As shown in this embodiment, the support substrate may be a partial SOI (Silicon On Insulator) substrate having an n-type high-concentration substrate connection region 91. That is, as in this embodiment, a structure may be used in which a semiconductor substrate 2 for forming elements is formed on a support substrate having an n-type high-concentration substrate connection region 91 formed thereon, penetrating a part of the SiO2 layer of an SOI substrate composed of a p-type semiconductor layer 90 and an SiO2 layer 92. As shown in Figure 40, in this embodiment, insulation isolation may also be achieved in the lateral direction by a trench insulation isolation SiO2 region 93.

[0086] It is known that the support substrate structure (partial insulating substrate) as shown in this embodiment reduces the electric field at the end of the n-type heavily doped drain region 13, thereby improving the breakdown voltage of the device (Non-Patent Document 2). [Example]

[0087] 41, an insulated gate semiconductor device 10M of Example 13 will be described. The semiconductor device 10M of this example differs from Example 1 in the configuration of the second conductivity type (p-type) carrier formation layer 40. The following mainly describes the differences from Example 1, and the same reference numerals are used to denote components common to Example 1, and redundant description will be omitted.

[0088] As shown in this embodiment, a heterostructure may be incorporated not only in the first conductivity type (n-type) carrier formation layer 30 but also in the second conductivity type (p-type) carrier formation layer 40. That is, as shown in FIG. 41 , a step exists in the valence band upper end Ev of the first semiconductor material Si and the second semiconductor material SiGe, and a heterointerface is formed at the interface between the spacer layer (non-doped Si layer) 41s and the non-doped SiGe layer 42. Because a step exists in the valence band upper end Ev of the spacer layer (non-doped Si layer) 41s and the non-doped SiGe layer 42 that constitute this heterointerface, a p-type doped Si region 41d on the semiconductor material Si side with a lower valence band upper end Ev may be doped with p-type impurities to generate a two-dimensional hole layer 42h in the SiGe region 42 on the semiconductor material side with a higher valence band upper end Ev.

[0089] Regardless of whether the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40 incorporate a heterointerface, a high breakdown voltage can be achieved as in Example 1 as long as the difference between the first conductivity type (n-type) carrier areal density and the second conductivity type (p-type) carrier areal density is small in the total carrier areal density of the entire semiconductor substrate 2 including the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40. In all of the other examples described above, both the first conductivity type (n-type) carrier formation layer 30 and the second conductivity type (p-type) carrier formation layer 40 may incorporate a heterointerface.

[0090] Specific examples of the technology disclosed in this specification have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or in the drawings exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0091] 1... Support substrate (p-type high-resistance semiconductor substrate, n-type high-resistance semiconductor substrate, i-type high-resistance semiconductor substrate, insulating substrate, partial insulating substrate, etc.) 2...Semiconductor substrate (n-type low-concentration drift layer, stacked body) 10 ... p-type high-concentration body region 10a ... p-type second high-concentration body region 10b...Buried p-type high-concentration body region 10x … n-type high-concentration body region 10y … n-type second high-concentration body region 11 ... p-type body region 11x … n-type body region 12...N-type high concentration source region 12x… p-type high concentration source region 13...N-type heavily doped drain region 13a ... n-type second heavily doped drain region 13x ... p-type heavily doped drain region 13y ... p-type second heavily doped drain region 14...Gate insulating film 15...n-type inversion layer 15x ... p-type inversion layer 16...gate electrode 16a ... trench gate electrode 17...Thick insulating film 18...Source electrode 19...Drain electrode 21p...p-type first low concentration Si layer 21n...N-type first low concentration Si layer 21...First low concentration Si layer 22...Second low concentration Si layer 23...Third low concentration Si layer 30...n-type carrier formation layer (n-type drift layer) 30d: n-type doped Si layer 30nd: Non-doped Si layer 31e, 33e ... Heterointerface two-dimensional electron layer (non-doped Si layer) 32...SiGe layer 32s: Spacer layer (non-doped SiGe layer) 32d...n-type doped SiGe layer 32nd: Non-doped SiGe layer 40 ... p-type carrier formation layer (p-type drift layer) 40a...Upper p-type drift layer 40b...lower p-type drift layer 40d: p-type doped Si layer 40nd: Non-doped Si layer 41d...p-type doped Si layer 41s: Spacer layer (non-doped Si layer) 42...SiGe layer 42h: Heterointerface two-dimensional hole layer (non-doped SiGe layer) 42nd: Non-doped SiGe layer 90 ... p-type semiconductor layer 91 ... n-type high concentration substrate connection region 92...SiO2 layer 93 ... Trench isolation SiO2 region 100... Drift region

Claims

1. a second conductivity type body region made of a first semiconductor material, a first conductivity type heavily doped source region, and a first conductivity type heavily doped drain region; a gate electrode in contact with a drift region through which a drift current flows in an on-state and which is depleted in an off-state, and the second conductivity type body region via a gate insulating film; and a first conductivity type inversion layer (two-dimensional carrier layer) generated at an interface between the second conductivity type body region and the gate insulating film in an on-state, In an insulated gate semiconductor device, the second conductivity type body region is electrically connected to the first conductivity type source region, The drift region includes a first low-concentration layer, a second low-concentration layer, and a third low-concentration layer, each of which is made of a first semiconductor material; a first-conductivity-type carrier-forming layer located either between the first low-concentration layer and the second low-concentration layer or between the second low-concentration layer and the third low-concentration layer, and a second-conductivity-type carrier-forming layer located in the other of the two, the first conductive type carrier formation layer has one or more different material layers made of a second semiconductor material different from the first semiconductor material; In the first conductive type carrier formation layer, a first conductive type two-dimensional carrier layer is formed, separated from a doping impurity, by each of one or a plurality of heterointerfaces formed between the first semiconductor material and the second semiconductor material; one end of the first conductivity type carrier formation layer in the drift region is electrically connected to the first conductivity type high concentration drain region, and the other end of the first conductivity type carrier formation layer in the drift region is electrically connected to the first conductivity type high concentration source region via the first conductivity type inversion layer; In addition, the second conductive type carrier formation layer is formed by one or more doping layers made of the first semiconductor material, an insulated gate semiconductor device electrically connected to the second conductivity type body region;

2. 2. The insulated gate semiconductor device according to claim 1, further comprising: a first conductivity type second drain region for electrically connecting the other end of the first conductivity type carrier formation layer in the drift region to the first conductivity type inversion layer; and a second conductivity type high concentration body region and / or a second conductivity type second high concentration body region for electrically connecting the second conductivity type carrier formation layer to the second conductivity type body region.

3. 2. The insulated gate semiconductor device according to claim 1, further comprising: a first low-concentration layer of a first conductivity type for electrically connecting the other end of the first conductivity type carrier formation layer in the drift region to the first conductivity type inversion layer; or a first low-concentration layer for directly connecting the other end of the first conductivity type carrier formation layer to the first conductivity type inversion layer; and a second high-concentration body region of a second conductivity type and / or a second high-concentration body region of a second conductivity type for electrically connecting the second conductivity type carrier formation layer to the second conductivity type body region.

4. 4. The insulated gate semiconductor device according to claim 1, wherein a non-doped spacer layer is provided between the doped impurity layer and the two-dimensional carrier layer in the first conductive type carrier formation layer, and the thickness of the non-doped spacer layer is about 10 nm or less.

5. 5. The insulated gate semiconductor device according to claim 1, wherein a non-doped layer is provided between a plurality of doped impurity layers in said first conductive type carrier formation layer and said second conductive type carrier formation layer.

6. 6. The insulated gate semiconductor device according to claim 1, wherein in the drift region, in a total carrier areal density of the entire semiconductor substrate 2 including the first conductivity type carrier formation layer and the second conductivity type carrier formation layer, the difference in carrier areal density between the first conductivity type and the second conductivity type is small, the difference being approximately 10% or less.

7. 7. The insulated gate semiconductor device according to claim 1, wherein the thickness of each of said different material layers is smaller than the thickness of the first semiconductor material, and is about 3 nm to 50 nm.

8. 8. The insulated gate semiconductor device according to claim 1 , wherein the carrier areal densities of the first low concentration layer, the second low concentration layer, and the third low concentration layer are smaller than the areal densities of the second conductivity type body region, the first conductivity type carrier formation layer, and the second conductivity type carrier formation layer, and are about 10% or less of them.

9. 9. The insulated gate semiconductor device according to claim 1, wherein the stack of the first low-concentration layer, the first-conductivity-type carrier formation layer, the second low-concentration layer, the second-conductivity-type carrier formation layer, and the third low-concentration layer, or the stack of the first low-concentration layer, the second-conductivity-type carrier formation layer, the second low-concentration layer, the first-conductivity-type carrier formation layer, and the third low-concentration layer, is repeatedly stacked in the drift region.

10. 10. The insulated gate semiconductor device according to claim 1, wherein the first low concentration layer, the second low concentration layer, and the third low concentration layer are omitted except for the low concentration layer that forms the first conductivity type inversion layer generated in the on state.

11. The support substrate of the insulated gate semiconductor device is a p-type, n-type or i-type high resistance semiconductor substrate, a semi-insulating substrate or a SiO ２ 11. The insulated gate semiconductor device according to claim 1, wherein the substrate is an insulating substrate such as a silicon nitride film or a partial insulating substrate partially having an insulating film.

12. 12. The insulated gate semiconductor device according to claim 1, wherein the combination of different material layers forming the hetero-interface is two of Si, SiGe, and SiGeC, or two of GaAs, InGaAs, AlGaAs, and InAlGaAs, or a combination of other semiconductors capable of forming a hetero-interface.

13. 13. The insulated gate semiconductor device according to claim 1, wherein only said first conductivity type heavily doped drain region is replaced with a second conductivity type heavily doped drain region.

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