Semiconductor Devices

Abstract

This semiconductor device comprises: a semiconductor layer of a first conductivity type, said semiconductor layer having a main surface; a well region of a second conductivity type, said well region being formed in a surface layer part of the main surface, while defining an active region and an outer region in the main surface, and having a high concentration part, in which the impurity concentration is high, on the active region side and a low concentration part, which has a lower impurity concentration than the high concentration part, on the outer region side; and an impurity region of the second conductivity type, said impurity region being formed in the surface layer part of the main surface in the active region.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including an n-type drift layer having an active region, and a p-type well layer formed in a termination region outside the active region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-158258 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present disclosure provides a semiconductor device capable of suppressing a decrease in breakdown voltage. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present disclosure provides a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface; a well region of a second conductivity type that partitions an active region and an outer region on the main surface and is formed in a surface layer portion of the main surface, the well region including a first concentration portion with a higher impurity concentration on the active region side and a second concentration portion with a lower impurity concentration than the first concentration portion on the outer region side; and an impurity region of the second conductivity type formed in the surface layer portion of the main surface in the active region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is an enlarged view of region III shown in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view showing the vicinity of the well region shown in FIG. [Figure 5] FIG. 5 is a graph showing the concentration gradient in the thickness direction of the well region shown in FIG. [Figure 6] FIG. 6 is a graph showing the concentration gradient in the width direction of the well region shown in FIG. [Figure 7A] 7A is a cross-sectional view of a portion corresponding to FIG. 2, and is a cross-sectional view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 7B] FIG. 7B is a cross-sectional view for explaining a step subsequent to FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view for explaining a step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a cross-sectional view for explaining a step subsequent to FIG. 7C. [Figure 7E] FIG. 7E is a cross-sectional view for explaining a step subsequent to FIG. 7D. [Figure 7F] FIG. 7F is a cross-sectional view for explaining a step subsequent to FIG. 7E. [Figure 7G] FIG. 7G is a cross-sectional view for explaining a step subsequent to FIG. 7F. [Figure 7H] FIG. 7H is a cross-sectional view for explaining a step subsequent to FIG. 7G. [Figure 7I] FIG. 7I is a cross-sectional view for explaining the step after FIG. 7H. [Figure 7J] FIG. 7J is a cross-sectional view for explaining a step subsequent to FIG. 7I. [Figure 8] FIG. 8 is a cross-sectional view corresponding to FIG. 3, showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view corresponding to FIG. 3, showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view of an active region of a semiconductor device according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] FIG. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is an enlarged view of region III shown in FIG. 2. FIG. 4 is an enlarged cross-sectional view showing the vicinity of a well region 7. The semiconductor device 1 is a semiconductor rectifying device including a pn junction diode as an example of a functional device. In this embodiment, the pn junction diode is a fast recovery diode.

[0009] 1 to 4, semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 2. Semiconductor chip 2 is made of a Si (silicon) chip. Semiconductor chip 2 has a first main surface 21 on one side, a second main surface 22 on the other side, and first to fourth side surfaces 23A to 23D connecting first main surface 21 and second main surface 22. First main surface 21 and second main surface 22 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0010] The first main surface 21 is a device surface on which functional devices are formed. The second main surface 22 is a non-device surface. The first side surface 23A and the second side surface 23B extend in a first direction X along the first main surface 21 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 23C and the fourth side surface 23D extend in the second direction Y and face the first direction X.

[0011] The semiconductor chip 2 includes an n-type (first conductivity type) semiconductor layer 3 formed at least in the surface layer portion of the first main surface 21. The n-type impurity concentration of the semiconductor layer 3 is 1.0×10 13 cm -3 Over 1.0 x 10 16 cm -3The semiconductor layer 3 may be as follows: The semiconductor layer 3 is exposed from the first main surface 21. That is, the semiconductor layer 3 has the first main surface 21. In this embodiment, the semiconductor layer 3 is formed over the entire surface portion of the first main surface 21, and is exposed from the first main surface 21 and the first to fourth side surfaces 23A to 23D.

[0012] Specifically, the semiconductor layer 3 is formed across the entire width and thickness of the semiconductor chip 2. That is, the semiconductor chip 2 has a single-layer structure made up of the semiconductor layer 3. The semiconductor layer 3 is formed as a cathode region of a pn junction diode. In the following, the semiconductor layer 3 will be used in place of the semiconductor chip 2 for explanation.

[0013] The semiconductor device 1 includes a p-type (second conductivity type) well region 7 formed in a surface layer portion of the first main surface 21. The well region 7 forms a pn junction with the semiconductor layer 3. The well region 7 is formed at a distance from the periphery of the first main surface 21 (i.e., the first to fourth side surfaces 23A to 23D) inward of the semiconductor layer 3, and is formed in a strip shape extending along the periphery of the first main surface 21 in a plan view.

[0014] Specifically, the well region 7 is formed in a ring shape surrounding the inner part of the semiconductor layer 3 in a plan view. In this embodiment, the well region 7 is formed in a quadrangular ring shape parallel to each side of the first main surface 21 in a plan view. The four corners of the well region 7 are each formed in an arc shape extending from the inner part of the first main surface 21 toward the peripheral edge thereof.

[0015] The well region 7 defines an active region 4 on the inner side of the first main surface 21, and defines an outer region 5 on the peripheral edge side of the first main surface 21. Specifically, the well region 7 defines the active region 4 by its inner edge, and defines the outer region 5 by its outer edge. The active region 4 is defined in a quadrangular shape having four sides parallel to the sides of the first main surface 21 (i.e., the first to fourth side surfaces 23A to 23D) in a plan view. The outer region 5 is defined in a quadrangular ring shape having four sides parallel to the sides of the first main surface 21 (i.e., the first to fourth side surfaces 23A to 23D) in a plan view.

[0016] The well region 7 includes a high-concentration portion 8 and a low-concentration portion 9. The high-concentration portion 8 is formed on the active region 4 side and has a relatively high p-type impurity concentration. The low-concentration portion 9 is formed on the outer region 5 side of the high-concentration portion 8 and has a p-type impurity concentration lower than the p-type impurity concentration of the high-concentration portion 8. The high-concentration portion 8 and the low-concentration portion 9 are referred to as a "high-concentration portion" and a "low-concentration portion," respectively, based on the relationship in the p-type impurity concentration between them. However, for example, the high-concentration portion may be referred to as a "first concentration portion having a first impurity concentration," and the low-concentration portion may be referred to as a "second concentration portion having a second impurity concentration lower than the first impurity concentration."

[0017] The high concentration portion 8 is formed in a ring shape surrounding the inner portion of the semiconductor layer 3 in a plan view. The low concentration portion 9 is formed integrally with the high concentration portion 8 and is formed in a ring shape surrounding the high concentration portion 8 in a plan view. In other words, the well region 7 defines the active region 4 by the high concentration portion 8 and defines the outer region 5 by the low concentration portion 9.

[0018] The p-type impurity concentration of the low concentration portion 9 may be 0.1 to 0.8 times the p-type impurity concentration of the high concentration portion 8. The p-type impurity concentration of the low concentration portion 9 is preferably 0.2 to 0.5 times the p-type impurity concentration of the high concentration portion 8. The p-type impurity concentration of the high concentration portion 8 is preferably 1×10 17 cm -3 More than 1×10 18 cm -3 The p-type impurity concentration of the low concentration portion 9 may be 1×10 16 cm -3 More than 1×10 17 cm -3 It may be the following:

[0019] The bottom 7a of the well region 7 is formed by the bottom 8a of the high-concentration portion 8 and the bottom 9a of the low-concentration portion 9. The bottom 9a of the low-concentration portion 9 is formed on the first main surface 21 side relative to the depth position of the bottom 8a of the high-concentration portion 8. Therefore, the bottom 7a of the well region 7 is recessed from the bottom 8a of the high-concentration portion 8 toward the bottom 9a of the low-concentration portion 9.

[0020] Referring to FIG. 4, the high-concentration portion 8 has a first thickness T1 and a first width W1. The first thickness T1 is the thickness of the high-concentration portion 8 along the thickness direction (normal direction Z) of the semiconductor layer 3. The first width W1 is the width in the direction orthogonal to the direction in which the high-concentration portion 8 extends. The first width W1 may be the largest width among the widths of the high-concentration portion 8 measured in the direction orthogonal to the direction in which the high-concentration portion 8 extends.

[0021] The first thickness T1 may be 1 μm or more and 15 μm or less. The first thickness T1 is preferably 5 μm or more and 12 μm or less. The first width W1 may be 10 μm or more and 30 μm or less. The first width W1 is preferably 25 μm or more and 30 μm or less. The high-concentration portion 8 has a horizontally long structure in which the ratio W1 / T1 of the first width W1 to the first thickness T1 exceeds 1 in a cross-sectional view. The ratio W1 / T1 is preferably more than 1 and 5 or less.

[0022] The low-concentration portion 9 has a second thickness T2 and a second width W2. The second thickness T2 is the thickness of the low-concentration portion 9 along the thickness direction (normal direction Z) of the semiconductor layer 3 with reference to the first main surface 21. The second width W2 is the width in the direction orthogonal to the direction in which the low-concentration portion 9 extends. The second width W2 may be the largest width among the widths of the low-concentration portion 9 measured in the direction orthogonal to the direction in which the low-concentration portion 9 extends.

[0023] The second thickness T2 is preferably less than the first thickness T1 (T2 < T1). The second thickness T2 may be 1 μm or more and 15 μm or less. The second thickness T2 is preferably 4 μm or more and 10 μm or less. The second width W2 may be 10 μm or more and 30 μm or less. The second width W2 is preferably 12 μm or more and 20 μm or less. The second width W2 is preferably less than the first width W1 of the high-concentration portion 8 (W2 < W1). The low-concentration portion 9 preferably has a horizontally long structure in which the ratio W2 / T2 of the second width W2 to the second thickness T2 exceeds 1 in a cross-sectional view. The ratio W2 / T2 is preferably more than 1 and 5 or less.

[0024] The concentration gradient in well region 7 will be described in detail below with reference to Figures 5 and 6. Figure 5 is a graph showing the concentration gradient in the thickness direction of well region 7 shown in Figure 1. In Figure 5, the horizontal axis represents the distance in the thickness direction from first main surface 21 as the zero point, and the vertical axis represents the p-type impurity concentration in well region 7.

[0025] Fig. 5 shows a first curve L1 and a second curve L2. The first curve L1 shows the p-type impurity concentration gradient in the high-concentration portion 8 along the line AA shown in Fig. 3. The second curve L2 shows the p-type impurity concentration gradient in the low-concentration portion 9 along the line BB shown in Fig. 3.

[0026] With reference to the first curve L1, the high-concentration portion 8 has a concentration gradient in which the p-type impurity concentration gradually decreases from the first main surface 21 in the thickness direction of the semiconductor layer 3. With reference to the second curve L2, the low-concentration portion 9 has a concentration gradient in which the p-type impurity concentration gradually decreases from the first main surface 21 in the thickness direction of the semiconductor layer 3. With reference to the first curve L1 and the second curve L2, the p-type impurity concentration of the low-concentration portion 9 is lower than the p-type impurity concentration of the high-concentration portion 8 throughout the entire thickness direction of the low-concentration portion 9 when the same thickness position is used as a reference.

[0027] Furthermore, with reference to the first curve L1, the high-concentration portion 8 has a first minimum value M1. The first minimum value M1 indicates the boundary (p-n junction) between the high-concentration portion 8 and the semiconductor layer 3. With reference to the second curve L2, the low-concentration portion 9 has a second minimum value M2. The second minimum value M2 indicates the boundary (p-n junction) between the low-concentration portion 9 and the semiconductor layer 3. Because the bottom 9a of the low-concentration portion 9 is located closer to the first main surface 21 than the bottom 8a of the high-concentration portion 8, the second minimum value M2 is located to the left of the first minimum value M1 on the graph. In other words, the p-n junction of the low-concentration portion 9 is located in a region closer to the first main surface 21 than the p-n junction of the high-concentration portion 8.

[0028] FIG. 6 is a graph showing the concentration gradient in the width direction of the well region 7 shown in FIG. 1. In FIG. 6, the horizontal axis represents the position along the direction orthogonal to the direction in which the well region 7 extends, and the vertical axis represents the p-type impurity concentration in the surface layer portion of the well region 7. In FIG. 6, a third curve L3 is shown. The third curve L3 shows the p-type impurity concentration gradient in the width direction of the well region 7 at a certain thickness position from the first main surface 21. The third curve L3 also shows the p-type impurity concentration in the impurity region 6 described later.

[0029] Referring to the third curve L3, the well region 7 has a concentration gradient in which the p-type impurity concentration gradually decreases from the high-concentration portion 8 toward the low-concentration portion 9. As can also be understood from the transition from the first curve L1 to the second curve L2 shown in FIG. 5, the well region 7 has a concentration gradient in which the p-type impurity concentration gradually decreases from the entire thickness direction of the high-concentration portion 8 toward the entire thickness direction of the low-concentration portion 9. That is, the p-type impurity concentration in the low-concentration portion 9 is less than the p-type impurity concentration in the high-concentration portion 8 at a thickness position where the distance from the first main surface 21 is the same.

[0030] Referring again to FIGS. 2 and 3, the semiconductor device 1 includes a p-type impurity region 6 formed in the surface layer portion of the first main surface 21 in the active region 4. The impurity region 6 forms a pn junction with the semiconductor layer 3. In the active region 4, a pn junction diode (fast recovery diode) including the semiconductor layer 3 as a cathode region and the impurity region 6 as an anode region is formed. <00,00169> The impurity region 6 has a region thickness T0. The region thickness T0 is the thickness of the impurity region 6 along the thickness direction (normal direction Z) of the semiconductor layer 3. The region thickness T0 is less than the first thickness T1 of the high-concentration portion 8 (T0 < T1). That is, the bottom 6a of the impurity region 6 is formed on the first main surface 21 side with respect to the depth position of the bottom 8a of the high-concentration portion 8. In this form, the region thickness T0 is less than the second thickness T2 of the low-concentration portion 9 (T0 < T2). That is, the bottom 6a of the impurity region 6 is formed on the first main surface 21 side with respect to the depth position of the bottom 9a of the low-concentration portion 9.

[0032] The impurity region 6 is formed in the active region 4 so as to be connected to the high concentration portion 8 of the well region 7, and is fixed at the same potential as the well region 7. The outer edge portion 6b of the impurity region 6 is connected to the high concentration portion 8 over the entire inner edge (entire periphery) of the well region 7. In this embodiment, the impurity region 6 is formed over the entire active region 4. The outer edge portion 6b of the impurity region 6 contains the p-type impurity of the high concentration portion 8. In other words, the p-type impurity concentration of the outer edge portion 6b of the impurity region 6 is increased by the amount of the p-type impurity of the high concentration portion 8.

[0033] The p-type impurity concentration of the impurity region 6 has a concentration gradient in which the p-type impurity concentration gradually decreases from the first main surface 21 toward the thickness direction of the semiconductor layer 3. As can be seen from the third curve L3 in FIG. 6 , the impurity region 6 has a p-type impurity concentration that is lower than the p-type impurity concentration of the well region 7. Specifically, the p-type impurity concentration of the impurity region 6 is lower than the p-type impurity concentration of the high-concentration portion 8 of the well region 7.

[0034] The p-type impurity concentration of the impurity region 6 is preferably lower than the p-type impurity concentration of the high concentration portion 8 throughout the entire thickness direction of the impurity region 6. The p-type impurity concentration of the impurity region 6 is more preferably lower than the p-type impurity concentration of the low concentration portion 9. Specifically, it is particularly preferable that the p-type impurity concentration of the impurity region 6 is lower than the p-type impurity concentration of the low concentration portion 9 at a thickness position that is the same distance from the first main surface 21. The p-type impurity concentration of the impurity region 6 is 5×10 15 cm -3 5x10 or more 16 cm -3 It may be the following:

[0035] 1 to 4, the semiconductor device 1 includes at least one p-type field limit region formed in the outer region 5 in a surface layer portion of the first main surface 21. Hereinafter, the field limit region will be abbreviated as FL (Field Limit) region. FIG. 2 shows an example in which three p-type FL regions 13A, 13B, and 13C are formed at intervals in this order from the well region 7 toward the periphery of the first main surface 21. The number of FL regions is adjusted according to the electric field to be relaxed, and may be 1 to 20 inclusive. The number of FL regions is preferably 4 or more.

[0036] The FL regions 13A to 13C are each formed in an electrically floating state. In plan view, the FL regions 13A to 13C each extend in a strip shape along the well region 7. Specifically, in plan view, the FL regions 13A to 13C each are formed in a ring shape surrounding the well region 7. As a result, the FL regions 13A to 13C are each formed as an FLR (Field Limiting Ring) region.

[0037] The FL regions 13A to 13C have a concentration gradient in which the p-type impurity concentration gradually decreases from the first main surface 21 in the thickness direction. The FL regions 13A to 13C have a p-type impurity concentration that exceeds the p-type impurity concentration of the impurity region 6. The p-type impurity concentration of the FL regions 13A to 13C is higher than the p-type impurity concentration of the low-concentration portion 9 throughout the entire thickness direction of the FL regions 13A to 13C.

[0038] When the centers of the FL regions 13A to 13C and the low-concentration portion 9 are used as references, the p-type impurity concentrations of the FL regions 13A to 13C are, specifically, higher than the p-type impurity concentration of the low-concentration portion 9 at thickness positions at the same distance from the first main surface 21. The impurity concentrations of the FL regions 13A to 13C may be approximately equal to the p-type impurity concentration of the high-concentration portion 8. The p-type impurity concentrations of the FL regions 13A to 13C are 1×10 17 cm -3 More than 1×10 18 cm -3 It may be the following:

[0039] The FL regions 13A to 13C each have a third thickness T3 and a third width W3. The third thickness T3 is the thickness of the FL regions 13A to 13C along the thickness direction (normal direction Z) of the semiconductor layer 3 with respect to the first main surface 21. The third width W3 is the width in a direction orthogonal to the direction in which the FL regions 13A to 13C extend. The third width W3 may be the largest width among the widths of the FL regions 13A to 13C measured in a direction orthogonal to the direction in which the FL regions 13A to 13C extend.

[0040] The third thickness T3 may be 1 μm or more and 15 μm or less. The third thickness T3 is preferably 5 μm or more and 12 μm or less. The third thickness T3 preferably exceeds the region thickness T0 of the impurity region 6 (T0 < T3). The third thickness T3 particularly preferably exceeds the second thickness T2 of the low-concentration portion 9 (T2 < T3). The third thickness T3 is preferably substantially equal to the first thickness T1 of the high-concentration portion 8 (T1 ≒ T3).

[0041] The third thickness T3 of the FL regions 13A to 13C is adjusted according to the electric field to be relaxed. The FL regions 13A to 13C may each have substantially equal third thicknesses T3, or may have different third thicknesses T3. The third thickness T3 of the FL regions 13A to 13C may be formed so as to gradually decrease from the well region 7 side toward the peripheral side of the first main surface 21.

[0042] The third width W3 may be equal to or greater than the first width W1 of the high-concentration portion 8 (W1 ≦ W3). The third width W3 is preferably greater than the first width W1 (W1 < W3). The third width W3 may be equal to or greater than the second width W2 of the low-concentration portion 9 (W2 ≦ W3). The third width W3 is preferably greater than the second width W2 (W2 < W3). The third width W3 is particularly preferably less than the sum value W1 + W2 of the first width W1 and the second width W2 (W3 < W1 + W2). The third width W3 may be 10 μm or more and 50 μm or less. The third width W3 is preferably 25 μm or more and 45 μm or less.

[0043] The third width W3 of the FL regions 13A to 13C is adjusted according to the electric field to be relaxed. The FL regions 13A to 13C may have substantially the same third width W3, or may have different third widths W3. The third width W3 of the FL regions 13A to 13C may be formed to gradually decrease from the well region 7 side toward the periphery of the first main surface 21. The FL regions 13A to 13C may be formed so that the order of the third width W3 of the FL region 13A > the third width W3 of the FL region 13B > the third width W3 of the FL region 13C is satisfied. In this case, the total value of the third widths W3 of the FL regions 13A to 13C can be reduced, thereby enabling the semiconductor chip 2 to be reduced in size.

[0044] Each of the FL regions 13A to 13C preferably has a laterally elongated structure in which the ratio W3 / T3 of the third width W3 to the third thickness T3 in a cross-sectional view exceeds 1. The ratio W3 / T3 is preferably greater than 1 and 5 or less.

[0045] The semiconductor device 1 includes an n-type channel stop region 37 formed in the outer region 5 in a surface layer portion of the peripheral portion of the first main surface 21. The channel stop region 37 has an n-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor layer 3, and is formed in an electrically floating state. The channel stop region 37 is formed at an interval from the outermost FL region 13C toward the peripheral edge of the first main surface 21 (i.e., toward the first to fourth side faces 23A to 23D).

[0046] The channel stop region 37 is formed in a band shape extending along the periphery of the first main surface 21 in a plan view. In this embodiment, the channel stop region 37 is formed in a ring shape extending along the periphery of the first main surface 21 in a plan view and surrounding the multiple FL regions 13A to 13C. The channel stop region 37 is preferably exposed from the first to fourth side surfaces 23A to 23D.

[0047] 2, the semiconductor device 1 includes a main surface insulating film 12 that selectively covers the first main surface 21. The main surface insulating film 12 may include an oxide film (SiO2 film) or a nitride film (SiN film). The oxide film may include a LOCOS (Local Oxidation Of Silicon) film. The thickness of the main surface insulating film 12 may be 0.5 μm or more and 5 μm or less. The thickness of the main surface insulating film 12 is preferably 1 μm or more and 3 μm or less.

[0048] The main surface insulating film 12 includes a thick film portion 12a having a first insulating thickness and a thin film portion 12b having a second insulating thickness less than the first insulating thickness. The thick film portion 12a covers the region between the well region 7 and the innermost FL region 13A, the regions between adjacent FL regions 13A to 13C, and the region between the outermost FL region 13C and the channel stop region 37.

[0049] The thick film portion 12a extends in a band shape (specifically, a ring shape) in a plan view in the region between the well region 7 and the innermost FL region 13A. The thick film portion 12a covers the outer edge of the well region 7 and the inner edge of the innermost FL region 13A. The thick film portion 12a covers the low concentration portion 9 of the well region 7 so as to expose the high concentration portion 8 of the well region 7. Specifically, the thick film portion 12a covers the outer edge of the low concentration portion 9 so as to expose the entire high concentration portion 8 and part of the low concentration portion 9.

[0050] The thick film portion 12a extends in a strip shape (specifically, an annular shape) in the region between the adjacent FL regions 13A to 13C in plan view. The thick film portion 12a covers the outer and inner edges of the adjacent FL regions 13A to 13C. The thick film portion 12a extends in a strip shape (specifically, annular shape) in the region between the adjacent outermost FL region 13C and channel stop region 37 in plan view. The thick film portion 12a covers the outer edge of the outermost FL region 13C and the inner edge of the channel stop region 37.

[0051] The thin film portion 12b selectively covers the first main surface 21 of the outer region 5. Specifically, the thin film portion 12b covers the well region 7, the FL regions 13A to 13C, and the channel stop region 37. The thin film portion 12b is formed integrally with the thick film portion 12a in the peripheral portion of the well region 7 (the peripheral portion of the low concentration portion 9), the peripheral portions of the FL regions 13A to 13C, and the peripheral portion of the channel stop region 37.

[0052] The thin film portion 12b covers the peripheral edge of the well region 7 and extends in a band shape (specifically, a ring shape) along the peripheral edge of the well region 7 in a plan view. Specifically, the thin film portion 12b covers the low concentration portion 9 so as to expose the high concentration portion 8 of the well region 7. More specifically, the thin film portion 12b partially covers the low concentration portion 9 so as to expose the entire high concentration portion 8 and a part of the low concentration portion 9. The thin film portion 12b is formed in a band shape (specifically, a ring shape) extending along the low concentration portion 9 in a plan view. The thin film portion 12b is formed integrally with the thick film portion 12a on the low concentration portion 9.

[0053] The main surface insulating film 12 has a first opening 12e that exposes the impurity region 6. The first opening 12e is defined by a thin film portion 12b. A wall portion 12c of the first opening 12e is located above the well region 7. This allows the first opening 12e to expose the impurity region 6 and a portion of the well region 7. The wall portion 12c may have an acute inclination angle with respect to the main surface insulating film 12. Specifically, the inclination angle of the wall portion 12c is the angle between the wall portion 12c and the first main surface 21 within the main surface insulating film 12. The inclination angle may be 25° or more and 65° or less. The inclination angle is preferably 30° or more and 55° or less.

[0054] The wall 12c of the first opening 12e is formed at an interval from the high-concentration portion 8 of the well region 7 toward the low-concentration portion 9, and is located above the low-concentration portion 9 of the well region 7. The wall 12c of the first opening 12e is preferably located closer to the periphery of the low-concentration portion 9 than to the center of the low-concentration portion 9. The wall 12c of the first opening 12e extends along the low-concentration portion 9 in a plan view. That is, the first opening 12e is formed in a quadrangular shape in a plan view.

[0055] The first opening 12e exposes the entire impurity region 6, the entire high-concentration portion 8, and a part of the low-concentration portion 9. The plane area of ​​the portion of the low-concentration portion 9 that is exposed from the main surface insulating film 12 preferably exceeds the plane area of ​​the portion of the low-concentration portion 9 that is covered by the main surface insulating film 12. The plane area of ​​the portion of the low-concentration portion 9 that is covered by the thin film portion 12b preferably exceeds the plane area of ​​the portion of the low-concentration portion 9 that is covered by the thick film portion 12a.

[0056] The main surface insulating film 12 has a plurality of second openings 39a that expose the plurality of FL regions 13A to 13C, respectively. The plurality of second openings 39a are formed in the thin film portion 12b, respectively, and expose the plurality of FL regions 13A to 13C in a one-to-one correspondence. Each of the second openings 39a is formed in a strip shape extending along each of the FL regions 13A to 13C. Preferably, each of the second openings 39a is formed in a ring shape extending along each of the FL regions 13A to 13C.

[0057] Wall portions 39b of each second opening 39a are located above one of the FL regions 13A to 13C. As a result, each second opening 39a exposes the inner portion of one of the FL regions 13A to 13C. It is preferable that the planar area of ​​the portion of each of the FL regions 13A to 13C covered by the main-surface insulating film 12 exceeds the planar area of ​​the portion of each of the FL regions 13A to 13C exposed from the main-surface insulating film 12.

[0058] The main surface insulating film 12 has a third opening 12d that exposes the channel stop region 37. The third opening 12d is formed in the thin film portion 12b. The third opening 12d is formed in a strip shape that extends along the channel stop region 37 in plan view. The third opening 12d is preferably formed in a ring shape that extends along the channel stop region 37 in plan view.

[0059] In this embodiment, the third opening 12d is formed as a notched opening that communicates with the first to fourth side surfaces 23A to 23D. It is preferable that the plane area of ​​the portion of the channel stop region 37 that is covered by the thin film portion 12b exceeds the plane area of ​​the portion of the channel stop region 37 that is covered by the thick film portion 12a.

[0060] The semiconductor device 1 includes a first principal surface electrode 36 connected to the impurity region 6 on the first principal surface 21. In this embodiment, the first principal surface electrode 36 is an anode electrode. The first principal surface electrode 36 covers the entire impurity region 6. The first principal surface electrode 36 is drawn from above the impurity region 6 to above the well region 7, and is connected to the impurity region 6 and the well region 7. Specifically, the first principal surface electrode 36 is connected to the high concentration portion 8 of the well region 7. More specifically, the first principal surface electrode 36 is connected to the entire high concentration portion 8 and part of the low concentration portion 9 of the well region 7.

[0061] The first principal surface electrode 36 has an extension portion 36a that is extended from above the well region 7 onto the principal surface insulating film 12. The extension portion 36a faces the low concentration portion 9 of the well region 7 across the thin film portion 12b of the principal surface insulating film 12. The extension portion 36a also faces the low concentration portion 9 of the well region 7 across the thick film portion 12a of the principal surface insulating film 12.

[0062] The connection area of ​​the portion of the first principal surface electrode 36 connected to the well region 7 preferably exceeds the facing area of ​​the portion of the first principal surface electrode 36 facing the well region 7 across the principal surface insulating film 12. In addition, the facing area of ​​the portion of the lead-out portion 36a facing the low-concentration portion 9 across the thin film portion 12b preferably exceeds the facing area of ​​the portion of the lead-out portion 36a facing the low-concentration portion 9 across the thick film portion 12a.

[0063] The semiconductor device 1 includes a plurality of field electrodes 41 on the first main surface 21, each connected to a corresponding one of the FL regions 13A to 13C. Each field electrode 41 is formed in an electrically floating state. The plurality of field electrodes 41 extend from above the main surface insulating film 12 into the plurality of second openings 39a, and are connected to the plurality of FL regions 13A to 13C in a one-to-one correspondence within the plurality of second openings 39a. Each field electrode 41 is formed in a strip shape extending along each of the FL regions 13A to 13C in a plan view. Preferably, each field electrode 41 is formed in a ring shape extending along each of the FL regions 13A to 13C in a plan view.

[0064] The semiconductor device 1 includes an equipotential electrode 42 connected to the channel stop region 37 on the first main surface 21. The equipotential electrode 42 extends from above the main surface insulating film 12 into the third opening 12d and is connected to the channel stop region 37 within the third opening 12d. The equipotential electrode 42 is formed in a strip shape extending along the channel stop region 37 in a plan view. The equipotential electrode 42 is preferably formed in a ring shape extending along the channel stop region 37 in a plan view. The equipotential electrode 42 is preferably formed at intervals from the first to fourth side surfaces 23A to 23D toward the inner portion of the semiconductor layer 3 so as to expose a portion of the channel stop region 37.

[0065] The semiconductor device 1 includes an organic insulating film 35 that covers the main surface insulating film 12. The organic insulating film 35 covers the first main surface electrode 36, the plurality of field electrodes 41, and the equipotential electrode 42 on the main surface insulating film 12. The organic insulating film 35 has a smaller elastic modulus than the inorganic insulating film (e.g., the main surface insulating film 12) and functions as a buffer material (protective film) against external forces. The organic insulating film 35 includes a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating film 35 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating film 35 includes polyimide.

[0066] The organic insulating film 35 covers the extended portion 36a of the first principal surface electrode 36 on the active region 4 side. In other words, the organic insulating film 35 faces the high-concentration portion 8 and the low-concentration portion 9 of the well region 7 across the extended portion 36a of the first principal surface electrode 36. The organic insulating film 35 has a pad opening 35a that exposes an inner portion of the first principal surface electrode 36 as a pad portion. The pad opening 35a may be formed in a quadrangle shape having four sides parallel to the sides of the first principal surface electrode 36 in a plan view. It is preferable that the wall surface of the pad opening 35a be formed at a distance from the inner edge of the well region 7 toward the inside of the first principal surface electrode 36 in a cross-sectional view.

[0067] The peripheral portion of the organic insulating film 35 is formed at a distance inward from the first to fourth side faces 23A to 23D on the outer region 5 side, and exposes a part of the channel stop region 37. The peripheral portion of the organic insulating film 35 preferably covers the entire equipotential electrode 42 and a part of the channel stop region 37 (first main surface 21 of the semiconductor layer 3).

[0068] The semiconductor device 1 includes a second principal surface electrode 33 covering the second principal surface 22. In this embodiment, the second principal surface electrode 33 is a cathode electrode. The second principal surface electrode 33 forms ohmic contact with the second principal surface 22 (semiconductor layer 3).

[0069] As described above, the semiconductor device 1 includes an n-type semiconductor layer 3, a p-type well region 7, and a p-type impurity region 6. The semiconductor layer 3 has a first main surface 21. The well region 7 is formed in a surface layer portion of the first main surface 21, and defines an active region 4 and an outer region 5 on the first main surface 21. The well region 7 includes a high-concentration portion 8 having a relatively high p-type impurity concentration on the active region 4 side, and a low-concentration portion 9 on the outer region 5 side having a p-type impurity concentration lower than the p-type impurity concentration of the high-concentration portion 8. The impurity region 6 is formed in the surface layer portion of the first main surface 21 in the active region 4.

[0070] During recovery operation of a pn junction diode, a recovery current (reverse current) flows from the cathode side to the anode side. Recovery operation refers to the operation of a pn junction diode from the ON state to the OFF state until it returns to a steady state. The well region 7 expands the depletion layer within the semiconductor layer 3 during recovery operation. Specifically, the well region 7 expands the depletion layer toward the active region 4 and outer region 5 as the recovery operation approaches the steady state.

[0071] Meanwhile, the impurity region 6 also expands the depletion layer in the semiconductor layer 3 during recovery operation. Specifically, as the recovery operation approaches a steady state, the impurity region 6 expands the depletion layer toward the active region 4 and the outer region 5. The depletion layer expanding from the impurity region 6 is integrated with the depletion layer expanding from the well region 7, and expands from the active region 4 side toward the outer region 5 side.

[0072] This reduces the current density in the surface layer portion of first main surface 21, and alleviates electric field concentration in the surface layer portion of first main surface 21. In well region 7, high concentration portion 8 and low concentration portion 9 are connected, so that a concentration gradient is formed between high concentration portion 8 and low concentration portion 9, in which the p-type impurity concentration gradually decreases from high concentration portion 8 toward low concentration portion 9. This concentration gradient alleviates the electric field compared to well region 7 having a constant p-type impurity concentration, and suppresses current concentration.

[0073] Furthermore, because the p-type impurity concentration of the low-concentration portion 9 is lower than the p-type impurity concentration of the high-concentration portion 8, the resistance value of the low-concentration portion 9 is higher than the resistance value of the high-concentration portion 8. Therefore, although the recovery current flows through both the high-concentration portion 8 and the low-concentration portion 9, the current density in the low-concentration portion 9, which has a relatively high resistance value, is reduced compared to when the well region 7 is formed with a constant p-type impurity concentration. From this perspective as well, current concentration is suppressed.

[0074] In this way, the semiconductor device 1 can suppress electric field concentration in the well region 7 and suppress a decrease in breakdown voltage originating from the well region 7. The semiconductor device 1 can particularly suppress electric field concentration in the low-concentration portion 9 that forms the outer edge of the well region 7. Specifically, the "breakdown voltage" referred to here means "RRSOA (Reverse Recovery Safe Operation Area) tolerance." RRSOA stands for reverse recovery safe operation area, and RRSOA tolerance means the non-destructive operation range when a recovery current is passed through. The higher the RRSOA tolerance, the wider the non-destructive operation range when a recovery current is passed through, and the better the device can be said to be.

[0075] The low-concentration portion 9 preferably has a concentration gradient in which the p-type impurity concentration gradually decreases from the first main surface 21 toward the thickness direction. The high-concentration portion 8 preferably has a concentration gradient in which the impurity concentration gradually decreases from the first main surface 21 toward the thickness direction. The low-concentration portion 9 preferably has a thickness less than that of the high-concentration portion 8. In other words, the bottom 7a of the well region 7 preferably recesses from the bottom 8a of the high-concentration portion 8 toward the bottom 9a of the low-concentration portion 9.

[0076] The p-type impurity concentration of the impurity region 6 is preferably lower than the p-type impurity concentration of the high concentration portion 8. The impurity region 6 is preferably connected to the high concentration portion 8. In this case, the p-type impurity concentration of the portion of the impurity region 6 connected to the high concentration portion 8 may be increased by the p-type impurity of the high concentration portion 8 from the p-type impurity concentration of the inner portion of the impurity region 6 by the amount of the p-type impurity of the high concentration portion 8.

[0077] The well region 7 is preferably formed in a ring shape surrounding the inner portion of the semiconductor layer 3 in a plan view, so as to define the active region 4 in the inner portion of the semiconductor layer 3 and define the outer region 5 in the peripheral portion of the semiconductor layer 3. With this structure, the well region 7 can alleviate electric field concentration all around the active region 4. In this case, it is preferable that the high concentration portion 8 is formed in a ring shape surrounding the inner portion of the semiconductor layer 3 in a plan view, and the low concentration portion 9 is formed in a ring shape surrounding the high concentration portion 8 in a plan view.

[0078] The semiconductor device 1 preferably further includes a first main surface electrode 36 connected to the impurity region 6 on the first main surface 21. In this case, the first main surface electrode 36 is preferably connected to the high concentration portion 8. With this structure, recovery current can be discharged to the first main surface electrode 36 not only from the impurity region 6 but also from the high concentration portion 8. This makes it possible to alleviate current concentration (i.e., electric field concentration) in the well region 7.

[0079] In this structure, the first principal surface electrode 36 is preferably connected to the low concentration region 9. With this structure, a recovery current can be discharged to the first principal surface electrode 36 via the impurity region 6, the high concentration region 8, and the low concentration region 9. This makes it possible to alleviate current concentration (i.e., electric field concentration) in the well region 7. This structure is particularly effective in suppressing current concentration (i.e., electric field concentration) in the low concentration region 9.

[0080] The high-concentration portion 8 preferably has a first thickness T1 and a first width W1, and has a horizontally elongated structure in which the ratio W1 / T1 of the first width W1 to the first thickness T1 exceeds 1 in a cross-sectional view. The low-concentration portion 9 preferably has a second thickness T2 and a second width W2, and has a horizontally elongated structure in which the ratio W2 / T2 of the second width W2 to the second thickness T2 exceeds 1 in a cross-sectional view.

[0081] Preferably, the semiconductor device 1 further includes p-type FL regions 13A-13D formed in the surface layer portion of the first main surface 21 at a distance from the well region 7 in the outer region 5. According to this structure, the FL regions 13A-13D expand the depletion layer in the semiconductor layer 3 during recovery operation. Specifically, the FL regions 13A-13D expand the depletion layer toward the active region 4 and the outer region 5 as the recovery operation approaches a steady state.

[0082] The depletion layer extending from the FL regions 13A to 13D is integrated with the depletion layer extending from the well region 7, and causes the depletion layer extending from the well region 7 to extend from the active region 4 toward the outer region 5. This further reduces the current density in the surface portion of the first main surface 21. The FL regions 13A to 13D (specifically, the innermost FL region 13A) further expand the depletion layer extending from the low-concentration portions 9 toward the outer region 5, thereby appropriately reducing current concentration (i.e., electric field concentration) in the low-concentration portions 9.

[0083] The FL regions 13A to 13D preferably have a p-type impurity concentration that exceeds the p-type impurity concentration of the impurity region 6. The FL regions 13A to 13D preferably have a p-type impurity concentration that exceeds the p-type impurity concentration of the low-concentration portion 9. The p-type impurity concentration of the FL regions 13A to 13D is preferably higher than the p-type impurity concentration of the low-concentration portion 9 throughout the entire thickness of the FL regions 13A to 13D. The FL regions 13A to 13D preferably have a thickness that exceeds the thickness of the impurity region 6. The FL regions 13A to 13D preferably have a thickness that exceeds the thickness of the low-concentration portion 9.

[0084] 7A to 7J are cross-sectional views of a portion corresponding to FIG. 2, and are cross-sectional views for explaining an example of a method for manufacturing the semiconductor device 1 shown in FIG.

[0085] Referring to FIG. 7A, a semiconductor wafer 24 is prepared. The semiconductor wafer 24 is made of a Si wafer. The semiconductor wafer 24 has a first wafer main surface 25 on one side and a second wafer main surface 26 on the other side. The semiconductor wafer 24 is a base member for the semiconductor chip 2, and has an n-type semiconductor layer 3 throughout its entire interior. The first wafer main surface 25 and the second wafer main surface 26 of the semiconductor wafer 24 correspond to the first main surface 21 and the second main surface 22 of the semiconductor chip 2 (semiconductor layer 3), respectively.

[0086] Next, a plurality of device regions 27 and cutting lines 28 that partition the plurality of device regions 27 are set on the semiconductor wafer 24. The plurality of device regions 27 are regions in which semiconductor devices 1 are respectively formed, and may be arranged in a matrix in the first direction X and the second direction Y in a plan view. The cutting lines 28 may be set in a lattice pattern corresponding to the arrangement of the plurality of device regions 27 in a plan view. In FIGS. 7A to 7J, a portion of one device region 27 (a portion on the outer region 5 side) is shown, and other regions are not shown.

[0087] Next, a first base insulating film 11a, which will be the base of the thick film portion 12a of the main surface insulating film 12, is formed on the first wafer main surface 25. The first base insulating film 11a may be formed by a CVD (Chemical Vapor Deposition) method and / or a thermal oxidation treatment method. In this embodiment, the first base insulating film 11a is made of a thermal oxide film formed by a thermal oxidation treatment method. Next, unnecessary portions of the first base insulating film 11a are removed by an etching method using a resist mask (not shown) having a predetermined pattern. As a result, the thick film portion 12a of the main surface insulating film 12 is formed on the first wafer main surface 25.

[0088] Next, referring to FIG. 7B, a second base insulating film 11b, which serves as a base for the thin film portion 12b of the main surface insulating film 12, is formed on the first wafer main surface 25. The second base insulating film 11b has a thickness less than that of the first base insulating film 11a (thick film portion 12a). The second base insulating film 11b may be formed by a CVD method and / or a thermal oxidation process. In this embodiment, the second base insulating film 11b is made of a thermal oxide film formed by a thermal oxidation process. This forms the main surface insulating film 12 having the thick film portion 12a and the thin film portion 12b.

[0089] 7C, regions where the active region 4 and outer region 5 are to be formed are set on the first wafer main surface 25, and well regions 7 are formed in the surface layer portion of the first wafer main surface 25 so as to partition the active region 4 and outer region 5. In this step, FL regions 13A to 13C are formed in the surface layer portion of the first wafer main surface 25 simultaneously with the well region 7. In this step, a resist mask 15 having a predetermined pattern is first formed on the main surface insulating film 12. The resist mask 15 has a first opening 15a that exposes a region on the first wafer main surface 25 where the high concentration portion 8 of the well region 7 is to be formed. The first opening 15a exposes the entire region where the high concentration portion 8 is to be formed.

[0090] The resist mask 15 further has a plurality of second openings 15b that expose regions in the first wafer main surface 25 where the low concentration portions 9 of the well region 7 are to be formed. That is, the resist mask 15 partially exposes the regions in which the low concentration portions 9 are to be formed by the plurality of second openings 15b, and at the same time partially covers the regions in which the low concentration portions 9 are to be formed outside the plurality of second openings 15b.

[0091] Each of the second openings 15b has an opening area that is less than the opening area of ​​the first opening 15a for the high-concentration region 8. The total opening area of ​​the second openings 15b for the low-concentration region 9 is preferably less than the opening area of ​​the first opening 15a for the high-concentration region 8. The second openings 15b may be formed in a ring shape so as to partially expose the region where the low-concentration region 9 is to be formed, or may be formed in a dot pattern (for example, a matrix or a staggered pattern). The second openings 15b do not necessarily have to have the same opening width. The second openings 15b may be formed, for example, so that the opening width gradually narrows from the active region 4 side toward the outer region 5 side.

[0092] The resist mask 15 also has a plurality of third openings 15c that expose regions where the plurality of FL regions 13A to 13C are to be formed on the first wafer main surface 25. The plurality of third openings 15c each expose the entire region where the plurality of FL regions 13A to 13C are to be formed. That is, the plurality of third openings 15c are formed in the same manner as the first openings 15a for the high-concentration portions 8.

[0093] Next, referring to FIG. 7D , p-type impurities (e.g., boron) are introduced into the surface layer portion of the first wafer main surface 25 through the resist mask 15. Specifically, the p-type impurities are introduced into the surface layer portion of the first wafer main surface 25 through the thin film portions 12b of the main surface insulating film 12 exposed from the first opening 15a, the plurality of second openings 15b, and the plurality of third openings 15c. The thin film portions 12b of the main surface insulating film 12 protect the first wafer main surface 25 from damage caused by the introduction of the p-type impurities. As a result, a well region 7 including a high-concentration portion 8 and a low-concentration portion 9, and a plurality of FL regions 13A to 13C are formed in the surface layer portion of the first wafer main surface 25. The well region 7 defines an active region 4 and an outer region 5 in each device region 27.

[0094] In this step, the introduction of p-type impurities is partially blocked by the resist mask 15 in regions where the low-concentration portions 9 are to be formed. Therefore, the amount of p-type impurities introduced into the surface layer portion of the first wafer main surface 25 through the multiple second openings 15b is less than the amount of p-type impurities introduced into the surface layer portion of the first wafer main surface 25 through the first openings 15a. Furthermore, the amount of p-type impurities introduced into the low-concentration portions 9 is less than the amount of p-type impurities introduced into the high-concentration portions 8, so the thickness of the low-concentration portions 9 is less than the thickness of the high-concentration portions 8. As a result, the high-concentration portions 8 and the low-concentration portions 9, each having a different p-type impurity concentration, are simultaneously formed in a single p-type impurity introduction step using one resist mask 15.

[0095] On the other hand, p-type impurities are introduced into the FL regions 13A-13C through third openings 15c similar to first openings 15a. Therefore, the p-type impurity concentration and thickness of the FL regions 13A-13C are approximately equal to those of the high-concentration portion 8. The resist mask 15 is removed after the well region 7 and the FL regions 13A-13C are formed.

[0096] In this step, an example has been described in which the FL regions 13A to 13C are formed simultaneously with the well region 7. However, the step of forming the FL regions 13A to 13C can be performed at any timing and does not necessarily have to be performed at this timing. The step of forming the FL regions 13A to 13C may be performed before the step of forming the well region 7, or may be performed after the step of forming the well region 7.

[0097] Next, a channel stop region 37 is formed outside the FL regions 13A to 13C in the surface layer portion of the first wafer main surface 25. The channel stop region 37 is formed along the cutting lines 28. The channel stop region 37 is formed by introducing n-type impurities into the surface layer portion of the first wafer main surface 25 through a resist mask (not shown). Thereafter, the resist mask (not shown) for the channel stop region 37 is removed. The process of forming the channel stop region 37 can be performed at any timing and does not necessarily have to be performed at this timing. The process of forming the channel stop region 37 may be performed prior to the process of forming the well region 7.

[0098] 7E, a resist mask 17 having a predetermined pattern is formed on main surface insulating film 12. Resist mask 17 has openings 17a that expose regions of first wafer main surface 25 where impurity regions 6 are to be formed.

[0099] Next, referring to FIG. 7F, p-type impurities are introduced into the surface layer portion of the first wafer main surface 25 via the resist mask 17. This forms the impurity regions 6. The resist mask 17 is then removed. The step of forming the impurity regions 6 can be performed at any timing and does not necessarily have to be performed at this timing. The step of forming the impurity regions 6 may be performed prior to the step of forming the channel stop regions 37, or prior to the step of forming the well regions 7.

[0100] 7G, a resist mask 18 having a predetermined pattern is formed on the main surface insulating film 12. The resist mask 18 has a plurality of openings 18a that expose regions of the main surface insulating film 12 where the first opening 12e, the plurality of second openings 39a, and the third openings 12d are to be formed. In this embodiment, the plurality of openings 18a each exposes a thin film portion 12b of the main surface insulating film 12.

[0101] 7H, unnecessary portions of the main surface insulating film 12 are removed by etching using the resist mask 18. The etching may be wet etching and / or dry etching. As a result, a first opening 12e, a plurality of second openings 39a, and a third opening 12d are formed in the main surface insulating film 12. The resist mask 18 is then removed.

[0102] Next, referring to FIG. 7I, a base electrode layer 29 serving as a base for the first principal surface electrode 36, the plurality of field electrodes 41, and the equipotential electrode 42 is formed on the first wafer principal surface 25. The base electrode layer 29 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the first wafer principal surface 25 side. The Ti-based metal film may include at least one of a Ti film and a TiN film. The Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The base electrode layer 29 (Ti-based metal film and Al-based metal film) may be formed by sputtering and / or vapor deposition.

[0103] 7J, a resist mask 30 having a predetermined pattern is formed on the base electrode layer 29. The resist mask 30 covers regions of the base electrode layer 29 where the first principal surface electrode 36, the plurality of field electrodes 41, and the equipotential electrode 42 are to be formed, and leaves the other regions exposed.

[0104] Next, unnecessary portions of the base electrode layer 29 are removed by etching through the resist mask 30. The etching may be wet etching and / or dry etching. This forms the first principal surface electrode 36, the plurality of field electrodes 41, and the equipotential electrode 42. The resist mask 30 is then removed.

[0105] Next, an organic insulating film 35 is applied onto the first wafer main surface 25 so as to cover the first main surface electrode 36, the plurality of field electrodes 41, and the equipotential electrode 42. Next, the organic insulating film 35 is selectively exposed and developed. As a result, pad openings 35a are formed in the organic insulating film 35, exposing the positions of the first main surface electrodes 36. Next, a second main surface electrode 33 is formed on the second wafer main surface 26. The second main surface electrode 33 may include a Ti film. The second main surface electrode 33 may be formed by sputtering and / or vapor deposition.

[0106] Thereafter, the semiconductor wafer 24 is cut along the cutting lines 28. As a result, a plurality of device regions 27 are cut out as the semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0107] 8 is a cross-sectional view showing a semiconductor device 51 according to a second embodiment of the present disclosure, corresponding to FIG. 3. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0108] In the semiconductor device 1, the first opening 12e is defined by the thin film portion 12b of the main surface insulating film 12. In contrast, in the semiconductor device 51, the first opening 12e is defined by the thick film portion 12a of the main surface insulating film 12. The wall portion 12c of the first opening 12e is located above the well region 7. This allows the first opening 12e to expose the impurity region 6 and a portion of the well region 7. The wall portion 12c of the first opening 12e is located above the low concentration portion 9 of the well region 7 and is formed in a quadrangular shape extending along the low concentration portion 9 in a plan view.

[0109] That is, the first opening 12e exposes the entire impurity region 6, the entire high-concentration portion 8, and part of the low-concentration portion 9. The plane area of ​​the portion of the low-concentration portion 9 that is exposed from the main surface insulating film 12 preferably exceeds the plane area of ​​the portion of the low-concentration portion 9 that is covered by the main surface insulating film 12. In this embodiment, the drawn-out portion 36a of the first main surface electrode 36 faces the low-concentration portion 9 of the well region 7 with the thick film portion 12a of the main surface insulating film 12 interposed therebetween.

[0110] Although not shown, the multiple second openings 39a for the FL regions 13A to 13C may be formed in the thick film portion 12a of the main surface insulating film 12, similar to the first openings 12e. Also, the third opening 12d for the channel stop region 37 may be formed in the thick film portion 12a of the main surface insulating film 12, similar to the first openings 12e. In other words, the main surface insulating film 12 of the semiconductor device 51 may not have the thin film portion 12b and may consist only of the thick film portion 12a. Such a main surface insulating film 12 is formed by removing all of the thin film portion 12b in the step of FIG. 7H.

[0111] As described above, the semiconductor device 51 can also achieve the same effects as those described for the semiconductor device 1.

[0112] 9 is a cross-sectional view showing a semiconductor device 61 according to a third embodiment of the present disclosure, corresponding to FIG. 3. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0113] In the semiconductor device 1, the wall portion 12c of the first opening 12e is formed on the low-concentration portion 9. In contrast, referring to FIG. 9 , in the semiconductor device 61, the wall portion 12c of the first opening 12e is formed on the high-concentration portion 8. That is, the main surface insulating film 12 covers the entire low-concentration portion 9, and exposes the entire impurity region 6 and a part of the high-concentration portion 8. In this embodiment, the first opening 12e is formed in the thin film portion 12b of the main surface insulating film 12.

[0114] The first principal surface electrode 36 is extended from above the impurity region 6 onto the high concentration portion 8 of the well region 7, and is connected to the impurity region 6 and the high concentration portion 8. The extended portion 36a of the first principal surface electrode 36 is extended from above the high concentration portion 8 onto the principal surface insulating film 12. In this form, the extended portion 36a faces a part of the high concentration portion 8 and the entire area of ​​the low concentration portion 9, with the principal surface insulating film 12 in between. The semiconductor device 61 is manufactured by changing the layout of a resist mask in the manufacturing method of the semiconductor device 1.

[0115] As described above, according to the semiconductor device 61, since the low concentration portions 9 are not connected to the first main surface electrode 36, the recovery current discharge effect by both the high concentration portions 8 and the low concentration portions 9 cannot be obtained, but other than that, the same effects as those described for the semiconductor device 1 can be achieved. In the semiconductor device 61, an example has been described in which the first opening 12e is formed in the thin film portion 12b of the main surface insulating film 12. However, the first opening 12e may be formed in the thick film portion 12a of the main surface insulating film 12, as in the semiconductor device 51 according to the second embodiment.

[0116] 10 is an enlarged cross-sectional view showing an active region 4 of a semiconductor device 71 according to a fourth embodiment of the present disclosure. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be assigned the same reference numerals and descriptions thereof will be omitted.

[0117] In the above-described embodiments, an example was described in which a pn junction diode was formed as an example of a functional device in the active region 4. However, the functional device formed in the active region 4 is arbitrary and is not limited to a pn junction diode. The semiconductor device 71 is formed of a semiconductor switching device including an IGBT (Insulated Gate Bipolar Transistor) in place of the pn junction diode in the active region 4.

[0118] Referring to FIG. 10, the semiconductor device 71 includes the aforementioned semiconductor layer 3 formed on the semiconductor chip 2. The semiconductor layer 3 is formed in the same manner as in the first embodiment. In this embodiment, the semiconductor layer 3 is formed as a drift layer of the IGBT. The semiconductor device 71 also includes the aforementioned impurity region 6 formed in a surface layer portion of the first main surface 21 in the active region 4. The impurity region 6 is formed in the same manner as in the first embodiment. In this embodiment, the impurity region 6 is formed as a base region of the IGBT.

[0119] The semiconductor device 71 includes a p-type collector region 32 formed in a surface layer portion of the second main surface 22 of the semiconductor layer 3. The collector region 32 forms the collector of the IGBT. The collector region 32 is formed over the entire surface layer portion of the second main surface 22 and is exposed from the second main surface 22.

[0120] The semiconductor device 71 includes a plurality of trench gate structures 43 formed on the first main surface 21 in the active region 4. The plurality of trench gate structures 43 form gates of the IGBT. The plurality of trench gate structures 43 may extend in the first direction X in a plan view and be formed at intervals in the second direction Y. In other words, the plurality of trench gate structures 43 may be formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0121] The plurality of trench gate structures 43 are each formed on the first main surface 21 so as to penetrate the impurity region 6 and reach the semiconductor layer 3. Each of the plurality of trench gate structures 43 includes a trench 44, a gate insulating film 45, and a gate electrode 46. The gate insulating film 45 is formed in the form of a film along the wall surface of the trench 44. The gate electrode 46 is buried in the trench 44 with the gate insulating film 45 sandwiched between them. The gate electrode 46 faces the semiconductor layer 3 and the impurity region 6 with the gate insulating film 45 sandwiched between them.

[0122] The semiconductor device 71 includes a plurality of emitter regions 47 formed in the surface layer portion of the first main surface 21 on the sides of the plurality of trench gate structures 43. The plurality of emitter regions 47 form the emitters of the IGBT. Each emitter region 47 has an n-type impurity concentration that exceeds the n-type impurity concentration of the semiconductor layer 3. Each emitter region 47 is formed at an interval from the bottom 6a of the impurity region 6 toward the first main surface 21, and forms a channel of the IGBT between itself and the semiconductor layer 3.

[0123] The semiconductor device 71 includes a plurality of p-type contact regions 48 formed in regions between two adjacent trench gate structures 43 in the surface layer portion of the first main surface 21. Each contact region 48 has a p-type impurity concentration that exceeds the p-type impurity concentration of the impurity region 6. Each contact region is formed in the center of two adjacent trench gate structures 43, and is electrically connected to the impurity region 6 and each emitter region 47.

[0124] The semiconductor device 71 includes an interlayer insulating film 40 formed on the first main surface 21 in the active region 4. The interlayer insulating film 40 may include an SiO2 film. The interlayer insulating film 40 covers a plurality of trench gate structures 43. The interlayer insulating film 40 has a plurality of emitter openings 49. Each emitter opening 49 is formed in a region between two adjacent trench gate structures 43 in a plan view, and exposes an emitter region 47 and a contact region 48, respectively.

[0125] The semiconductor device 71 includes the aforementioned first principal surface electrode 36 formed on the first principal surface 21 in the active region 4. In this embodiment, the first principal surface electrode 36 is an emitter electrode of the IGBT. The first principal surface electrode 36 extends from above the interlayer insulating film 40 into the multiple emitter openings 49. The first principal surface electrode 36 is connected to the emitter regions 47 and contact regions 48 within the multiple emitter openings 49.

[0126] The semiconductor device 71 includes the aforementioned second principal surface electrode 33 covering the second principal surface 22 of the semiconductor layer 3. In this embodiment, the second principal surface electrode 33 is the collector electrode of the IGBT. The second principal surface electrode 33 forms ohmic contact with the second principal surface 22 (collector region 32).

[0127] As described above, even when an IGBT is formed in place of a pn junction diode in the active region 4, as in the semiconductor device 71, it is possible to achieve the same effects as those described for the semiconductor device 1. The structure in which an IGBT is formed in the active region 4 is not limited to the first embodiment, but can also be applied to the second and third embodiments.

[0128] The present disclosure may be embodied in still other forms.

[0129] In the above-described embodiments, examples have been described in which the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0130] In the fourth embodiment described above, an n-type drain region may be formed instead of the p-type collector region 32. With this structure, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) can be provided instead of the IGBT. A specific configuration in this case can be obtained by replacing the "impurity region 6 (base region)" of the IGBT with the "impurity region 6 (body region)" of the MISFET, the "emitter" of the IGBT with the "source" of the MISFET, and the "collector" of the IGBT with the "drain" of the MISFET in the above description. In this case, the drain region of the semiconductor chip 2 may be formed of a semiconductor substrate (Si substrate), and the semiconductor layer 3 may be formed of an epitaxial layer (Si epitaxial layer).

[0131] Examples of features extracted from this specification and drawings are given below. The following [Appendix 1] to [Appendix 20] provide a method for manufacturing a semiconductor device.

[0132] [Appendix 1] A method for manufacturing a semiconductor device (1, 51, 61, 71), comprising the steps of: preparing a semiconductor wafer (3, 24) of a first conductivity type having a main surface (25); defining regions on the main surface (25) where an active region (4) and an outer region (5) are to be formed; partitioning the active region (4) and the outer region (5) by selectively introducing second conductivity type impurities into a surface layer portion of the main surface (25), thereby forming a well region (7) of a second conductivity type, the well region (7) including a first concentration portion (8) having a higher impurity concentration on the active region (4) side and a second concentration portion (9) having a lower impurity concentration than the first concentration portion (8) on the outer region (5) side; and forming an impurity region (6) of the second conductivity type by introducing second conductivity type impurities into a surface layer portion of the main surface (25) in the active region (4).

[0133] [Appendix 2] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to Appendix 1, wherein the amount of second conductivity type impurity introduced into the region where the second concentration portion (9) is to be formed is less than the amount of second conductivity type impurity introduced into the region where the first concentration portion (8) is to be formed.

[0134] [Appendix 3] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to Appendix 1 or Appendix 2, wherein the step of forming the well region (7) includes a step of introducing a second conductivity type impurity into a surface layer portion of the main surface (25) through a mask having a first opening (15a) that exposes the entire region in the semiconductor wafer (3, 24) where the first concentration portion (8) is to be formed, and a second opening (15b) that partially exposes the region in the semiconductor wafer (3, 24) where the second concentration portion (9) is to be formed.

[0135] [Appendix 4] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 3, wherein the second concentration portion (9) has a concentration gradient in which the impurity concentration gradually decreases from the main surface (25) in the thickness direction.

[0136] [Appendix 5] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 4, wherein the first concentration portion (8) has a concentration gradient in which the impurity concentration gradually decreases from the main surface (25) in the thickness direction.

[0137] [Appendix 6] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 5, wherein the second concentration region (9) has a thickness less than the thickness of the first concentration region (8).

[0138] [Appendix 7] A method for manufacturing a semiconductor device (1, 51, 61, 71) described in any one of Appendices 1 to 6, wherein the well region (7) has a bottom (7a) recessed from the bottom (8a) of the first concentration portion (8) toward the bottom (9a) of the second concentration portion (9).

[0139] [Appendix 8] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 7, wherein the impurity region (6) has an impurity concentration lower than the impurity concentration of the first concentration portion (8).

[0140] [Supplementary Note 9] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Supplementary Notes 1 to 8, wherein the impurity region (6) is connected to the first concentration portion (8).

[0141] [Appendix 10] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 9, wherein the well region (7) is formed in a ring shape surrounding the active region (4) in a plan view.

[0142] [Appendix 11] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to Appendix 10, wherein the first concentration region (8) is formed in a ring shape surrounding an inner portion of the semiconductor wafer (3, 24) in a planar view, and the second concentration region (9) is formed in a ring shape surrounding the first concentration region (8) in a planar view.

[0143] [Appendix 12] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 11, further comprising the steps of: forming a main surface insulating film (12) covering the main surface (25); removing unnecessary portions of the main surface insulating film (12) to expose the impurity region (6) and the first concentration portion (8) from the main surface insulating film (12); and forming a main surface electrode (36) on the main surface (25) that is electrically connected to the impurity region (6) and the first concentration portion (8).

[0144] [Appendix 13] A method for manufacturing a semiconductor device (1, 51, 71) according to any one of Appendices 1 to 12, wherein the step of removing the main surface insulating film (12) includes a step of exposing the second concentration portion (9) from the main surface insulating film (12), and the step of forming the main surface electrode (36) includes a step of forming the main surface electrode (36) that is electrically connected to the second concentration portion (9).

[0145] [Appendix 14] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 1 to 13, further comprising the step of forming a field limit region (13A to 13C) of the second conductivity type by introducing a second conductivity type impurity into a surface layer portion of the main surface (25) at a distance from the well region (7) in the outer region (5).

[0146] [Appendix 15] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to appendix 14, wherein the step of forming the field limit regions (13A to 13C) is carried out simultaneously with the step of forming the well region (7).

[0147] [Appendix 16] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to appendix 14 or appendix 15, wherein the impurity concentration of the field limit regions (13A to 13C) is higher than the impurity concentration of the impurity region (6).

[0148] [Supplementary Note 17] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Supplementary Note 14 to Supplementary Note 16, wherein the impurity concentration of the field limit region (13A to 13C) is higher than the impurity concentration of the second concentration portion (9).

[0149] [Appendix 18] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 14 to 17, wherein the impurity concentration of the field limit region (13A to 13C) is higher than the impurity concentration of the second concentration portion (9) over the entire thickness direction of the field limit region (13A to 13C).

[0150] [Appendix 19] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 14 to 18, wherein the field limit region (13A to 13C) has a thickness greater than the thickness of the impurity region (6).

[0151] [Appendix 20] A method for manufacturing a semiconductor device (1, 51, 61, 71) according to any one of Appendices 14 to 19, wherein the field limit region (13A to 13C) has a thickness greater than the thickness of the second concentration region (9).

[0152] In addition, various design modifications can be made within the scope of the claims.

[0153] This application corresponds to Patent Application No. 2020-110721 filed with the Japan Patent Office on June 26, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0154] 1. Semiconductor device 3 Semiconductor layer 4 Active Area 5 Outer area 6 Impurity region 7 Well Area 7a Bottom of well area 8 High concentration area 8a Bottom of high concentration area 9 Low concentration area 9a Bottom of low concentration area 12 Main surface insulating film 13A FL area (field limit area) 13B FL area (field limit area) 13C FL region (field limit region) 21 First main surface 36 Main surface electrode 36a Drawer section 51 Semiconductor devices 61 Semiconductor devices 71 Semiconductor Devices T1 First thickness of the high density area T2 Second thickness of low density area T3 Third thickness in the FL region W1 1st width W2 Second width

Claims

1. a first conductivity type semiconductor layer having a major surface; a well region of a second conductivity type that partitions the main surface into an active region and an outer region, is formed in a surface layer portion of the main surface, includes a first concentration portion with a higher impurity concentration on the active region side, and a second concentration portion with a lower impurity concentration than the first concentration portion on the outer region side; an impurity region of a second conductivity type formed in a surface layer portion of the main surface in the active region; a main surface electrode on the main surface directly connected to the first concentration portion and the second concentration portion without interposing the impurity region therebetween; The impurity region has a thickness less than a thickness of the first concentration portion.

2. 2. The semiconductor device according to claim 1, wherein said second concentration portion has a concentration gradient in which the impurity concentration gradually decreases from said main surface toward a thickness direction.

3. 3. The semiconductor device according to claim 1, wherein said first concentration portion has a concentration gradient in which the impurity concentration gradually decreases from said main surface toward a thickness direction.

4. 4. The semiconductor device according to claim 1, wherein the second concentration portion has a thickness less than a thickness of the first concentration portion.

5. 5. The semiconductor device according to claim 1, wherein the bottom of said well region is recessed from the bottom of said first concentration region toward the bottom of said second concentration region.

6. 6. The semiconductor device according to claim 1, wherein the impurity concentration of said impurity region is lower than the impurity concentration of said first concentration portion and the impurity concentration of said second concentration portion.

7. 7. The semiconductor device according to claim 1, wherein the impurity region is connected to the first concentration portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein the well region defines an active region in an inner part of the semiconductor layer in a planar view, defines the outer region in a peripheral part of the semiconductor layer, and is formed in a ring shape surrounding the inner part of the semiconductor layer.

9. the first concentration portion is formed in a ring shape surrounding an inner portion of the semiconductor layer in a plan view, 9. The semiconductor device according to claim 8, wherein said second concentration portion is formed in a ring shape surrounding said first concentration portion in a plan view.

10. 10. The semiconductor device according to claim 1, wherein the main surface electrode is connected to the impurity region.

11. The semiconductor device according to claim 10 , wherein the principal surface electrode is connected to the first concentration portion.

12. 12. The semiconductor device according to claim 11, wherein the main surface electrode is drawn from the impurity region onto the first concentration portion and the second concentration portion, and is directly connected to each of the impurity region, the first concentration portion, and the second concentration portion.

13. the first concentration portion has a first thickness T1 and a first width W1, and has a horizontally elongated structure in a cross-sectional view in which a ratio W1 / T1 of the first width W1 to the first thickness T1 exceeds 1; The semiconductor device according to any one of claims 1 to 12, wherein the second concentration portion has a second thickness T2 and a second width W2, and has a horizontally elongated structure in which the ratio W2 / T2 of the second width W2 to the second thickness T2 exceeds 1 in a cross-sectional view.

14. 14. The semiconductor device according to claim 1, further comprising a field limit region of a second conductivity type formed in a surface layer portion of said main surface at a distance from said well region in said outer region.

15. 15. The semiconductor device according to claim 14, wherein the impurity concentration of said field limit region is higher than the impurity concentration of said impurity region.

16. 16. The semiconductor device according to claim 14, wherein the impurity concentration of said field limit region is higher than the impurity concentration of said second concentration portion.

17. 17. The semiconductor device according to claim 14, wherein the impurity concentration of said field limit region is higher than the impurity concentration of said second concentration portion over the entire area of ​​said field limit region in the thickness direction.

18. 18. The semiconductor device according to claim 14, wherein the field limit region has a thickness greater than a thickness of the impurity region.

19. 19. The semiconductor device according to claim 14, wherein the field limit region has a thickness greater than a thickness of the second concentration portion.

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