Semiconductor Devices

Abstract

To provide a semiconductor device in which an effect of an active region expansion is improved.SOLUTION: A semiconductor device comprises a semiconductor element (40) in which an emitter electrode (42) is arranged on one surface (41a) of a semiconductor substrate (41) and a collector electrode (43) is arranged on a rear surface. The emitter electrode (42) has an exposed part (421) that is exposed from an opening (561) of a protection film (56) to provide a junction region. The semiconductor substrate (41) has an active region (45) that is a formation region of an RC-IGBT, as a vertical element flowing current between the emitter electrode (42) and the collector electrode. The active region (45) includes an overlapping region (451) that overlaps with the exposed part (421) in a plan view and a non-overlapping region that does not overlap with the exposed part (421). A ratio of a diode region (45d) in the non-overlapping region that includes a region (452a) at a lateral side of a pad is higher than a ratio of the diode region (45d) in the overlapping region (451).SELECTED DRAWING: Figure 5

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Patent Application No. 2021-119227 filed in Japan on July 20, 2021, and the contents of the original application are incorporated by reference in their entirety. [Technical Field]

[0002] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0003] Patent Document 1 discloses a semiconductor device in which main electrodes are arranged on both sides of a semiconductor substrate. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-5692 Summary of the Invention

[0005] In Patent Document 1, the active region in which the elements are formed extends outward beyond the lower portion of the terminal. The elements are arranged so that when the switching elements in the extended region and the switching elements in the region below the terminal are turned on, the current density in the extended region is lower than the current density in the region below the terminal. In this way, the current density in the extended region is low. Further improvements are required in semiconductor devices in the above-mentioned respects and in other respects not mentioned.

[0006] The present disclosure has been made in view of the above-mentioned problems, and aims to provide a semiconductor device that can enhance the effect of expanding the active region.

[0007] The semiconductor device disclosed herein comprises: a semiconductor substrate having one surface and a back surface opposite to the one surface in a thickness direction; a protective film disposed on one surface of a semiconductor substrate and having an opening; a first main electrode disposed on one surface of the semiconductor substrate and having an exposed portion exposed through the opening to provide a junction region; a second main electrode disposed on the back surface of the semiconductor substrate; the semiconductor substrate has an active region which is a region for forming an IGBT having a diode connected in antiparallel as a vertical element for causing a current to flow between a first main electrode and a second main electrode; the opening is provided so as to overlap with the active area in a plan view in the plate thickness direction, the active region includes an overlapping region that overlaps with the exposed portion of the first main electrode in a plan view and a non-overlapping region that does not overlap with the exposed portion; The ratio of the diode formation area in the non-overlapping area is higher than the ratio of the diode formation area in the overlapping area. Rotten, The semiconductor substrate has a plurality of gate electrodes (55) of a trench structure formed to a predetermined depth from one surface, The gate electrode is formed in the overlapping and non-overlapping regions in the active region.

[0008] In the disclosed semiconductor device, the active area includes an overlapping area and a non-overlapping area, i.e., the active area is expanded, and the ratio of the diode formation area in the non-overlapping area is made higher than the ratio of the diode formation area in the overlapping area.

[0009] Increasing the ratio of the diode formation area in the non-overlapping area increases the ratio of the IGBT formation area in the overlapping area, but heat generated by the operation of the IGBT can be dissipated from the exposed portion of the first main electrode to the joining object. Also, by increasing the ratio of the diode formation area in the non-overlapping area, it is possible to prevent the temperature of the non-overlapping area from becoming higher than that of the overlapping area. In other words, it is possible to prevent the IGBT from having to be turned off due to a temperature rise in the non-overlapping area. As a result, the effect of expanding the active area can be enhanced.

[0010] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied; [Figure 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 1 is a plan view showing a semiconductor element. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 10 is a plan view showing a semiconductor element in a semiconductor device according to a second embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 10 is a plan view showing a semiconductor element in a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a plan view showing a semiconductor element in a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 10 is a plan view showing another modified example. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0013] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile object using a rotating electric machine as a drive source. The mobile object is, for example, an electric vehicle such as an electric vehicle (EV), a hybrid vehicle (HV), or a plug-in hybrid vehicle (PHV), an aircraft such as a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0014] (First embodiment) First, the schematic configuration of a vehicle drive system will be described with reference to FIG.

[0015] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0016] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0017] <Power conversion device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a smoothing capacitor 5 and an inverter 6.

[0018] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power line on the high potential side, and an N line 8, which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0019] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0020] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is made up of a conductive member such as a bus bar.

[0021] The elements constituting each arm include an insulated gate bipolar transistor 11 (hereinafter referred to as IGBT 11) which is a switching element, and a freewheeling diode 12. In this embodiment, an n-channel IGBT 11 is used. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. The emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0022] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage increase and decrease. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0023] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0024] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit. The control circuit generates the drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as the drive command. The control circuit is configured to include, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

[0025] <Semiconductor device> Next, a schematic configuration of a semiconductor device to which the semiconductor element is applied will be described with reference to Figures 2 and 3. Figure 2 is a plan view showing the semiconductor device. Figure 2 is a top plan view of the semiconductor device. Figure 3 is a cross-sectional view taken along line III-III in Figure 2. Figure 3 illustrates a simplified structure of the semiconductor element.

[0026] In the following, the thickness direction of the semiconductor substrate is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the X direction. The direction perpendicular to both the Z direction and the X direction is referred to as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction is simply referred to as the planar view.

[0027] 2 and 3, the semiconductor device 20 includes a sealing resin body 30, a semiconductor element 40, heat sinks 60 and 70, a conductive spacer 80, and an external connection terminal 90. The semiconductor device 20 constitutes one of the arms described above. In other words, two semiconductor devices 20 constitute one phase of the upper and lower arm circuits 9.

[0028] The encapsulating resin body 30 encapsulates some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulating resin body 30. The encapsulating resin body 30 is made of, for example, an epoxy resin. The encapsulating resin body 30 is formed, for example, by a transfer molding method. As shown in FIG. 2, the encapsulating resin body 30 has a generally rectangular planar shape. The encapsulating resin body 30 has one surface 30a and a back surface 30b that is the surface opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces.

[0029] The semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon, and a vertical element is formed on the semiconductor substrate 41. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0030] The vertical element is configured to pass a main current in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), i.e., in the Z direction. The vertical element of this embodiment is an IGBT 11 and a diode 12 that form one arm. The vertical element is an IGBT with the diode 12 connected in reverse parallel, i.e., an RC (Reverse Conducting)-IGBT. The vertical element is a heat-generating element that generates heat when current is applied. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.

[0031] The semiconductor substrate 41 has one surface 41a and a back surface 41b as plate surfaces on which main electrodes are provided. The one surface 41a is the surface of the semiconductor substrate 41 facing the one surface 30a of the sealing resin body 30. The back surface 41b is the surface opposite to the one surface 41a in the plate thickness direction. An emitter electrode 42, which is one of the main electrodes, is disposed on the one surface 41a of the semiconductor substrate 41. A collector electrode 43, which is the other of the main electrodes, is disposed on the back surface 41b of the semiconductor substrate 41. The emitter electrode 42 corresponds to a first main electrode, and the collector electrode 43 corresponds to a second main electrode.

[0032] When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed on almost the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one surface 41a of the semiconductor substrate 41.

[0033] The pads 44 are electrodes for signals. The pads 44 are formed on one surface 41a of the semiconductor substrate 41 in a region different from the region where the emitter electrodes 42 are formed. The pads 44 are formed at the end opposite the region where the emitter electrodes 42 are formed in the Y direction. The pads 44 are provided alongside the emitter electrodes 42 in the Y direction. The pads 44 include at least a pad for a gate electrode. Details of the semiconductor element 40 will be described later.

[0034] The heat sinks 60, 70 are metal plates made of a metal with good conductivity, such as Cu or a Cu alloy. The heat sinks 60, 70 are arranged in the Z direction to sandwich multiple semiconductor elements 40. The heat sinks 60, 70 are arranged so that at least a portion of each element faces each other in the Z direction. The heat sinks 60, 70 contain the semiconductor elements 40 in a plan view.

[0035] The heat sink 60 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the heat sink 70 is electrically connected to the collector electrode 43 and provides a wiring function. The heat sinks 60, 70 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. The heat sinks 60, 70 may have a plating film of Ni, Au, or the like on their surfaces. The heat sink 60 of this embodiment is electrically connected to the emitter electrode 42 via a conductive spacer 80. The heat sink 60 and the conductive spacer 80 correspond to a first wiring member. The heat sink 70 corresponds to a second wiring member.

[0036] The heat sink 60 has an opposing surface 60a, which is the surface facing the semiconductor element 40, and a back surface 60b, which is the surface opposite the opposing surface 60a. Similarly, the heat sink 70 also has an opposing surface 70a and a back surface 70b. The heat sinks 60 and 70 have a generally rectangular planar shape. The back surfaces 60b and 70b of the heat sinks 60 and 70, respectively, are exposed from the sealing resin body 30. The back surfaces 60b and 70b are sometimes referred to as heat dissipation surfaces or exposed surfaces. The back surface 60b of the heat sink 60 is generally flush with one surface 30a of the sealing resin body 30. The back surface 70b of the heat sink 70 is generally flush with the back surface 30b of the sealing resin body 30.

[0037] The conductive spacer 80 is interposed between the semiconductor element 40 and the heat sink 60. The conductive spacer 80 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the heat sink 60. For example, the conductive spacer 80 ensures a height required to electrically connect the corresponding signal terminal 93 to the pad 44 of the semiconductor element 40. The conductive spacer 80 is located midway along the electrical and thermal conduction paths between the emitter electrode 42 of the semiconductor element 40 and the heat sink 60, and provides wiring and heat dissipation functions.

[0038] The conductive spacer 80 contains a metal material such as Cu that has good electrical and thermal conductivity. The conductive spacer 80 may have a plating film on its surface. The conductive spacer 80 may also be called a terminal, a terminal block, a metal block, or the like. The semiconductor device 20 includes the same number of conductive spacers 80 as the semiconductor elements 40. The conductive spacers 80 are individually connected to the semiconductor elements 40. The conductive spacer 80 is, for example, a columnar body having a substantially rectangular shape in plan view. The conductive spacer 80 has a size that is approximately the same as or slightly smaller than the exposed portion 421 described below in plan view.

[0039] The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to external devices. The external connection terminals 90 are formed using a metal material with good conductivity, such as copper. The external connection terminals 90 are, for example, a plate material. The external connection terminals 90 are sometimes called leads. The external connection terminals 90 include main terminals 91 and 92 and a signal terminal 93. The main terminals 91 and 92 are external connection terminals 90 electrically connected to main electrodes of the semiconductor element 40.

[0040] The main terminal 91 is electrically connected to the emitter electrode 42. The main terminal 91 is sometimes referred to as an emitter terminal. The main terminal 91 is connected to one end of the heat sink 60 in the Y direction. The thickness of the main terminal 91 is thinner than that of the heat sink 60. The main terminal 91 is connected to the heat sink 60 so as to be, for example, approximately flush with the opposing surface 60a. The main terminal 91 may be connected by being provided integrally with the heat sink 60, or may be provided as a separate member and connected by joining.

[0041] The main terminal 91 in this embodiment is provided integrally with the heat sink 60 as part of the lead frame. The main terminal 91 extends in the Y direction from the heat sink 60 and protrudes to the outside from the side surface 30c of the sealing resin body 30. The main terminal 91 has a bent portion midway through the portion covered by the sealing resin body 30, and protrudes from near the center in the Z direction on the side surface 30c.

[0042] The main terminal 92 is electrically connected to the collector electrode 43. The main terminal 92 is sometimes referred to as a collector terminal. The main terminal 92 is connected to the collector electrode 43 via the heat sink 70. The main terminal 92 is connected to one end of the heat sink 70 in the Y direction. The thickness of the main terminal 92 is thinner than that of the heat sink 70. The main terminal 92 is connected to the heat sink 70 so as to be approximately flush with the opposing surface 70a, for example. The main terminal 92 may be connected by being provided integrally with the heat sink 70, or may be provided as a separate member and connected by joining.

[0043] The main terminal 92 in this embodiment is provided integrally with the heat sink 70 as part of a lead frame separate from the main terminal 91. The main terminal 92 extends in the Y direction from the heat sink 70 and protrudes to the outside from the same side surface 30c as the main terminal 91. The main terminal 92 also has a bent portion midway through the portion covered by the sealing resin body 30, and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 91, 92 are arranged side by side in the X direction with their side surfaces facing each other.

[0044] The signal terminals 93 are electrically connected to the pads 44 of the semiconductor element 40. In this embodiment, the electrical connection is via bonding wires 100. The signal terminals 93 extend in the Y direction and protrude to the outside from the side surface 30d of the sealing resin body 30. The side surface 30d is the surface opposite the side surface 30c in the Y direction. The semiconductor device 20 of this embodiment has five signal terminals 93 corresponding to the pads 44. The signal terminals 93 are configured on a lead frame common to the heat sink 70 and the main terminals 92, for example. The multiple signal terminals 93 are electrically isolated from each other by cutting tie bars (not shown).

[0045] The emitter electrode 42 of the semiconductor element 40 is bonded to the conductive spacer 80 via a bonding material 101. The conductive spacer 80 is bonded to the heat sink 60 via a bonding material 102. The collector electrode 43 of the semiconductor element 40 is bonded to the heat sink 70 via a bonding material 103. The bonding materials 101 to 103 are conductive bonding materials. For example, solder can be used as the bonding materials 101 to 103. One example of solder is a multi-component lead-free solder containing Cu, Ni, and the like in addition to Sn. A sinter-based bonding material such as sintered silver may be used instead of solder. The bonding materials 101 to 103 may be made of the same material or different materials. In this embodiment, solder is used as the bonding materials 101, 102, and 103.

[0046] As described above, in the semiconductor device 20, the semiconductor element 40 that constitutes one arm is encapsulated by the encapsulating resin body 30. The encapsulating resin body 30 integrally encapsulates the semiconductor element 40, a portion of the heat sink 60, a portion of the heat sink 70, the conductive spacer 80, and a portion of each of the external connection terminals 90.

[0047] The semiconductor element 40 is disposed between the heat sinks 60 and 70 in the Z direction. The semiconductor element 40 is sandwiched between the heat sinks 60 and 70, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 60b of the heat sink 60 is substantially flush with one surface 30a of the sealing resin body 30. The back surface 70b of the heat sink 70 is substantially flush with the back surface 30b of the sealing resin body 30. Because the back surfaces 60b and 70b are exposed surfaces, heat dissipation can be improved.

[0048] <Semiconductor element> Next, the semiconductor element 40 will be described with reference to FIGS. 4 and 5. FIG. 4 is a plan view showing one surface of the semiconductor element 40. For convenience, in FIG. 4, the active region including the IGBT region and the diode region is shown by a solid line. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. In the following, the terms "inside" and "outside" refer to a relative positional relationship with the center of the active region of the semiconductor element as the reference position. The side closer to the center is the inside, and the side farther from the center is the outside.

[0049] As shown in FIG. 4, the semiconductor substrate 41 has a generally rectangular shape in plan view. The semiconductor substrate 41 has an active region 45. The active region 45 is a region where a vertical element is formed. The active region 45 may also be referred to as a main region, a main cell region, a cell region, an element region, an element forming region, or the like. The active region 45 has an IGBT region 45i where the IGBT is formed, and a diode region 45d where the diode is formed, of the RC-IGBT. The IGBT regions 45i and the diode regions 45d are provided alternately in the Y direction. The active region 45 has a plurality of cells (unit structural parts). The RC-IGBT is configured by connecting the plurality of cells in parallel with each other.

[0050] The semiconductor substrate 41 has a peripheral region 46 that surrounds the active region 45. In a plan view, the peripheral region 46 is a region that is located outside the peripheral edge of the active region 45. Although not shown, a breakdown voltage structure such as a guard ring is formed in the peripheral region 46.

[0051] 5, the semiconductor substrate 41 has a collector region 47, a cathode region 48, a buffer region 49, a drift region 50, a base region 51, and an emitter region 52. The semiconductor substrate 41 is formed with each semiconductor region by ion implantation of impurities or the like. The semiconductor region may also be referred to as a semiconductor layer, a diffusion layer, or the like.

[0052] The collector region 47 is formed in the surface layer on the back surface 41b side of the semiconductor substrate 41. The collector region 47 is a p-conductivity type (p+) semiconductor region having a higher impurity concentration than the base region 51. The cathode region 48 is also formed in the surface layer on the back surface 41b side. The cathode region 48 is an n-conductivity type (n+) semiconductor region having a higher impurity concentration than the drift region 50. The cathode region 48 is provided alongside the collector region 47 in the XY plane. The collector region 47 is provided in the IGBT region 45i, and the cathode region 48 is provided in the diode region 45d. The cathode regions 48 are provided alternately with the collector regions 47 in the Y direction.

[0053] The buffer region 49 is formed on the surface of the collector region 47 and the cathode region 48 opposite to the back surface 41b. The buffer region 49 is formed between the collector region 47 and the cathode region 48 and the drift region 50. The buffer region 49 is an n-conductivity type semiconductor region (n) that has a lower impurity concentration than the cathode region 48 and a higher impurity concentration than the drift region 50. The provision of the buffer region 49 can prevent the depletion layer from spreading toward the collector region 47.

[0054] The drift region 50 is formed on the surface of the buffer region 49 opposite to the surface on the collector region 47 side. The drift region 50 is an n-conductivity type (n-) semiconductor region having a lower impurity concentration than the buffer region 49.

[0055] The base region 51 is formed on the surface of the drift region 50 opposite to the surface on the buffer region 49 side. The base region 51 is a semiconductor region of p-conductivity type (p) with a lower impurity concentration than the collector region 47. The base region 51 is mainly provided in the active region 45 of the semiconductor substrate 41. The base region 51 is formed in the surface layer on the one surface 41a side of the semiconductor substrate 41. The base region 51 is sometimes referred to as a channel region. If the n-conductivity type is the first conductivity type, the p-conductivity type is the second conductivity type.

[0056] The emitter region 52 is provided in the surface layer on the one surface 41a side of the base region 51. The emitter region 52 is an n-conductivity type (n+) semiconductor region having a higher impurity concentration than the drift region 50. The emitter region 52 is formed in the IGBT region 45i of the active region 45. The emitter region 52 is provided in the IGBT region 45i so as to contact the side surface of a trench 53, which will be described later.

[0057] A trench 53 is formed in the semiconductor substrate 41 having the above-described configuration. The trench 53 is formed to a predetermined depth from one surface 41a. The trench 53 penetrates the base region 51. The tip of the trench 53 reaches the drift region 50. A plurality of trenches 53 are formed in the active region 45 of the semiconductor substrate 41. Each trench 53 extends in the X direction. The plurality of trenches 53 are arranged at approximately equal intervals in the Y direction, forming a stripe shape in plan view. The trenches 53 define cells. Each cell includes one trench 53, and the plurality of cells are arranged side by side in the Y direction.

[0058] A gate insulating film 54 is formed on the wall surface of the trench 53. A gate electrode 55 is formed on the surface of the gate insulating film 54 so as to fill the trench 53. The gate electrode 55 penetrates the base region 51 and reaches the drift region 50. A plurality of gate electrodes 55 are formed in the active region 45 of the semiconductor substrate 41. Each gate electrode 55 extends in the X direction. The plurality of gate electrodes 55 are arranged at approximately equal intervals in the Y direction and form a stripe shape in a plan view.

[0059] An emitter electrode 42 is formed on one surface 41a of the semiconductor substrate 41. The emitter electrode 42 is formed mainly on the active region 45. The emitter electrode 42 is electrically connected to the emitter region 52 and the base region 51. The emitter electrode 42 is electrically isolated from the gate electrode 55. The emitter electrode 42 may be electrically connected to the base region 51 via a base contact region. The base contact region is provided in a surface layer on the one surface 41a side within the base region 51. The base contact region is provided adjacent to the emitter region 52. The base contact region is a p-type (p+) semiconductor region having a higher impurity concentration than the base region 51.

[0060] Pads 44, which are signal electrodes, are also formed on one surface 41a of the semiconductor substrate 41. The semiconductor element 40 of this embodiment has five pads 44. Specifically, there are pads 44 for a gate electrode, a Kelvin emitter that detects the emitter potential of the IGBT 12, a current sensor, an anode potential of a temperature-sensitive diode (temperature-sensitive element) that detects the temperature of the semiconductor element 40, and a cathode potential of the same. The Kelvin emitter pad 44 is electrically connected to the emitter electrode 42. The other pads 44 are electrically isolated from the emitter electrode 42. The five pads 44 are formed together at one end in the Y direction of the semiconductor substrate 41, which has a substantially rectangular shape in plan view, and are also formed side by side in the X direction. The five pads 44 are arranged near the center of the side of the semiconductor substrate 41 along the X direction.

[0061] A collector electrode 43 is formed on the rear surface 41b of the semiconductor substrate 41. The collector electrode 43 is formed over almost the entire rear surface 41b. The collector electrode 43 is electrically connected to the collector region 47 and the cathode region .

[0062] In the semiconductor device 40 described above, an IGBT structure is formed in each cell of the IGBT region 45i. The IGBT structure includes a collector region 47, a buffer region 49, a drift region 50, a base region 51, an emitter region 52, and a gate electrode 55. Furthermore, a diode structure is formed in each cell of the diode region 45d. The diode structure includes a cathode region 48, a buffer region 49, the drift region 50, and a base region 51 that functions as an anode.

[0063] <Emitter electrode> Next, the emitter electrode 42 will be described in detail with reference to Figures 4 and 5. In Figure 4, the protective film is omitted.

[0064] The semiconductor element 40 has a protective film 56 disposed on one surface 41a of the semiconductor substrate 41. The protective film 56 is an insulating film provided on the one surface 41a of the semiconductor substrate 41 so as to cover the peripheral edge of the emitter electrode 42. Examples of materials that can be used for the protective film 56 include polyimide and silicon nitride. The protective film 56 has an opening 561 that defines the bonding region between the emitter electrode 42 and the bonding material 101. The opening 561 is a through-hole that penetrates the protective film 56 in the Z direction. Similarly, the protective film 56 has an opening (not shown) that defines the bonding region of the pad 44.

[0065] The emitter electrode 42 has an exposed portion 421 that is exposed from the opening 561 of the protective film 56 and provides a bonding area. The exposed portion 421 forms a bonding portion with the bonding material 101. The emitter electrode 42 has a multi-layer structure. The emitter electrode 42 has a base electrode 422 and a connection electrode 423. The pad 44 has a similar configuration to the emitter electrode 42.

[0066] The base electrode 422 is a metal layer formed adjacent to the semiconductor substrate 41 in the multi-layered emitter electrode 42. The base electrode 422 may also be referred to as a lower electrode, a lower-layer electrode, a wiring electrode, a first metal layer, etc. The base electrode 422 is connected to one surface 41a of the semiconductor substrate 41. The base electrode 422 is formed using a material containing Al (aluminum) as a main component, for example. In this embodiment, an Al alloy such as AlSi or AlSiCu is used as the material.

[0067] In a plan view, the base electrode 422 extends onto the outer periphery region 46 while encompassing the active region 45. The base electrode 422 is connected to the emitter region 52 and the base region 51. The base electrode 422 has a peripheral edge portion 422a that surrounds the exposed portion 421 in a plan view. The peripheral edge portion 422a is a portion of the base electrode 422 that overlaps with the protective film 56. The protective film 56 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral edge portion 422a of the base electrode 422.

[0068] The connection electrode 423 is layered on the base electrode 422 for the purposes of improving the bonding strength with the bonding material 101 and improving wettability with respect to the bonding material 101. The connection electrode 423 is also referred to as a top electrode, an upper electrode, an upper layer electrode, or a second metal layer. The connection electrode 423 includes at least one metal layer. The metal layer constituting the connection electrode 423 includes, for example, any of Ni, Pd, Au, Pt, and Ag.

[0069] The connection electrode 423 of this embodiment includes at least a Ni (nickel) layer. Ni is harder than the Al alloy that constitutes the base electrode 422. An Au (gold) layer may be further provided on the Ni layer. The Au layer, for example, suppresses oxidation of the Ni layer and improves wettability with the solder that is the bonding material 101. Because Au diffuses into the solder during soldering, the Au layer exists in the state before soldering, but does not exist in the state after soldering.

[0070] The connection electrode 423 is disposed on the base electrode 422 and exposed from the opening 561. As an example, the connection electrode 423 of this embodiment is disposed on the base electrode 422 within the opening 561. The outer peripheral edge of the connection electrode 423 is in contact with, for example, the wall surface of the protective film 56 that defines the opening 561. The exposed portion 421 of the emitter electrode 42 is composed of the connection electrode 423 and a portion of the base electrode 422 that overlaps with the opening 561 in a plan view. The exposed portion 421 has a substantially rectangular shape in plan view.

[0071] <Positional relationship between exposed area and active area> Next, the positional relationship between the exposed portion 421 of the emitter electrode 42 and the active region 45 will be described with reference to Fig. 4. For convenience, the outer peripheral edge of the exposed portion 421 of the emitter electrode 42, i.e., the opening edge of the protective film 56, is indicated by a dashed line in Fig. 4.

[0072] 4, the active region 45 includes an overlapping region 451 that overlaps with the exposed portion 421 of the emitter electrode 42 in a plan view, and a non-overlapping region 452 that does not overlap with the exposed portion 421. The overlapping region 451 is a region of the active region 45 that is directly below the exposed portion 421. The non-overlapping region 452 is a region of the active region 45 that is outside the exposed portion 421.

[0073] The overlapping region 451 is aligned with the pad 44 in the Y direction. The non-overlapping region 452 is continuous with the overlapping region 451 in the Y direction. That is, the non-overlapping region 452 is aligned with the exposed portion 421 in the Y direction. The non-overlapping region 452 is provided on the pad 44 side of the exposed portion 421. Most of the non-overlapping region 452 is aligned with the pad 44 in the X direction. The non-overlapping region 452 includes a pad-side region 452a aligned with the pad 44 in the X direction. The non-overlapping region 452 includes two pad-side regions 452a. The two pad-side regions 452a are provided on both sides of the pad 44 in the X direction, sandwiching the pad 44 between them. The Y direction corresponds to a first direction, which is the alignment direction of the pads and the overlapping regions, and the X direction corresponds to a second direction.

[0074] In this embodiment, the entire non-overlapping region 452 is the diode region 45d. No IGBT region 45i is provided in the non-overlapping region 452. Only a diode structure (diode) is formed in the region 452a beside the pad. An IGBT structure (IGBT) and a diode structure are formed in the overlapping region 451. In the overlapping region 451, the IGBT regions 45i and the diode regions 45d are alternately provided at a predetermined pitch in the Y direction, which is the arrangement direction of the trenches 53. In the overlapping region 451, the area of ​​each IGBT region 45i is larger than the area of ​​each diode region 45d. In other words, the number of cells in each IGBT region 45i is greater than the number of cells in each diode region 45d. The area is the area along the XY plane.

[0075] <Summary of the First Embodiment> As described above, in this embodiment, the active region 45 includes an overlapping region 451 with the exposed portion 421 that contributes to bonding, and a non-overlapping region 452. In other words, the active region 45 is expanded outside the exposed portion 421. The ratio of the diode region 45d in the non-overlapping region 452 is made higher than the ratio of the diode region 45d in the overlapping region 451.

[0076] In order for the RC-IGBT to perform the desired function, the active region 45 has a predetermined ratio of IGBT regions 45i and diode regions 45d. In this embodiment, the ratio of the diode regions 45d is increased in the non-overlapping region 452, and accordingly the ratio of the IGBT regions 45i is increased in the overlapping region 451. In other words, heat from the overlapping region 451 where the IGBT structural components are concentrated, that is, heat generated mainly by IGBT operation, can be efficiently dissipated from the exposed portion 421 located directly above to the conductive spacer 80 to be joined, and ultimately to the heat sink 60.

[0077] The amount of heat generated by the diode structure portion is smaller than that of the IGBT structure portion. In this embodiment, as described above, the ratio of the diode region 45d in the non-overlapping region 452 is increased. This prevents the temperature of the non-overlapping region 452 from becoming higher than that of the overlapping region 451. In other words, it is possible to prevent the IGBT from having to be turned off due to a temperature rise in the non-overlapping region 452. This prevents the semiconductor device 20 from being unable to pass any more current even though the overlapping region 451 is not yet at a very high temperature, and allows a large current to pass through the semiconductor device 20 until the overlapping region 451 becomes too hot. As a result, the effect of expanding the active area can be enhanced.

[0078] The above configuration can suppress a temperature rise throughout the active region 45 when the IGBT is operated to supply a large current to the motor-generator 3, for example, during hot spot operation such as climbing a slope or overtaking. Furthermore, increasing the proportion of the IGBT region 45i in the overlap region 451 and suppressing temperature rise through heat dissipation through the exposed portion 421 can suppress a decrease in the short-circuit resistance of the IGBT due to temperature rise. Furthermore, increasing the proportion of the diode region 45d in the non-overlap region 452 ensures the area of ​​the diode region 45d in the entire active region 45. This reduces the current density during diode operation and suppresses electromigration.

[0079] In this embodiment, the non-overlapping region 452 includes a region 452a beside the pad that is aligned with the pad 44 in the X direction, which is the second direction. This makes it possible to effectively utilize the empty space beside the pad 44, thereby expanding the active region 45 without changing the area of ​​the semiconductor substrate 41, i.e., the chip area.

[0080] In this embodiment, only the diode region 45d is provided in the region 452a beside the pad. That is, only the diode structure (diode) is formed in the region 452a beside the pad. As described above, the amount of heat generated by the diode structure is smaller than that of the IGBT structure, so that the temperature of the non-overlapping region 452 can be more effectively prevented from becoming higher than the temperature of the overlapping region 451.

[0081] (Second embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, only the diode region 45d is provided in the region 452a beside the pad. Instead, the IGBT region 45i may be provided in the region 452a beside the pad.

[0082] The arrangement of the IGBT regions 45i in the region 452a beside the pad is not particularly limited. In a configuration in which the region 452a beside the pad includes the IGBT regions 45i, it is sufficient that the ratio of the diode regions 45d in the non-overlapping region 452 is higher than the ratio of the diode regions 45d in the overlapping region 451. For example, the IGBT regions 45i and the diode regions 45d may be provided alternately in the region 452a beside the pad.

[0083] FIG. 6 shows an example of a semiconductor element 40 in the semiconductor device 20 according to this embodiment. FIG. 6 is a plan view corresponding to FIG. 4. In FIG. 6, as in FIG. 4, the outer peripheral edge of the exposed portion 421 of the emitter electrode 42 is indicated by a dashed line, and the active region 45 including the IGBT region 45i and the diode region 45d is indicated by a solid line. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6.

[0084] In the example shown in FIGS. 6 and 7 , a diode region 45d and an IGBT region 45i are provided in the pad-side region 452a. In the pad-side region 452a, the IGBT region 45i is provided at the end on the peripheral region 46 side. That is, the IGBT region 45i is provided at the end of the pad-side region 452a adjacent to the peripheral region 46, not at the end at the boundary with other regions of the active region 45. The IGBT region 45i is provided at the end of the pad-side region 452a facing the guard ring 57. The trenches 53 (not shown) are arranged side by side in the Y direction, as in the previous embodiment. In this embodiment, the IGBT region 45i is provided at the end of the pad-side region 452a in the Y direction, i.e., at the end of the active region 45.

[0085] As shown in FIG. 7 , a guard ring 57 is formed in the peripheral region 46 of the semiconductor substrate 41. The guard ring 57 extends the depletion layer extending from the base region 51 along the surface 41 a of the semiconductor substrate 41 when a high voltage is applied to the IGBT region 45 i, thereby reducing the electric field strength and increasing the breakdown voltage of the semiconductor device 20. The guard ring 57 is provided to surround the active region 45. The number of guard rings 57 is not particularly limited; it is sufficient to have at least one. In the example shown in FIG. 7 , one of the guard rings 57 is provided adjacent to the edge of the base region 51. The other guard ring 57 is provided at a position away from the inner guard ring 57. The other configuration is the same as that described in the preceding embodiment.

[0086] <Summary of the second embodiment> When the diode is forward biased, the guard ring 57 has the same potential as the base region 51. Therefore, holes are supplied to the drift region 50 from the guard ring 57, which is a p-type semiconductor.

[0087] In this embodiment, the IGBT region 45i is provided at the end of the pad-side region 452a. The IGBT region 45i at the end distances the diode region 45d from the guard ring 57. This prevents a large number of holes from accumulating in the drift region 50 near the boundary between the pad-side region 452a and the peripheral region 46 when the diode region 45d is forward biased. Therefore, when the diode region 45d is reverse biased, a large number of holes can be prevented from flowing into the base region 51, which functions as an anode, preventing local current concentration. This improves the diode's recovery tolerance. This embodiment enhances the effect of expanding the active area while improving the recovery tolerance.

[0088] As shown in FIG. 6, in this embodiment, an IGBT region 45i is also provided at the end of the active region 45 opposite the pad 44 in the Y direction. This also improves the recovery tolerance of the diode. Furthermore, in the X direction, the end of the diode region 45d is located more inward than the end of the IGBT region 45i. This also improves the recovery tolerance of the diode. In this way, the recovery tolerance of the diode can also be improved in the overlap region 451. Note that the previous embodiment also has a similar configuration as shown in FIG. 4. Therefore, the above-mentioned effects can be achieved.

[0089] Although an example in which the IGBT region 45i is provided at the end in the Y direction in the region 452a beside the pad has been shown, this is not limiting. For example, the IGBT region 45i may be provided at the end on the opposite side in the X direction from the pad 44. The IGBT region 45i may also be provided at both the end in the Y direction and the end in the X direction.

[0090] The breakdown voltage structure of the peripheral region 46 is not limited to the guard ring 57 described above. Any structure including a p-type semiconductor region that has the same potential as the base region 51 when the diode is forward biased may be used. For example, a RESURF structure may be employed. In this case, the p-type semiconductor region is formed in the surface layer of the drift region 50 in the peripheral region 46. This semiconductor region extends outward from the base region 51. Even in such a RESURF structure, providing an IGBT region 45i at the end of the region 452a next to the pad can improve recovery capability while enhancing the effect of expanding the active area. RESURF is an abbreviation for Reduced Surface Electric Field.

[0091] (Third embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used in this embodiment. In the previous embodiment, the non-overlapping region 452 is provided so as to be continuous with the end of the overlapping region 451 on the pad 44 side. Alternatively, the non-overlapping region 452 may be provided so as to be aligned with the exposed portion 421.

[0092] Fig. 8 shows the semiconductor element 40 in the semiconductor device 20 according to this embodiment. Fig. 8 is a plan view corresponding to Fig. 4. In Fig. 8, as in Fig. 4, the outer peripheral edge of the exposed portion 421 of the emitter electrode 42 is indicated by a dashed line, and the active region 45 including the IGBT region 45i and the diode region 45d is indicated by a solid line.

[0093] As shown in FIG. 8 , the IGBT region 45i extends across the exposed portion 421 in the X direction. The diode region 45d also extends across the exposed portion 421 in the X direction. The non-overlapping region 452 includes a region 452b beside the exposed portion that is aligned with the exposed portion 421 in the X direction. Of the non-overlapping region 452, the region 452a beside the pad is a first region, and the region 452b beside the exposed portion is a second region. The regions 452b beside the exposed portion are provided on both sides of the exposed portion 421 in the X direction. As in the previous embodiment, the non-overlapping region 452 includes the region 452a beside the pad. The non-overlapping region 452 is a region excluding the region 452a beside the pad and further includes a region outside the exposed portion 421 in the Y direction. The other configurations are the same as those described in the previous embodiment.

[0094] <Summary of the third embodiment> In the region 452b beside the exposed portion, the ratio of the IGBT region 45i to the diode region 45d is approximately the same as the ratio in the overlapping region 451. That is, the ratio of the diode region 45d in the region 452a beside the pad is higher than the ratio of the diode region 45d in the region 452b beside the exposed portion. This makes the ratio of the diode region 45d in the entire non-overlapping region 452 higher than the ratio of the diode region 45d in the overlapping region 451. Therefore, the active region 45 can be expanded around the exposed portion 421 to increase the area of ​​the active region 45, while enhancing the effect of expanding the active region.

[0095] The configuration described in this embodiment can be combined with either the configuration described in the first embodiment or the configuration described in the second embodiment.

[0096] (Fourth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In the preceding embodiment, no particular reference was made to a temperature-sensitive diode for detecting the temperature of the semiconductor element 40, but the temperature-sensitive diode may be provided at a predetermined position in a configuration having the lateral pad region 452a. In the preceding embodiment, the pads 44 were provided near the center of the side of the semiconductor substrate 41 in the X direction. Alternatively, the pads 44 may be arranged together at one end in the X direction.

[0097] Fig. 9 shows a semiconductor element 40 in the semiconductor device 20 according to this embodiment. Fig. 9 is a plan view corresponding to Fig. 4. In Fig. 9, as in Fig. 4, the outer peripheral edge of the exposed portion 421 of the emitter electrode 42 is indicated by a dashed line, and the active region 45 including the IGBT region 45i and the diode region 45d is indicated by a solid line.

[0098] 9, the pads 44 are arranged together at one end in the X direction. The pads 44 are arranged unevenly in the X direction. The pad side region 452a is provided at the end opposite the pad 44 arrangement region in the X direction. The active region 45 includes only one pad side region 452a. The active region 45 including the pad side region 452a has a substantially L-shape in plan view.

[0099] The semiconductor element 40 has a temperature-sensitive diode 58. The temperature-sensitive diode 58 is configured to include, for example, impurity-doped polysilicon and an aluminum-based wiring material, and is provided on one surface 41a of the semiconductor substrate 41. The temperature-sensitive diode 58 is not provided in a position overlapping with the active region 45 in a plan view, but is provided between the pad 44 and a region 452a beside the pad in the X direction. The anode of the temperature-sensitive diode 58 is electrically connected to the anode pad 44, and the cathode is electrically connected to the cathode pad 44. The other configurations are the same as those described in the preceding embodiment.

[0100] <Summary of the Fourth Embodiment> As described above, in this embodiment, the temperature sensing diode 58 is provided outside the active region 45. This increases the area of ​​the exposed portion 421, thereby improving heat dissipation. In other words, even if the ratio of the IGBT region 45i in the overlap region 451 directly below the exposed portion 421 is increased, generated heat can still be efficiently dissipated.

[0101] The pad side region 452a is a region outside the exposed portion 421, and is less susceptible to heat dissipation through the exposed portion 421 than the overlap region 451. In this embodiment, the temperature sensing diode 58 is provided between the pad 44 and the pad side region 452a. That is, the temperature sensing diode 58 is provided near the pad side region 452a. The temperature near the pad side region 452a is relatively high in the region outside the exposed portion 421. Therefore, the temperature sensing diode 58 can detect the temperature of the semiconductor element 40 even though it is provided outside the active region 45. Furthermore, the wiring connecting the temperature sensing diode 58 and the pad 44 can be shortened.

[0102] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, and the third embodiment.

[0103] As described above, in a configuration in which the pad 44 is biased toward one end in the X direction and the pad side region 452a is provided at the other end, the temperature-sensitive diode 58 may be provided at a position overlapping the active region 45 in plan view, for example, the overlapping region 451. In a configuration in which the temperature-sensitive diode 58 is provided near the center of the side of the pad 44 as described in the previous embodiment, the temperature-sensitive diode 58 may be provided between the pad 44 and the pad side region 452a.

[0104] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0105] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0106] When an element or layer is referred to as being "on," "coupled," "connected," or "coupled," it may be directly on, coupled, connected, or coupled to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0107] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0108] The vehicle drive system 1 is not limited to the above-described configuration. For example, although an example has been shown in which one motor generator 3 is provided, this is not limiting. Multiple motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, this is not limiting. For example, a configuration with multiple inverters may be provided. A configuration with at least one inverter and a converter may be provided. Or only a converter may be provided.

[0109] The configuration of the semiconductor device 20 is not limited to the above example. The semiconductor device 20 may include at least the semiconductor element 40.

[0110] Although an example has been shown in which the back surfaces 60b, 70b of the heat sinks 60, 70 are exposed from the sealing resin body 30, this is not limiting. At least one of the back surfaces 60b, 70b may be covered by the sealing resin body 30. At least one of the back surfaces 60b, 70b may be covered by an insulating member (not shown) that is separate from the sealing resin body 30. Although an example has been shown in which the semiconductor device 20 includes the sealing resin body 30, this is not limiting. A configuration without the sealing resin body 30 may also be used.

[0111] In the example shown, a heat sink 60 and a conductive spacer 80 are provided as the first wiring member connected to the emitter electrode 42 (first main electrode), and a heat sink 70 is provided as the second wiring member connected to the collector electrode 43 (second main electrode). However, the wiring members are not limited to the above example. For example, instead of the heat sinks 60 and 70, a substrate having metal bodies disposed on both sides of an insulating base material may be used. An example of the substrate is a DBC substrate. DBC is an abbreviation for Direct Bonded Copper. Instead of the conductive spacer 80, a protrusion may be provided on the heat sink 60. Similarly, a protrusion may be provided on the metal body on the inner surface of the substrate.

[0112] Although the semiconductor device 20 has been shown as having a double-sided heat dissipation structure, it is not limited to this. A single-sided heat dissipation structure is also possible. For example, the collector electrode 43 is connected to a heat sink or a metal body of the substrate, and the emitter electrode 42 is connected to a lead.

[0113] Although an example has been shown in which the semiconductor device 20 includes only one semiconductor element 40 that configures one arm, this is not limiting. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure one arm. In other words, multiple semiconductor elements 40 may be connected in parallel to configure one arm. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure upper and lower arm circuits 9 for one phase. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure upper and lower arm circuits 9 for multiple phases.

[0114] Although the opening shape of the opening 561, i.e., the planar shape of the exposed portion 421, is generally rectangular in the example shown, the present invention is not limited to this. The active area 45 includes an overlapping area 451 and a non-overlapping area 452 regardless of the shape of the exposed portion 421.

[0115] There is no particular limitation on the number of pads 44. The semiconductor element 40 only needs to have at least one pad 44. The pads 44 only need to include at least a pad for the gate electrode 55.

[0116] The arrangement of the trenches 53 (gate electrodes 55) is not limited to the above-described stripe pattern. The arrangement of the IGBT regions 45i and the diode regions 45d is not limited to the above-described alternate arrangement in the Y direction.

[0117] The active region 45 may be divided into multiple regions. For example, in the example shown in FIG. 10, the active region 45 is divided into two in the X direction. A gate runner (gate wiring) (not shown) is disposed between the active regions 45. The gate runner electrically connects the gate electrode 55 and the gate electrode pad 44. FIG. 10 is a plan view corresponding to FIG. 4.

[0118] Although an example has been shown in which the non-overlapping region 452 includes the region 452a beside the pad, this is not limiting. A configuration that does not include the region 452a beside the pad is also possible. The proportion of the diode region 45d may be increased in a position other than the region 452a beside the pad. The technical ideas that can be understood from the embodiments and modifications described so far will be described below as supplementary notes. <Appendix 1> a semiconductor substrate (41) having one surface (41a) and a back surface (41b) opposite to the one surface in the thickness direction; a protective film (56) disposed on the one surface of the semiconductor substrate and having an opening (561); a first main electrode (42) disposed on the one surface of the semiconductor substrate and having an exposed portion (421) exposed through the opening to provide a junction region; a second main electrode (43) disposed on the back surface of the semiconductor substrate; Equipped with the semiconductor substrate has an active region (45) which is a region for forming an IGBT having a diode connected in antiparallel as a vertical element for causing a current to flow between the first main electrode and the second main electrode; the opening is provided so as to overlap the active area in a plan view in the plate thickness direction, the active region includes an overlapping region (451) that overlaps with the exposed portion of the first main electrode in the plan view, and a non-overlapping region (452) that does not overlap with the exposed portion, a ratio of the diode formation area in the non-overlapping area to a ratio of the diode formation area in the overlapping area. <Appendix 2> a pad (44) which is an electrode for a signal and is arranged on the one surface of the semiconductor substrate; The semiconductor device of Appendix 1, wherein the non-overlapping region includes a region (452a) next to the pad that is aligned with the pad in a first direction in which the pad and the overlapping region are aligned and in a second direction perpendicular to the thickness direction. <Appendix 3> 3. The semiconductor device according to claim 2, wherein only the diode is formed in the region beside the pad. <Appendix 4> the semiconductor substrate has a peripheral region (46) surrounding the active region in the plan view, The diode and the IGBT are formed in the region beside the pad, 3. The semiconductor device according to claim 2, wherein the IGBT is provided at an end on the outer peripheral region side in a region beside the pad. <Appendix 5> the non-overlapping region includes a region beside the pad and a region beside the exposed portion (452b) aligned with the exposed portion; 5. The semiconductor device according to claim 2, wherein a ratio of the area where the diode is formed to the area beside the pad is higher than a ratio of the area where the diode is formed to the area beside the exposed portion. <Appendix 6> 5. The semiconductor device according to any one of claims 2 to 4, further comprising a temperature-sensitive diode (58) provided between the pad and a region beside the pad. <Appendix 7> a first wiring member (60, 80) electrically connected to the first main electrode; 2. The semiconductor device according to claim 1, further comprising: a second wiring member (70) electrically connected to the second main electrode.

Claims

1. a semiconductor substrate (41) having one surface (41a) and a back surface (41b) opposite to the one surface in the thickness direction; a protective film (56) disposed on the one surface of the semiconductor substrate and having an opening (561); a first main electrode (42) disposed on the one surface of the semiconductor substrate and having an exposed portion (421) exposed through the opening to provide a junction region; a second main electrode (43) disposed on the back surface of the semiconductor substrate; Equipped with the semiconductor substrate has an active region (45) which is a region for forming an IGBT having a diode connected in antiparallel as a vertical element for passing a current between the first main electrode and the second main electrode; the opening is provided so as to overlap the active area in a plan view in the plate thickness direction, the active region includes an overlapping region (451) that overlaps with the exposed portion of the first main electrode in the plan view, and a non-overlapping region (452) that does not overlap with the exposed portion, a ratio of a formation area of ​​the diode in the non-overlapping region is made higher than a ratio of a formation area of ​​the diode in the overlapping region; The semiconductor substrate has a plurality of gate electrodes (55) of a trench structure formed to a predetermined depth from the one surface, The semiconductor device, wherein the gate electrode is formed in the overlapping region and the non-overlapping region in the active region.

2. The semiconductor device described in claim 1, wherein the semiconductor substrate has a drift region (50) of a first conductivity type and a collector region (47) of a second conductivity type formed on the surface layer of the back surface side in the formation region of the IGBT, on the back surface side of the drift region, and electrically connected to the second main electrode.

3. The semiconductor device described in claim 1, wherein the semiconductor substrate has a drift region (50) of a first conductivity type and an emitter region (52) of a first conductivity type formed on the surface layer of the one side of the IGBT formation region, on the one side of the drift region, and electrically connected to the first main electrode.

4. The semiconductor device described in claim 1, wherein the semiconductor substrate has a drift region (50) of a first conductivity type, a collector region (47) of a second conductivity type formed on the back surface side of the drift region in the IGBT formation region and in the surface layer of the back surface side, and electrically connected to the second main electrode, and an emitter region (52) of a first conductivity type formed on the one surface side of the drift region in the IGBT formation region and in the surface layer of the one surface side, and electrically connected to the first main electrode.

5. The semiconductor device described in claim 1, wherein the semiconductor substrate has a drift region (50) of a first conductivity type, a cathode region (48) of a first conductivity type formed on the back surface side of the drift region in the diode formation region and on the surface layer of the back surface side, and electrically connected to the second main electrode, and a base region (51) of a second conductivity type formed on the one surface side of the drift region in the diode formation region and on the surface layer of the one surface side, and electrically connected to the first main electrode.

6. The semiconductor device described in claim 1, wherein the semiconductor substrate has a drift region (50) of a first conductivity type and a buffer region (49) of the first conductivity type that is located on the back surface side of the drift region and has a higher impurity concentration than the drift region.

7. A semiconductor element (40) having the semiconductor substrate, the first main electrode, the second main electrode, and a pad (44) disposed on the one surface of the semiconductor substrate and provided at a position different from that of the second main electrode; a wiring member (70) electrically connected to the second main electrode; a signal terminal (93) electrically connected to the pad; Equipped with the semiconductor element and the signal terminal are aligned in a predetermined direction, 2. The semiconductor device according to claim 1, wherein said non-overlapping region includes a region (452a) provided on said signal terminal side of said semiconductor element in said predetermined direction.

8. An output terminal (91) electrically connected to a winding (3a) of a corresponding phase of the rotating electric machine (3), 8. The semiconductor device according to claim 7, wherein the output terminal is disposed on an opposite side of the semiconductor element from the signal terminal.

9. A semiconductor element (40) having the semiconductor substrate, the first main electrode, the second main electrode, and a pad (44) disposed on the one surface of the semiconductor substrate and provided at a position different from that of the second main electrode; a wiring member including a first wiring member (60, 80) electrically connected to the first main electrode and a second wiring member (70) electrically connected to the second main electrode; a signal terminal (93) electrically connected to the pad; Equipped with the semiconductor element and the signal terminal are aligned in a predetermined direction, 2. The semiconductor device according to claim 1, wherein said non-overlapping region includes a region (452a) provided on said signal terminal side of said semiconductor element in said predetermined direction.

10. An output terminal (91) electrically connected to a corresponding phase winding (3a) of a rotating electric machine (3), 10. The semiconductor device according to claim 9, wherein the output terminal is disposed on an opposite side of the semiconductor element from the signal terminal.

11. A semiconductor device as described in claim 7 or claim 9, wherein the wiring member is a substrate having metal bodies arranged on both sides of an insulating base material.

12. 9. The semiconductor device according to claim 7, wherein the semiconductor elements comprise a plurality of elements constituting upper and lower arm circuits (9) for one phase or for multiple phases.

Images