Semiconductor Devices

Abstract

In the present invention, an epitaxial layer (2) is formed on a substrate (1). A field effect transistor (3) is formed on the epitaxial layer (2). A drain pad (8) is formed on the epitaxial layer (2). The drain pad (8) is connected to a drain electrode (5) of the field effect transistor (3). A reverse surface electrode (13) is formed on the reverse surface of the substrate (1) and is connected to a source electrode (6) of the field effect transistor (3). A wire (16) is bonded to the drain pad (8). A hollow (17) is formed in the substrate (1) directly below the drain pad (8). The hollow (17) is not formed directly below the bonded portion of the wire (16).

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In a field-effect transistor, a source pad and a drain pad are formed on the front side of a substrate, and a backside electrode is formed on the backside of the substrate. The backside electrode and the source pad are connected by a via hole. The drain pad of a field-effect transistor used in a high-power amplifier is formed large so that multiple wires can be inserted to allow a large current to flow. A large parasitic capacitance is formed between this drain pad on the front side and the n-type semiconductor substrate or backside electrode on the backside. To reduce this parasitic capacitance, a technology has been proposed in which the substrate is etched from the backside to form a cavity below the drain pad (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2002-270822 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the past, a cavity was formed directly below the wire bonding portion, making it difficult to ensure the strength to withstand the impact of the wire bond.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to obtain a semiconductor device that can withstand the impact of wire bonds while reducing parasitic capacitance. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a substrate, an epitaxial layer formed on the substrate, a field effect transistor formed on the epitaxial layer, a drain pad formed on the epitaxial layer and connected to a drain electrode of the field effect transistor, a backside electrode formed on a backside of the substrate and connected to a source electrode of the field effect transistor, and a wire bonded to the drain pad, wherein a cavity is formed in the substrate directly below the drain pad, and the cavity is not formed directly below the bonding portion of the wire. [Effects of the Invention]

[0007] In the present disclosure, a cavity is formed in the substrate directly below the drain pad. This reduces the parasitic capacitance between the drain pad and the backside electrode without reducing the area of ​​the drain pad. Furthermore, the cavity is not formed directly below the wire bonding portion. This allows the substrate to withstand the impact of wire bonding. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line I-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line III-IV in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line V-VI in FIG. [Figure 5] FIG. 1 is a cross-sectional view showing a semiconductor device according to a first comparative example. [Figure 6] FIG. 10 is a cross-sectional view showing a semiconductor device according to Comparative Example 2. [Figure 7] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line I-II in FIG. 7. [Figure 9] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. [Figure 10]FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] Embodiment 1 Fig. 1 is a plan view showing a semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view taken along line I-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-IV in Fig. 1. Fig. 4 is a cross-sectional view taken along line V-VI in Fig. 1.

[0011] An epitaxial layer 2 is formed on a substrate 1. The substrate 1 is a semi-insulating substrate made of GaAs, SiC, InP, sapphire, GaN, diamond, or the like. The material of the epitaxial layer 2 is, for example, GaAs, GaN, or InP. However, the substrate 1 may also be an n-type semiconductor substrate made of n-type silicon, in which case the epitaxial layer 2 is also made of silicon.

[0012] A field effect transistor 3 is formed on the epitaxial layer 2. The field effect transistor 3 has a plurality of gate electrodes 4, a plurality of drain electrodes 5, and a plurality of source electrodes 6. Each gate electrode 4 is disposed between an adjacent drain electrode 5 and source electrode 6.

[0013] A gate pad 7, a drain pad 8, and a source pad 9 are formed on the epitaxial layer 2. The gate pad 7 is connected to a plurality of gate electrodes 4 via gate wiring 10. The drain pad 8 is connected to a plurality of drain electrodes 5 via air bridge wiring 11. The source pad 9 is connected to a plurality of source electrodes 6 via air bridge wiring 12 that straddles the gate wiring 10.

[0014] A back electrode 13 is formed on the back surface of the substrate 1. The back electrode 13 is connected to the source pad 9 through a via hole 14 that penetrates the substrate 1 and the epitaxial layer 2. A wire 15 is bonded to the gate pad 7. A plurality of wires 16 are bonded to the drain pad 8. The bonding size of the wires 15 and 16 is 50 to 60 μm.

[0015] The substrate 1 is etched from the back surface side, and multiple cavities 17 are formed in the substrate 1 and epitaxial layer 2 directly below the drain pad 8. The width of each cavity 17 is about 80 μm. The multiple cavities 17 are not formed directly below the bonding portions of the multiple wires 16.

[0016] Next, the effects of this embodiment will be described in comparison with Comparative Examples 1 and 2. FIG. 5 is a cross-sectional view showing a semiconductor device according to Comparative Example 1. In Comparative Example 1, a cavity 17 is formed directly below the bonding portion of the wire 16. This makes it difficult to ensure strength sufficient to withstand the impact of the wire bond. FIG. 6 is a cross-sectional view showing a semiconductor device according to Comparative Example 2. In Comparative Example 2, no cavity 17 is provided in the substrate 1, and a portion of the back surface electrode 13 is removed directly below the drain pad 8. However, because the semiconductor device is mounted on the GND 18 of the package, parasitic capacitance occurs between the drain pad 8 and the GND 18 of the package. Therefore, even if a portion of the back surface electrode 13 is removed, the parasitic capacitance remains almost unchanged.

[0017] In contrast to this, in this embodiment, a cavity 17 is formed in the substrate 1 directly below the drain pad 8. The inside of the cavity 17 is air or vacuum, and the dielectric constant of the inside of the cavity 17 is smaller than that of the substrate 1. Therefore, the parasitic capacitance between the drain pad 8 and the back surface electrode 13 can be reduced without reducing the area of ​​the drain pad 8.

[0018] Furthermore, the cavity 17 is not formed directly below the bonding portion of the wire 16. Therefore, the thin drain pad 8 above the cavity 17 is not mechanically or physically destroyed and can withstand the impact of the wire bond. Even if a portion of the wire material that has been crushed and spread by the wire bond is present above the cavity 17, it is sufficient as long as the drain pad 8 above the cavity 17 is not destroyed.

[0019] Furthermore, the etching reaches the back surface of the drain pad 8, and a cavity 17 is formed not only in the substrate 1 but also in the epitaxial layer 2. This further reduces the parasitic capacitance. However, even if the thin epitaxial layer 2 remains, the parasitic capacitance can be sufficiently reduced.

[0020] Embodiment 2 FIG. 7 is a plan view showing a semiconductor device according to a second embodiment. FIG. 8 is a cross-sectional view taken along line I-II in FIG. 7. The drain pad 8 is separated into multiple pads by slits 19. A wire 16 straddles the slit 19 and is bonded to the drain pad 8. The inside of the slit 19 is air or a vacuum. This ensures substrate strength against wire bonding while reducing parasitic capacitance between the drain pad 8 and the back electrode 13. Other configurations and effects are the same as those of the first embodiment.

[0021] Embodiment 3 9 is a plan view showing a semiconductor device according to a third embodiment. In the second embodiment, the drain pad 8 is separated into multiple pads, and therefore the drain pad 8 must be probed with multiple probes when evaluating electrical characteristics during wafer processing or when testing the wafer. In contrast, in the present embodiment, the multiple pads of the drain pad 8 separated by slits 19 are connected to each other by thin wiring 20. This allows the drain pad 8 to be probed with only one probe, making testing easier. Other configurations and effects are the same as those of the second embodiment.

[0022] Embodiment 4 10 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. This figure corresponds to the cross-sectional view taken along line I-II in FIG. 7. Each drain pad 8 separated by slits 19 has an underlying portion 8a and a protruding portion 8b formed on the outer periphery of the underlying portion 8a. The underlying portion 8a and the protruding portion 8b are formed together by Au plating.

[0023] The wire 16 is bonded to the protrusions 8b arranged on both sides of the slit 19. The height of the slit 19 is about 10 μm in the second embodiment and about 15 μm in the present embodiment. Therefore, the height of the slit 19 can be increased. The parasitic capacitance is mainly the result of connecting the capacitor in the slit 19 part and the capacitor in the substrate 1 part in series. Because the dielectric constant of the slit 19 is about 1 / 10 of the dielectric constant of the substrate 1, a large capacitance reduction effect can be expected simply by making the slit 19 slightly taller. Furthermore, because only the outer periphery of the pad is thickened, the amount of Au material can be reduced compared to when the entire pad is thickened.

[0024] Furthermore, plating time can be reduced by forming the protrusions 8b simultaneously when forming the air bridge wiring 11 connecting the drain electrode 5 and the drain pad 8. In this case, the material and thickness of the protrusions 8b in the portion not crushed by wire bonding are the same as those of the air bridge wiring 11. Other configurations and effects are the same as those of the second or third embodiment.

[0025] Embodiment 5 FIG. 11 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. This figure corresponds to the cross-sectional view taken along line I-II in FIG. 7. A back surface electrode 13 is formed on the entire back surface of the substrate 1. For example, a wafer-shaped metal plate is used as the back surface electrode 13, and is pressure-bonded to the back surface of the wafer-shaped substrate 1 using Au particles. The back surface electrode 13 closes the cavity 17, thereby preventing conductive resin or solder from entering the cavity 17 during mounting. Other configurations and effects are the same as those of the first to fourth embodiments. [Explanation of symbols]

[0026] 1 substrate, 2 epitaxial layer, 3 field effect transistor, 5 drain electrode, 6 source electrode, 8 drain pad, 8a base portion, 8b protrusion portion, 11 air bridge wiring, 13 back electrode, 16 wire, 17 cavity, 19 slit, 20 wiring

Claims

1. A substrate; an epitaxial layer formed on the substrate; a field effect transistor formed on the epitaxial layer; a drain pad formed on the epitaxial layer and connected to a drain electrode of the field effect transistor; a backside electrode formed on a backside of the substrate and connected to a source electrode of the field effect transistor; a wire bonded to the drain pad; a cavity is formed in the substrate directly below the drain pad; The semiconductor device is characterized in that the cavity is not formed directly below the bonding portion of the wire.

2. 2. The semiconductor device according to claim 1, wherein the cavity is formed in the substrate and the epitaxial layer.

3. the drain pad is separated into a plurality of pads by slits; 3. The semiconductor device according to claim 1, wherein the wire is bonded to the drain pad across the slit.

4. 4. The semiconductor device according to claim 3, wherein the plurality of pads are connected to each other by wiring.

5. Each of the plurality of pads has a base portion and a protrusion portion formed on an outer periphery of the base portion, 4. The semiconductor device according to claim 3, wherein the wire is bonded to the protrusions disposed on both sides of the slit.

6. further comprising an air bridge wiring connecting the drain electrode and the drain pad; 6. The semiconductor device according to claim 5, wherein the protrusions in the portions not crushed by wire bonding and the air bridge wiring are made of the same material and have the same thickness.

7. 3. The semiconductor device according to claim 1, wherein the back electrode closes the cavity.

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