Semiconductor Devices

Abstract

To provide a semiconductor device 100 capable of suppressing poor connection between a bonding wire 41 and a substrate 10.SOLUTION: A semiconductor device 100 includes a substrate 10, a semiconductor chip 20, a connecting material 30, a bonding wire 41, and a partition 61. The semiconductor chip 20 is arranged on the substrate 10 with the connecting material 30 interposed therebetween. The bonding wire 41 has a first end 41a and a second end 41b, and is connected to the semiconductor chip 20 at the first end 41a and to the substrate 10 at the second end 41b. The partition 61 is arranged on the substrate 10 so as to be positioned between the semiconductor chip 20 and the second end 41b in plan view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] For example, Japanese Patent Laid-Open No. 2020-167366 (Patent Document 1) describes a semiconductor light-emitting device. The semiconductor light-emitting device described in Patent Document 1 has a substrate, a semiconductor light-emitting element, and a wire. The substrate has a base material and a conductive portion. The conductive portion is disposed on a main surface of the base material. The semiconductor light-emitting element is disposed on the conductive portion. The wire has a first end and a second end, and is connected to the semiconductor light-emitting element at the first end and to the conductive portion at the second end. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-167366 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor light-emitting element is connected to the conductive portion, for example, by a die bonding paste interposed between the semiconductor light-emitting element and the conductive portion. When connecting the semiconductor light-emitting element and the conductive portion, the die bonding paste may bleed. If the bleed of the die bonding paste reaches the portion of the conductive portion connected to the second end of the wire, a connection failure may occur between the second end of the wire and the conductive portion.

[0005] The present disclosure has been made in view of the above-described problems of the conventional technology. More specifically, the present disclosure provides a semiconductor device that can suppress connection failures between bonding wires and a substrate. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a substrate, a semiconductor chip, a connecting material, a bonding wire, and a partition wall. The semiconductor chip is disposed on the substrate with the connecting material interposed therebetween. The bonding wire has a first end and a second end, and is connected to the semiconductor chip at the first end and to the substrate at the second end. The partition wall is disposed on the substrate so as to be located between the semiconductor chip and the second end in a plan view. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, connection failures between the bonding wires and the substrate can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device 100. As shown in FIG. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a process diagram showing a method for manufacturing the semiconductor device 100. [Figure 4] FIG. 4 is a cross-sectional view illustrating the preparation step S1. [Figure 5] FIG. 5 is a cross-sectional view illustrating the reflector forming step S2. [Figure 6] FIG. 6 is a cross-sectional view illustrating the die bonding step S3. [Figure 7] FIG. 7 is a cross-sectional view illustrating the wire bonding step S4. [Figure 8] FIG. 8 is a cross-sectional view illustrating the resin sealing step S5. [Figure 9] FIG. 9 is a cross-sectional view of the semiconductor device 200. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device 100 according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0010] (Configuration of the semiconductor device according to the embodiment) The configuration of the semiconductor device according to the embodiment will be described below. The semiconductor device according to the embodiment is referred to as a semiconductor device 100.

[0011] FIG. 1 is a plan view of a semiconductor device 100. Note that the sealing resin 70 is not shown in FIG. 1. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. As shown in FIGS. 1 and 2, the semiconductor device 100 includes a substrate 10, a semiconductor chip 20, a connecting material 30, bonding wires 41 and 42, a reflector 50, partition walls 61 and 62, and the sealing resin 70.

[0012] The substrate 10 has, for example, a base material 11, a conductor pattern 12, a conductor pattern 13, a conductor pattern 14, a conductor pattern 15, and a resist 16. The longitudinal direction of the substrate 10 is defined as a first direction DR1. A direction perpendicular to the first direction DR1 in a plan view is defined as a second direction DR2. A direction perpendicular to the first direction DR1 and the second direction DR2 is defined as a third direction DR3.

[0013] The base material 11 has, for example, a rectangular shape in a plan view. The base material 11 is made of an electrically insulating material. The base material 11 is made of, for example, glass epoxy. The base material 11 has a first main surface 11a and a second main surface 11b. The first main surface 11a and the second main surface 11b are end surfaces of the base material 11 in the third direction DR3. The second main surface 11b is the surface opposite to the first main surface 11a.

[0014] The conductor patterns 12 and 13 are arranged on the first main surface 11a. The conductor patterns 12 and 13 are, for example, rectangular in plan view. The conductor patterns 12 and 13 are arranged at intervals along the first direction DR1. The conductor patterns 12 and 13 are made of a conductor. The conductor patterns 12 and 13 are made of, for example, copper (Cu).

[0015] The conductor patterns 14 and 15 are arranged on the second main surface 11b. The conductor patterns 14 and 15 are, for example, rectangular in plan view. The conductor patterns 14 and 15 are arranged at intervals along the first direction DR1. The conductor patterns 14 and 15 are made of a conductor. The conductor patterns 14 and 15 are made of, for example, copper. The conductor patterns 14 and 15 are arranged, for example, at both ends of the second main surface 11b in the first direction DR1.

[0016] Although not shown, a first through hole and a second through hole are formed in the substrate 11. The first through hole is arranged so as to overlap the conductor patterns 12 and 14 in a plan view. The second through hole is arranged so as to overlap the conductor patterns 13 and 15 in a plan view. A conductor (not shown) embedded in the first through hole electrically connects the conductor patterns 12 and 14. A conductor (not shown) embedded in the second through hole electrically connects the conductor patterns 13 and 15.

[0017] The resist 16 is disposed on the second main surface 11b. The resist 16 is disposed between the conductive pattern 14 and the conductive pattern 15 in the first direction DR1. The resist 16 is formed of, for example, a solder resist.

[0018] The semiconductor chip 20 is, for example, a light-emitting element. The semiconductor chip 20 is, for example, an LED (Light Emitting Diode). The semiconductor chip 20 has a bottom surface 20a and a top surface 20b. The semiconductor chip 20 is disposed on the substrate 10. More specifically, the semiconductor chip 20 is disposed on the conductive pattern 12. The bottom surface 20a and the top surface 20b are end surfaces of the semiconductor chip 20 in the third direction DR3. The bottom surface 20a faces the substrate 10 (the conductive pattern 12). The top surface 20b is the surface opposite to the bottom surface 20a. Bonding pads 21 and 22 are formed on the top surface 20b.

[0019] The connection material 30 is disposed between the semiconductor chip 20 (bottom surface 20a) and the substrate 10 (conductor pattern 12). This connects the semiconductor chip 20 to the substrate 10. The connection material 30 is formed of, for example, die bonding paste. The die bonding paste contains a resin material. The die bonding paste is, for example, non-conductive.

[0020] The bonding wire 41 has a first end 41a and a second end 41b. The second end 41b is the end opposite to the first end 41a. The bonding wire 41 is connected to the bonding pad 21 at the first end 41a. The bonding wire 41 is connected to the conductive pattern 12 at the second end 41b. The bonding wire 41 is made of, for example, gold (Au).

[0021] The bonding wire 42 has a first end 42a and a second end 42b. The second end 42b is the end opposite to the first end 42a. The bonding wire 42 is connected to the bonding pad 22 at the first end 42a. The bonding wire 42 is connected to the conductive pattern 13 at the second end 42b. The bonding wire 42 is made of, for example, gold.

[0022] The reflector 50 is disposed on the substrate 10. For example, the reflector 50 is disposed so as to surround the conductive patterns 12 and 13 in a plan view. More specifically, the reflector 50 is disposed along the outer periphery of the first main surface 11a in a plan view. The reflector 50 rises from the substrate 10 in the third direction DR3. The reflector 50 is formed of a material that reflects light generated in the semiconductor chip 20. The reflector 50 is formed of a resin material mixed with titanium oxide (TiO2), for example. The inner wall surface of the reflector 50 may be inclined so that the distance from the outer wall surface of the reflector 50 increases as the distance approaches the bottom end of the reflector 50. Note that the light from the semiconductor chip 20 reflected by the reflector 50 is emitted from above the semiconductor device 100.

[0023] The partition walls 61 and 62 are arranged on the substrate 10. More specifically, the partition walls 61 are arranged on the conductor pattern 12, and the partition walls 62 are arranged on a portion of the first main surface 11a between the conductor patterns 12 and 13. The partition walls 61 and 62 extend along the second direction DR2 in a plan view. The upper ends of the partition walls 61 and 62 protrude from the surfaces of the conductor patterns 12 (13). However, preferably, the upper ends of the partition walls 61 and 62 are closer to the substrate 10 than the upper surface 20b. The partition walls 61 and 62 are made of, for example, a resin material. Preferably, the partition walls 61 and 62 are made of the same material as the reflector 50.

[0024] The sealing resin 70 is disposed in the space defined by the reflector 50 and the substrate 10 so as to cover the semiconductor chip 20, the connecting material 30, the bonding wires 41 and 42, and the partition walls 61 and 62. The sealing resin 70 is formed of, for example, a transparent resin.

[0025] (Method of manufacturing a semiconductor device according to an embodiment) A method for manufacturing the semiconductor device 100 will be described below.

[0026] Fig. 3 is a process diagram showing a manufacturing method of the semiconductor device 100. As shown in Fig. 3, the manufacturing method of the semiconductor device 100 includes a preparation step S1, a reflector formation step S2, a die bonding step S3, a wire bonding step S4, a resin sealing step S5, and a singulation step S6.

[0027] 4 is a cross-sectional view illustrating the preparation step S1. As shown in FIG. 4, in the preparation step S1, a substrate 80 is prepared. The substrate 80 includes a plurality of substrates 10.

[0028] 5 is a cross-sectional view illustrating the reflector forming step S2. As shown in FIG. 5, in the reflector forming step S2, the reflector 50 is formed. Also, in the reflector forming step S2, the partitions 61 and 62 are formed. The reflector 50, the partitions 61, and the partitions 62 are formed by, for example, transfer molding using a mold 90. The portions of the mold 90 where the reflector 50, the partitions 61, and the partitions 62 are formed serve as flow paths for the resin material that forms the reflector 50, the partitions 61, and the partitions 62. Therefore, the resin material that forms the reflector 50, the partitions 61, and the partitions 62 is injected between the mold 90 and the substrate 80 and then cured, thereby forming the reflector 50, the partitions 61, and the partitions 62.

[0029] 6 is a cross-sectional view illustrating the die bonding step S3. As shown in FIG. 6, in the die bonding step S3, the semiconductor chip 20 is connected to the conductive pattern 12 using a connecting material 30. In the die bonding step S3, first, the uncured connecting material 30 is applied onto the conductive pattern 12. Second, the semiconductor chip 20 is mounted on the uncured connecting material 30. Third, the connecting material 30 is heated and cured, thereby connecting the semiconductor chip 20 to the conductive pattern 12 via the connecting material 30.

[0030] 7 is a cross-sectional view illustrating the wire bonding step S4. In the wire bonding step S4, as shown in FIG. 7, wire bonding is performed to connect the bonding pad 21 and the conductor pattern 12 with a bonding wire 41, and also connect the bonding pad 22 and the conductor pattern 13 with a bonding wire 42.

[0031] 8 is a cross-sectional view illustrating the resin sealing step S5. In the resin sealing step S5, uncured sealing resin 70 is potted using a dispenser into the space defined by the substrate 10 and the reflector 50 and then heated and cured. In the singulation step S6, the substrate 80 is cut to separate into a plurality of semiconductor devices 100. As a result, the semiconductor device 100 having the structure shown in FIGS. 1 and 2 is formed.

[0032] (Effects of the semiconductor device according to the embodiment) The effects of the semiconductor device 100 will be described below in comparison with a semiconductor device according to a comparative example.

[0033] 9 is a cross-sectional view of the semiconductor device 200. As shown in FIG. 9, the semiconductor device 200 has a substrate 10, a semiconductor chip 20, a connecting material 30, bonding wires 41 and 42, a reflector 50, and a sealing resin 70. In this respect, the configuration of the semiconductor device 200 is common to the configuration of the semiconductor device 100. The semiconductor device 200 does not have a partition wall 61 and a partition wall 62. In this respect, the configuration of the semiconductor device 200 is different from the configuration of the semiconductor device 100.

[0034] In the semiconductor device 200, when the semiconductor chip 20 is connected to the conductive pattern 12 by the connecting material 30, the connecting material 30 may ooze. This oozing may also spread onto the conductive pattern 13, but it is particularly likely to spread onto the conductive pattern 12. If the oozing of the connecting material 30 spreads to the portion of the conductive pattern 12 connected by the second end 41b or the portion of the conductive pattern 13 connected by the second end 42b, this may cause a poor connection between the bonding wire 41 and the conductive pattern 12 or a poor connection between the bonding wire 42 and the conductive pattern 13.

[0035] In the semiconductor device 100, too, when the semiconductor chip 20 is connected to the conductive pattern 12 by the connecting material 30, the connecting material 30 may ooze. However, in the semiconductor device 100, a partition wall 61 is disposed between the second end 41b and the semiconductor chip 20, and a partition wall 62 is disposed between the second end 42b and the semiconductor chip 20. Therefore, the oozing of the connecting material 30 is stopped by the partition walls 61 and 62, and the spreading of the connecting material 30 to the portion of the conductive pattern 12 connected by the second end 41b and the portion of the conductive pattern 13 connected by the second end 42b is suppressed. Therefore, the semiconductor device 100 can suppress poor connection between the bonding wire 41 and the conductive pattern 12 and poor connection between the bonding wire 42 and the conductive pattern 13.

[0036] When the partitions 61 and 62 are formed from the same material as the reflector 50, the partitions 61 and 62 and the reflector 50 can be formed simultaneously, thereby preventing an increase in the manufacturing cost of the semiconductor device 100 while also preventing poor connections between the bonding wire 41 and the conductor pattern 12 and between the bonding wire 42 and the conductor pattern 13.

[0037] If the substrate 10 does not have the resist 16, the substrate 10 may bend when the mold 90 is brought into contact with the substrate 10. If the substrate 10 bends, a gap is formed between the mold 90 and the substrate 10, and the resin material constituting the reflector 50, the partition walls 61, and the partition walls 62 flows into the gap. On the other hand, if the substrate 10 has the resist 16, the substrate 10 is supported at three points by the conductive pattern 14, the conductive pattern 15, and the resist 16 when the mold 90 and the substrate 10 come into contact with each other, and the substrate 10 is less likely to bend.

[0038] If the positions of the upper ends of the partition walls 61 and 62 in the third direction DR3 are too high, the partition walls 61 and 62 may interfere with filling the sealing resin 70 into the space defined by the substrate 10 and the reflector 50. If the upper ends of the partition walls 61 and 62 are closer to the substrate 10 than the upper surface 20b, it is possible to prevent the partition walls 61 and 62 from interfering with filling the sealing resin 70.

[0039] (Variation) Modifications of the semiconductor device 100 will be described below.

[0040] FIG. 10 is a cross-sectional view of a semiconductor device 100 according to a modified example. As shown in FIG. 10, the substrate 10 may be a lead frame 17. The lead frame 17 has a first portion 17a and a second portion 17b. The semiconductor chip 20 is disposed on the first portion 17a with a connecting material 30 interposed therebetween. The bonding wire 41 is connected to the bonding pad 21 at a first end 41a and to the second portion 17b at a second end 41b. The partition wall 63 is disposed between the semiconductor chip 20 and the second end 41b in a plan view. The partition wall 63 is preferably formed of the same material as the reflector 50. In this case, the partition wall 63 suppresses the permeation of the connecting material 30, thereby preventing poor connection between the bonding wire 41 and the substrate 10 (lead frame 17).

[0041] Although the embodiments of the present disclosure have been described above, the above-described embodiments can be modified in various ways. Furthermore, the scope of the present invention is not limited to the above-described embodiments. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0042] 10 substrate, 11 base material, 11a first main surface, 11b second main surface, 12, 13, 14, 15 conductor pattern, 16 resist, 17 lead frame, 17a first portion, 17b second portion, 20 semiconductor chip, 20a bottom surface, 20b top surface, 21, 22 bonding pad, 30 connecting material, 41, 42 bonding wire, 41a, 42a first end, 41b, 42b second end, 50 reflector, 61, 62, 63 partition wall, 70 sealing resin, 80 substrate, 90 mold, 100, 200 semiconductor device, DR1 first direction, DR2 second direction, DR3 third direction, S1 preparation process, S2 reflector formation process, S3 die bonding process, S4 wire bonding process, S5 resin sealing process, S6 singulation process.

Claims

1. A substrate; A semiconductor chip; A connecting material; A bonding wire; a bulkhead; the semiconductor chip is disposed on the substrate with the connecting material interposed therebetween, the bonding wire has a first end and a second end, and is connected to the semiconductor chip at the first end and to the substrate at the second end; The partition wall is disposed on the substrate so as to be located between the semiconductor chip and the second end in a plan view. the substrate includes a base material having a first main surface and a second main surface, and a first conductor pattern and a second conductor pattern disposed on the first main surface; the first conductor pattern and the second conductor pattern are arranged at intervals along the longitudinal direction of the substrate in a plan view, A semiconductor device, wherein the partition wall is arranged on the first main surface, positioned between the first conductor pattern and the second conductor pattern so as not to cover the surface of the first conductor pattern and the surface of the second conductor pattern.

2. further comprising a reflector disposed on the substrate; the semiconductor chip is a light-emitting element, 2. The semiconductor device according to claim 1, wherein said partition wall is made of the same material as said reflector.

3. the semiconductor chip is disposed on the first conductor pattern with the connecting material interposed therebetween, The semiconductor device according to claim 1 , wherein the second end of the bonding wire is connected to the first conductor pattern.

4. the substrate further includes a third conductor pattern and a fourth conductor pattern disposed on the second principal surface, and a resist disposed on the second principal surface; 4. The semiconductor device according to claim 1, wherein the resist is disposed between the third conductor pattern and the fourth conductor pattern in the longitudinal direction.

5. 5. The semiconductor device according to claim 1, wherein the upper end of the partition wall is closer to the substrate than the upper surface of the semiconductor chip.

6. 6. The semiconductor device according to claim 1, wherein the connecting material is a die bonding paste containing a resin material.

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