Semiconductor Devices

Abstract

To provide a technique of reducing the influence of avalanche current on an upper electrode in a semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate having an element region having a plurality of trenches provided on an upper surface; an upper electrode covering the upper surface of the semiconductor substrate in the element region; and a protection film. The element region includes: a source region; a body region; a drift region; a bottom region disposed below the trench, extending in a first direction, and arranged with a space in a second direction orthogonal to the first direction; and a connection region extending from a position in contact with the upper electrode to the bottom region, extending in a third direction intersecting with the first direction, and arranged with a space in a fourth direction orthogonal to the third direction. An average value of the space in the fourth direction of the connection region in a covered part where an upper surface of the upper electrode is covered with the protection film is lower than an average value of the space in the fourth direction of the connection region in an exposed part where the upper surface of the upper electrode is exposed from the protection film.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate having an element region on its upper surface with multiple trenches, a gate insulating film covering the inner surface of each trench, a gate electrode disposed in each trench, and an upper electrode covering the upper surface of the semiconductor substrate within the element region. In this semiconductor device, the semiconductor substrate has an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, multiple p-type bottom regions (i.e., electric field blocking layers), and multiple p-type connection regions (i.e., coupling layers). The source region is in contact with the upper electrode and the gate insulating film. The body region is in contact with the gate insulating film below the source region. The drift region is in contact with the gate insulating film below the body region. Each bottom region is disposed below the trench with a gap therebetween, extends parallel to the trench, and is arranged at a gap in a direction perpendicular to the trench. Each connection region extends from a position in contact with the top electrode to the bottom region, extends in a direction perpendicular to the trench, and is arranged at intervals in a direction parallel to the trench.

[0003] When the semiconductor device of Patent Document 1 is turned off, a depletion layer extends from the bottom region into the drift region. The depletion layer extending from the bottom region into the drift region suppresses electric field concentration around the gate insulating film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-16775 Summary of the Invention [Problem to be solved by the invention]

[0005] When a high reverse bias voltage is applied to a pn junction (e.g., a pn junction between a bottom region and a drift region) inside the semiconductor substrate while the semiconductor device of Patent Document 1 is off, an avalanche current flows. The avalanche current flows from the drift region to the top electrode via the bottom region and the connection region. At this time, the avalanche current causes each connection region to generate heat. Because each connection region is in contact with the top electrode, the heat generated in the connection region is transferred to the top electrode. As a result, the upper electrode becomes hot above each connection region, and the temperature of the upper electrode decreases the further away from each connection region. In this way, a temperature gradient occurs in the top electrode.

[0006] In this type of semiconductor device, the upper electrode may be covered with a protective film at the periphery of the element region. In the portion of the upper electrode covered by the protective film, heat is less likely to diffuse and the temperature is less likely to be uniform. Therefore, when an avalanche current flows, a temperature gradient is more likely to occur in the portion of the upper electrode covered by the protective film than in the portion not covered by the protective film. Therefore, repeated avalanche current flow can adversely affect the portion of the upper electrode covered by the protective film. This specification proposes a technology for reducing the effect of avalanche current on the upper electrode in a semiconductor device. [Means for solving the problem]

[0007] The semiconductor device (10, 100, 200, 300) disclosed in this specification comprises a semiconductor substrate (12) having an element region (14) in an upper surface (12a) of which a plurality of trenches (22) are provided, a gate insulating film (24) covering the inner surface of each of the trenches, a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film, an upper electrode (70) covering the upper surface of the semiconductor substrate within the element region, and a protective film (40). The element region is in contact with the upper electrode and includes an n-type source region (30) in contact with the gate insulating film in each of the trenches, a p-type body region (32) in contact with the gate insulating film in each of the trenches below the source region, and an n-type drift region (34) in contact with the gate insulating film in each of the trenches below the body region and separated from the source region by the body region, each of which is disposed below the trench at a distance from the bottom surface of the trench and is surrounded by the drift region, The semiconductor device includes a plurality of p-type bottom regions (36, 136) extending in a first direction when the semiconductor substrate is viewed from above and arranged at intervals in a second direction perpendicular to the first direction when the semiconductor substrate is viewed from above, and a plurality of p-type connection regions (38, 138, 238, 338) each extending from a position in contact with the upper electrode to the bottom region, each extending in a third direction intersecting the first direction when the semiconductor substrate is viewed from above, and arranged at intervals in a fourth direction perpendicular to the third direction when the semiconductor substrate is viewed from above. A covering portion (60) in which an upper surface of the upper electrode is covered with the protective film is provided on the outer periphery (14b) of the element region, and an exposed portion (62) in which the upper surface of the upper electrode is exposed from the protective film is provided in the central portion (14a) of the element region. The average value of the spacing in the fourth direction of the connection regions in the covering portion is smaller than the average value of the spacing in the fourth direction of the connection regions in the exposed portion.

[0008] In the semiconductor device described above, the semiconductor substrate has a covered portion in which the upper surface of the upper electrode is covered with a protective film in the periphery of the element region, and an exposed portion in which the upper surface of the upper electrode is exposed from the protective film in the center of the element region. The average spacing between the connection regions in the covered portion is smaller than the average spacing between the connection regions in the center. That is, the connection regions are densely arranged in the covered portion compared to the exposed portion. Therefore, in the covered portion, the avalanche current is dispersed among the densely arranged multiple connection regions, and the density of the avalanche current flowing in each connection region is reduced. As a result, in the covered portion, the degree of heat generation in each connection region is reduced, and the temperature gradient occurring in the upper electrode is also reduced. In this way, the semiconductor device described above can reduce the impact of the avalanche current on the upper electrode. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a partially enlarged plan view of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] 3 is a cross-sectional view taken along line VV in FIG. 2. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 2. [Figure 7] FIG. 10 is a partially enlarged plan view of a semiconductor device according to a second embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 11 is a partially enlarged plan view of a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is a partially enlarged plan view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the semiconductor device disclosed in this specification as an example, the semiconductor substrate may be made of SiC.

[0011] In one example semiconductor device disclosed herein, the upper surface of the upper electrode in the exposed portion of the element region may be connected to the conductor plate via a solder layer. In the exposed portion, heat transferred from the connection region to the upper electrode is suitably diffused via the solder layer. Therefore, in the above configuration, even if the average value of the spacing in the fourth direction between the connection regions in the exposed portion is relatively large, the temperature of the upper electrode is likely to be uniform.

[0012] Example 1 FIG. 1 shows a semiconductor device 10 according to a first embodiment. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and includes a semiconductor substrate 12, electrodes, an insulating film, and the like. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the material of the semiconductor substrate 12 is not particularly limited and may be other semiconductor materials such as silicon (Si) or gallium nitride (GaN). As shown in FIG. 1, the semiconductor substrate 12 includes an element region 14 and a peripheral region 16. The element region 14 is a region in which a plurality of trenches 22 (described later) are formed. A trench-type MOSFET structure is formed in the element region 14. The element region 14 is located on the central side of the semiconductor substrate 12. The peripheral region 16 is located around the element region 14. A peripheral breakdown voltage structure is formed in the peripheral region 16. A plurality of small signal pads 18 are provided on the semiconductor substrate 12 corresponding to the peripheral region 16. The small signal pad 18 is, for example, a gate pad for inputting a gate signal, a temperature sense pad for outputting a temperature sense signal, a current sense pad for outputting a current sense signal, etc. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the semiconductor substrate 12 and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0013] FIG. 2 is an enlarged view of region A indicated by a dashed line in FIG. 1 as viewed from above. As shown in FIG. 2, a plurality of trenches 22 are provided in the upper surface 12a of the semiconductor substrate 12 within the element region 14. Each trench 22 extends longitudinally along the y direction. Each trench 22 extends parallel to one another. Each trench 22 is arranged at intervals in the x direction. Note that FIG. 2 does not illustrate the configuration (insulating film, electrodes, etc.) on the upper surface 12a of the semiconductor substrate 12. As shown in FIGS. 3, 4, and 6, a gate insulating film 24 and a gate electrode 26 are disposed within each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is disposed within each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

[0014] The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28. An upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 contacts the upper surface 12a of the semiconductor substrate 12 in the element region 14 in a portion where the interlayer insulating film 28 is not provided. The interlayer insulating film 28 is also provided on the upper surface 12a of the semiconductor substrate 12 in an area spanning from the outer periphery of the peripheral region 16 to part of the element region 14. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 contacts substantially the entire lower surface 12b of the semiconductor substrate 12.

[0015] 1 and 2, the element region 14 has a central portion 14a and a peripheral portion 14b. The central portion 14a is located on the central side of the element region 14. The peripheral portion 14b is located around the central portion 14a. The peripheral portion 14b is located in the range between the central portion 14a of the element region 14 and the peripheral region 16.

[0016] As shown in FIGS. 3 to 6 , a protective film 40 is provided in a range spanning from the outer periphery 14b of the element region 14 to the peripheral region 16. The protective film 40 covers an area spanning from the upper surface 70a of the upper electrode 70 in the outer periphery 14b of the element region 14 to the upper surface of the interlayer insulating film 28 in the peripheral region 16. The protective film 40 is made of, for example, polyimide. In the central portion 14a of the element region 14, the upper electrode 70 is exposed from the protective film 40, and a solder layer 42 is provided on the upper surface 70a. A conductor plate 44 is provided on top of the solder layer 42. The conductor plate 44 is made of, for example, copper. In the central portion 14a, the upper surface 70a of the upper electrode 70 and the conductor plate 44 are joined by the solder layer 42. In the following, within the element region 14, the area where the upper surface 70a of the upper electrode 70 is covered with the protective film 40 is referred to as the covered portion 60, and the area where the upper surface 70a of the upper electrode 70 is exposed from the protective film is referred to as the exposed portion 62. In this embodiment, as shown in Figures 3 to 6, when the semiconductor substrate 12 is viewed from above, the boundary between the central portion 14a and the outer peripheral portion 14b and the boundary between the exposed portion 62 and the covered portion 60 approximately coincide with each other.

[0017] The element region 14 includes a plurality of source regions 30, a plurality of body regions 32, a drift region 34, a drain region 35, a plurality of bottom regions 36, and a plurality of connection regions 38.

[0018] Each source region 30 is an n-type region. As shown in FIGS. 2 and 3 to 5, each source region 30 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 on the side surface of the trench 22.

[0019] Each body region 32 is a p-type region. As shown in Figures 3 to 5, each body region 32 contacts the source region 30 from below. Each body region 32 contacts the gate insulating film 24 below the source region 30.

[0020] The drift region 34 is an n-type region. As shown in FIGS. 3 to 5, the drift region 34 is disposed below the body region 32. The drift region 34 contacts the body region 32 from below. The drift region 34 contacts the gate insulating film 24 below the body region 32. The drift region 34 is separated from each source region 30 by the body region 32. The drift region 34 is disposed across from the element region 14 into the peripheral region 16.

[0021] The drain region 35 is an n-type region. The drain region 35 is disposed below the drift region 34. The drain region 35 contacts the drift region 34 from below. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is exposed at the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72 at the lower surface 12b of the semiconductor substrate 12. The drain region 35 is disposed across from the element region 14 into the peripheral region 16.

[0022] Each bottom region 36 is a p-type region. As shown in FIGS. 3, 4, and 6, each bottom region 36 extends in a direction parallel to the trench 22 (the y direction). The bottom regions 36 are arranged at intervals in the x direction. Each bottom region 36 is disposed below the trench 22 at an interval from the bottom surface of the trench 22. Each bottom region 36 is surrounded by the drift region 34.

[0023] Each connection region 38 is a p-type region. As shown in FIGS. 4 to 6, each connection region 38 extends in a direction (x direction) perpendicular to the bottom region 36. The connection regions 38 are arranged at intervals in the y direction. As shown in FIG. 2, each connection region 38 is disposed in a range between two source regions 30 when the semiconductor substrate 12 is viewed from above. That is, when the semiconductor substrate 12 is viewed from above, the source regions 30 and the connection regions 38 are disposed alternately along the y direction.

[0024] As shown in FIGS. 4 and 5 , each connection region 38 has a high-concentration region 38a and a low-concentration region 38b. The high-concentration region 38a is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. The high-concentration region 38a is in ohmic contact with the upper electrode 70. The high-concentration region 38a contacts the gate insulating film on the side surface of the trench 22. As shown in FIG. 5 , the lower end of the high-concentration region 38a is located above the lower end of the source region 30. The low-concentration region 38b has a p-type impurity concentration lower than that of the high-concentration region 38a and higher than that of the body region 32. The low-concentration region 38b is provided below the high-concentration region 38a. The low-concentration region 38b extends from the lower end of the high-concentration region 38a to the bottom region 36. That is, each connection region 38 extends from a position exposed on the upper surface 12a of the semiconductor substrate 12 to the bottom region 36. Therefore, each bottom region 36 is connected to the upper electrode 70 via each connection region 38. Therefore, the potential of each bottom region 36 is approximately equal to the potential of the upper electrode 70.

[0025] 2 and 5, the distance d1 between adjacent connection regions 38 in the y direction in the covered portion 60 is narrower than the distance d2 between adjacent connection regions 38 in the y direction in the exposed portion 62. In other words, the connection regions 38 are arranged more densely in the covered portion 60 than in the exposed portion 62.

[0026] 2 to 6, a plurality of p-type guard rings 50 are provided in the peripheral region 16. Each guard ring 50 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. Although only a portion is shown in FIG. 2, each guard ring extends around the element region 14.

[0027] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 72 than to the upper electrode 70. When a voltage equal to or greater than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to a level below the gate threshold, the channel disappears and the semiconductor device 10 is turned off.

[0028] When the semiconductor device 10 is off, the potential of the bottom electrode 72 is much higher than the potential of the top electrode 70. In this state, the drift region 34 has a potential close to that of the bottom electrode 72. As described above, the bottom region 36 has a potential substantially equal to that of the top electrode 70. Therefore, a high reverse voltage is applied to the p-n junction at the interface between the drift region 34 and the bottom region 36. As a result, a depletion layer spreads over a wide area from each bottom region 36 into the drift region 34. This suppresses electric field concentration near the bottom end of the trench 22, ensuring the breakdown voltage of the semiconductor device 10. In addition, a reverse voltage is also applied to the p-n junction at the interface between the connection region 38 and the drift region 34. As a result, a depletion layer spreads from the connection region 38 into the drift region 34.

[0029] When the semiconductor device 10 is turned off, a depletion layer extending from the body region 32, the connection region 38, and the bottom region 36 depletes substantially the entire drift region 34. When a high voltage is applied to the bottom electrode 72 while the semiconductor device 10 is turned off, avalanche breakdown occurs within the semiconductor substrate 12, causing an avalanche current to flow from the drift region 34 to the top electrode 70 via the bottom region 36 and the connection region 38. When the avalanche current flows, each connection region 38 generates heat. Because the multiple connection regions 38 are spaced apart, a temperature gradient occurs within the semiconductor substrate 12 according to the spacing between them. That is, a temperature gradient occurs in which the connection regions 38 are hotter and the temperatures further away from the connection regions 38 are colder. Furthermore, because each connection region 38 is in contact with the top electrode 70, heat generated in the connection regions 38 is transferred to the top electrode 70, creating a temperature gradient in the top electrode 70 similar to that within the semiconductor substrate 12. That is, a temperature gradient occurs in which the upper part of the connection region 38 is hot and the position away from the upper part of the connection region 38 is cold.

[0030] In the semiconductor device 10 of this embodiment, the semiconductor substrate 12 has a covering portion 60 in which the upper electrode 70 is covered with a protective film 40 in the outer peripheral portion 14b of the element region 14. The presence of the protective film 40 makes it difficult for heat from the upper electrode 70 to diffuse in the covering portion 60, making it difficult to uniformize the temperature of the upper electrode 70. Therefore, repeated avalanche current may adversely affect the portion of the upper electrode 70 covered by the protective film 40. However, in this embodiment, the spacing d1 between the connection regions 38 in the covering portion 60 is narrower than the spacing d2 between the connection regions 38 in the exposed portion 62. That is, the connection regions 38 are densely arranged in the covering portion 60 compared to the exposed portion 62. Therefore, in the covering portion 60, the avalanche current flows dispersedly among the densely arranged multiple connection regions 38, reducing the density of the avalanche current flowing through each connection region 38. As a result, in the covering portion 60, the degree of heat generation in each connection region 38 is reduced, and the temperature gradient inside the semiconductor substrate 12 is reduced. Therefore, in the covering portion 60, the temperature gradient occurring in the upper electrode 70 is also reduced. In this way, in the semiconductor device 10 of this embodiment, by densely arranging the connection regions 38 located directly below the range of the upper electrode 70 where heat diffusion is difficult, the degree of the temperature gradient occurring in the upper electrode 70 is reduced, and the effect of the avalanche current on the upper electrode 70 can be reduced.

[0031] Furthermore, in this embodiment, in the exposed portion 62 of the element region 14, the upper surface 70a of the upper electrode 70 is connected to the conductor plate 44 via the solder layer 42. Because the solder layer 42 has high thermal conductivity, in the exposed portion 62, heat transferred from the connection region 38 to the upper electrode 70 is suitably diffused via the solder layer 42. Therefore, in the exposed portion 62, even if the spacing d2 of the connection region 38 is relatively wide, the temperature of the upper electrode 70 is likely to be uniform. By making the spacing d2 of the connection region 38 relatively wide, the source region 30 can be arranged over a wide area. This allows a wide active area to be secured, which functions as a current path.

[0032] Furthermore, in this embodiment, the direction in which the bottom region 36 extends (y direction) and the direction in which the connection region 38 extends (x direction) intersect, so that the bottom region 36 and the connection region 38 can be more reliably connected compared to, for example, a configuration in which the bottom region 36 and the connection region 38 extend parallel to each other.

[0033] In the above-described embodiment, the spacing d1 between adjacent connection regions 38 in the covered portion 60 is substantially equal at any position, and the spacing d2 between adjacent connection regions 38 in the exposed portion 62 is substantially equal at any position. However, the spacing d1 between the connection regions 38 in the covered portion 60 may vary depending on the position, and the same applies to the spacing d2 between the connection regions 38 in the exposed portion 62. In this case, it is sufficient that the average value of the spacing d1 is smaller than the average value of the spacing d2. In other words, when the semiconductor substrate 12 is viewed from above, it is sufficient that the density of the connection regions 38 in the covered portion 60 is greater than the density of the connection regions 38 in the exposed portion 62. The same applies to the other embodiments described below.

[0034] The y direction is an example of a "first direction" and a "fourth direction," and the x direction is an example of a "second direction" and a "third direction."

[0035] Example 2 In the semiconductor device 100 of Example 2, the configurations of the bottom region 36 and the connection region 38 are different from those of Example 1. In Example 2, as shown in FIGS. 7 and 9, each connection region 138 extends in a direction parallel to the trench 22 (y direction). As shown in FIGS. 7 and 8, each connection region 138 is arranged at intervals in the x direction. Also, as shown in FIGS. 7 and 8, each bottom region 136 extends in a direction perpendicular to the connection region 138 (x direction). As shown in FIGS. 7 and 9, the bottom regions 136 are arranged at intervals in the y direction. Note that FIG. 7 also shows the bottom region 136 located inside the semiconductor substrate 12.

[0036] 7 and 8, the distance d3 between adjacent connection regions 138 in the x-direction in the covered portion 60 is narrower than the distance d4 between adjacent connection regions 138 in the x-direction in the exposed portion 62. In other words, the connection regions 138 are arranged more densely in the covered portion 60 than in the exposed portion 62.

[0037] In the semiconductor device 100 of Example 2, the spacing d3 of the connection regions 138 in the covered portion 60 is narrower than the spacing d4 of the connection regions 138 in the exposed portion 62. Therefore, also in the semiconductor device 100 of Example 2, the temperature gradient of the upper electrode 70 caused by the avalanche current is reduced in the covered portion 60, and the effect of the avalanche current on the upper electrode 70 can be reduced.

[0038] The x direction is an example of a "first direction" and a "fourth direction," and the y direction is an example of a "second direction" and a "third direction."

[0039] Example 3 The semiconductor device 200 of Example 3 differs from Example 2 in the configuration of the connection regions 138. In Example 3, as shown in FIG. 10 , each connection region 238 is intermittently arranged in a direction parallel to the trenches 22 (y direction) in the range between two adjacent trenches 22. The connection regions 238 are arranged at intervals in the x direction. In other words, in Example 3, when the semiconductor substrate 12 is viewed from above, the connection regions 238 are arranged in a staggered pattern. The interval d5 between adjacent connection regions 238 in the x direction in the covered portion 60 is narrower than the interval d6 between adjacent connection regions 238 in the x direction in the exposed portion 62. In other words, the connection regions 238 are arranged more densely in the covered portion 60 than in the exposed portion 62. Therefore, in the semiconductor device 200 of Example 3 as well, the temperature gradient in the upper electrode 70 caused by the avalanche current is smaller in the covered portion 60, and the effect of the avalanche current on the upper electrode 70 can be reduced. Furthermore, in Example 3, when the semiconductor substrate 12 is viewed from above, the source region 30 can be disposed over a wider area within the element region 14 than in Example 2, thereby ensuring a wider active region. Note that the peripheral region 16 is not shown in Figure 10. The same applies to Figure 11.

[0040] The x direction is an example of a "first direction" and a "fourth direction," and the y direction is an example of a "second direction" and a "third direction."

[0041] Example 4 The semiconductor device 300 of Example 4 differs from Example 2 in the configuration of the connection regions 138. In Example 4, as shown in FIG. 11 , each connection region 338 extends in a direction inclined with respect to both the extension direction of the trench 22 (y direction) and the extension direction of the bottom region 136 (x direction). The connection regions 338 are arranged at intervals in a direction perpendicular to the extension direction (hereinafter referred to as the spacing direction). The spacing d7 between adjacent connection regions 338 in the spacing direction in the covered portion 60 is narrower than the spacing d8 between adjacent connection regions 338 in the spacing direction in the exposed portion 62. In other words, the connection regions 338 are arranged more densely in the covered portion 60 than in the exposed portion 62. Therefore, in the semiconductor device 300 of Example 4, the temperature gradient in the upper electrode 70 caused by the avalanche current is smaller in the covered portion 60, and the effect of the avalanche current on the upper electrode 70 can be reduced.

[0042] The x direction is an example of a “first direction,” and the y direction is an example of a “second direction.” A direction that is inclined with respect to both the y direction and the x direction is an example of a “third direction,” and a direction that is perpendicular to the inclined direction is an example of a “fourth direction.”

[0043] In the first embodiment described above, each connection region 38 may extend to the lower end of the bottom region 36. In other words, a p-type region that connects the bottom regions 36 adjacent to each other in the x direction may be further provided below each connection region 38. This configuration allows the bottom region 36 and the connection region 38 to be more reliably connected. The same applies to the other embodiments.

[0044] Furthermore, in each of the above-described embodiments, when the semiconductor substrate 12 is viewed from above, the boundary between the central portion 14a and the outer peripheral portion 14b and the boundary between the exposed portion 62 and the covered portion 60 are substantially aligned. However, for example, the boundary between the exposed portion 62 and the covered portion 60 may be located closer to the outer periphery of the semiconductor substrate 12 than the boundary between the central portion 14a and the outer peripheral portion 14b. In other words, there may be a region in part of the central portion 14a where the spacing between the connection regions is narrow.

[0045] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0046] 10: semiconductor device, 12: semiconductor substrate, 12a: upper surface, 12b: lower surface, 14: element region, 14a: central portion, 14b: peripheral portion, 16: peripheral region, 22: trench, 24: gate insulating film, 26: gate electrode, 28: interlayer insulating film, 30: source region, 32: body region, 34: drift region, 35: drain region, 36: bottom region, 38: connection region, 40: protective film, 42: solder layer, 44: conductor plate, 60: covering portion, 62: exposed portion, 70: upper electrode, 72: lower electrode

Claims

1. A semiconductor device (10, 100, 200, 300), a semiconductor substrate (12) having an element region (14) on an upper surface (12a) of which a plurality of trenches (22) are provided; a gate insulating film (24) covering the inner surface of each trench; a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; an upper electrode (70) covering the upper surface of the semiconductor substrate in the device region; A protective film (40); It is equipped with The element region is an n-type source region (30) in contact with the upper electrode and in contact with the gate insulating film in each of the trenches; a p-type body region (32) below the source region and in contact with the gate insulating film in each of the trenches; an n-type drift region (34) in contact with the gate insulating film in each trench below the body region and separated from the source region by the body region; a plurality of p-type bottom regions (36, 136) each disposed below the trench at a distance from the bottom surface of the trench, each surrounded by the drift region, each extending in a first direction when the semiconductor substrate is viewed from above, and arranged at intervals in a second direction perpendicular to the first direction when the semiconductor substrate is viewed from above; a plurality of p-type connection regions (38, 138, 238, 338) each extending from a position in contact with the upper electrode to the bottom region, each extending in a third direction intersecting the first direction when the semiconductor substrate is viewed from above, and arranged at intervals in a fourth direction perpendicular to the third direction when the semiconductor substrate is viewed from above; It is equipped with a covering portion (60) in which the upper surface of the upper electrode is covered with the protective film is provided in the peripheral portion (14b) of the element region, and an exposed portion (62) in which the upper surface of the upper electrode is exposed from the protective film is provided in the central portion (14a) of the element region; an average value of the intervals in the fourth direction between the connection regions in the covered portion is smaller than an average value of the intervals in the fourth direction between the connection regions in the exposed portion; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of SiC.

3. 3. The semiconductor device according to claim 1, wherein the upper surface of the upper electrode in the exposed portion of the element region is connected to a conductor plate (44) via a solder layer (42).

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