Semiconductor device and power conversion device

Abstract

This semiconductor device comprises an insulating film covering an electrode and a base surface of a semiconductor substrate. The insulating film has a first upper surface and a protrusion protruding from the first upper surface, respectively corresponding to the base surface of the semiconductor substrate and at least a portion of the electrode protruding from the base surface. The distance between a connecting portion connecting the base surface of the semiconductor substrate and the first upper surface and the surface of the protrusion of the insulating film is equal to or more than the distance between the base surface of the substrate and a second upper surface of the electrode.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Silicon carbide (SiC) has superior voltage resistance, low resistance, and heat resistance compared to silicon (Si). Power semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) made of SiC have been proposed for use in semiconductor devices with high voltage resistance, low loss, and in high-temperature environments.

[0003] For these SiC semiconductor devices, for example, technologies have been proposed to miniaturize the semiconductor device by increasing the current density of the semiconductor device, or to reduce the number of semiconductor devices by using parasitic diodes (e.g., Patent Documents 1 and 2). These technologies reduce the manufacturing costs of SiC semiconductor devices, and it is expected that they will be used in various components such as inverter components in the future. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-75411 [Patent Document 2] Japanese Patent Publication No. 2020-13916 Summary of the Invention [Problem to be solved by the invention]

[0005] In SiC semiconductor devices, smaller, more efficient semiconductor devices have been developed by taking advantage of the high breakdown field of SiC. However, increasing the number of wirings to ensure current capacity increases the number of locations where stress is applied during assembly, and stress increases due to the rise in temperature during operation caused by the increase in current density when current is passed through. As a result, there has been a problem in that electrodes such as the gate electrode of the semiconductor device are damaged, thereby compromising the reliability of the semiconductor device.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can improve the reliability of a semiconductor device. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a semiconductor substrate, an electrode at least a portion of which protrudes upward from a reference surface of the semiconductor substrate, and an insulating film covering the reference surface of the semiconductor substrate and the electrode, wherein the insulating film has a first upper surface and a protruding portion protruding from the first upper surface, which correspond to the reference surface of the semiconductor substrate and the at least a portion of the electrode protruding from the reference surface, respectively, and h1 / h2, which is a ratio of h1, which is a distance between the reference surface of the semiconductor substrate and a connection portion connecting the first upper surface of the insulating film and a surface of the protruding portion, to h2, which is a distance between the reference surface of the semiconductor substrate and a second upper surface of the electrode, is 1 or more and 1.5 or less. The electrode includes a first electrode portion protruding from the reference surface of the semiconductor substrate and a second electrode portion provided in a trench provided in the reference surface of the semiconductor substrate. . [Effects of the Invention]

[0008] According to the present disclosure, the distance between the reference surface of the semiconductor substrate and the connection portion is equal to or greater than the distance between the reference surface of the semiconductor substrate and the second upper surface of the electrode. This configuration can improve the reliability of the semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a top view showing the overall configuration of a SiC semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a first embodiment. [Figure 3] 3 is a flowchart showing a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 12] 1 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a first embodiment. [Figure 13] 1 is a cross-sectional view showing an SEM image of the configuration of the SiC semiconductor device according to the first embodiment. [Figure 14] 1 is a cross-sectional view showing a mounting example of the SiC semiconductor device according to the first embodiment. [Figure 15] FIG. 10 shows test results. [Figure 16] FIG. 10 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a second embodiment. [Figure 17] 10 is a flowchart showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 19]10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 20] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 21] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 22] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 23] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 24] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 25] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 26] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 27] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 28] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 29] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 30] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 31] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 32] 10A to 10C are cross-sectional views showing a manufacturing process of a SiC semiconductor device according to a second embodiment. [Figure 33] FIG. 10 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a second embodiment. [Figure 34] FIG. 10 shows test results. [Figure 35] FIG. 10 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a third embodiment. [Figure 36] FIG. 10 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a third embodiment. [Figure 37] FIG. 10 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a third embodiment. [Figure 38] FIG. 10 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "back" may not necessarily correspond to positions and directions in actual implementation.

[0011] <First Embodiment> Hereinafter, the semiconductor device according to the first embodiment will be described as a SiC semiconductor device including silicon carbide (SiC) which is a wide band gap semiconductor. However, the material of the semiconductor device according to the first embodiment may be ordinary silicon (Si) or a wide band gap semiconductor other than silicon carbide (SiC). Wide band gap semiconductors other than silicon carbide (SiC) include, for example, gallium nitride (GaN) and diamond.

[0012] When semiconductor devices are made of wide bandgap semiconductors, they can be used in high-voltage, low-loss, and high-temperature environments. In particular, SiC has a higher breakdown field than Si, so the breakdown layer (e.g., drift layer) can be made thinner to achieve the same breakdown voltage, and the impurity doping amount in the breakdown layer can be increased, which reduces on-resistance and other characteristics.

[0013] FIG. 1 is a top view showing the overall configuration of the SiC semiconductor device according to the first embodiment, and FIG. 2 is a cross-sectional view showing the configuration of the SiC semiconductor device according to the first embodiment taken along line A-A' in FIG.

[0014] The SiC semiconductor device includes an insulating protective film provided in the peripheral insulating region 10 of FIG. 1, a gate connection portion 11, and the configuration of FIG. 2 that is surrounded by the peripheral insulating region 10 and electrically connected to the gate connection portion 11.

[0015] The configuration of FIG. 2 includes a SiC substrate 1 which is an n-type semiconductor substrate, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, a gate electrode 6 which is an electrode, an interlayer insulating film 7 which is an insulating film, a source electrode 8, and a drain electrode 9.

[0016] The gate connection portion 11 in Fig. 1 is electrically connected to the gate electrode 6 in Fig. 2. The above n-type and p-type may be replaced with p-type and n-type, respectively.

[0017] The SiC semiconductor device according to the first embodiment is a MOSFET with a planar gate structure, and FIG. 2 shows a main cell structure of the SiC semiconductor device. In the overall configuration of an actual SiC semiconductor device, the cell configuration shown in FIG. 1 is repeatedly provided in the planar direction of an SiC substrate 1. The SiC semiconductor device according to the present disclosure may be a MOSFET with a trench gate structure, an IGBT, an RC-IGBT (Reverse Conducting IGBT), an SBD (Schottky Barrier Diode), or a PND (PN junction diode). An example in which the SiC semiconductor device according to the present disclosure is a MOSFET with a trench gate structure will be described in the second embodiment.

[0018] FIG. 3 is a flowchart showing the manufacturing steps of the SiC semiconductor device according to the first embodiment, in the order in which the SiC semiconductor device is manufactured.

[0019] In the semiconductor substrate preparation process of step S1, drift layer 2 containing SiC is formed as an epitaxial film on a first main surface (hereinafter referred to as the front surface) of SiC substrate 1, as shown in FIG.

[0020] 5, in the base region formation process of step S2, a mask (not shown) made of resist or the like is formed on the n-type drift layer 2, and then p-type impurities are selectively ion-implanted to selectively form the base region 3 on the drift layer 2. The p-type impurities are, for example, boron (B) and aluminum (Al).

[0021] 5, in the source region formation process of step S3, a mask (not shown) made of resist or the like is formed on the p-type base region 3, and then n-type impurities are selectively ion-implanted to selectively form the source region 4 above the base region 3. The n-type impurities are, for example, phosphorus (P) and nitrogen (N).

[0022] Then, after the above-described ion implantation is performed to activate the base region 3 and the source region 4, the SiC substrate 1 is heat-treated at a high temperature using a heat treatment device (not shown). As a result, the p-type and n-type ions implanted into the base region 3 and the source region 4 are electrically activated.

[0023] Next, in step S4, a gate insulating film formation process, as shown in FIG. 6, a gate insulating film 5 is formed on the drift layer 2, the base region 3, and the source region 4 by a deposition method such as thermal oxidation or chemical vapor deposition.

[0024] Then, in step S5, a gate electrode forming process, a gate electrode 6 is formed on the gate insulating film 5. The gate electrode 6 may be formed by depositing polycrystalline Si or polysilicon using chemical vapor deposition or the like, or, if higher speed operation of the SiC semiconductor device is desired, a tungsten film or tungsten silicide (WSi x ) film may be deposited.

[0025] 7, the gate insulating film 5 and the gate electrode 6 are patterned using photolithography and dry or wet etching. The gate electrode 6 is patterned so that the pair of base regions 3 and the pair of source regions 4 are located below both ends of the gate electrode 6, and a portion of the drift layer 2 located between the pair of base regions 3 is located below the center of the gate electrode 6.

[0026] Next, in step S6, which is the process of forming an interlayer insulating film, a film made of TEOS (Tetra Ethoxy Silane) or the like is formed as the interlayer insulating film 7 by using, for example, a chemical vapor deposition (CVD) method, as shown in Fig. 8. Next, as shown in Fig. 9, the interlayer insulating film 7 is patterned by using photolithography and dry etching or wet etching techniques to expose a part of the source region 4.

[0027] Next, in step S7, a source electrode formation process, as shown in Fig. 10, a source electrode 8 is formed on the source region 4 and the interlayer insulating film 7. The source electrode 8 is formed by appropriately forming a barrier metal made of titanium or a titanium compound such as titanium nitride (TiN) on a film of, for example, aluminum, an aluminum alloy made of aluminum and silicon, or nickel. Although not shown, the source electrode 8 is then patterned using photolithography and dry or wet etching techniques.

[0028] Thereafter, an insulating protective film is formed in the peripheral insulating region 10 shown in FIG. 1. The insulating protective film is made of, for example, polyimide resin or silicone resin. To achieve high precision in the shape of the insulating protective film, it is preferable to use photolithography technology to form the insulating protective film, and etching technology may also be used in combination with this. However, the method for forming the insulating protective film is not limited to this, and for example, screen printing technology or drawing application technology may also be used.

[0029] Next, in step S8, the thinning process of the SiC substrate, the second main surface (hereinafter referred to as the back surface) of the SiC substrate 1 is thinned by machining using a grinding wheel, thereby thinning the SiC substrate 1 as shown in Figure 11.

[0030] Thereafter, in the drain electrode formation process of step S9, a drain electrode 9 is formed on the back side of the SiC substrate 1. This completes the SiC semiconductor device of FIG. 2. The drain electrode 9 is formed by depositing, for example, a nickel film of about 600 nm using a sputtering method or other suitable method. If the surface of the nickel is oxidized, the wettability between the solder alloy and the nickel deteriorates, resulting in a poor bonding condition during chip bonding. For this reason, a protective film made of a less reactive metal such as gold or silver may be formed on the surface of the nickel, thereby forming the drain electrode 9 as a laminated film of the nickel film and the protective film.

[0031] Fig. 12 is a cross-sectional view showing the gate electrode 6 and its surrounding components in the configuration of Fig. 2, and Fig. 13 is a cross-sectional view showing an image of the configuration of Fig. 12 taken with a scanning electron microscope (SEM). In Fig. 12, the upper surface of SiC substrate 1 is shown as a reference surface 1a.

[0032] The entire gate electrode 6 is disposed above the reference surface 1a of the SiC substrate 1, and the interlayer insulating film 7 covers the reference surface 1a of the SiC substrate 1 and the gate electrode 6. The interlayer insulating film 7 has a first upper surface 7a and a protruding portion 7b protruding from the first upper surface 7a, and the first upper surface 7a and the protruding portion 7b correspond to the reference surface 1a of the SiC substrate 1 and the gate electrode 6 protruding from the reference surface 1a, respectively.

[0033] 12 shows the connection portion 7c that connects the first upper surface 7a of the interlayer insulating film 7 and the surface of the protrusion 7b, and also shows the distance h1 between the reference surface 1a of the SiC substrate 1 and the connection portion 7c. Also shown in FIG. 12 is the distance h2 between the reference surface 1a of the SiC substrate 1 and the second upper surface 6a of the gate electrode 6. In the first embodiment, the distance h1 is equal to or greater than the distance h2. That is, the ratio (h1 / h2) of the distance h1 to the distance h2 is equal to or greater than 1.

[0034] Fig. 14 is a cross-sectional view showing an example of mounting of the SiC semiconductor device according to the first embodiment. In Fig. 14, the SiC semiconductor device of Fig. 2 is shown as SiC semiconductor device 12. As shown in Fig. 14, the back surface of SiC semiconductor device 12 is connected to lead frame 14a via solder 13, and the front surface of SiC semiconductor device 12 is connected to lead frame 14b via wire 15. SiC semiconductor device 12 and its surrounding area are covered with mold resin 16.

[0035] An assembly test of a SiC semiconductor device was carried out for the configuration shown in Fig. 14. In the assembly test, the tool load during wire bonding of wire 15 was set to 1.5 times the standard load in order to evaluate accelerated deterioration caused by repeated stress.

[0036] Fig. 15 is a diagram showing the results of an assembly test. The horizontal axis indicates the ratio (h1 / h2) of the distance h1 to the distance h2, and the vertical axis indicates the yield rate of SiC semiconductor devices determined to be non-defective in the assembly test. As shown in Fig. 15, when the ratio (h1 / h2) is 1 or more, the yield rate of SiC semiconductor devices after assembly can be increased. As described above, in the SiC semiconductor device according to the first embodiment, the distance h1 is equal to or greater than the distance h2, and the ratio (h1 / h2) is 1 or more, so that the yield rate of SiC semiconductor devices can be increased, and ultimately the reliability can be improved.

[0037] In the above description, the electrode covered with the interlayer insulating film 7 is the gate electrode 6, but this is not limiting. For example, the electrode covered with the interlayer insulating film 7 may be a dummy electrode used as a dummy for the gate electrode 6. This also applies to the second embodiment described below.

[0038] <Embodiment 2> The SiC semiconductor device according to the first embodiment is a semiconductor device with a planar gate structure, whereas the SiC semiconductor device according to the second embodiment is a semiconductor device with a trench gate structure. A top view showing the overall configuration of the SiC semiconductor device according to the second embodiment is the same as the top view (FIG. 1) showing the overall configuration of the SiC semiconductor device according to the first embodiment.

[0039] Fig. 16 is a cross-sectional view showing the configuration of the SiC semiconductor device according to the second embodiment taken along line A-A' in Fig. 1. The configuration in Fig. 16 includes a SiC substrate 1 which is an n-type semiconductor substrate, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, a gate electrode 6 which is an electrode, an interlayer insulating film 7 which is an insulating film, a source electrode 8, a drain electrode 9, and a p-type bottom base region 17.

[0040] The gate connection portion 11 in FIG. 1 is electrically connected to the gate electrode 6 in FIG. 16. The above n-type and p-type may be replaced with p-type and n-type, respectively. Although three trench gate structures are shown in FIG. 16, the number of trench gate structures is not limited to this. In the overall configuration of an actual SiC semiconductor device, any number of trench gate structures shown in FIG. 16 are repeatedly provided in the planar direction of the SiC substrate 1.

[0041] FIG. 17 is a flowchart showing the manufacturing steps of the SiC semiconductor device according to the second embodiment, in which the SiC semiconductor device is manufactured in this order.

[0042] In the semiconductor substrate preparation process of step S11, drift layer 2 containing SiC is formed as an epitaxial film on the surface of SiC substrate 1 as shown in FIG.

[0043] 19, in the base region formation process of step S12, a mask (not shown) made of resist or the like is formed on the n-type drift layer 2, and then p-type impurities are selectively ion-implanted to selectively form the base region 3 on the drift layer 2. The p-type impurities are, for example, boron (B) or aluminum (Al).

[0044] 20, in the source region formation process of step S13, a mask (not shown) made of resist or the like is formed on the p-type base region 3, and then n-type impurities are selectively ion-implanted to selectively form the source region 4 above the base region 3. The n-type impurities are, for example, phosphorus (P) and nitrogen (N).

[0045] Then, after the above-described ion implantation is performed to activate the base region 3 and the source region 4, the SiC substrate 1 is heat-treated at a high temperature using a heat treatment device (not shown). As a result, the p-type and n-type ions implanted into the base region 3 and the source region 4 are electrically activated.

[0046] Next, in the trench formation process of step S14, a mask (not shown) made of resist or the like is formed to open a portion of the source region 4, and then the trench shown in FIG. 21 is formed by dry etching using plasma or the like. At this time, if a resist mask that is sufficiently resistant to dry etching cannot be formed, an oxide film made of, for example, TEOS may be formed on the surfaces of the base region 3 and source region 4 in FIG. 20, and dry etching may be performed using the oxide film as a mask. In this case, a deeper trench can be formed.

[0047] 22, in order to reduce the electric field at the bottom of the trench gate structure, p-type impurities such as boron (B) or aluminum (Al) are ion-implanted into the bottom of the trench to form bottom base region 17. Note that if reduction of the electric field is not required, bottom base region 17 does not have to be formed.

[0048] Then, in step S15, a gate insulating film is formed, and drift layer 2 is oxidized using thermal oxidation to remove plasma damage from drift layer 2 that occurred during trench formation. A large amount of oxidation is desirable to remove plasma damage, but a large amount of oxidation reduces the impurity layer formed in drift layer 2. Measurement of leakage current between gate electrode 6 and source electrode 8 in the finished product confirmed that a thermal oxide film of 20 to 80 nm, more preferably 30 to 70 nm, sufficiently removes plasma damage from drift layer 2 without substantially reducing the impurity layer.

[0049] 23, a gate insulating film 5 is formed in the trench by a deposition method such as thermal oxidation or chemical vapor deposition. The thickness of the gate insulating film 5 on the side of the trench is preferably equal to or greater than the thickness of the gate insulating film 5 on the bottom of the trench, and more preferably equal to or greater than 10% of the thickness of the gate insulating film 5 on the bottom of the trench.

[0050] Then, in the gate electrode formation process of step S16, a gate electrode 6 is formed, part of which is provided in the trench, as shown in Fig. 24. The gate electrode 6 may be formed by depositing polycrystalline Si or polysilicon using chemical vapor deposition or the like, or, if higher speed operation of the SiC semiconductor device is desired, a tungsten film or tungsten silicide (WSi x ) film may be deposited.

[0051] 25, the gate electrode 6 is patterned using photolithography and dry or wet etching. It is desirable to use isotropic etching for patterning the gate electrode 6, and for example, dry etching is performed using plasma containing SF, and wet etching is performed using a mixed acid containing hydrofluoric acid and nitric acid.

[0052] In the second embodiment, as shown in FIG. 25 , the gate electrode 6 includes a first electrode portion 6b protruding from a reference plane, which is the upper surface of the SiC substrate, and a second electrode portion 6c provided in a trench provided in the reference plane of the SiC substrate 1. In the planar direction of the SiC substrate 1, the width of the first electrode portion 6b is greater than the width of the second electrode portion 6c, and the gate electrode 6 has a T-shape as a whole. This configuration increases the contact area between the gate electrode 6 and the drift layer 2, the base region 3, and the source region 4. This suppresses the sliding phenomenon of the gate electrode 6, which is the shifting of the gate electrode 6 in its longitudinal direction (the front-to-back direction in FIG. 25 ) when stress occurs during wiring or electrode bonding during assembly. The inventors actually confirmed through an assembly experiment using wiring that the sliding phenomenon is suppressed by using the T-shaped gate electrode 6 described above.

[0053] Thereafter, a thermal oxidation method is used to form an oxide layer (not shown) on the surface of the gate electrode 6. The oxidation temperature at this time is preferably, for example, 850 to 1050°C, and more preferably about 900 to 1000°C.

[0054] Next, in step S17, a process of forming an interlayer insulating film, a film made of TEOS or the like is formed as the interlayer insulating film 7 by using, for example, chemical vapor deposition (CVD), as shown in Fig. 26. Next, as shown in Fig. 27, the interlayer insulating film 7 is patterned by using photolithography and dry etching or wet etching to expose parts of the base region 3 and the source region 4.

[0055] Next, in step S18, a source electrode is formed on the base region 3, the source region 4, and the interlayer insulating film 7, as shown in Fig. 28. The source electrode 8 is formed by appropriately forming a barrier metal made of titanium or a titanium compound such as titanium nitride (TiN) on a film of, for example, aluminum, an aluminum alloy made of aluminum and silicon, or nickel. Although not shown, the source electrode 8 is then patterned using photolithography and dry or wet etching techniques.

[0056] Thereafter, an insulating protective film is formed in the peripheral insulating region 10 shown in FIG. 1. The insulating protective film is made of, for example, polyimide resin or silicone resin. To achieve high precision in the shape of the insulating protective film, it is preferable to use photolithography technology to form the insulating protective film, and etching technology may also be used in combination with this. However, the method for forming the insulating protective film is not limited to this, and for example, screen printing technology or drawing application technology may also be used.

[0057] Next, in step S19, a SiC substrate thinning step, the rear surface of the SiC substrate 1 is machined using a grinding wheel to thin the SiC substrate 1 as shown in FIG.

[0058] Thereafter, in the drain electrode formation process of step S20, a drain electrode 9 is formed on the back side of the SiC substrate 1. This completes the SiC semiconductor device of FIG. 16. The drain electrode 9 is formed by depositing, for example, a nickel film of about 600 nm using a sputtering method or other suitable method. If the surface of the nickel is oxidized, the wettability between the solder alloy and the nickel deteriorates, resulting in a poor bonding condition during chip bonding. For this reason, a protective film made of a less reactive metal such as gold or silver may be formed on the surface of the nickel, thereby forming the drain electrode 9 as a laminated film of the nickel film and the protective film.

[0059] Next, another example will be described in which the steps subsequent to the step S17 of forming the interlayer insulating film are different from the above example. In this example, the interlayer insulating film 7 is a TEOS film or an SOG (Spin-On-Glass) film doped with impurities such as B (boron) or P (phosphorus). When the interlayer insulating film 7 is a TEOS film, a heat treatment is performed at 700 to 900°C after the TEOS film is formed. When the interlayer insulating film 7 is an SOG film, a heat treatment is performed at 400 to 500°C after the SOG film is formed. By performing a heat treatment according to the material of the interlayer insulating film 7 in this way, as shown in FIG. 30, the corners of the protruding portion 7b protruding from the first upper surface 7a of the interlayer insulating film 7, which are circled with dashed lines, can be rounded more than the corners in FIG. 26.

[0060] Thereafter, the interlayer insulating film 7 is patterned. Then, in the source electrode formation process of step S18, the source electrode 8 is formed on the base region 3, the source region 4, and the interlayer insulating film 7, as shown in Fig. 31. Next, the SiC substrate thinning process of step S19 and the drain electrode formation process of step S20 are performed, and the SiC semiconductor device as shown in Fig. 32 is completed.

[0061] In the configuration of FIG. 32 , the corners of the protrusion 7 b are rounded, so that the recess marked with a dashed circle on the upper surface of the source electrode 8 in FIG. 32 is shallower than the recess in FIG. 16 , and the upper surface of the source electrode 8 is flattened. The inventors have confirmed that the configuration of FIG. 32 in which the upper surface of the source electrode 8 is flattened increases the bond strength between the wire and the source electrode 8 after wiring compared to the bond strength in the configuration of FIG. 16 , thereby improving the reliability of the SiC semiconductor device. This is effective in a configuration such as FIG. 14 in which the SiC semiconductor device 12 is subjected to stress from various components such as the wire 15, the mold resin 16, and the lead frames 14 a and 14 b. The fact that the configuration of FIG. 32 in which the corners of the protrusion 7 b are rounded and the upper surface of the source electrode 8 is flattened improves the reliability of the SiC semiconductor device will be described later.

[0062] Fig. 33 is a cross-sectional view showing the gate electrode 6 and its peripheral components in the configuration of Fig. 32. In Fig. 32, the upper surface of the SiC substrate 1 is shown as a reference surface 1a.

[0063] A first electrode portion 6b of the gate electrode 6 protrudes from the reference surface 1a of the SiC substrate 1, and the interlayer insulating film 7 covers the reference surface 1a of the SiC substrate 1 and the gate electrode 6. The interlayer insulating film 7 has a first upper surface 7a and a protruding portion 7b protruding from the first upper surface 7a, and the first upper surface 7a and the protruding portion 7b correspond to the reference surface 1a of the SiC substrate 1 and the gate electrode 6 protruding from the reference surface 1a, respectively.

[0064] FIG. 33 shows the connection portion 7c connecting the first upper surface 7a of the interlayer insulating film 7 and the surface of the protruding portion 7b, and also shows the distance h1 between the reference surface 1a of the SiC substrate 1 and the connection portion 7c. FIG. 33 also shows the distance h2 between the reference surface 1a of the SiC substrate 1 and the second upper surface 6a of the first electrode portion 6b. In the second embodiment, similar to the first embodiment, the distance h1 is equal to or greater than the distance h2, and the ratio of the distance h1 to the distance h2 (h1 / h2) is equal to or greater than 1. This allows the second embodiment, similar to the first embodiment, to increase the yield rate of assembled SiC semiconductor devices, thereby increasing the reliability of the SiC semiconductor devices. This is true for both the configuration of FIG. 16 and the configuration of FIG. 32.

[0065] Fig. 33 shows the angle θ1 formed between the reference plane 1a of the SiC substrate 1 and the second side surface 7e of the lower portion 7d below the first upper surface 7a of the interlayer insulating film 7. The angle θ1 in the example of Fig. 33 is the angle formed between the reference plane 1a of the SiC substrate 1 and the second side surface 7e at a position halfway through the thickness of the lower portion 7d.

[0066] 33 also shows the angle θ2 formed between the reference plane 1a of the SiC substrate 1 and the first side surface 7f of the protruding portion 7b of the interlayer insulating film 7. The first side surface 7f of the protruding portion 7b is, for example, a surface other than the top surface of the protruding portion 7b. The angle θ2 in the example of FIG. 33 is the angle formed between the reference plane 1a of the SiC substrate 1 and the first side surface 7f at a position halfway through the thickness of the protruding portion 7b. In the configurations of FIGS. 32 and 33, the angle θ1 is greater than or equal to the angle θ2, and the ratio of the angle θ1 to the angle θ2 (θ1 / θ2) is greater than or equal to 1.

[0067] FIG. 34 is a graph showing the yield rate of SiC semiconductor devices after a 10,000-cycle switching test to evaluate accelerated degradation in a configuration in which the ratio (h1 / h2) of distance h1 to distance h2 is 1. In this test, the rated current is doubled. The horizontal axis shows the ratio (θ1 / θ2) of angle θ1 to angle θ2, and the vertical axis shows the yield rate of SiC semiconductor devices determined to be good in the switching test. As shown in FIG. 34, it was confirmed that the reliability of SiC semiconductor devices can be improved when the ratio (θ1 / θ2) is 1 or greater.

[0068] A ratio (θ1 / θ2) of 1 or more is essentially the same as rounding the corners of the protrusion 7b. Therefore, when the ratio (θ1 / θ2) of angle θ1 to angle θ2 is 1 or more, the upper surface of the source electrode 8 can be flattened, and the bonding strength between the wire 15 and the source electrode 8 after wiring can be increased. Note that a configuration in which the ratio (θ1 / θ2) is 1 or more can be applied not only to the trench gate structure according to the second embodiment but also to the planar gate structure according to the first embodiment.

[0069] <Third Embodiment> In the present third embodiment, the same components as those in the first or second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The top view showing the overall configuration of the SiC semiconductor device according to the third embodiment is the same as the top view (FIG. 1) showing the overall configuration of the SiC semiconductor device according to the first or second embodiment.

[0070] Fig. 35 is a cross-sectional view showing the configuration of the SiC semiconductor device according to the third embodiment taken along line A-A' in Fig. 1. The configuration in Fig. 35 includes a SiC substrate 1 which is an n-type semiconductor substrate, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, a gate electrode 6 which is an electrode, an interlayer insulating film 7 which is an insulating film, a source electrode 8, and a drain electrode 9.

[0071] The gate connection portion 11 in Fig. 1 is electrically connected to the gate electrode 6 in Fig. 35. The above n-type and p-type may be replaced with p-type and n-type, respectively.

[0072] Fig. 36 is an enlarged view showing the relative positions of the gate insulating film 5, gate electrode 6, and interlayer insulating film 7 in Fig. 35. Fig. 37 is an enlarged view showing the relative positions of the end of the gate electrode 6 and the interlayer insulating film 7 in Fig. 36.

[0073] In the third embodiment, the outer edge of the protruding portion 7b of the interlayer insulating film 7 has a curved portion 7g in a cross-sectional view. A connection portion 7i between the straight portion 7h and the curved portion 7g in a cross-sectional view of the upper surface of the protruding portion 7b is located directly above the end of the gate electrode 6 or directly above and outside the end. In other words, the outer edge of the protruding portion 7b has a radius of curvature R, and when the distance between the center point of the arc of the radius of curvature R and the end of the gate electrode 6 in the left-right direction of the page in FIG. 37 is d, d is equal to or greater than 0.

[0074] The SiC semiconductor device according to the third embodiment is a MOSFET with a planar gate structure, but may be a MOSFET with a trench gate structure, an IGBT, an RC-IGBT (Reverse Conducting - IGBT), an SBD (Schottky Barrier Diode), or a PND (PN junction diode).

[0075] The manufacturing process of the SiC semiconductor device according to the third embodiment is the same as the manufacturing process shown in the flowchart of Fig. 3, and the SiC semiconductor device is manufactured in this order. From step S1 to step S5, the same manufacturing process as in the first embodiment is performed as shown in Figs.

[0076] In the interlayer insulating film formation process of step S6, as shown in FIG. 8, a film made of TEOS (Tetra Ethoxy Silane) or SOG (Spin-On Glass) film is formed as the interlayer insulating film 7 by, for example, chemical vapor deposition (CVD). At this time, the boron concentration contained in the interlayer insulating film 7 is set to 3 wt % or less. As a result, when the interlayer insulating film 7 is a TEOS film, by performing a heat treatment at 700 to 900°C after the formation of the TEOS film, the connection portion 7i between the linear portion 7h and the curved portion 7g of the interlayer insulating film 7 can be positioned immediately above and outside the end of the gate electrode 6. Similarly, when the interlayer insulating film 7 is an SOG film, by performing a heat treatment at 400 to 500°C after the formation of the SOG film, the connection portion 7i between the linear portion 7h and the curved portion 7g of the interlayer insulating film 7 can be positioned immediately above and outside the end of the gate electrode 6.

[0077] Then, as shown in FIG. 9, the interlayer insulating film 7 is patterned using photolithography and dry or wet etching techniques to expose a part of the source region 4.

[0078] Thereafter, from step S7 to step S9, the same manufacturing steps as those in the first embodiment are carried out as shown in FIGS. 10 and 11, and the semiconductor device shown in FIG. 35 is completed.

[0079] According to the above-described configuration, as shown in FIG. 15, in an assembly test of the SiC semiconductor device with the configuration of FIG. 14, the ratio (h1 / h2) was 1 or more, i.e., the interlayer insulating film 7 covered the side surfaces of the gate electrode 6. This can reduce the lateral force applied to the gate electrode 6 during wiring, thereby increasing the yield rate of the assembled SiC semiconductor device. In addition, in the third embodiment, the connection portion 7i between the linear portion 7h and the curved portion 7g in a cross-sectional view of the upper surface of the protruding portion 7b of the interlayer insulating film 7 is located directly above the end of the gate electrode 6 or directly above the outer side of the end. This can reduce the vertical force applied to the gate electrode 6 during wiring, thereby increasing the yield rate of the assembled SiC semiconductor device and thereby increasing reliability.

[0080] <Fourth Embodiment> In the fourth embodiment, the SiC semiconductor device according to any one of the first to third embodiments is applied to a power conversion device. The power conversion device according to the fourth embodiment is not limited to a specific power conversion device, but hereinafter, a case where the power conversion device according to the fourth embodiment is applied to a three-phase inverter will be described.

[0081] 38 is a block diagram schematically showing the configuration of a power conversion system to which a power conversion device 200 according to the fourth embodiment is applied. The power conversion system includes a power supply 100, a power conversion device 200, and a load 300.

[0082] Power supply 100 is a DC power supply and supplies DC power to power conversion device 200. Power supply 100 can be configured with various power sources, for example, it may be configured with a DC system, a solar cell, a storage battery, or it may be configured with a rectifier circuit or an AC / DC converter connected to an AC system. Power supply 100 may also be configured with a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0083] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts DC power supplied from the power source 100 into AC power and supplies it to the load 300. The power conversion device 200 includes a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts input DC power into AC power and outputs the AC power. The control circuit 203 outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0084] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0085] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). By switching the switching elements, the main conversion circuit 201 converts DC power supplied from the power source 100 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201. However, the main conversion circuit 201 according to the fourth embodiment is a two-level three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is implemented using the SiC semiconductor device 12 according to any of the first to third embodiments and their modifications. Two switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0086] The main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit outputs, to the control electrodes of each switching element, a drive signal that turns the switching element on and a drive signal that turns the switching element off, in accordance with a control signal from a control circuit 203 (described later). When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0087] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state, based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by pulse width modulation (PWM) control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that, at each point in time, an on signal is output to a switching element that should be in the on state, and an off signal is output to a switching element that should be in the off state. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0088] The method for manufacturing the power conversion device 200 includes the following steps. SiC semiconductor device 12 is manufactured by the manufacturing method described in any of the first to third embodiments or their modifications. A main conversion circuit 201 having this SiC semiconductor device 12 is formed. Furthermore, a control circuit 203 is formed. In this way, the power conversion device 200 is formed. When the main conversion circuit 201 is formed, for example, as shown in FIG. 14 , the drain electrode 9 of SiC semiconductor device 12 is joined to lead frame 14a via solder 13, and the source electrode 8 is joined to lead frame 14b via wire 15.

[0089] According to the fourth embodiment, the SiC semiconductor device 12 according to any one of the first to third embodiments is used as at least one of the semiconductor devices constituting the main conversion circuit 201. This makes it possible to suppress unexpected adverse effects due to stress during assembly of the SiC semiconductor device 12, while also suppressing defects caused by stress from peripheral components during switching operations. This improves the reliability of the main conversion circuit 201. This in turn improves the reliability of the power conversion device 200.

[0090] In the fourth embodiment, an example in which the SiC semiconductor device 12 is applied to a two-level three-phase inverter has been described, but the fourth embodiment is not limited to this and can be applied to various power conversion devices. In the fourth embodiment, the power conversion device is a two-level power conversion device, but it may be a multi-level power conversion device such as a three-level power conversion device. Furthermore, when power is supplied to a single-phase load, the power conversion device may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the power conversion device may be applied to a DC / DC converter or an AC / DC converter.

[0091] Furthermore, the power conversion device according to the fourth embodiment is not limited to the case where the load is an electric motor, but can also be used as a power supply device for, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.

[0092] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate. [Explanation of symbols]

[0093] 1 SiC substrate, 1a reference surface, 6 gate electrode, 6a second upper surface, 6b first electrode portion, 6c second electrode portion, 7 interlayer insulating film, 7a first upper surface, 7b protruding portion, 7c connecting portion, 7d lower portion, 7e second side surface, 7f first side surface, 7g curved portion, 7h straight portion, 7i connecting portion, 12 SiC semiconductor device, 201 main conversion circuit, 203 control circuit.

Claims

1. a semiconductor substrate; an electrode at least part of which protrudes upward from a reference surface of the semiconductor substrate; an insulating film covering the reference surface and the electrodes of the semiconductor substrate; Equipped with The insulating film is a first upper surface and a protruding portion protruding from the first upper surface, the first upper surface and the protruding portion corresponding to the reference surface of the semiconductor substrate and the at least part of the electrode protruding from the reference surface, respectively; a ratio h1 / h2 of a distance h1 between the reference surface of the semiconductor substrate and a connection portion that connects the first upper surface of the insulating film and a surface of the protruding portion to a distance h2 between the reference surface of the semiconductor substrate and a second upper surface of the electrode is equal to or greater than 1 and equal to or less than 1.5, The electrode is a first electrode portion protruding from the reference surface of the semiconductor substrate; a second electrode portion provided in a trench provided in the reference surface of the semiconductor substrate; 10. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the ratio of the angle formed between the reference surface of the semiconductor substrate and a first side surface of the protruding portion of the insulating film to the angle formed between the reference surface of the semiconductor substrate and a second side surface of a lower portion of the insulating film that is lower than the first upper surface is 1 or greater.

3. 2. The semiconductor device according to claim 1, an outer edge of the protrusion has a curved portion in a cross-sectional view; A semiconductor device, wherein a connection portion between the straight portion and the curved portion in a cross-sectional view of the top surface of the protrusion is located directly above an end of the electrode or directly outside the end.

4. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the material of the semiconductor device includes a wide bandgap semiconductor.

5. a main conversion circuit having the semiconductor device according to claim 1, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit; A power conversion device comprising:

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