Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing contact resistance.SOLUTION: A gate runner 34 and a gate pad are provided on a front surface of a semiconductor substrate 10 in a connection region 43. A part of first trenches 7 where a gate electrode 9 is embedded extends in a first directing X from an active region 41, and is opposed and connected to a runner connection region 51 of a projection 34a of the gate runner 34 in a depth direction Z. The protrusion 34a of the gate runner 34 has a recess 34b on an opposite side of the first trench 7 as viewed from the runner connection region 51 in the first direction X, and there is provided a contact hole 11b in an interlayer insulation film 11 in the recess 34b. Inside the contact hole 11b, a p+ type contact region 6 forming a PiN diode is exposed on the front surface of the semiconductor substrate 10. A conductive layer 22 constituting a SBD is embedded in the contact hole 11b.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: insulated gate field effect transistors, hereafter referred to as SiC-MOSFETs) that use silicon carbide (SiC) as the semiconductor material have a p-type base region and an n-type - When a parasitic pn diode formed at the pn junction with the semiconductor drift region is forward biased and a bipolar current flows through the parasitic pn diode, stacking faults grow inside the semiconductor substrate (semiconductor chip), and this stacking fault growth causes degradation of forward characteristics.

[0003] This degradation of forward characteristics can be suppressed by incorporating a Schottky barrier diode (SBD) on the same semiconductor substrate as the SiC-MOSFET. The reason for this is that when the parasitic pn diode of the SiC-MOSFET is forward biased, bipolar current flows via the SBD at a forward voltage lower than the forward voltage at which bipolar current begins to flow via the parasitic pn diode. In addition, preventing bipolar current from flowing via the parasitic pn diode makes it possible to reduce the on-resistance of the SiC-MOSFET.

[0004] The structure of a conventional SiC-MOSFET will be described. Fig. 14 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device shown in Fig. 14 is a vertical SiC-MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 210 made of silicon carbide, and a trench sidewall SBD 220 (described later) is built into the same semiconductor substrate 210. The trench gate structure has a p-type base region 204, an n-type base region 206, and a n-type base region 208 provided in an active region 241. + type source region 205, p +It comprises a mold contact region 206 , a first trench 207 , a gate insulating film 208 and a gate electrode 209 .

[0005] The first trench 207 has n + The first trench 207 penetrates the p-type source region 205 and the p-type base region 204 to reach the n-type current diffusion region 203. A gate electrode 209 is provided inside the first trench 207 via a gate insulating film 208. A second trench 221 is provided between adjacent first trenches 207 and spaced apart from the first trenches 207. The second trench 221 has a p + The second trench 221 penetrates the p-type contact region 206 and the p-type base region 204 to reach the n-type current spreading region 203. A conductive layer 222 made of titanium (Ti) or tungsten (W) is buried inside the second trench 221.

[0006] An SBD (hereinafter referred to as a trench sidewall SBD) 220 is formed on the sidewall of the second trench 221 by a Schottky junction between the conductive layer 222 and the n-type current diffusion region 203. + p reaching a predetermined depth to the drain region 201 side + A mold area 216 is provided. + The mold region 216 protrudes in a direction parallel to the front surface of the semiconductor substrate 210 beyond the sidewalls of the first and second trenches 207 and 221. - The structure includes a type drift region, an interlayer insulating film, a source electrode, a barrier metal, a source pad, and a drain electrode.

[0007] A conventional MOSFET having an SBD built into the same semiconductor substrate has been proposed, in which an n-type region with a lower impurity concentration than the drain region of the MOSFET is provided in the center of the semiconductor substrate as the cathode region of the SBD (see, for example, Patent Document 1 below (paragraphs 0101-0103, figures 42-44)). Another conventional MOSFET having an SBD built into the same semiconductor substrate has been proposed, in which MOSFET cells and SBD cells are arranged in a striped pattern (see, for example, Patent Document 2 below (paragraphs 0086-0096, figures 24-27)). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-042056 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-175100 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the conventional silicon carbide semiconductor device described above, when gate electrode 209 is formed by etching back polysilicon deposited to fill first trench 207 and leaving the polysilicon only inside first trench 207, the following problem occurs. Figures 15 and 16 are plan views showing the layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of the semiconductor substrate. Figure 15 shows the layout of active region 241, edge termination region 242, connecting region 243, and gate pad region 244. Figure 16 shows the layout of the formation regions of trench sidewall SBD 220 and PiN diode 230 (shown as "SBD" and "PiN," respectively, in Figure 16).

[0010] FIG. 17 is an enlarged plan view of the region enclosed by the rectangular frame AA in FIGS. 15 and 16. The region enclosed by the rectangular frame AA in FIGS. 15 and 16 is the same portion of the semiconductor substrate 210, and shows the vicinity of the boundary between the recessed portion 241a of the active region 241 and the protruding portion 243a of the connecting region 243 (described later). A pair of opposite vertices AA1 and AA2 of this rectangular frame AA are located in the active region 241 and the connecting region 243, respectively. Specifically, FIG. 17 shows the layout of the first and second trenches 207 and 221 near the protruding portion 243a of the connecting region 243. FIG. 18 is an enlarged plan view of the connecting region in FIG. 15. FIG. 19 is a cross-sectional view showing the cross-sectional structure taken along the section line BB1-BB3 in FIG. 17.

[0011] The conventional silicon carbide semiconductor device shown in Figures 15 to 19 is a SiC-MOSFET having a gate pad region 244 provided in a region (hereinafter referred to as a bridging region) 243 between an active region 241 and an edge termination region 242 of a semiconductor substrate 210. The active region 241 has a substantially rectangular planar shape, with one side having a recess 241a recessed inward into a substantially rectangular shape. Unit cells of the SiC-MOSFET and trench sidewall SBD 220 are arranged in the active region 241. The cross-sectional structure of the active region 241 (Figure 17) is similar to that of the conventional SiC-MOSFET shown in Figure 14. The edge termination region 242 surrounds the periphery of the active region 241. No device structure is arranged in the edge termination region 242 (shown as "non" in Figure 16).

[0012] The connecting region 243 is disposed in a substantially annular shape surrounding the periphery of the active region 241, and has a planar shape with a protruding portion 243a that protrudes in a substantially rectangular shape so that a portion of the protruding portion 243a fits exactly into the recessed portion 241a of the active region 241. The connecting region 243 is formed by a p-type region provided in the surface region of the front surface of the semiconductor substrate 210. This p-type region and n - A parasitic PiN diode 230 is formed at the pn junction with the type drift region 202. A gate pad region 244 where a gate pad 235 (see FIG. 17) is arranged is provided on a protruding portion 243a of the connecting region 243. In FIG. 15, the connecting region 243 and the gate pad region 244 are indicated by dotted and diagonal hatching, respectively.

[0013] 17, in the active region 241, first trenches 207 constituting the trench gate structure of the unit cell of the SiC-MOSFET and second trenches 221 constituting the trench sidewall SBD 220 are arranged in a stripe pattern extending in a direction X (hereinafter referred to as the first direction) parallel to the front surface of the semiconductor substrate 210. The first trenches 207 and the second trenches 221 are arranged alternately in a direction Y (hereinafter referred to as the second direction) parallel to the front surface of the semiconductor substrate 210 and perpendicular to the first direction X. The first trench 207a (207) is arranged closest to the protrusion 243a of the connecting region 243 in the second direction Y.

[0014] The p + The mold region 216 (231) extends over the entire connecting region 243 (see FIG. 19). + The portion of the type region 216 that extends to the connecting region 243 is denoted by reference numeral 231. + The p-type contact region 206 and the p-type base region 204 extend over the entire connecting region 243 (see FIG. 19). + Between the type region 231 and p + A mold area 232 is provided.

[0015] These connecting regions 243 p + p-type contact region 206, p-type base region 204, p + Type region 232 and p + The p-type region is made up of a p-type region 231, an n-type current diffusion region 203, and an n-type - type drift region 202 and n +A parasitic PiN diode 230 is formed at the pn junction between the active region 241 and the drain region 201. The PiN diode 230 has approximately the same surface area and planar shape as the connecting region 243. In the connecting region 243, a gate runner 234 made of polysilicon (poly-Si) is provided on the front surface of the semiconductor substrate 210 via a field oxide film 233. Like the connecting region 243, the gate runner 234 extends in an annular shape surrounding the periphery of the active region 241, and has a planar shape with a protrusion 234a that protrudes in an approximately rectangular shape into the protrusion 243a of the connecting region 243.

[0016] In the annular portion (not shown) and the protruding portion 243a of the connecting region 243, the gate runner 234 (n + An end of the first trench 207 extends to the source contact hole 211a (the source drain region 201 side). At the end of this first trench 207, the gate electrode 209 and the gate pad 235 are electrically connected via a gate runner 234. Reference numeral 214a denotes an end of the source pad 214. On the other hand, the end of the second trench 221 terminates at a position away from the connecting region 243 (the portion surrounded by a rectangular frame labeled with reference numeral 251 in FIG. 17). In FIG. 17, the first trench 207 covered with the interlayer insulating film 211 is indicated by a dashed line, and the second trench 221 exposed to the source contact hole 211a of the interlayer insulating film 211 is indicated by a solid line.

[0017] Furthermore, a margin for forming the source contact hole 211a cannot be secured in the region 252 between the first trench 207a, which is disposed closest to the convex portion 243a of the connecting region 243 in the second direction Y, and the convex portion 234a of the gate runner 234. Therefore, it is not possible to form the trench sidewall SBD 220 in this region 252. As such, it is difficult to arrange the trench sidewall SBD 220 at the boundary between the concave portion 241a of the active region 241 and the convex portion 243a of the connecting region 243. Furthermore, the p + Since the distance C101 from the contact region 206 to the source electrode 212 is long, the p +The contact resistance of the contact region 206 increases, causing a decrease in avalanche resistance.

[0018] Furthermore, since the trench sidewall SBD 220 cannot be disposed near the boundary between the recess 241a of the active region 241 and the protrusion 243a of the connecting region 243, the trench sidewall SBD 220 and the p + The distance C102 between the trench sidewall SBD 220 and the unipolar contact region 206 increases. That is, the distance between the trench sidewall SBD 220 and the PiN diode 230 increases. This makes it easier for bipolar current to flow, making it easier for the PiN diode 230 to turn on when a large current flows. Figure 20 is a characteristics diagram showing the relationship between the distance between the PiN diode and the unipolar element arranged on the same semiconductor substrate and the bipolar current. Figure 21 is a cross-sectional view showing the cross-sectional structure of the sample used in the verification of Figure 20.

[0019] The horizontal axis of FIG. 20 is the distance d between the PiN diode 260a and the unipolar element 260b in FIG. 21. The vertical axis of FIG. 20 is the ratio of the current amount of the bipolar element disposed on the semiconductor substrate 265 to the current amount of the unipolar element 260b (=current amount of bipolar element / current amount of unipolar element). FIG. 20 shows the ratio of the current amount of the bipolar element disposed on the semiconductor substrate 265 to the current amount of the unipolar element 260b (hereinafter referred to as the bipolar current amount ratio), measured while changing the critical current density Jc of the bipolar element in various ways. When this bipolar current amount ratio is 1×10 -1 In the above range E, it is assumed that forward degradation occurs in the bipolar element of FIG. 21 due to the operation of the PiN diode 260a.

[0020] 21, a unipolar element 260b is built in the same semiconductor substrate 265 as a bipolar element (not shown). The semiconductor substrate 265 is made of silicon carbide. + On the starting substrate 261 - The silicon carbide epitaxial substrate is formed by epitaxially growing a mold layer 262. - of the mold layer 262, n +Two p-type regions 263 were selectively formed, spaced apart from each other, on the surface layer opposite to the starting substrate 261 (the surface layer on the front surface of the semiconductor substrate 265). - The width w of the portion of the type layer 262 sandwiched between the two p-type regions 263 (hereinafter referred to as the JFET region) 264 JFET The thickness was set to 1.0 μm. An SBD (not shown) was disposed on the JFET region 264 via an oxide film.

[0021] The bipolar current ratio was measured by varying the critical current density Jc of the bipolar element in Figure 21. In Figure 21, the arrow labeled 266 points in the direction in which the PiN diode 260a moves away from the unipolar element 260b (i.e., the direction in which the distance d between the PiN diode 260a and the unipolar element 260b increases). Figure 20 shows the relationship between the distance d between the PiN diode 260a and the unipolar element 260b and the bipolar current ratio. As Figure 20 shows, it was confirmed that the longer the distance d between the PiN diode 260a and the unipolar element 260b, the more easily the bipolar current flows. This result becomes more pronounced as the critical current density Jc of the bipolar element increases.

[0022] An object of the present invention is to provide a semiconductor device capable of reducing contact resistance. [Means for solving the problem]

[0023] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. That is, a semiconductor device including a semiconductor substrate made of silicon carbide, the semiconductor device including: a source pad provided on a front surface of the semiconductor substrate; a conductive layer electrically connected to the source pad; a gate runner provided on the front surface of the semiconductor substrate; a first trench having a conductive portion therein connected to the gate runner; and an interlayer insulating film provided between the first trench and the source pad, wherein the first trenches are arranged in a stripe pattern extending in a first direction parallel to the front surface of the semiconductor substrate, and the gate runners include a first gate runner having a runner connection region connected to the first trench, and a second gate runner located on the opposite side of the first trench in the first direction as viewed from the runner connection region, and a recess formed by one end of the first gate runner in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the first direction, and the second gate runner located more inward from the gate runner than the one end in the second direction, and a contact hole in the interlayer insulating film is provided in the recess of the gate runner, and the conductive layer is embedded in the contact hole. [Effects of the Invention]

[0024] The semiconductor device according to the present invention has the effect of reducing the contact resistance. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 2] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 3] FIG. 3 is an enlarged plan view showing the area surrounded by a rectangular frame A in FIGS. [Figure 4] FIG. 2 is an enlarged plan view showing a connecting region in FIG. [Figure 5] 4 is a cross-sectional view showing a cross-sectional structure taken along the line B1-B2 in FIG. 3. [Figure 6] FIG. 10 is a plan view showing a layout of a silicon carbide semiconductor device according to a second embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 7] 7 is a cross-sectional view showing the cross-sectional structure taken along the line D1-D2 in FIG. 6. [Figure 8] FIG. 11 is a plan view showing a layout of a silicon carbide semiconductor device according to a third embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 9] 9 is a cross-sectional view showing a cross-sectional structure taken along the line E1-E2 in FIG. 8. [Figure 10] FIG. 11 is a plan view showing a layout of a silicon carbide semiconductor device according to a fourth embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 11] 11 is a cross-sectional view showing a cross-sectional structure taken along the cutting line F1-F2 in FIG. 10. [Figure 12] FIG. 11 is a plan view showing a layout of a silicon carbide semiconductor device according to a fifth embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 13] 13 is an enlarged plan view showing the connecting region of FIG. 12. FIG. [Figure 14] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 15] FIG. 1 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. [Figure 16] FIG. 1 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. [Figure 17] FIG. 17 is an enlarged plan view showing the area surrounded by the rectangular frame AA in FIGS. [Figure 18] FIG. 16 is an enlarged plan view showing the connecting region of FIG. [Figure 19] 18 is a cross-sectional view showing the cross-sectional structure taken along the line BB1-BB3 in FIG. 17. [Figure 20] FIG. 10 is a characteristic diagram showing the relationship between the distance between a PiN diode and a unipolar element arranged on the same semiconductor substrate and the bipolar current. [Figure 21] FIG. 21 is a cross-sectional view showing the cross-sectional structure of a sample used in the verification of FIG. 20. DETAILED DESCRIPTION OF THE INVENTION

[0026] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0027] (Embodiment 1) The structure of a silicon carbide semiconductor device according to a first embodiment will be described. Figures 1 and 2 are plan views showing the layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. Figure 2 shows the layout of the formation regions of trench sidewall SBD 20 and PiN diode 30 (shown as "SBD" and "PiN," respectively, in Figure 2). Figure 2 also shows, with dashed lines, the layout of active region 41, edge termination region 42, connection region 43, and gate pad region 44 shown in semiconductor substrate (semiconductor chip) 10 in Figure 1.

[0028] FIG. 3 is an enlarged plan view of the region enclosed by the rectangular frame A in FIGS. 1 and 2. The region enclosed by the rectangular frame A in FIGS. 1 and 2 is the same location on the semiconductor substrate 10, and shows the vicinity of the boundary between the recessed portion 41a of the active region 41 and the protruding portion 43a of the connecting region 43 (described later). A pair of opposite vertices A1 and A2 of this rectangular frame A are located in the active region 41 and the connecting region 43, respectively. FIG. 3 shows the layout of the first and second trenches 7 and 21 near the protruding portion 43a of the connecting region 43. FIG. 4 is an enlarged plan view of the connecting region in FIG. 1.

[0029] Silicon carbide semiconductor device 40 according to the first embodiment shown in FIGS. 1 to 4 is a SiC-MOSFET having a gate pad region 44 provided in a region (bridging region) 43 between active region 41 and edge termination region 42 of semiconductor substrate 10. As shown in FIGS. 1 and 2, active region 41 has a substantially rectangular planar shape, with one side thereof having a recess 41a recessed inward. Active region 41 is a region through which a main current flows when the SiC-MOSFET is in an on-state. A unit cell of the SiC-MOSFET and trench sidewall SBD 20 are arranged in active region 41.

[0030] Edge termination region 42 is a region between active region 41 and the side surface of semiconductor substrate 10. It surrounds active region 41 and relieves the electric field on the front surface side of semiconductor substrate 10 to maintain a breakdown voltage. The breakdown voltage is the maximum voltage at which a semiconductor device does not malfunction or break down. Common breakdown voltage structures such as guard rings, field plates, and resurf structures are disposed in edge termination region 42. No device structures are disposed in edge termination region 42 (shown as "non" in FIG. 2).

[0031] The connecting region 43 is disposed between the active region 41 and the edge termination region 42, contacting both regions, and is disposed in a substantially annular shape surrounding the periphery of the active region 41. The connecting region 43 has a planar shape with a protruding portion 43a that protrudes in a substantially rectangular shape and is sized to fit into the recessed portion 41a of the active region 41. The connecting region 43 is formed by a p-type region provided in the surface region of the front surface of the semiconductor substrate 10. This p-type region and n - A parasitic PiN diode 30 is formed at the pn junction with the type drift region 2. The PiN diode 30 is formed on the entire surface of the connecting region 43.

[0032] The p-type region constituting the connecting region 43 is a p + The p-type contact region 6 and the p-type base region 4 and p + It is composed of mold regions 31 and 32. +Mold regions 31 and 32 have approximately the same surface area and planar shape as connecting region 43. Furthermore, connecting region 43 is provided with gate runner 34 made of polysilicon (poly-Si) on the front surface of semiconductor substrate 10 via gate insulating film 8 and field oxide film 33 (see FIG. 5).

[0033] The gate runner 34 is arranged in a substantially annular shape surrounding the periphery of the active region 41, and has a planar shape with a protruding portion 34a that protrudes in a substantially rectangular shape and is sized to fit exactly in a recessed portion 41a of the active region 41. The protruding portion 34a of the gate runner 34 has a recessed portion 34b formed inward by patterning one of the three outer periphery sides of the protruding portion 34a that is parallel to the first direction X, thereby removing a portion of the protruding portion 34a. As will be described later, a second trench 21a (21) of the trench sidewall SBD 20 is disposed in the recessed portion 34b of the protruding portion 34a of the gate runner 34 (see FIGS. 3 and 4).

[0034] Furthermore, a gate pad region 44 is provided on the protruding portion 43a of the connecting region 43. The gate pad region 44 has, for example, a substantially rectangular planar shape with a smaller surface area than the protruding portion 43a of the connecting region 43. A gate pad 35 is disposed in the gate pad region 44. The gate pad 35 is provided on the gate runner 34 via the interlayer insulating film 11 (see FIG. 5). In FIG. 1, the connecting region 43 and the gate pad region 44 are indicated by dotted and diagonal hatching, respectively.

[0035] 3, first trenches 7 constituting the trench gate structure of a unit cell (a constituent unit of an element) of a SiC-MOSFET and second trenches 21 constituting trench sidewall SBDs 20 are arranged in a stripe pattern extending in a direction (first direction) X parallel to the front surface of semiconductor substrate 10 in active region 41. The first trenches 7 and second trenches (second, third, and fourth trenches) 21 are arranged alternately and repeatedly in a direction (second direction) Y parallel to the front surface of semiconductor substrate 10 and perpendicular to first direction X.

[0036] A gate electrode (conductive portion) 9 is provided inside the first trench 7 via a gate insulating film 8 (see FIG. 5). The gate insulating film 8 is not shown in FIG. 3. The first trench 7 is covered with an interlayer insulating film 11. A conductive layer 22 is buried inside the second trench 21. The second trench 21 is formed between the p + The source electrode 11a is exposed to the first source contact hole 11a of the interlayer insulating film 11 together with the source contact region 6.

[0037] In Fig. 3, the interlayer insulating film 11 is indicated by dotted hatching, and the conductive layer 22 is indicated by diagonal hatching. Also in Fig. 3, the first trench 7 covered with the interlayer insulating film 11 is indicated by dashed lines, and the second trench 21 exposed to the first source contact hole 11a in the interlayer insulating film 11 is indicated by solid lines. The second trench 21a (21) exposed to the second source contact hole 11b in the interlayer insulating film 11, which will be described later, is also indicated by solid lines (the same applies to Figs. 6, 8, 10, and 12).

[0038] The first trenches 7 extend in the first direction X to an annular portion (not shown) of the connecting region 43. Of the multiple first trenches 7, the first trench 7 in the active region 41 that faces the protruding portion 43a of the connecting region 43 in the first direction X extends in the first direction X to the protruding portion 43a of the connecting region 43 (portion indicated by reference numeral 51: runner connection region). An end of the first trench 7 faces the gate runner 34 in the depth direction Z in the connecting region 43. At the end of the first trench 7, the gate electrode 9 and the gate pad 35 are electrically connected via the gate runner 34.

[0039] The second trench 21 terminates at a position away from the connecting region 43 in the first direction X. In addition, when the first and second trenches 7, 21 are alternately and repeatedly arranged in the second direction Y, the second trench 21a (21) is arranged closest to the convex portion 43a of the connecting region 43 in the second direction Y. This second trench (second trench) 21a is arranged at a position 52 closest to the concave portion 34b of the convex portion 34a of the gate runner 34, and its entirety faces the concave portion 34b of the convex portion 34a of the gate runner 34 in the second direction Y (see FIG. 4). Part or all of the second trench 21a may be arranged within the concave portion 34b of the convex portion 34a of the gate runner 34.

[0040] Next, a cross-sectional structure of silicon carbide semiconductor device 40 according to the first embodiment will be described. Fig. 5 is a cross-sectional view showing the cross-sectional structure taken along line B1-B2 in Fig. 3. Semiconductor substrate 10 has n + The n-type drain region 1 is made of silicon carbide. + On the front surface of the starting substrate, - The epitaxial substrate is formed by epitaxially growing silicon carbide layers 61, 62 in order to form the n-type drift region 2 and the p-type base region 4. The main surface of the semiconductor substrate 10 on the side of the p-type silicon carbide layer 62 is the front surface, and the n-type silicon carbide layer 62 is the back surface. + Type starting substrate (n + The main surface on the side of the type drain region 1) is referred to as the back surface.

[0041] n - An n-type region (hereinafter referred to as n-type current diffusion region) 3 is provided within the p-type silicon carbide layer 61, extending from the interface with the p-type silicon carbide layer 62 to a predetermined depth. The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 has a uniform thickness in a direction parallel to the front surface of the semiconductor substrate 10, and extends from the active region 41 to the bridging region 43. The n-type current diffusion region 3 may extend to the edge termination region 42.

[0042] n - The portion of the silicon carbide layer 61 other than the n-type current diffusion region 3 is n -The n-type drift region 2 is an n-type current diffusion region 3. - The n-type silicon carbide layer 62 is exposed on the side walls of the first and second trenches 7 and 21 between the n-type drift region 2 and the p-type base region 4 (p-type silicon carbide layer 62). + Type source region 5 and p + The p-type silicon carbide layer 62 has n-type contact regions 6 selectively formed thereon. + Type source region 5 and p + The portion other than the p-type contact region 6 is the p-type base region 4 .

[0043] The p-type silicon carbide layer 62 is provided with n-type + A first trench 7 is provided which penetrates the p-type source region 5 and the p-type base region 4 in the depth direction Z and reaches the n-type current diffusion region 3. A gate electrode 9 made of polysilicon is provided inside the first trench 7 via a gate insulating film 8. Furthermore, the p-type silicon carbide layer 62 is provided with a p-type silicon carbide layer 9 extending from the front surface of the semiconductor substrate 10. + A second trench 21 is provided which penetrates the p-type contact region 6 and the p-type base region 4 in the depth direction Z and reaches the n-type current diffusion region 3.

[0044] A conductive layer 22 made of titanium (Ti) or tungsten (W) is buried inside the second trench 21. On each side wall of the second trench 21, an SBD (trench sidewall SBD) 20 is formed by a Schottky junction between the conductive layer 22 and the n-type current diffusion region 3. The conductive layer 22 extends from the side wall of the second trench 21 onto the front surface of the semiconductor substrate 10, and + The conductive layer 22 covers a part of the contact region 6. The conductive layer 22 is connected to the source electrode 12 on the front surface of the semiconductor substrate .

[0045] An interlayer insulating film 11 is provided on the front surface of the semiconductor substrate 10 so as to cover the gate electrode 9. A first source contact hole 11a of the interlayer insulating film 11 is provided with an n + Type source region 5, p +The source electrode 12 is formed by a semiconductor portion (n + Type source region 5 and p + The source electrode 12 is in ohmic contact with the gate contact region 6. The barrier metal 13 covering the entire surface of the interlayer insulating film 11 prevents the source electrode 12 from contacting the interlayer insulating film 11 and the gate insulating film 8.

[0046] The source electrode 12 may be, for example, a nickel silicide (NiSi) film formed by a reaction between nickel atoms in a nickel (Ni) film deposited on the semiconductor substrate 10 inside the first source contact hole 11a and silicon (Si) atoms in the semiconductor substrate 10. The barrier metal 13 has the function of preventing, for example, the diffusion of metal atoms from the source pad 14 (described later) to the interlayer insulating film 11 side, and preventing mutual reaction between regions facing each other across the barrier metal 13. The barrier metal 13 may be, for example, a titanium nitride (TiN) film.

[0047] A conductive layer 22 extends from the inside of the second trench 21 onto the surfaces of the source electrode 12 and the barrier metal 13. The source electrode 12 and the barrier metal 13 are covered with the conductive layer 22. A source pad 14 is provided on the surface of the conductive layer 22. The source pad 14 is made of, for example, aluminum (Al). The source pad 14 and the conductive layer 22 may extend to a gate pad region 44 of the junction region 43. Reference numeral 14a in FIG. 3 denotes an end of the source pad 14.

[0048] The source pad 14 and the conductive layer 22 terminate at a position away from the gate pad 35. + n-type drain region 1 +A drain electrode 15 is provided on the entire back surface of the semiconductor substrate 10 (the back surface of the starting substrate). The drain electrode 15 is in ohmic contact with the back surface of the semiconductor substrate 10. The drain electrode 15 may be, for example, a silicide film formed by a reaction between nickel atoms and titanium atoms in a nickel film and a titanium (Ti) film deposited in this order on the back surface of the semiconductor substrate 10 and silicon atoms in the semiconductor substrate 10.

[0049] In the active region 41, p-type current diffusion regions 3 are formed at positions facing the first and second trenches 7 and 21 in the depth direction Z. + A mold region 16 is selectively provided. + The first and second trenches 7 and 21 may terminate inside the mold region 16. + The p-type region 16 is provided apart from the p-type base region 4. + The mold region 16 has the function of suppressing leakage current when the SiC-MOSFET is turned off and of mitigating the electric field applied to the bottom surfaces of the first and second trenches 7 and 21.

[0050] The connecting region 43 includes the n-type current diffusion region 3, the p-type base region 4, and the p + The n-type contact region 6 extends through the connecting region 43. + The mold areas 31 and 32 are provided. + The p-type region 32 is in contact with the p-type base region 4. + The type region 31 is p + contacts the mold region 32, and p + The region is located deeper from the front surface of the semiconductor substrate 10 than the mold region 32. + The type region 31 is, for example, a p-type region of the active region 41. + It is formed at the same time as the mold region 16 .

[0051] In these connecting regions 43, + the p-type contact region 6, the p-type base region 4 and the p + A p-type region consisting of p-type regions 32 and 31 and an n-type current diffusion region 3 and n-type current diffusion region - Type drift region 2 and n +A parasitic PiN diode 30 is formed at the pn junction between the first and second drain regions 1 and 1. The PiN diode 30 has the same planar shape as the connecting region 43 and a surface area that is approximately the same as or slightly smaller than that of the connecting region 43. In addition, a gate runner 34 is provided on the front surface of the semiconductor substrate 10 in the connecting region 43 (including the gate pad region 44) via a gate insulating film 8 and a field oxide film 33.

[0052] As described above, the gate runner 34 has a protruding portion 34a protruding into the protruding portion 43a of the connection region 43, and a recessed portion 34b formed by recessing a part of the protruding portion 34a inward. + A second source contact hole 11b is provided to expose the type contact region 6. In addition, a p + A second trench 21a (21) is provided which penetrates the p-type contact region 6 and the p-type base region 4 in the depth direction Z and reaches the n-type current diffusion region 3.

[0053] That is, by providing the second trench 21a in the recess 34b of the protrusion 34a of the gate runner 34, the second trench 21a can be provided in a position closer to the protrusion 43a of the junction region 43 in the second direction Y than the first trench 7, and facing the protrusion 43a of the junction region 43 in the second direction Y. The conductive layer 22 is also embedded in this second trench 21a, and a trench sidewall SBD 20 is formed on the sidewall of the second trench 21a by a Schottky junction between the conductive layer 22 and the n-type current diffusion region 3. In addition, the p-type source electrode 21b exposed in the second source contact hole 11b is formed on the sidewall of the second trench 21a. + A source electrode 12 is in ohmic contact with the contact region 6 .

[0054] Since there is no first trench 7 between the bridging region 43 and the second trench 21a, the trench sidewall SBD 20 can be disposed at a position closer to the PiN diode 30 than in the conventional structure (see FIGS. 14 to 19). +In this embodiment, the length C103 of the mold region 231 (see FIG. 19) is the distance from the bottom surface of the first trench 7a (7) that is closest to the protrusion 43a of the connecting region 43 in the second direction Y to the p + This corresponds to the length C3 from the end of the mold region 16 farther from the connecting region 43 to the edge termination region 42.

[0055] p of the connecting region 43 in this embodiment + The mold regions 31 and 32 are p regions facing the bottom surface of the second trench 21a in the depth direction Z. + The p + The length C3 from the end of the mold region 16 far from the connecting region 43 to the edge termination region 42 is + The trench sidewall SBD 20 can be disposed at a position closer to the PiN diode 30 than in the conventional structure by a length C1 obtained by subtracting the length C2 of the mold regions 31 and 32.

[0056] In addition, the source electrode 12 and the p + A contact (electrical contact portion) can be formed with the p-type contact region 6. + The contact region 6 can be brought into direct contact with the source electrode 12. This allows a p-type contact region to be formed near the boundary between the recessed portion 41a of the active region 41 and the protruding portion 43a of the connecting region 43. + Since the contact resistance of the contact region 6 can be reduced, a decrease in avalanche resistance can be prevented.

[0057] The gate runner 34 is covered with an interlayer insulating film 11. The interlayer insulating film 11 in the junction region 43 is covered with a barrier metal 13. In the gate pad region 44 of the junction region 43, a gate pad 35 (see FIGS. 3 and 4) is provided on the barrier metal 13. The gate pad 35 may have the same layered structure as the source pad 14. The gate pad 35 faces the gate runner 34 in the depth direction Z, with the barrier metal 13 and the interlayer insulating film 11 sandwiched between them. The gate pad 35 is electrically connected to the gate runner 34.

[0058] As described above, according to the first embodiment, the gate runner is made of polysilicon, is disposed in the transition region between the active region and the edge termination region, and surrounds the periphery of the active region. The gate runner has a protruding portion that protrudes inward in a substantially rectangular shape so as to face the gate pad in the depth direction. The protruding portion of the gate runner has a recess that is recessed inward by removing a portion of the protruding portion.

[0059] By locating the second trench constituting the trench-sidewall SBD within the recess of the protruding portion of the gate runner, the trench-sidewall SBD can be located closer to the protruding portion of the bridging region in the second direction than the first trench, facing the protruding portion of the bridging region. This allows the trench-sidewall SBD to be located closer to the PiN diode than in conventional structures, making it harder for bipolar current to flow and making it harder for the PiN diode to turn on when a large current is applied. This suppresses parasitic PiN diode operation.

[0060] Furthermore, according to the first embodiment, the conductive layer in the second trench arranged in the recess of the protrusion of the gate runner and the p + The p-type contact region is exposed to the second source contact hole. + This allows the type contact region to be in direct contact with the source electrode. This allows the p-type contact region to be in direct contact with the source electrode near the boundary between the recessed portion of the active region and the protruding portion of the connecting region. +Since the contact resistance of the mold contact region can be reduced, a decrease in avalanche resistance can be prevented.

[0061] (Embodiment 2) Next, the structure of a silicon carbide semiconductor device according to a second embodiment will be described. FIG. 6 is a plan view showing the layout of the silicon carbide semiconductor device according to the second embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 6 shows an enlarged view of the area surrounded by a rectangular frame A in FIGS. 1 and 2. The layout of active region 41, edge termination region 42, connecting region 43, and gate pad region 44, as well as the layout of the regions for forming trench sidewall SBD 20 and PiN diode 30, are the same as those in the first embodiment (see FIGS. 1 and 2). The planar shape of protrusion 34a of gate runner 34 is the same as that in the first embodiment (see FIG. 4). FIG. 7 is a cross-sectional view showing the cross-sectional structure taken along line D1-D2 in FIG. 6.

[0062] Silicon carbide semiconductor device 50 according to the second embodiment differs from silicon carbide semiconductor device 40 according to the first embodiment in that width w2 of second source contact hole 11b′ formed in recess 34b of protrusion 34a of gate runner 34 is wider than width w1 of first source contact hole 11a in active region 41, thereby + The surface area of ​​the contact between the contact region 6 and the source electrode 12 is increased. + By increasing the surface area of ​​the contact region 6 and the source electrode 12, a p + The contact resistance of the mold contact region 6 can be further reduced.

[0063] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, by widening the width of the second source contact hole formed in the recess of the protrusion of the gate runner, it is possible to further prevent a decrease in avalanche resistance.

[0064] (Embodiment 3) Next, the structure of a silicon carbide semiconductor device according to a third embodiment will be described. FIG. 8 is a plan view showing the layout of the silicon carbide semiconductor device according to the third embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 8 shows an enlarged view of the area surrounded by a rectangular frame A in FIGS. 1 and 2. The layout of active region 41, edge termination region 42, connecting region 43, and gate pad region 44, as well as the layout of the regions for forming trench sidewall SBD 20 and PiN diode 30, are the same as those in the first embodiment (see FIGS. 1 and 2). The planar shape of protrusion 34a of gate runner 34 is the same as that in the first embodiment (see FIG. 4). FIG. 9 is a cross-sectional view showing the cross-sectional structure taken along line E1-E2 in FIG. 8.

[0065] Silicon carbide semiconductor device 60 according to the third embodiment differs from silicon carbide semiconductor device 40 according to the first embodiment in that a flat SBD (hereinafter referred to as a planar SBD) 20' is provided on the front surface of semiconductor substrate 10, instead of trench sidewall SBD 20, in second source contact hole 11b formed in recess 34b of protrusion 34a of gate runner 34. Planar SBD 20' is formed by a Schottky junction between n-type region 23 exposed on the front surface of semiconductor substrate 10 in second source contact hole 11b, and conductive layer 22 provided along the front surface of semiconductor substrate 10 in second source contact hole 11b.

[0066] Specifically, the second source contact hole 11b formed in the recess 34b of the protrusion 34a of the gate runner 34 contains the n-type region 23 and the p-type region 24. + The n-type contact region 6 is exposed. The n-type region 23 penetrates the p-type silicon carbide layer 62 from the front surface of the semiconductor substrate 10 in the depth direction Z in the second source contact hole 11b to reach the n-type current diffusion region 3. The conductive layer 22 extends from the active region 41 into the second source contact hole 11b and is provided along the front surface of the semiconductor substrate 10. The p-type region 23 exposed in the second source contact hole 11b + The source electrode 12 is in ohmic contact with the contact region 6, as in the first embodiment.

[0067] Directly below the plane SBD20' (n + In the n-type drain region 1 side, inside the n-type current diffusion region 3, + A mold area 24 is optionally provided. + The n-type region 24 is connected to the n-type region 23 and the p-type region 41. + The p-type region 16, the p-type base region 4 of the junction region 43, and the p + It is arranged apart from the mold regions 31 and 32. + The p-type region 24 is the active region 41 + It may be formed at the same time as the mold region 16. + The p-type region 24 is adjacent to the active region 41. + The p-type regions 16 are spaced apart at intervals equal to or smaller than the intervals between the p-type regions 16 in the active region 41. + p of the mold region 16 and the connecting region 43 + It is separated from the mold regions 31 and 32.

[0068] Also, p + The n-type region 24 may be located in the active region 41, in the junction region 43, or across the active region 41 and the junction region 43, as long as at least a portion of the n-type region 24 is located directly below the planar SBD 20'. + By providing the p-type region 24, it is possible to alleviate the electric field concentration at the end of the p-type base region 4 in the connecting region 43. This makes it possible to maintain a predetermined breakdown voltage near the boundary between the active region 41 and the connecting region 43.

[0069] As described above, according to the second embodiment, even when a planar SBD is provided instead of the trench sidewall SBD, the same effects as those of the first embodiment can be obtained.

[0070] (Fourth embodiment) Next, the structure of a silicon carbide semiconductor device according to a fourth embodiment will be described. FIG. 10 is a plan view showing the layout of the silicon carbide semiconductor device according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 10 shows an enlarged view of the area surrounded by a rectangular frame A in FIGS. 1 and 2. The layout of the active region 41, edge termination region 42, connection region 43, and gate pad region 44, as well as the layout of the regions for forming the trench sidewall SBD 20 and PiN diode 30, are the same as those in the first embodiment (see FIGS. 1 and 2). The planar shape of the protrusion 34a of the gate runner 34 is the same as that in the first embodiment (see FIG. 4). FIG. 11 is a cross-sectional view showing the cross-sectional structure taken along the cutting line F1-F2 in FIG. 10.

[0071] In the silicon carbide semiconductor device 70 according to the fourth embodiment, the second embodiment is applied to the silicon carbide semiconductor device 60 according to the third embodiment, and the width w2 of the second source contact hole 11b' formed in the recess 34b of the protrusion 34a of the gate runner 34 is made wider than the width w1 of the first source contact hole 11a in the active region 41. That is, the second source contact hole 11b' is provided with a flat SBD 20'. In addition, the p + This further reduces the contact resistance of the mold contact region 6.

[0072] As described above, according to the fourth embodiment, even when a planar SBD is provided instead of the trench sidewall SBD, the same effects as those of the second embodiment can be obtained.

[0073] (Embodiment 5) Next, the structure of a silicon carbide semiconductor device according to a fifth embodiment will be described. FIG. 12 is a plan view showing the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 12 shows an enlarged view of the region surrounded by a rectangular frame A in FIGS. 1 and 2. The layout of active region 41, edge termination region 42, connecting region 43, and gate pad region 44, as well as the layout of the regions for forming trench sidewall SBD 20 and PiN diode 30, are the same as those in the first embodiment (see FIGS. 1 and 2). The cross-sectional structure taken along line G1-G2 in FIG. 12 is the same as that in the first embodiment (see FIG. 5). FIG. 13 is a plan view showing an enlarged view of the connecting region in FIG. 12.

[0074] The silicon carbide semiconductor device 80 according to the fifth embodiment differs from the silicon carbide semiconductor device 40 according to the first embodiment in the following two points. The first difference is that no recess is provided in the protruding portion 34a' of the gate runner 34. That is, the protruding portion 34a' of the gate runner 34 has a substantially rectangular planar shape, as in the conventional structure. The second difference is that a trench (hereinafter referred to as a connecting trench) 7b having a substantially U-shaped planar shape is arranged by connecting ends of adjacent first trenches 7 in the second direction Y across a corner 34c of the protruding portion 34a' of the gate runner 34. The corner 34c of the protruding portion 34a' of the gate runner 34 is a vertex shared by one side parallel to the first direction X and one side parallel to the second direction Y, out of the three sides of the periphery of the protruding portion 34a' of the gate runner 34.

[0075] The first trenches 7 connected by the connecting trenches 7b in this manner surround the corners 34c of the protrusions 34a' of the gate runner 34 and face only the corners 34c of the protrusions 34a' of the gate runner 34 in the second direction Y. The second trench 21b (21), which is located closest to the protrusions 43a of the connecting region 43 in the second direction Y, faces the protrusions 43a of the connecting region 43 across the connecting trench 7b in the second direction Y. The second trench 21b faces the protrusions 43a of the connecting region 43 in the second direction Y at a portion other than the corners 34c of the protrusions 34a' of the gate runner 34, without sandwiching the first trench 7 between itself and the protrusions 43a of the connecting region 43 in the second direction Y. A gate electrode 9 is provided inside the connecting trench 7b via a gate insulating film 8, similar to the first trench 7.

[0076] As described above, according to embodiment 5, by connecting adjacent ends of the first trench 7 in the second direction near the corners of the convex portion of the gate runner, it is possible to obtain the same effects as embodiments 1 to 4 without providing a concave portion in the convex portion of the gate runner.

[0077] The present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, in the above-described first to fourth embodiments, a recess is provided on one of the three outer periphery sides of the protruding portion of the gate runner that is parallel to the first direction. However, the present invention is not limited to this, and it is sufficient that a recess is provided on one of the three outer periphery sides of the protruding portion of the gate runner that is parallel to the first and second trenches. Therefore, if the first and second trenches are arranged in a stripe pattern extending in the second direction, a recess may be provided on each of two of the three outer periphery sides of the protruding portion of the gate runner that are parallel to the second direction, and an SBD may be disposed in each of the two recesses. [Industrial Applicability]

[0078] As described above, this embodiment is useful for a semiconductor device including a semiconductor substrate made of silicon carbide. [Explanation of symbols]

[0079] 1n + Type drain region 2n - Type Drift Region 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6 p + Mold contact area 7,7a Gate trench (first trench) of MSOFET 7b Connecting trench 8 Gate insulating film 9 Gate electrode 10. Semiconductor substrate 11 Interlayer insulating film 11a, 11b, 11b' Source contact holes 12 Source electrode 13 Barrier Metal 14 Saucepad 15 Drain electrode 16,31,32 p + type area 20 Trench sidewall SBD 20' Planar SBD 21, 21a, 21b Trench sidewalls of SBD (second trench) 22 Conductive layer 23 n-type region 30 PiN diodes 33 Field oxide 34 Gate Runner 34a, 34a' Convex part of gate runner 34b Concave part of convex part of gate runner 34c Corner of the convex part of the gate runner 35 Gate Pad 40,50,60,70,80 Silicon carbide semiconductor device 41 Active area 41a Recessed portion of active region 42 Edge Termination Area 43 Connecting Area 43a Convex part of the connecting area 44 Gate pad area 52 Position near the convex part of the connecting area 61n- mold silicon carbide layer 62 p-type silicon carbide layer X: Direction parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate, perpendicular to the first direction (second direction) Z depth direction w1, w2 Width of source contact hole

Claims

1. A semiconductor device including a semiconductor substrate made of silicon carbide, a source pad provided on a front surface of the semiconductor substrate; a conductive layer electrically connected to the source pad; a gate runner provided on a front surface of the semiconductor substrate; a first trench having a conductive portion therein connected to the gate runner; an interlayer insulating film provided between the first trench and the source pad; Equipped with a plurality of the first trenches are arranged in a stripe pattern extending in a first direction parallel to the front surface of the semiconductor substrate; The gate runner is a first gate runner having a runner connection region connected to the first trench; and a second gate runner located on an opposite side of the runner connection region from the first trench in the first direction, a recess formed by one end of the first gate runner in a second direction that is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction, and the second gate runner that is positioned more inward than the one end of the first gate runner in the second direction; a contact hole in the interlayer insulating film is provided in the recess of the gate runner; The semiconductor device is characterized in that the conductive layer is buried in the contact hole.

2. 2. The semiconductor device according to claim 1, wherein the conductive layer is made of titanium or tungsten.

3. 2. The semiconductor device according to claim 1, wherein the conductive layer is a tungsten layer.

4. The semiconductor substrate is an active region provided with an n-type source region; an edge termination region including a guard ring, a field plate, or a resurf; a transition region between the active region and the edge termination region; 4. The semiconductor device according to claim 1, wherein a p-type region is provided in a surface region of the front surface of the semiconductor substrate in the connecting region, and the p-type region forms a PiN diode.

5. 5. The semiconductor device according to claim 4, wherein the p-type region is exposed in the contact hole.

6. a second trench extending from an opposite side to the first trench toward the runner connection region in the first direction; 6. The semiconductor device according to claim 4, wherein the second trench is exposed to the contact hole.

7. 7. The semiconductor device according to claim 6, wherein the conductive layer is buried in the second trench and forms a Schottky barrier diode in the connecting region.

8. 8. The semiconductor device according to claim 6, further comprising a third trench facing the first trench and the second trench in the second direction.

9. 9. The semiconductor device according to claim 6, further comprising a fourth trench provided between the first trenches adjacent to each other in the second direction and facing the second trench in the first direction.

10. another contact hole is provided in the interlayer insulating film between the first trenches adjacent to each other in the second direction, facing the contact hole in the first direction; 10. The semiconductor device according to claim 1, wherein the conductive layer is buried in the other contact hole.

11. a gate pad provided on the front surface of the semiconductor substrate and electrically connected to the gate runner; 11. The semiconductor device according to claim 1, wherein the gate runner is made of polysilicon.

12. 12. The semiconductor device according to claim 1, wherein the source pad is provided on a surface of the conductive layer.

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