Imaging devices and electronic devices

Abstract

[Problem] To increase a frame rate and reduce power consumption while widening a dynamic range during photoelectric conversion. [Solution] This imaging device comprises: a first photoelectric conversion unit; a first readout circuit for reading out to a first signal line a first pixel signal corresponding to a charge obtained by means of photoelectric conversion performed by the first photoelectric conversion unit; a second photoelectric conversion unit having a smaller light receiving surface area than the first photoelectric conversion unit; a second readout circuit for reading out to a second signal line a second pixel signal corresponding to a charge obtained by means of photoelectric conversion performed by the second photoelectric conversion unit; a pixel signal selector for selecting either the first pixel signal or the second pixel signal on the basis of a result obtained by comparing the second pixel signal with a reference signal; and an analog-to-digital converter for converting the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing the pixel signal with a reference signal having a potential level that changes over time.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and an electronic device. [Background technology]

[0002] A CMOS (Complementary Metal Oxide Semiconductor) image sensor (hereinafter also referred to as CIS) is known that performs analog-to-digital (AD) conversion of pixel signals by using a comparator to compare an analog pixel signal with a linearly changing reference signal and counting the time it takes for the reference signal to cross the pixel signal.

[0003] There are various types of CIS, and one type of CIS has been proposed that expands the dynamic range during photoelectric conversion by providing multiple photoelectric conversion elements with different light-receiving areas within a pixel and performing AD conversion by switching the pixel sensitivity and charge-to-voltage conversion efficiency in multiple ways (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-175345 Summary of the Invention [Problem to be solved by the invention]

[0005] AD conversion is usually performed on a pixel column basis, and each pixel arranged in the row (line) direction must be read out within one horizontal line period. As mentioned above, if the readout of each pixel is performed while switching the sensitivity and conversion efficiency, it takes time to read out, which makes it difficult to increase the frame rate. In addition, the pixel signal on the vertical signal line must be changed every time the sensitivity or conversion efficiency is switched, which increases power consumption.

[0006] Therefore, the present disclosure provides an imaging device and electronic device that can increase the frame rate and reduce power consumption while widening the dynamic range during photoelectric conversion. [Means for solving the problem]

[0007] In order to solve the above problems, according to the present disclosure, there is provided a photoelectric conversion element including: a first photoelectric conversion unit; a first readout circuit that outputs a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit to a first signal line; a second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit; a second readout circuit that outputs a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit to a second signal line; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing it with a reference signal whose potential level changes over time.

[0008] a plurality of pixels arranged in a first direction and a second direction; the first pixel signal and the second pixel signal output from each of two or more pixels arranged in the second direction are output to a common first signal line and a common second signal line, respectively; the analog-to-digital converter is arranged for each pixel column consisting of two or more pixels arranged in the second direction, each of the plurality of pixels includes the first photoelectric conversion unit, the first readout circuit, the second photoelectric conversion unit, and the second readout circuit; The pixel signal selector may be provided for each of the pixel columns arranged in the second direction.

[0009] The analog-to-digital converter a comparator that compares the pixel signal selected by the pixel signal selector with the reference signal; a counter that performs a counting operation until the comparator detects a match between the pixel signal and the reference signal, The digital pixel signal may be generated according to the pixel signal selected by the pixel signal selector, based on the count value of the counter.

[0010] the comparator determines whether or not the illuminance at the start of imaging is equal to or greater than a predetermined reference level by comparing the pixel signal selected by the pixel signal selector with the reference signal; The pixel signal selector may select the second pixel signal when the illuminance at the start of imaging is equal to or greater than the reference level, and may select the first pixel signal when the illuminance is less than the reference level.

[0011] a first floating diffusion region that accumulates charges photoelectrically converted by the first photoelectric conversion unit; a second floating diffusion region that accumulates charges photoelectrically converted by the second photoelectric conversion unit, The pixel signal selector may select the first pixel signal or the second pixel signal based on a result of a comparison made by the comparator between the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region and the reference signal.

[0012] the comparator, when starting imaging, performs a first comparison process of comparing the second pixel signal corresponding to the potential of the second floating diffusion region in a state in which the charge of the second floating diffusion region has been discharged with the reference signal, and then performs a second comparison process of comparing the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region with the reference signal; The pixel signal selector may select the first pixel signal or the second pixel signal based on a result of the second comparison process.

[0013] the comparator determines whether or not the illuminance at the start of image capture is equal to or greater than the reference level through the second comparison process; The pixel signal selector may select the second pixel signal when the illuminance is equal to or greater than the reference level, and may select the first pixel signal when the illuminance is less than the reference level.

[0014] When the second comparison process determines that the illuminance is equal to or greater than the reference level, the comparator may perform a third comparison process in which the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region is compared with the reference signal, and then perform a fourth comparison process in which the second pixel signal corresponding to the potential of the second floating diffusion region in a state in which the charge in the second floating diffusion region has been drained is compared with the reference signal.

[0015] the first readout circuit is capable of varying charge-to-voltage conversion efficiency; When the second comparison process determines that the illuminance is less than the reference level, the comparator may perform a fifth comparison process in which the first pixel signal corresponding to the potential of the first floating diffusion region in a state where the charge of the first floating diffusion region has been discharged is compared with the reference signal, then a sixth comparison process in which the first pixel signal corresponding to the potential of the first floating diffusion region in a state where the charge of the first floating diffusion region has been discharged is compared with the reference signal with a charge-to-potential conversion efficiency higher than that of the fifth comparison process, then a seventh comparison process in which the first pixel signal corresponding to the charge photoelectrically converted in the first photoelectric conversion unit at the same charge-to-potential conversion efficiency as that of the sixth comparison process is compared with the reference signal, and then an eighth comparison process in which the first pixel signal corresponding to the charge photoelectrically converted in the first photoelectric conversion unit at the same charge-to-potential conversion efficiency as that of the fifth comparison process is compared with the reference signal.

[0016] The comparator a first differential transistor pair that compares the pixel signal selected by the pixel signal selector with the reference signal when the illuminance is determined to be less than the reference level in the second comparison process; The image sensor may further include a second differential transistor pair that compares the pixel signal selected by the pixel signal selector with the reference signal when the first comparison process is performed and when the second comparison process determines that the illuminance is equal to or greater than the reference level.

[0017] the first differential transistor pair includes a first transistor and a second transistor; the second differential transistor pair includes a third transistor and a fourth transistor; The comparator a first switch and a first capacitor connected in series between the gate of the first transistor and an output node of the pixel signal selector; a second switch and a second capacitor connected in series between the gate of the second transistor and the input node of the reference signal; a third switch and a third capacitor connected in series between the gate of the third transistor and the output node of the pixel signal selector; a fourth switch and a fourth capacitor connected in series between the gate of the fourth transistor and the input node of the reference signal; a fifth switch that switches whether or not the gate and drain of the first transistor are short-circuited; a sixth switch that switches whether or not the gate and the drain of the second transistor are short-circuited; a seventh switch that switches whether or not the gate and drain of the third transistor are short-circuited; An eighth switch that switches whether or not the gate and drain of the fourth transistor are short-circuited may be provided.

[0018] When starting imaging at each pixel, the comparator may turn off the first switch, the second switch, the third switch, and the fourth switch, turn on the fifth switch and the sixth switch, and turn on the seventh switch and the eighth switch once and then turn them off, thereby storing charge corresponding to the second pixel signal selected by the pixel signal selector in the third capacitor and storing charge corresponding to the reference signal in the fourth capacitor.

[0019] a sample and hold circuit including first and second holding circuits that alternately hold pixel signals selected by the pixel signal selector, and a sample and hold selector that alternately selects and outputs the pixel signals held by the first and second holding circuits; The analog-to-digital converter may convert the output signal of the sample-and-hold circuit into the digital pixel signal.

[0020] During a period in which one of the first and second holding circuits inputs the pixel signal it has held to the analog-to-digital converter, the other of the first and second holding circuits may hold the pixel signal selected by the pixel signal selector.

[0021] The analog-to-digital converter a comparator that compares the output signal of the sample-and-hold circuit with the reference signal; a counter that performs a counting operation until a match between the output signal and the reference signal is detected by the comparator, The digital pixel signal may be generated according to the pixel signal selected by the pixel signal selector, based on the count value of the counter.

[0022] the comparator determines whether the illuminance at the start of imaging is equal to or greater than a predetermined reference level by comparing the output signal of the sample-and-hold circuit with the reference signal; The pixel signal selector may select the second pixel signal when the illuminance at the start of imaging is equal to or greater than the reference level, and may select the first pixel signal when the illuminance is less than the reference level.

[0023] a first floating diffusion region that accumulates charges photoelectrically converted by the first photoelectric conversion unit; a second floating diffusion region that accumulates charges photoelectrically converted by the second photoelectric conversion unit, The pixel signal selector may select the first pixel signal or the second pixel signal based on a result of a comparison made by the comparator between the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region and the reference signal.

[0024] the first holding circuit holds the second pixel signal corresponding to the potential of the second floating diffusion region in a state where the charge of the second floating diffusion region has been discharged when starting imaging, and then inputs the held second pixel signal to the comparator; the second holding circuit holds the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region in synchronization with a timing at which the first holding circuit inputs the second pixel signal to the comparator, and then inputs the held second pixel signal to the comparator; The pixel signal selector may select the first pixel signal or the second pixel signal based on a result of a comparison made by the comparator between the second pixel signal output from the second holding circuit and the reference signal.

[0025] the sample and hold circuit is capable of outputting, without holding, at least a portion of the pixel signal selected by the pixel signal selector; When the comparator determines that the second pixel signal is less than the reference signal, the sample and hold circuit may input at least a portion of the pixel signal selected by the pixel signal selector to the comparator without holding it.

[0026] According to the present disclosure, an imaging device that outputs a digital pixel signal corresponding to an imaged pixel signal; a signal processing unit that performs signal processing based on the digital pixel signal, The imaging device is a first photoelectric conversion unit; a first readout circuit that outputs a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit to a first signal line; a second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit; a second readout circuit that outputs a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit to a second signal line; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; and an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing the pixel signal with a reference signal whose potential level changes over time. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a block diagram showing a schematic configuration of an imaging device according to a first embodiment of the present disclosure. [Figure 2] FIG. 1 is a conceptual diagram showing an example of an imaging device in which a semiconductor chip of a pixel array portion and a semiconductor chip of a processing circuit are stacked. [Figure 3] FIG. 1 is a circuit diagram showing the basic configuration of a high dynamic range pixel. [Figure 4] 4 is a timing chart showing the start of exposure of the pixel in FIG. 3; [Figure 5] 4 is a timing chart for reading out pixel signals in FIG. 3. [Figure 6] 1 is a circuit diagram of a main part of an imaging device according to a first embodiment. [Figure 7] 4 is a diagram showing a charge discharge period and exposure start timing of a first photoelectric conversion unit and a second photoelectric conversion unit. FIG. [Figure 8] FIG. 10 is a diagram showing the relationship between illuminance and the potential level of a vertical signal line. [Figure 9] FIG. 2 is a timing chart of the imaging device according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram of a pixel PX according to a comparative example in which a reset transistor is shared by two circuit blocks. [Figure 11] Timing diagram in Figure 10. [Figure 12] FIG. 10 is a circuit diagram showing the configuration of the main part of an imaging device according to a second embodiment. [Figure 13] FIG. 13 is a timing diagram of the imaging device of FIG. [Figure 14] FIG. 14 is a timing diagram according to a modification of FIG. 13; [Figure 15] FIG. 1 is a cross-sectional view of a semiconductor chip incorporating an imaging device according to the first or second embodiment. [Figure 16] FIG. 2 is a planar layout diagram of the light incident surface side of the imaging device according to the first and second embodiments. [Figure 17] FIG. [Figure 18] FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 19] FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments of an imaging device and an electronic device will be described with reference to the drawings. The following description will focus on the main components of the imaging device and the electronic device, but the imaging device and the electronic device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] (First embodiment) 1 is a block diagram showing a schematic configuration of an image pickup device 100 according to a first embodiment of the present disclosure. The image pickup device 100 includes a pixel array unit 101, a timing control circuit 102, a vertical scanning circuit 103, a DAC (digital-to-analog converter) 104, an ADC (analog-to-digital converter) group 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0030] The pixel array section 101 has unit pixels (hereinafter simply referred to as pixels) arranged in a matrix, each of which includes a photoelectric conversion element that photoelectrically converts incident light into an electric charge (pixel signal) corresponding to the amount of light. A specific circuit configuration of the unit pixel will be described later with reference to FIG. 2. In the pixel array section 101, pixel drive lines 109 are wired for each row of the matrix-like pixel arrangement along the left-right direction of the drawing (the horizontal direction of the pixel arrangement in the pixel row), and vertical signal lines VSL are wired for each column along the up-down direction of the drawing (the vertical direction of the pixel arrangement in the pixel column). One end of each pixel drive line 109 is connected to an output terminal of the vertical scanning circuit 103 corresponding to each row. While FIG. 1 shows one pixel drive line 109 for each pixel row, two or more pixel drive lines 109 may be provided for each pixel row.

[0031] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. The timing control circuit 102 controls the driving of the vertical scanning circuit 103, the DAC 104, the ADC group 105, the horizontal transfer scanning circuit 106, etc., based on the various timing signals generated by the timing generator, in response to externally applied control signals, etc.

[0032] The vertical scanning circuit 103 is made up of a shift register, an address decoder, etc. Although the specific configuration is not shown here, the vertical scanning circuit 103 includes a read scanning system and a sweep scanning system.

[0033] The readout scanning system sequentially selects and scans the unit pixels from which signals are read out, row by row. Meanwhile, the sweep scanning system performs sweep scanning on the readout row being read out by the readout scanning system, sweeping out (resetting) unnecessary charges from the photoelectric conversion elements of the unit pixels of that readout row, prior to the readout scanning by the readout scanning system by the shutter speed. This sweeping out (resetting) of unnecessary charges by the sweep scanning system performs a so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charge in the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charge). The signal read out by the readout operation by the readout scanning system corresponds to the amount of light incident since the previous readout operation or electronic shutter operation. The period from the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the photoelectric charge accumulation time (exposure time) in the unit pixel.

[0034] Pixel signals (analog signals) output from each unit pixel of a pixel row selected and scanned by the vertical scanning circuit 103 are supplied to an ADC group 105 via a plurality of vertical signal lines VSL corresponding to each column.

[0035] The DAC 104 generates a reference signal RAMP, which is a signal with a linearly changing ramp waveform, and supplies the reference signal RAMP to the ADC group 105. The DAC 104 is commonly connected to a plurality of comparators 121 via a reference signal line 114, and supplies the same reference signal RAMP to the plurality of comparators 121. The reference signal line 114 transmits the reference signal RAMP to the plurality of comparators 121.

[0036] The ADC group 105 includes a plurality of comparators 121, a plurality of counters 122, and a plurality of latch circuits 123. The ADC group 105 converts pixel signals (analog signals) from the pixel array unit 101 into digital signals.

[0037] The comparator 121, the counter 122, and the latch circuit 123 are provided corresponding to the pixel columns of the pixel array unit 101, and constitute the ADC 105a. The ADC 105a is provided for each pixel column in the column direction.

[0038] The comparator 121 compares the voltage of a signal obtained by adding the pixel signal output from each pixel and the reference signal RAMP via a capacitor with a predetermined reference voltage, and supplies an output signal indicating the comparison result to the counter 122.

[0039] The counter 122 counts the time until the voltage magnitude relationship between the pixel signal and the reference signal RAMP is inverted based on the output signal of the comparator 121. This converts the analog pixel signal into a digital pixel signal represented by a count value. The counter 122 supplies the count value to the latch circuit 123.

[0040] The latch circuit 123 holds the count value supplied from the counter 122. Furthermore, the latch circuit 123 performs CDS (Correlated Double Sampling) by calculating the difference between the data signal count value corresponding to the pixel signal at the signal level and the reset signal count value corresponding to the pixel signal at the reset level.

[0041] The horizontal transfer scanning circuit 106 is configured with a shift register, an address decoder, etc., and sequentially selects and scans circuit portions corresponding to pixel columns of the ADC group 105. Through the selective scanning by this horizontal transfer scanning circuit 106, the digital pixel signals held in the latch circuit 123 are sequentially transferred to the amplifier circuit 107 via the horizontal transfer line 111.

[0042] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch circuit 123 and supplies the amplified signal to the signal processing circuit 108 .

[0043] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signals supplied from the amplifier circuit 107 to generate two-dimensional image data. For example, the signal processing circuit 108 corrects vertical line defects and point defects, clamps the signal, and performs digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a downstream device.

[0044] 1 may be configured as a single semiconductor chip as a whole, or may be configured as multiple semiconductor chips. When the imaging device 100 is configured as multiple semiconductor chips, the pixel array unit 101 and other processing circuits may be formed as separate semiconductor chips 511 and 512, and the semiconductor chips 511 and 512 may be stacked.

[0045] For example, Fig. 2 is a conceptual diagram showing an example of an imaging device 100 in which a semiconductor chip 511 of a pixel array unit 101 and a semiconductor chip 512 of a processing circuit are stacked. As shown in Fig. 2, the imaging device 100 is configured with two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0046] The semiconductor chip 511 includes a pixel array unit 101 formed on a semiconductor substrate. The semiconductor chip 512 includes an ADC group 105, a logic circuit 516, and a peripheral circuit 517 formed on another semiconductor substrate. The logic circuit 516 includes a timing control circuit 102, a vertical scanning circuit 103, a DAC 104, a horizontal transfer scanning circuit 106, etc. The peripheral circuit 517 includes a signal processing circuit 108, etc.

[0047] Each pixel of the pixel array unit 101 of the semiconductor chip 511 and elements of the processing circuits (105, 516, 517) of the semiconductor chip 512 may be electrically connected using, for example, through electrodes such as TSVs (Through Silicon Vias) provided in via regions 513 and 514. The ADC group 105 can transmit and receive signals to and from the pixel array unit 101 via the TSVs. Furthermore, both semiconductor chips may be bonded together (Cu-Cu bonding) so that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 512 are in contact with each other. Furthermore, although not shown, the pixel array unit 101 and part of the processing circuits (105, 516, 517) may be configured as one semiconductor chip 511, and the remaining components may be configured as another semiconductor chip 512.

[0048] 1 outputs a pixel signal of high dynamic range (hereinafter also referred to as HDR). Before describing the specific configuration of a pixel according to the first embodiment, the basic configuration of a pixel of high dynamic range will be described. (Basic structure of high dynamic range pixels)

[0049] Fig. 3 is a circuit diagram showing the basic configuration of a high dynamic range pixel. The pixel PX in Fig. 3 is configured to include a first photoelectric conversion unit PD11a, a second photoelectric conversion unit PD11b, first to fourth transfer gate units T12a to T12d, a reset transistor T13, a charge accumulation unit C14, a first floating diffusion region (floating diffusion) FD15a, a second floating diffusion region (floating diffusion) FD15b, an amplification transistor T16, and a selection transistor T17.

[0050] 3 are arranged in multiple rows and columns, and each row of pixels arranged in the row direction is provided with a pixel drive line 109 shown in Fig. 1. Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical scanning circuit 103 shown in Fig. 1 via multiple drive lines.

[0051] The first photoelectric conversion unit PD11a is made up of, for example, a PN junction photodiode. The first photoelectric conversion unit PD11a generates and accumulates electric charges according to the amount of light received. The second photoelectric conversion unit PD11b is made up of, for example, a PN junction photodiode, similar to the first photoelectric conversion unit PD11a. The second photoelectric conversion unit PD11b generates and accumulates electric charges according to the amount of light received.

[0052] Comparing the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b, the first photoelectric conversion unit PD11a has a larger light-receiving surface area and higher sensitivity than the second photoelectric conversion unit PD11b.

[0053] The first transfer gate unit T12a is connected between the first photoelectric conversion unit PD11a and the first floating diffusion region FD15a. A drive signal TGL is applied to the gate electrode of the first transfer gate unit T12a. When the drive signal TGL becomes active, the first transfer gate unit T12a becomes conductive, and the charges accumulated in the first photoelectric conversion unit PD11a are transferred to the first floating diffusion region FD15a via the first transfer gate unit T12a.

[0054] The second transfer gate unit T12b is connected between the charge storage unit 104 and the second floating diffusion region FD15b. A drive signal FCG is applied to the gate electrode of the second transfer gate unit T12b. When the drive signal FCG becomes active, the second transfer gate unit T12b becomes conductive, and the potentials of the charge storage unit 104 and the second floating diffusion region FD15b are coupled.

[0055] The conversion efficiency switching transistor T12c is connected between the first floating diffusion region FD15a and the second floating diffusion region FD15b. A drive signal FDG is applied to the gate electrode of the conversion efficiency switching transistor T12c. When the drive signal FDG becomes active, the conversion efficiency switching transistor T12c becomes conductive, and the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0056] The fourth transfer gate unit T12d is connected between the second photoelectric conversion unit PD11b and the charge accumulation unit C14. A drive signal TGS is applied to the gate electrode of the fourth transfer gate unit T12d. When the drive signal TGS becomes active, the fourth transfer gate unit T12d becomes conductive, and the charges accumulated in the second photoelectric conversion unit PD11b are transferred to the charge accumulation unit C14 via the fourth transfer gate unit T12d.

[0057] Furthermore, the potential below the gate electrode of the fourth transfer gate unit T12d is slightly deeper, and an overflow path is formed that transfers charge that exceeds the saturated charge amount of the second photoelectric conversion unit PD11b and overflows from the second photoelectric conversion unit PD11b to the charge accumulation unit C14. Note that, hereinafter, the overflow path formed below the gate electrode of the fourth transfer gate unit T12d will be simply referred to as the overflow path of the fourth transfer gate unit T12d.

[0058] The reset transistor T13 is connected between a power supply (hereinafter, the power supply may also be referred to as VDD) that supplies a power supply voltage VDD and the second floating diffusion region FD15b. A drive signal RST is applied to the gate electrode of the reset transistor T13. When the drive signal RST is activated, the reset transistor T13 is turned on. As a result, for example, the potential of a region where the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled, or a region where the potentials of the charge accumulation portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled, is reset to the level of the power supply voltage VDD.

[0059] The charge storage unit C14 is made up of, for example, a capacitor, and the counter electrode of the charge storage unit C14 is connected to the power supply VDD. The charge storage unit C14 stores the charge transferred from the second photoelectric conversion unit PD11b.

[0060] The first floating diffusion region FD15a and the second floating diffusion region FD15b convert the charges of the first or second photoelectric conversion unit PD11a or PD11b into a voltage signal and output the converted signal. By electrically connecting or disconnecting the first floating diffusion region FD15a and the second floating diffusion region FD15b, the capacitance of the entire floating diffusion region of the pixel PX can be switched. By switching the capacitance of the floating diffusion region of the pixel PX, the pixel PX can output a pixel signal with a plurality of charge-voltage conversion efficiencies.

[0061] The amplifier transistor T16 has a gate electrode connected to the first floating diffusion region FD15a and a drain electrode connected to a power supply VDD, and serves as an input part of a readout circuit (a so-called source follower circuit) that reads out the charge held in the first floating diffusion region FD15a. That is, the amplifier transistor T16 has a source electrode connected to the vertical signal line VSL via the selection transistor T17, and thereby forms a source follower circuit together with a constant current source CS18 connected to one end of the vertical signal line VSL.

[0062] The selection transistor T17 is connected between the source electrode of the amplification transistor T16 and the vertical signal line VSL. A drive signal SEL is applied to the gate electrode of the selection transistor T17. When the drive signal SEL is activated, the selection transistor T17 is turned on, and the pixel PX in FIG. 3 is selected. As a result, the pixel signal output from the amplification transistor T16 is output to the vertical signal line VSL via the selection transistor T17.

[0063] In the following, when each drive signal is in an active state, it is referred to as the drive signal being turned on, and when each drive signal is in an inactive state, it is referred to as the drive signal being turned off. In the following, when each gate unit or each transistor is in a conductive state, it is referred to as the gate unit or each transistor being turned on, and when each gate unit or each transistor is in a non-conductive state, it is referred to as the gate unit or each transistor being turned off.

[0064] (Example of operation at the start of exposure of pixel PX in Figure 3) First, an example of operation at the start of exposure of the pixel PX in Fig. 3 will be described with reference to the timing chart in Fig. 4. This process is performed in a predetermined scanning order, for example, for each pixel row or for each set of multiple pixel rows in the pixel array unit 101. Note that Fig. 4 shows a timing chart of the horizontal synchronization signal XHS and the drive signals SEL, RST, FDG, TGL, TGS, and FCG.

[0065] First, at time t1, the horizontal synchronization signal XHS is input, and the exposure process of the pixel PX in FIG. 3 begins.

[0066] Next, at time t2, the drive signals RST and FDG are turned on, turning on the reset transistor T13 and the conversion efficiency switching transistor T12c, thereby coupling the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b, and the potential of the coupled region is reset to the level of the power supply voltage VDD.

[0067] Next, at time t3, the drive signal TGL is turned on, turning on the first transfer gate unit T12a, which transfers the charges accumulated in the first photoelectric conversion unit PD11a to the region where the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled via the first transfer gate unit T12a, resetting the first photoelectric conversion unit PD11a.

[0068] Next, at time t4, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, which starts the accumulation of charges in the first photoelectric conversion unit PD11a and starts the exposure period.

[0069] Next, at time t5, the drive signals TGS and FCG are turned on, and the fourth transfer gate unit T12d and the second transfer gate unit T12b are turned on. This couples the potentials of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b. Furthermore, the charge accumulated in the second photoelectric conversion unit PD11b is transferred to the coupled region via the fourth transfer gate unit T12d, and the second photoelectric conversion unit PD11b and the charge storage unit C14 are reset.

[0070] Next, at time t6, the drive signal TGS is turned off, and the fourth transfer gate unit T12d is turned off, thereby starting the accumulation of charges in the second photoelectric conversion unit PD11b.

[0071] Next, at time t7, the drive signal FCG is turned off and the second transfer gate unit T12b is turned off, causing the charge accumulation unit C14 to start accumulating the charge that overflows from the second photoelectric conversion unit PD11b and is transferred via the overflow path of the fourth transfer gate unit T12d.

[0072] Next, at time t8, the drive signals RST and FDG are turned off, and the reset transistor T13 and the conversion efficiency switching transistor T12c are turned off.

[0073] Then, at time t9, the horizontal synchronization signal XHS is input.

[0074] (Example of operation when reading out pixel PX in Figure 3) Next, an example of operation when reading out pixel signals from the pixels PX in Fig. 3 will be described with reference to the timing chart in Fig. 5. This processing is performed, for example, for each pixel row or for each set of pixel rows in the pixel array unit 101 in a predetermined scanning order a predetermined time after the processing in Fig. 4 is performed. Note that Fig. 5 shows a timing chart of the horizontal synchronization signal XHS and the drive signals SEL, RST, FDG, TGL, TGS, and FCG.

[0075] First, at time t21, the horizontal synchronization signal XHS is input, and the readout period of the pixel PX in FIG. 3 begins.

[0076] Next, at time t22, the drive signals SEL, RST, and FDG are turned on, turning on the selection transistor T17, reset transistor T13, and conversion efficiency switching transistor T12c. This selects the pixel PX in FIG. 3. The potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled, and the potential of the coupled region is reset to the level of the power supply voltage VDD.

[0077] Next, at time t23, the drive signal RST is turned off, and the reset transistor T13 is turned off.

[0078] Next, at time ta between times t23 and t24, a signal NH2 based on the potential of the coupled first floating diffusion region FD15a and second floating diffusion region FD15b is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The signal NH2 is a signal obtained by detecting the reset states of the first photoelectric conversion unit PD11a and the floating diffusion regions FD15a and FD15b in FIG. 3 using the coupled region of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0079] Hereinafter, the signal NH2 will also be referred to as the high-sensitivity reset signal NH2.

[0080] Next, at time t24, the drive signal FDG is turned off, and the conversion efficiency switching transistor T12c is turned off, thereby dissolving the potential coupling between the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0081] Next, at time tb between time t24 and time t25, a signal NH1 based on the potential of the first floating diffusion region FD15a is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The signal NH1 is a signal obtained by detecting the reset states of the first photoelectric conversion unit PD11a and the first floating diffusion region FD15a shown in FIG. 3 using the first floating diffusion region FD15a.

[0082] Hereinafter, the signal NH1 will also be referred to as the high-sensitivity reset signal NH1.

[0083] Next, at time t25, the drive signal TGL is turned on, and the first transfer gate unit T12a is turned on, so that the charges generated and accumulated in the first photoelectric conversion unit PD11a during the exposure period are transferred to the first floating diffusion region FD15a via the first transfer gate unit T12a.

[0084] At this time t25, the readout of pixel signals starts and the exposure period ends.

[0085] Next, at time t26, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, thereby stopping the transfer of charges from the first photoelectric conversion unit PD11a to the first floating diffusion region FD15a.

[0086] Next, at time tc between times t26 and t27, a signal SH1 based on the potential of the first floating diffusion region FD15a is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The signal SH1 is a signal based on the potential of the first floating diffusion region FD15a when charges generated in the first photoelectric conversion unit PD11a during the exposure period are accumulated in the first floating diffusion region FD15a.

[0087] Hereinafter, the signal SH1 will also be referred to as the high-sensitivity data signal SH1.

[0088] Next, at time t27, the drive signals FDG and TGL are turned on, turning on the conversion efficiency switching transistor T12c and the first transfer gate unit T12a. This couples the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b, and the charge remaining in the first photoelectric conversion unit PD11a that was not transferred between time t25 and time t26 is transferred to the coupled region via the first transfer gate unit T12a. Note that when reading out the high-sensitivity data signal SH1, the capacity for charge-to-voltage conversion is small compared to the amount of charge handled, so the remaining charge in the first photoelectric conversion unit PD11a does not pose a problem. The remaining charge in the first photoelectric conversion unit PD11a can be transferred when reading out the high-sensitivity data signal SH2, and does not damage the charge in the first photoelectric conversion unit PD11a.

[0089] Next, at time t28, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, thereby stopping the transfer of charges from the first photoelectric conversion unit PD11a to the region where the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0090] Next, at time td, between times t28 and t29, a signal SH2 based on the potential of the region where the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplifier transistor T16 and the select transistor T17. The signal SH2 is a signal based on the potential of the coupled region of the first floating diffusion region FD15a and the second floating diffusion region FD15b, which is generated by the first photoelectric conversion unit PD11a during the exposure period and accumulated in the coupled region of the first floating diffusion region FD15a and the second floating diffusion region FD15b. Therefore, the capacitance for charge-to-voltage conversion when reading out the signal SH2 is the combined capacitance of the first floating diffusion region FD15a and the second floating diffusion region FD15b, which is larger than the capacitance when reading out the high-sensitivity data signal SH1 at time tc.

[0091] Hereinafter, the signal SH2 will also be referred to as the high-sensitivity data signal SH2.

[0092] Next, at time t29, the drive signal RST is turned on, turning on the reset transistor T13, thereby resetting the potential of the region where the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled to the level of the power supply voltage VDD.

[0093] Next, at time t30, the drive signal SEL is turned off, turning off the selection transistor T17, thereby putting the pixel PX in FIG.

[0094] Next, at time t31, the drive signal RST is turned off, and the reset transistor T13 is turned off.

[0095] Next, at time t32, the drive signals SEL, TGS, and FCG are turned on, turning on the selection transistor T17, the fourth transfer gate unit T12d, and the second transfer gate unit T12b. This selects the pixel PX in FIG. 3. Furthermore, the potentials of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled, and the charge accumulated in the second photoelectric conversion unit PD11b is transferred to the coupled region. This causes the charge accumulated in the second photoelectric conversion unit PD11b and the charge accumulation unit C14 during the exposure period to be accumulated in the coupled region.

[0096] Next, at time t33, the drive signal TGS is turned off, and the fourth transfer gate unit T12d is turned off, thereby stopping the transfer of charges from the second photoelectric conversion unit PD11b.

[0097] Next, at time te between times t33 and t34, a signal SL based on the potential at the coupling region of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The signal SL is a signal based on the potential at the coupling region of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b when the charges generated by the second photoelectric conversion unit PD11b and accumulated in the second photoelectric conversion unit PD11b and the charge accumulation unit C14 are accumulated in the coupling region. Therefore, the capacitance for charge-to-voltage conversion when reading out the signal SL is the combined capacitance of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b. This capacitance is larger than when the high-sensitivity data signal SH1 is read out at time tc and when the high-sensitivity data signal SH2 is read out at time td.

[0098] Hereinafter, the signal SL will also be referred to as a low-sensitivity data signal SL.

[0099] Next, at time t34, the drive signal RST is turned on, and the reset transistor T13 is turned on, thereby resetting the coupling region of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b.

[0100] Next, at time t35, the drive signals SEL and FCG are turned off, and the selection transistor T17 and the second transfer gate unit T12b are turned off. This causes the pixel PX in FIG. 3 to enter a non-selected state. Furthermore, the potential of the charge storage unit C14 is separated from the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0101] Next, at time t36, the drive signal RST is turned off, and the reset transistor T13 is turned off.

[0102] Next, at time t37, the drive signals SEL and FCG are turned on, turning on the selection transistor T17 and the second transfer gate unit T12b. This selects the pixel PX in FIG. 3. The potential of the charge storage unit C14 is coupled to the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0103] Next, at time tf between time t37 and time t38, a signal NL based on the potential at the coupling region of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This signal NL is a signal based on the potential at the coupling region of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b in the reset state.

[0104] Hereinafter, the signal NL will also be referred to as a low-sensitivity reset signal NL.

[0105] Next, at time t38, the drive signals SEL, FDG, and FCG are turned off, and the selection transistor T17, the conversion efficiency switching transistor T12c, and the second transfer gate unit T12b are turned off. This causes the pixel PX in FIG. 3 to enter a non-selected state. Furthermore, the potential coupling between the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b is released.

[0106] Next, at time t39, the horizontal synchronization signal XHS is input, and the readout period of the pixel signal from pixel PX in FIG. 3 ends.

[0107] The ADC group 105 performs AD conversion on pixel signals from the high-dynamic-range pixels PX shown in FIG. 3. In this case, when reading out one pixel signal, the ADC group 105 sequentially AD-converts the high-sensitivity reset signal NH2, the high-sensitivity reset signals NH1 and NL, the high-sensitivity data signals SH1 and SH2, the low-sensitivity data signal SL, and the low-sensitivity reset signal NL. These AD conversions must be performed within one horizontal line period, which can hinder an increase in frame rate. Furthermore, frequent changes in the potential of the vertical signal lines transmitting the pixel signals can increase power consumption.

[0108] Therefore, the imaging device 100 according to the first and second embodiments described below is characterized in that switching between multiple sensitivity and conversion efficiency does not hinder the frame rate from being increased and does not increase power consumption.

[0109] (Configuration of main parts of imaging device 100) Fig. 6 is a circuit diagram of the main parts of the imaging device 100 according to the first embodiment. Although only one pixel is shown in Fig. 6, in reality, a plurality of pixels are arranged in the row and column directions to form the pixel array section of Fig. 1.

[0110] 6, a VSL selector (pixel signal selector) 11, a VSL boost circuit 12, and an ADC 105a are arranged for each pixel column arranged in the column direction. The ADC 105a has a comparator 121, a counter 122, a latch 13, and a plurality of signal selectors (first to fourth signal selectors) 14 to 17. As will be described later, the latch 13 is provided separately from the latch circuit 123 of FIG. 1.

[0111] Each pixel PX has a first photoelectric conversion unit PD11a, a second photoelectric conversion unit PD11b, first to fourth transfer gate units T12a to T12d, reset transistors T13a and T13b, a charge accumulation unit C14, a first floating diffusion region FD15a, a second floating diffusion region FD15b, amplification transistors T16a and T16b, and selection transistors T17a and T17b.

[0112] The pixel PX in Figure 6 differs from the pixel PX in Figure 3 in that it has two vertical signal lines VSL_A and VSL_B, two reset transistors T13a and T13b, two amplification transistors T16a and T16b, and two selection transistors T17a and T17b.

[0113] Of the two vertical signal lines VSL_A and VSL_B, one VSL_B transmits a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit PD11a having a large light receiving area, and the other VSL_A transmits a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit PD11b having a small light receiving area.

[0114] The gate of the amplification transistor T16a is connected to the first floating diffusion region FD15a, the source of the amplification transistor T16a is connected to the drain of the selection transistor T17a, and the source of the selection transistor T17a is connected to the vertical signal line VSL_B.

[0115] The gate of the amplification transistor T16b is connected to the second floating diffusion region FD15b, the source of the amplification transistor T16b is connected to the drain of the selection transistor T17b, and the source of the selection transistor T17b is connected to the vertical signal line VSL_A.

[0116] The VSL selector 11 selects either the first pixel signal or the second pixel signal on the two vertical signal lines VSL_B and VSL_A and outputs it to the vertical signal line VSL. The VSL selector 11 selects the first pixel signal or the second pixel signal based on the output signal of the latch 13 that holds the output signal of the comparator 121 in the ADC 105a.

[0117] For example, when the output signal of the latch 13 is at a high level, the VSL selector 11 selects a first pixel signal on the vertical signal line VSL_B, and when the output signal of the latch 13 is at a low level, the VSL selector 11 selects a second pixel signal on the vertical signal line VSL_A. As will be described later, the output signal of the latch 13 becomes high when the illuminance at the start of imaging is below a reference level, and becomes low when the illuminance at the start of imaging is equal to or higher than the reference level. In this embodiment, when the illuminance is equal to or higher than the reference level, multiple AD conversions are performed at low sensitivity, and when the illuminance is lower than the reference level, multiple AD conversions are performed at high sensitivity while switching the charge-voltage conversion efficiency.

[0118] In this specification, the amplification transistor T16a and selection transistor T17a, etc. that output the first pixel signal to the vertical signal line VSL_B are referred to as the first readout circuit, and the amplification transistor T16b and selection transistor T17b, etc. that output the second pixel signal to the vertical signal line VSL_A are referred to as the second readout circuit.

[0119] The pixel signal selected by the VSL selector 11 is input to the ADC 105a via the vertical signal line VSL. The vertical signal line VSL is also connected to a VSL boost circuit 12. The VSL boost circuit 12 is provided to quickly stabilize the potential of the vertical signal line VSL.

[0120] The VSL boost circuit 12 includes n-type transistors Tn6 to Tn8, a capacitor C310, and a constant current source CS310. The gate of the transistor Tn8 is connected to the vertical signal line VSL. The drain of the transistor Tn8 is connected to the power supply VDD, and its source is connected to the constant current source CS310. As a result, the transistor Tn8 and the constant current source CS310 function as a source follower, and the gain thereof is smaller than "1."

[0121] One end of the capacitor C310 is connected to the gate of the transistor Tn8 via the transistor Tn6. The other end of the capacitor C310 is connected to the source of the transistor Tn8. As a result, the source of the transistor Tn6 sees a signal of the same polarity obtained by dividing the pixel signal of the vertical signal line VSL by the gain of the transistor Tn6, and the source of the transistor Tn8 sees a signal obtained by multiplying the fluctuation of the pixel signal of the vertical signal line VSL by the gain of the source follower. As a result, across the capacitor C310, it appears as if a gain of the same polarity that is larger than that of the source of the transistor Tn6 is being applied to the source of the transistor Tn8. As a result, the VSL boost circuit 12 operates as a negative capacitance circuit.

[0122] The transistor Tn7 is connected between one end of the capacitor C310 and ground GND. The transistor Tn6 is connected between one end of the capacitor C310 and the vertical signal line VSL. The transistor Tn7 functions as a constant current source for the vertical signal line VSL.

[0123] Parasitic capacitance occurs in the vertical signal line VSL. Assume that a voltage of +Vs is applied to the parasitic capacitance of the vertical signal line VSL. In this case, if the gain of the transistor Tn8 functioning as a source follower and the constant current source CS310 in the negative capacitance circuit 310 is set to 0.9 and the source-to-drain gain of the transistor Tn6 is set to 10, 0.1×Vs is applied to the terminal of the capacitor C310 on the vertical signal line VSL side, and 0.9×Vs is applied to the terminal on the opposite side. Therefore, when the potential (0.9×Vs) on the opposite side to the vertical signal line VSL is used as a reference, a voltage of −0.8×Vs is applied to the capacitor C310. As a result, +Vs is applied to the parasitic capacitance of the vertical signal line VSL, and −0.8×Vs is applied to the capacitor C310, so the wiring capacitance of the vertical signal line VSL is reduced compared to when the negative capacitance circuit 310 is not present.

[0124] By providing the VSL boost circuit 12, the potential of the vertical signal line VSL can be quickly stabilized, and the settling time can be shortened.

[0125] In this disclosure, the transistor Tn8 functioning as a source follower and the constant current source Cs310 are used, but other configurations capable of non-inverting amplification may be used as long as the influence of the parasitic capacitance of the vertical signal line 110 can be sufficiently reduced.

[0126] The comparator 121 in the ADC 105a includes a first differential transistor pair 18, a second differential transistor pair 19, first to eighth switches Sw11 to Sw18, first to fourth capacitors C11 to C14, a current mirror circuit 20, a current source 21, a capacitor C15, and an output circuit 22.

[0127] When the illuminance is determined to be less than the reference level, the first differential transistor pair 18 and 19 alternately compare the pixel signal selected by the VSL selector 11 with a reference signal. The reference signal is, for example, a ramp signal whose voltage level changes continuously over time, and is generated by the DAC 104 in Fig. 1. The pixel signal selected by the VSL selector 11 and the reference signal are alternately input to either the first differential transistor pair 18 or 19, and a comparison operation is performed.

[0128] The second differential transistor pair 19 compares the pixel signal selected by the VSL selector 11 with the reference signal at the start of imaging and when it is determined that the illuminance at the start of imaging is equal to or higher than the reference level.

[0129] In this way, when the illuminance is determined to be less than the reference level, the first differential transistor pair 18 and 19 alternately compare the pixel signal selected by the VSL selector 11 with the reference signal.

[0130] The first differential transistor pair 18 includes a first transistor T21 and a second transistor T22. The second differential transistor pair 19 includes a third transistor T23 and a fourth transistor T24. The first to fourth transistors T21 to T24 are NMOS transistors.

[0131] A first switch Sw11 and a first capacitor C11 are connected in series between the gate of the first transistor T21 and the vertical signal line VSL. A second switch Sw12 and a second capacitor C12 are connected in series between the gate of the second transistor T22 and the reference signal input node. The reference signal input node is equivalent to the output node of the DAC 104 in FIG. 1.

[0132] A third switch Sw13 and a third capacitor C13 are connected in series between the gate of the third transistor T23 and the vertical signal line VSL. A fourth switch Sw14 and a fourth capacitor C14 are connected in series between the gate of the fourth transistor T24 and the input node of the reference signal.

[0133] A fifth switch Sw15 is connected between the gate and drain of the first transistor T21, and switches whether or not the gate and drain of the first transistor T21 are short-circuited. A sixth switch Sw16 is connected between the gate and drain of the second transistor T22, and switches whether or not the gate and drain of the second transistor T22 are short-circuited.

[0134] A seventh switch Sw17 is connected between the gate and drain of the third transistor T23, and switches whether or not the gate and drain of the third transistor T23 are short-circuited. An eighth switch Sw18 is connected between the gate and drain of the fourth transistor T24, and switches whether or not the gate and drain of the fourth transistor T24 are short-circuited.

[0135] The signals sel1_A, sel1_B, sel2_A, sel2_B, AZ1_A, AZ1_B, AZ2_A, and AZ2_B input to the first to fourth signal selectors 14 to 17 are signals common to all columns.

[0136] The first signal selector 14 generates a signal sel1 that switches the first switch Sw11 and the second switch Sw12 on or off based on the output signal of the latch 13. When the output signal of the latch 13 is at a low level, the first signal selector 14 sets the signal sel1 to sel1_A. sel1_A is a low-level signal. Therefore, when the output signal of the latch 13 is at a low level, both the first switch Sw11 and the second switch Sw12 are turned off. When the output signal of the latch 13 is at a high level, the first signal selector 14 sets the signal sel1 to sel1_B. sel1_B is a signal that alternates between a high level and a low level. Therefore, the first switch Sw11 and the second switch Sw12 alternately turn on and off.

[0137] The second signal selector 15 generates a signal sel2 that switches the third switch Sw13 and the fourth switch Sw14 on or off based on the output signal of the latch 13. When the output signal of the latch 13 is low, the second signal selector 15 sets the signal sel2 to sel2_A. sel2_A is a high-level signal. Therefore, when the output signal of the latch 13 is low, the third switch Sw13 and the fourth switch Sw14 are both turned on, one end of the third capacitor C13 is connected to the vertical signal line VSL, and one end of the fourth capacitor C14 is connected to the input node of the reference signal. When the output signal of the latch 13 is high, the second signal selector 15 sets the signal sel2 to sel2_B. sel2_B is a signal that alternates between high and low levels. Therefore, the third switch Sw13 and the fourth switch Sw14 alternately turn on and off.

[0138] The third signal selector 16 generates a signal AZ1 that switches the fifth switch Sw15 and the sixth switch Sw16 on or off based on the output signal of the latch 13. When the output signal of the latch 13 is at a low level, the third signal selector 16 sets the signal AZ1 to AZ1_A. AZ1_A is a low-level signal. Therefore, when the output signal of the latch 13 is at a low level, both the fifth switch Sw15 and the sixth switch Sw16 are turned off. When the output signal of the latch 13 is at a high level, the third signal selector 16 sets the signal AZ1 to AZ1_B. AZ1_B outputs a pulse signal once within one horizontal line period. While AZ1_B is outputting a pulse signal, the fifth switch Sw15 and the sixth switch Sw16 are turned on.

[0139] The fourth signal selector 17 generates a signal AZ2 that switches the seventh switch Sw17 and the eighth switch Sw18 on or off based on the output signal of the latch 13. When the output signal of the latch 13 is at a low level, the fourth signal selector 17 sets the signal AZ2 to AZ2_A. AZ2_A outputs a pulse signal twice in one horizontal line period. While AZ2_A is outputting a pulse signal, the seventh switch Sw17 and the eighth switch Sw18 are turned on. When the output signal of the latch 13 is at a high level, the fourth signal selector 17 sets the signal AZ2 to AZ2_B. AZ2_B outputs a pulse signal twice in one horizontal line period. While AZ2_B is outputting a pulse signal, the seventh switch Sw17 and the eighth switch Sw18 are turned on.

[0140] The output circuit 22 in the comparator 121 has seventh to tenth transistors T27 to T30, a switch Sw19, and a capacitor C16. The seventh transistor T27 and the ninth transistor T29 are PMOS transistors, and the eighth transistor T28 and the tenth transistor T30 are NMOS transistors.

[0141] The seventh transistor T27 and the eighth transistor T28 are cascode-connected between the power supply node and the ground node. The gate of the seventh transistor T27 is connected to the drains of the first and third transistors T21 and T23. A capacitor C15 is connected between the gate of the seventh transistor T27 and the power supply node. A switch Sw19 is connected between the drain and gate of the eighth transistor T28. A capacitor C16 is connected between the gate of the eighth transistor T28 and the ground node.

[0142] The ninth transistor T29 and the tenth transistor T30 form an inverter, which inverts the logic of the connection node between the seventh transistor T27 and the eighth transistor T28 and outputs the inverted signal. The output signal of this inverter is input to the counter 122 and also to the latch 13. The latch 13 holds the output signal of the inverter at a predetermined timing.

[0143] 6 measures illuminance using the first photoelectric conversion unit PD11b at the start of imaging, and if the measured illuminance is equal to or greater than a reference level, performs multiple AD conversions at low sensitivity, whereas if the measured illuminance is less than the reference level, performs multiple AD conversions at high sensitivity while switching the charge-to-voltage conversion efficiency. The reference level may be, for example, an illuminance near the center of the variable range of illuminance, or may be another illuminance.

[0144] In this embodiment, the first photoelectric conversion unit PD11a, which has a small light-receiving area, is used to measure the illuminance at the start of imaging. FIG. 7 is a diagram showing the charge discharge periods and exposure start timing of the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b. The first floating diffusion region FD15a, which accumulates charge from the first photoelectric conversion unit PD11a, which has a large light-receiving area, discharges charge during the period when the drive signal TGL is high (times t1 to t2), and then exposure starts. On the other hand, the second floating diffusion region FD15b, which accumulates charge from the second photoelectric conversion unit PD11b, which has a small light-receiving area, discharges charge during the period when the drive signal TGS is high (times t3 to t4), and then exposure starts. Although the first photoelectric conversion unit PD11a starts exposure before the second photoelectric conversion unit PD11b, the first photoelectric conversion unit PD11a is prone to saturation of photoelectrically converted charge, which may prevent accurate measurement of illuminance.

[0145] FIG. 8 is a diagram showing the relationship between illuminance and the potential level of the vertical signal line. FIG. 8 shows cases where photoelectric conversion and AD conversion are performed with a high sensitivity and high conversion efficiency (hereinafter also referred to as SP1H), a high sensitivity and low conversion efficiency (hereinafter also referred to as SP1L), a low sensitivity and no capacitance (hereinafter referred to as SP2H), and a low sensitivity and capacitance (hereinafter referred to as SP2L). As shown in the figure, SP1H and SP1L, which use the first photoelectric conversion unit PD11a with a large light-receiving area, saturate the potential of the vertical signal line even if the illuminance is not very high. On the other hand, SP2H and SP2L, which use the second photoelectric conversion unit PD11b with a small light-receiving area, do not saturate the potential of the vertical signal line even if the illuminance is high.

[0146] 8, using the second photoelectric conversion unit PD11b with a smaller light-receiving area allows for more accurate determination of illuminance without the risk of potential saturation. Therefore, in this embodiment, before starting imaging of each pixel PX, the second photoelectric conversion unit PD11b is used to determine whether the illuminance is equal to or greater than a reference level. If the illuminance is equal to or greater than the reference level, the second photoelectric conversion unit PD11b continues to be used to perform multiple AD conversions at low sensitivity. If the illuminance is less than the reference level, the first photoelectric conversion unit PD11a is used to perform multiple AD conversions at high sensitivity while switching the conversion efficiency.

[0147] 9 is a timing diagram of the imaging device 100 according to the first embodiment. As described above, at the start of imaging, the illuminance is measured using the second photoelectric conversion unit PD11b, and if the illuminance is equal to or higher than a reference level (hereinafter referred to as high illuminance), AD conversion processing is performed multiple times within one horizontal line period in the order of SP2H (data acquisition period), SP2L (data acquisition period), and SP2L (reset period). Also, if the illuminance is less than the reference level (hereinafter referred to as low illuminance), AD conversion processing is performed multiple times within one horizontal line period in the order of SP1L (reset period), SP1H (reset period, data acquisition period), and SP1L (data acquisition period). The upper half of FIG. 9 shows a timing diagram for when high illuminance is determined, and the lower half shows a timing diagram for when low illuminance is determined. In the drawings accompanying this specification, SP2H (data acquisition period) is represented as SP2H (D phase), SP2L (data acquisition period) is represented as SP2L (D phase), SP2L (reset period) is represented as SP2L (P phase), SP1L (reset period) is represented as SP1L (P phase), SP1H (reset period, data acquisition period) is represented as SP1H, and SP1L (data acquisition period) is represented as SP1L (D phase).

[0148] In this specification, SP2H (reset period) will be referred to as the first comparison process, SP2H (data acquisition period) as the second comparison process, SP2L (data acquisition period) as the third comparison process, SP2L (reset period) as the fourth comparison process, SP1L (reset period) as the fifth comparison process, SP1H (reset period) as the sixth comparison process, SP1H (data acquisition period) as the seventh comparison process, and SP1L (data acquisition period) as the eighth comparison process.

[0149] First, at time t1, the reset transistor T13 is turned on, and the charge in the second floating diffusion region FD15b is discharged to the power supply node. After time t2, the second photoelectric conversion unit PD12b starts photoelectric conversion, but the transfer transistor T12d is not turned on until time t5, so the second floating diffusion region FD15b holds the reset potential until time t5. In addition, in the initial state before starting imaging, the VSL selector 11 is set to select the second pixel signal on the vertical signal line VSL_A.

[0150] Furthermore, after time t1, the third switch Sw13 and the fourth switch Sw14 are turned on. During the period from time t1 to t3, the seventh switch Sw17 and the eighth switch Sw18 are turned on, the gate and drain of the third transistor T23 are shorted, and the gate and drain of the fourth transistor T24 are shorted, performing an auto-zero operation to discharge the charges stored in the third capacitor C13 and the fourth capacitor C14.

[0151] At time t4, the second pixel signal corresponding to the potential of the second floating diffusion region FD15b intersects with the reference signal. This causes the output signal of the comparator 121 to transition to a low level. The counter 122 counts the time until the output signal of the comparator 121 transitions to a low level. The count value of the counter 122 represents the reset level of SP2H.

[0152] Then, at time t5, the transfer transistor T12d is turned on, and the charge photoelectrically converted by the second photoelectric conversion unit PD11b is accumulated in the second floating diffusion region FD15b via the transfer transistor T12d. Therefore, the signal level of the second pixel signal on the vertical signal line VSL_A starts to decrease. At time t5, the VSL selector 11 selects the second pixel signal, and the second pixel signal is input to the comparator 121.

[0153] At time t6, when the second pixel signal intersects with the reference signal, the output signal of the comparator 121 transitions to a low level. When the output signal of the comparator 121 transitions to a low level at time t6, the latch 13 holds the output signal of the comparator 121. The output of the comparator 121 transitions to a low level at time t6 when the second pixel signal is less than the reference signal, indicating high illuminance.

[0154] In this way, the illuminance can be determined based on whether the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit PD11b intersects with the reference signal. If the second pixel signal intersects with the reference signal, the illuminance is determined to be high, and if not, the illuminance is determined to be low.

[0155] At time t6, when the second pixel signal intersects with the reference signal, the signal held by the latch 13 becomes low level. Because the signal held by the latch 13 is low level even in the initial state, the selection target of the VSL selector 11 does not change, and the selection targets of the first to fourth signal selectors 14 to 17 do not change either. Specifically, the VSL selector 11 continues to select the vertical signal line VSL_B. Furthermore, the first signal selector 14 selects sel1_A as the signal sel1, the second signal selector 15 selects sel2_A as the signal sel2, the third signal selector 16 selects AZ1_A as the signal sel3, and the fourth signal selector 17 selects AZ2_A as the signal sel4.

[0156] From time t7 to t9, AD conversion operation is performed during the SP2H data acquisition period. At time t8, when the second pixel signal intersects with the reference signal, the output of the comparator 121 transitions to low level. The count value of the counter 122 until the output of the comparator 121 transitions to low level represents the data (pixel signal) level of SP2H.

[0157] When the signal AZ2 of the fourth signal selector 17 goes high at time t9, the seventh switch Sw17 and the eighth switch Sw18 are turned on, and the charges stored in the third capacitor C13 and the fourth capacitor C14 are discharged. After that, when the second pixel signal intersects with the reference signal at time t11, the output signal of the comparator 121 goes low, and the count value of the counter 122 until the output signal of the comparator 121 goes low represents the data (pixel signal) level of SP2L.

[0158] Then, at time t12, a drive signal RST2 is input to the gate of the reset transistor T13, turning on the reset transistor T13. This causes the accumulated charge in the second floating diffusion region FD15b to be discharged to the power supply node. Then, at time t13, when the second pixel signal intersects with the reference signal, the output signal of the comparator 121 transitions to a low level, and the count value of the counter 122 until the output signal of the comparator 121 transitions to a low level represents the reset level of SP2L.

[0159] On the other hand, if the illuminance is determined to be less than the reference level, the operation shown in the lower half of the timing diagram in Fig. 9 is performed. The timing from times t1 to t7 in the lower half of the timing diagram in Fig. 9 is the same as that in the upper half, and illuminance determination is performed using the second photoelectric conversion unit PD11b. From time t8 onwards, exposure processing is performed using the first photoelectric conversion unit PD11b.

[0160] Even at time t7, if the second pixel signal does not intersect with the reference signal, it is determined that the illuminance is below the reference level, and the VSL selector 11 selects the vertical signal line VSL_B, the second signal selector 15 selects sel2_B as signal sel2, the third signal selector 16 selects AZ1_B as signal sel3, and the fourth signal selector 17 selects AZ2_B as signal sel4.

[0161] After time t7, the first pixel signal corresponding to the potential of the first floating diffusion region FD15a is selected by the VSL selector 11 and input to the comparator 121. When the first pixel signal intersects with the reference signal at time t8, the output signal of the comparator 121 transitions to low level, and the count value of the counter 122 until the output signal of the comparator 121 transitions to low level represents the reset level of SP1L.

[0162] At time t9, signal FDG transitions to low level, and charge-to-voltage conversion efficiency remains high until time t12. When transfer transistor T12a is turned on at time t11, charge photoelectrically converted by first photoelectric conversion unit PD11a is accumulated in first floating diffusion region FD15a via transfer transistor T12a, and the first pixel signal begins to decrease accordingly. When the first pixel signal intersects with the reference signal at time t12, the output signal of comparator 121 transitions to low level, and the count value counted by counter 122 until the output signal of comparator 121 transitions to low level represents the data (pixel signal) level of SP1H.

[0163] Then, at time t13, the signal FDG transitions to a high level, and the charge-to-voltage conversion efficiency is reduced from time t13 onwards. Also at time t13, the transfer transistor T12a is turned on, and the charge photoelectrically converted by the first photoelectric conversion unit PD11a is accumulated in the first floating diffusion region FD15a via the transfer transistor T12a. This changes the signal level of the first pixel signal input from the VSL selector 11 to the comparator 121. At time t14, when the first pixel signal intersects with the reference signal, the output signal of the comparator 121 transitions to a low level, and the count value counted by the counter 122 until the output signal of the comparator 121 transitions to a low level represents the data (pixel signal) level of SP1L.

[0164] In Figure 6, a circuit block consisting of a transfer transistor T12a, a conversion efficiency switching transistor T12c, a reset transistor T13a, an amplification transistor T16a, a selection transistor T17a, and a vertical signal line VSL_B connected to the first photoelectric conversion unit PD11a in the pixel PX, and a circuit block consisting of a transfer transistor T12d, a transfer transistor T12b, a reset transistor T13, an amplification transistor T16b, a selection transistor T17b, and a vertical signal line VSL_A connected to the second photoelectric conversion unit PD11b are provided separately, and no signals are sent or received between these circuit blocks.

[0165] In contrast to this, FIG. 10 is a circuit diagram of a pixel PX according to a comparative example in which the reset transistor T13a is shared by two circuit blocks.

[0166] FIG. 11 is a timing diagram of FIG. 10. When the illuminance is equal to or greater than the reference level, AD conversion processing is performed using the second photoelectric conversion unit PD11b. However, as shown in FIG. 11, the signal FDG, which is unrelated to the operation on the low sensitivity side, must be lowered to low level at time t7. Furthermore, when the illuminance is below the reference level, the reset transistor T13a shared by the two circuit blocks must be turned on at time t7. Furthermore, when the illuminance is below the reference level, the transfer transistor T12c, which is essentially unrelated, must be turned off at time t7.

[0167] In this way, if part of the signal path of the two circuit blocks within the pixel PX is shared, it will be necessary to feed back the illuminance determination result to the pixel control signal. To avoid this, it is desirable to provide two independent circuit blocks within the pixel PX, as shown in Figure 6.

[0168] As described above, in the image pickup device 100 according to the first embodiment, the second photoelectric conversion unit PD11b, which has a small light-receiving area, determines whether the illuminance is equal to or greater than a reference level, and if it is determined that the illuminance is equal to or greater than the reference level, multiple low-sensitivity AD conversions (AD conversions of the SP2H data (pixel signal) level, the SP2L data (pixel signal) level, and the SP2L reset level) are performed in sequence, whereas if it is determined that the illuminance is less than the reference level, multiple high-sensitivity AD conversions (AD conversions of the SP1L reset level, the SP1H data (pixel signal) levels, and the SP1L data (pixel signal) levels) are performed in sequence while switching between high sensitivity and charge-voltage conversion efficiency. In this embodiment, only AD conversion processing according to the measured illuminance is performed, which enables a faster frame rate and reduces power consumption because there is no need to frequently switch signals on the vertical signal lines.

[0169] Moreover, the ADC 105a according to the first embodiment includes a comparator 121 having a first differential transistor pair 18 and a second differential transistor pair 19. Depending on the result of the illuminance determination, the first differential transistor pair 18 and the second differential transistor pair 19 are switched and used for the comparison operation, so that it is possible to quickly switch between two types of comparison operation without any time loss.

[0170] (Second embodiment) In the second embodiment, a sample-and-hold circuit is provided in front of the ADC 105a to hold multiple pixel signals with different sensitivities and conversion efficiencies in parallel, and the pixel signals held by the sample-and-hold circuit are switched depending on the illuminance determination result.

[0171] Fig. 12 is a circuit diagram showing the configuration of the main parts of an image pickup device 100 according to the second embodiment. The image pickup device 100 in Fig. 12 includes a sample-and-hold circuit (SH) 125 between a vertical signal line VSL output from a VSL selector 11 and an ADC 105a. A VSL boost circuit 12 is connected to the vertical signal line VSL. The internal configuration of the VSL boost circuit 12 is similar to that of the VSL boost circuit 12 in Fig. 6, and therefore a detailed description thereof will be omitted.

[0172] The sample and hold circuit 125 includes a first hold circuit SHC1, a second hold circuit SHC2, a bypass signal line BP, and a multiplexer (sample and hold selector) MUX. The vertical signal line VSL output from the VSL selector 11 is connected to input nodes of the first hold circuit SHC1 and the second hold circuit SHC2, and is also directly connected to the bypass signal line BP.

[0173] (Configuration and Function of First Holding Circuit SHC1) The first holding circuit SHC1 is configured to sample and hold the pixel signal selected by the VSL selector 11. The first holding circuit SHC1 includes a capacitor Cp1, a transistor Tr1, switches Sw1 to Sw3, and a constant current source Cs1.

[0174] One end of the capacitor Cp1 is connected to the vertical signal line VSL via the switch Sw1, and can store a pixel signal, and the other end of the capacitor Cp1 is connected to the gate of the transistor Tr1.

[0175] The gate of transistor Tr1 is connected to the other end of capacitor Cp1. The drain of transistor Tr1 is connected to constant current source Cs1 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source Cs1 is connected between power supply VDD and the drain of transistor Tr1, and passes a constant current to the drain of transistor Tr1. Transistor Tr1 passes a current between its drain and source that depends on the potential of its gate. As a result, the drain of transistor Tr1 has a potential that corresponds to the potential of its gate. The drain of transistor Tr1 is connected to multiplexer MUX, and the drain voltage of transistor Tr1 is output as the output signal of first holding circuit SHC1.

[0176] The switch Sw1 is connected between the capacitor Cp1 and the vertical signal line VSL. The switch Sw2 is connected between the drain of the transistor Tr1 and one end of the capacitor Cp1. The switch Sw3 is connected between the drain of the transistor Tr1 and the other end of the capacitor Cp1.

[0177] When the first holding circuit SHC1 samples the pixel signal selected by the VSL selector 11 to the capacitor Cp1, the switches Sw1 and Sw3 are turned on (conductive). At this time, the switch Sw2 is turned off (non-conductive). As a result, the pixel signal is transmitted to one end of the capacitor Cp1, and the capacitor node opposite the gate of the transistor Tr1 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp1 holds the pixel signal, the switches Sw1 and Sw3 are turned off and the switch Sw2 is turned on. As a result, the pixel signal stored in the capacitor Cp1 is held. At this time, the transistor Tr1 is turned on (analog state) in accordance with the pixel signal, and the drain of the transistor Tr1 is maintained at a potential corresponding to the pixel signal. Therefore, the first holding circuit SHC1 outputs an output signal corresponding to the pixel signal from the drain of the transistor Tr1 to the multiplexer MUX.

[0178] (Configuration and Function of Second Holding Circuit SHC2) Similar to the first holding circuit SHC1, the second holding circuit SHC2 is provided between the pixel array unit 101 and the comparator 121 and is configured to sample and hold pixel signals. The second holding circuit SHC2 includes a capacitor Cp2, a transistor Tr2, switches Sw4 to Sw6, and a constant current source Cs2. The second holding circuit SHC2 samples pixel signals from the same vertical signal line VSL as the first holding circuit SHC1, but at different timings. Therefore, the first and second holding circuits SHC1 and SHC2 can sample and hold multiple pixel signals with different sensitivities or conversion efficiencies from the same pixel PX.

[0179] One end of the capacitor Cp2 is connected to the vertical signal line VSL via the switch Sw4, and can store a pixel signal, and the other end of the capacitor Cp2 is connected to the gate of the transistor Tr2.

[0180] The gate of transistor Tr2 is connected to the other end of capacitor Cp2. The drain of transistor Tr2 is connected to constant current source Cs2 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source Cs2 is connected between power supply VDD and the drain of transistor Tr2, and passes a constant current through the drain of transistor Tr2. Transistor Tr2 passes a current between its drain and source that depends on the potential of its gate. As a result, the drain of transistor Tr2 has a potential that corresponds to the potential of its gate. The drain of transistor Tr2 is connected to multiplexer MUX, and the drain voltage of transistor Tr2 is output as the output signal of second holding circuit SHC2.

[0181] The switch Sw4 is connected between the capacitor Cp2 and the vertical signal line VSL. The switch Sw5 is connected between the drain of the transistor Tr2 and one end of the capacitor Cp2. The switch Sw6 is connected between the drain of the transistor Tr2 and the other end of the capacitor Cp2.

[0182] When the second holding circuit SHC2 samples the pixel signal selected by the VSL selector 11 to the capacitor Cp2, the switches Sw4 and Sw6 are turned on. At this time, the switch Sw5 is turned off. As a result, the pixel signal is transmitted to one end of the capacitor Cp2, and the capacitor node opposite the gate of the transistor Tr2 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp2 holds the pixel signal, the switches Sw4 and Sw6 are turned off and the switch Sw5 is turned on. As a result, the pixel signal stored in the capacitor Cp2 is held. At this time, the gate of the transistor Tr2 is brought into a conductive state (analog state) corresponding to the pixel signal, and the drain of the transistor Tr2 is maintained at a potential corresponding to the pixel signal. Therefore, the second holding circuit SHC2 outputs an output signal corresponding to the pixel signal to the multiplexer MUX.

[0183] In this way, the first and second holding circuits SHC1 and SHC2 are each configured as active elements, which makes them resistant to fluctuations in the voltage of the ground GND and the power supply VDD, and can cancel variations in the characteristics of the transistors Tr1 and Tr2.

[0184] (Configuration and function of bypass signal line BP) The bypass signal line BP is provided between the vertical signal line VSL and the comparator 121 of the ADC group 105, and transmits the pixel signal selected by the VSL selector 11 directly via the multiplexer MUX. The bypass signal line BP directly outputs the output signal OUTbp via the multiplexer MUX without holding the pixel signal in a capacitor or the like. This prevents noise caused by the capacitors Cp1 and Cp2 and the transistors Tr1 and Tr2 from being carried over to the pixel signal. In other words, the bypass signal line BP can be used when signal degradation components added by the holding circuits SHC1 and SHC2 cannot be tolerated, for example, when high conversion efficiency is desired and noise near dark signals needs to be minimized.

[0185] (Multiplexer MUX) The multiplexer MUX is connected between the first and second holding circuits SHC1 and SHC2, the bypass signal line BP, and the comparator 121. The multiplexer MUX can selectively connect any one of the first holding circuit SHC1, the second holding circuit SHC2, and the bypass signal line BP to the comparator 121 of the ADC group 105. This allows the multiplexer MUX to selectively transmit to the comparator 121 the pixel signal held in the first holding circuit SHC1, the pixel signal held in the second holding circuit SHC2, or the pixel signal transmitted over the bypass signal line BP. The multiplexer MUX selects the holding circuits SHC1 and SHC2 or the bypass signal line BP to be connected to the comparator 121 based on a selection signal SEL2. The selection signal SEL2 is received from the vertical scanning circuit 103. The selection signal SEL2 may be set to select either the holding circuits SHC1, SHC2 or the bypass signal line BP in accordance with the control signals TGL, TGS, FDG, FCG, and SEL of the pixel PX. The multiplexer MUX may be configured with any switch circuit capable of performing the above operations.

[0186] (Configuration and Function of Comparator 121) The comparator 121 includes an input comparison circuit 121a and an output circuit 121b.

[0187] The input comparison circuit 121a includes p-type transistors Tp1 and Tp2, n-type transistors Tn1 to Tn3, capacitors Cvsl and Cref, and an AZ switch SwAZ.

[0188] One end of the capacitors Cvsl and Cref is connected to the output of the sample-and-hold circuit 125 and the reference signal line 114. The other ends of the capacitors Cvsl and Cref are commonly connected to the gate of the transistor Tp1.

[0189] The transistors Tn1, Tp1, and Tn2 are connected in series in this order between a power supply VDD and a ground GND.

[0190] The drain of the transistor Tn1 is connected to the power supply VDD, and the source of the transistor Tp1. The transistor Tn1 functions as an LDO (Low Dropout) linear regulator.

[0191] As described above, the gate of transistor Tp1 is commonly connected to the other ends of capacitors Cvsl and Cref. The source of transistor Tp1 is connected to the source of transistor Tn1, and the drain of transistor Tp1 is connected to the drain of transistor Tn2 and the gate of transistor Tp2. When the sum of the output signal from multiplexer MUX of sample-and-hold circuit 125 and reference signal RAMP from DAC 104 exceeds a threshold voltage, transistor Tp1 changes from a conductive state to a non-conductive state, inverting the voltage level of the gate of transistor Tp2 from a high level to a low level. In other words, transistor Tp1a functions as an amplifier that amplifies and detects the level of the output signal from multiplexer MUX.

[0192] The gate of the transistor Tp2 is connected to the drain of the transistor Tp1. The source of the transistor Tp2 is connected to the source of the transistor Tn1 in common with the source of the transistor Tp1. The drain of the transistor Tp2 is connected to the drain of the transistor Tn2. When the transistor Tp1 changes from a conductive state to a non-conductive state, the transistor Tp2 changes from a non-conductive state to a conductive state, thereby inverting the drain voltage of the transistor Tp2 from a low level to a high level.

[0193] The transistor Tn2 is connected between the drain of the transistor Tp1 and the ground GND and functions as a constant current source for supplying a constant current to the transistor Tp1. The transistor Tn3 is connected between the drain of the transistor Tp2 and the ground GND and functions as a constant current source for supplying a constant current to the transistor Tp2.

[0194] The AZ switch SwAZ is connected between the gate of the transistor Tp1 and the gate of the transistor Tp2, and performs an auto-zero operation by equalizing the potential between the gate and drain of the transistor Tp1 before detecting the output signal of the sample-and-hold circuit 125.

[0195] The output circuit 121b includes p-type transistors Tp3 and Tp4 and n-type transistors Tn4 and Tn5. The transistor Tp3 is connected between a power supply VDD and the output terminal OUT121 of the comparator 121. The transistor Tn5 is connected between the source of the transistor Tn4 and ground GND. The gates of the transistors Tp3 and Tn5 are connected in common. The transistors Tp3 and Tn5 fix the output OUT121 to a high level outside the count period. The transistors Tp4 and Tn4 are connected in series between the power supply VDD and the drain of the transistor Tn5. The node between the transistors Tp4 and Tn4 forms the output terminal OUT121. The gates of the transistors Tp4 and Tn4 are connected in common to the output of the input comparison circuit 121a (the drain of the transistor Tp2). The transistors Tp4 and Tn4 function as an inverter circuit.

[0196] When the drain voltage of the transistor Tp2 is inverted from low to high, the output terminal OUT of the comparator 121 is inverted from high to low by the transistors Tp4 and Tn4. The inversion of the voltage level of the output terminal OUT121 is used to stop the operation of the counter 122, thereby enabling AD conversion.

[0197] Fig. 13 is a timing diagram of the imaging device 100 of Fig. 12. As in Fig. 7, the upper half of Fig. 13 shows the timing at high illuminance, and the lower half shows the timing at low illuminance.

[0198] At the start of imaging, the VSL selector 11 selects the second pixel signal on the vertical signal line VSL_A and outputs it to the vertical signal line VSL. At time t1, the switches Sw1 and Sw3 in the first holding circuit SHC1 are turned on, and the switch Sw2 is turned off. This causes the first holding circuit SHC1 to sample the second pixel signal. The sampled second pixel signal is at the reset level of SP2H. At this time, the first holding circuit SHC1 maintains the sampling state until the potential of the second floating diffusion region FD15b stabilizes. The period during which the first holding circuit SHC1 maintains the sampling state is the settling period. Meanwhile, at time t1, the switches Sw4 to Sw6 in the second holding circuit SHC2 are off. Therefore, the second holding circuit SHC2 does not perform the settling operation of the first pixel signal at time t1.

[0199] At time t3, the switches Sw1 and Sw3 in the first holding circuit SHC1 are turned off and the switch Sw2 is turned on, whereby the sampled second pixel signal is sent to the ADC 105a and AD converted, generating reset level data for SP2H.

[0200] At time t3, the switches Sw4 and Sw6 in the second hold circuit SHC2 are turned on, and the switch Sw5 is turned off. This causes the second hold circuit SHC2 to sample the second pixel signal. The sampled second pixel signal is at the data (pixel signal) level of SP2H.

[0201] At time t4, the switches Sw4 and Sw6 in the second holding circuit SHC2 are turned off and the switch Sw5 is turned on, whereby the sampled second pixel signal is sent to the ADC 105a and AD converted to generate data at the data (pixel signal) level of SP2H.

[0202] At this time, the comparator 121 determines the illuminance based on the data (pixel signal) level of SP2H. The upper half of FIG. 13 shows the timing when the comparator 121 determines that the illuminance is high. If the illuminance is determined to be high, the VSL selector 11 does not change the selection target and continues to select the second pixel signal. At time t5, the first holding circuit SHC1 turns on the switches Sw1 and Sw3 and turns off the switch Sw2. This causes the first holding circuit SHC1 to sample the second pixel signal. The sampled second pixel signal is at the data (pixel signal) level of SP2L. Furthermore, the second holding circuit SHC2 continues to turn on the switches Sw4 and Sw6 and turn off the switch Sw5, as at time t4. This causes the ADC 105a to generate data at the data (pixel signal) level of SP2H.

[0203] Then, at time t6, the first holding circuit SHC1 turns off the switches Sw1 and Sw3 and turns on the switch Sw2. As a result, the second pixel signal sampled by the first holding circuit SHC1 is sent to the ADC 105a and is AD converted to generate data at the SP2L data (pixel signal) level. Meanwhile, the second holding circuit SHC2 turns on the switches Sw4 and Sw6 and turns off the switch Sw5. As a result, the second holding circuit SHC2 samples the second pixel signal. The sampled second pixel signal is at the SP2L reset level.

[0204] Then, at time t7, the first holding circuit SHC1 turns off the switches Sw1 to Sw3. Furthermore, the second holding circuit SHC2 turns off the switches Sw4 and Sw6 and turns on the switch Sw5. As a result, the second pixel signal sampled by the second holding circuit SHC2 is sent to the ADC 105a and AD converted, and data of the reset level of SP2L is generated.

[0205] On the other hand, if the comparator 121 determines that the illuminance is low between times t4 and t5, the operation shown in the lower half of the timing chart in Fig. 13 is performed. If the illuminance is determined to be low, the output signal of the comparator 121 remains at a high level, and the output signal of the latch 13 becomes a high level. Therefore, the VSL selector 11 switches to selecting the first pixel signal and outputs the first pixel signal to the vertical signal line VSL.

[0206] At time t5, the first holding circuit SHC1 turns on the switches Sw1 and Sw3 and turns off the switch Sw2. This causes the first holding circuit SHC1 to sample the first pixel signal. The sampled first pixel signal is at the reset level of SP1L. Meanwhile, at time t5, the second holding circuit SHC2 turns off the switches Sw4 to Sw6.

[0207] At time t6, the first holding circuit SHC1 turns off switches Sw1 and Sw3 and turns on switch Sw2. As a result, the first pixel signal sampled by the first holding circuit SHC1 is sent to the ADC 105a and is AD converted to generate data at the reset level of SP1L. In addition, the second holding circuit SHC2 turns on switches Sw4 and Sw6 and turns off switch Sw5. As a result, the second holding circuit SHC2 samples the first pixel signal. The sampled first pixel signal is at the reset level of SP1H.

[0208] At time t7, the first holding circuit SHC1 turns on the switches Sw1 and Sw3 and turns off the switch Sw2. This causes the first holding circuit SHC1 to sample the first pixel signal. The sampled first pixel signal is at the data (pixel signal) level of SP1H. Furthermore, the second holding circuit SHC2 turns off the switches Sw4 and Sw6 and turns on the switch Sw5. This causes the second pixel signal sampled by the second holding circuit SHC2 to be sent to the ADC 105a and subjected to AD conversion, generating data at the reset level of SP1H.

[0209] At time t8, the first holding circuit SHC1 turns off the switches Sw1 and Sw3 and turns on the switch Sw2. As a result, the first pixel signal sampled by the first holding circuit SHC1 is sent to the ADC 105a and is AD converted to generate data at the data (pixel signal) level of SP1H. In addition, the second holding circuit SHC2 turns on the switches Sw4 and Sw6 and turns off the switch Sw5. As a result, the second holding circuit SHC2 samples the first pixel signal. The sampled first pixel signal is at the data (pixel signal) level of SP1L.

[0210] At time t9, the first holding circuit SHC1 turns off the switches Sw1 to Sw3. Furthermore, the second holding circuit SHC2 turns off the switches Sw4 and Sw6 and turns on the switch Sw5. As a result, the second pixel signal sampled by the second holding circuit SHC2 is sent to the ADC 105a and AD converted, generating data at the data (pixel signal) level of SP1L.

[0211] 12 holds pixel signals and then AD converts the held pixel signals, the AD-converted digital pixel data may be affected by noise or offsets caused by capacitors or transistors. Therefore, at least some pixel signals may be sent to the ADC 105a without passing through the sample and hold circuit 125.

[0212] Fig. 14 is a timing diagram according to a modification of Fig. 13. The upper half of Fig. 14 shows the timing when the illuminance is determined to be high, and the lower half shows the timing when the illuminance is determined to be low. The timing in the upper half of Fig. 14 is the same as that in Fig. 13, so a description thereof will be omitted.

[0213] If the comparator 121 determines that the illuminance is low during the period from time t4 to t5, the VSL selector 11 switches to select the first pixel signal and outputs the first pixel signal to the vertical signal line VSL. At time t5, the first holding circuit SHC1 turns on the switches Sw1 and Sw3 and turns off the switch Sw2 to sample the first pixel signal. The sampled first pixel signal is at the reset level of SP1L. Furthermore, the second holding circuit SHC2 turns off the switches Sw4 to Sw6 during the period from time t5 to t10.

[0214] At time t6, the first pixel signal generated in the pixel PX is sent directly to the ADC 105a via the VSL selector 11. This first pixel signal corresponds to the reset level of SP1H. Because it takes time for the potential of the first floating diffusion region FD15a in the pixel PX to stabilize, the first pixel signal is continuously sent to the ADC 105a from time t6 to t7. The period from time t6 to t7 is a settling period for the first pixel signal. At time t7, the ADC 105a performs AD conversion on the first pixel signal to generate data at the reset level of SP1H.

[0215] At time t8, the first pixel signal generated in the pixel PX is sent directly to the ADC 105a via the VSL selector 11. This first pixel signal corresponds to the data (pixel signal) level of SP1H. Because it takes time for the potential of the first floating diffusion region FD15a in the pixel PX to stabilize, the first pixel signal is continuously sent to the ADC 105a during the period from time t8 to t9. The period from time t8 to t9 is a settling period for the first pixel signal. At time t9, the ADC 105a performs AD conversion on the first pixel signal to generate data at the data (pixel signal) level of SP1H.

[0216] At time t10, the first holding circuit SHC1 turns off the switches Sw1 and Sw3 and turns on the switch Sw2. As a result, the first pixel signal sampled by the first holding circuit SHC1 at time t5 is sent to the ADC 105a and A / D converted, generating data at the reset level of SP1L. In addition, the second holding circuit SHC2 turns on the switches Sw4 and Sw6 and turns off the switch Sw5. As a result, the second holding circuit SHC2 samples the first pixel signal. The sampled first pixel signal is at the data (pixel signal) level of SP1L.

[0217] At time t11, the first holding circuit SHC1 turns off the switches Sw1 to Sw3. Furthermore, the second holding circuit SHC2 turns off the switches Sw4 and Sw6 and turns on the switch Sw5. As a result, the second pixel signal sampled by the second holding circuit SHC2 is sent to the ADC 105a and AD converted, generating data at the data (pixel signal) level of SP1L.

[0218] As described above, in the image capture device 100 of FIG. 12, the first holding circuit SHC1 and the second holding circuit SHC2 in the sample-and-hold circuit 125 alternately sample pixel signals. While one of the first holding circuit SHC1 and the second holding circuit SHC2 is settling the pixel signal, the other sends the settled pixel signal to the ADC 105a. This allows AD conversion to be performed without being limited by the settling time of the pixel signal. Furthermore, like the image capture device 100 of FIG. 6, the image capture device 100 of FIG. 12 determines illuminance using the first photoelectric conversion unit PD11a, which has a small light-receiving area, and performs multiple AD conversion processes that match the determined illuminance, thereby enabling a faster frame rate. Furthermore, power consumption can be reduced because the pixel signal on the vertical signal line VSL does not need to be frequently switched.

[0219] (Cross-sectional structure of the imaging device 100) The imaging device 100 according to the first or second embodiment can be realized by a single semiconductor chip. Fig. 15 is a cross-sectional view of a semiconductor chip 30 incorporating the imaging device 100 according to the first or second embodiment. The semiconductor chip 30 in Fig. 15 is roughly divided into three semiconductor regions (hereinafter, first to third semiconductor regions 31 to 33). The first to third semiconductor regions 31 to 33 are stacked in order, and each semiconductor region may be formed of a plurality of semiconductor layers.

[0220] A first photoelectric conversion unit PD11a with a large light-receiving area and a second photoelectric conversion unit PD11b with a small light-receiving area are arranged in the first semiconductor region 31 on the light incident surface side for each pixel PX. A part of the readout circuit may be arranged in the first semiconductor region 31. An on-chip lens 34 is arranged on the light incident surface side of the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b. In addition, a light-shielding layer 37 is arranged between the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b.

[0221] At least a part of the readout circuit of each pixel PX (for example, an amplification transistor, a selection transistor, etc.) is arranged in the second semiconductor region 32. In the third semiconductor region 33, the ADC group 105 and the like are arranged.

[0222] The first semiconductor region 31 and the second semiconductor region 32 are stacked on, for example, a first substrate 35. The third semiconductor region 33 is formed on, for example, a second substrate 36. The first substrate 35 and the second substrate 36 are joined by Cu-Cu connections 38, vias, bumps, or the like.

[0223] (Plane layout of the imaging device 100) FIG. 16 is a planar layout diagram of the light incident surface side of the imaging device 100 according to the first and second embodiments. As shown in FIG. 16, a first on-chip lens 151 is disposed on a rectangular first photoelectric conversion unit PD11a. An inter-pixel light shielding unit 181 is disposed around the first photoelectric conversion unit PD11a. The outer shape of the inter-pixel light shielding unit 181 is octagonal, and a gap is generated between adjacent inter-pixel light shielding units. A rectangular second photoelectric conversion unit PD11b is disposed in this gap. A second on-chip lens 152 is disposed on the second photoelectric conversion unit PD11b.

[0224] Fig. 16 is an example of a planar layout, and is not limited to this. Fig. 17 is a planar layout diagram according to a modified example. In Fig. 16, the shape of the inter-pixel light-shielding portion is close to a regular octagon, whereas in Fig. 17, the shape is an octagon formed by cutting the four corners of a rectangle. In addition, the inter-pixel light-shielding portion of the second photoelectric conversion unit PD11b is not octagonal but rectangular.

[0225] <Application to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0226] FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0227] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0228] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0229] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0230] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0231] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0232] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0233] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0234] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0235] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0236] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to passengers in the vehicle or to the outside of the vehicle. In the example of Fig. 18, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0237] FIG. 19 is a diagram showing an example of the installation position of the imaging unit 12031.

[0238] In FIG. 19, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0239] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0240] 19 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0241] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0242] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0243] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0244] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0245] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above. Specifically, the imaging device 100 according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a clearer captured image can be obtained, thereby reducing driver fatigue.

[0246] The present technology can be configured as follows: (1) a first photoelectric conversion unit; a first readout circuit that outputs a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit to a first signal line; a second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit; a second readout circuit that outputs a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit to a second signal line; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing it with a reference signal whose potential level changes over time. (2) A plurality of pixels arranged in a first direction and a second direction; the first pixel signal and the second pixel signal output from each of two or more pixels arranged in the second direction are output to a common first signal line and a common second signal line, respectively; the analog-to-digital converter is arranged for each pixel column consisting of two or more pixels arranged in the second direction, each of the plurality of pixels includes the first photoelectric conversion unit, the first readout circuit, the second photoelectric conversion unit, and the second readout circuit; The imaging device according to (1), wherein the pixel signal selector is provided for each of the pixel columns arranged in the second direction. (3) The analog-to-digital converter a comparator that compares the pixel signal selected by the pixel signal selector with the reference signal; a counter that performs a counting operation until the comparator detects a match between the pixel signal and the reference signal, The imaging device according to (1) or (2), wherein the digital pixel signal is generated according to the pixel signal selected by the pixel signal selector based on the count value of the counter. (4) a comparator compares the pixel signal selected by the pixel signal selector with the reference signal to determine whether the illuminance at the start of imaging is equal to or greater than a predetermined reference level; The imaging device described in (3), wherein the pixel signal selector selects the second pixel signal when the illuminance at the start of imaging is equal to or greater than the reference level, and selects the first pixel signal when the illuminance is less than the reference level. (5) a first floating diffusion region that accumulates charges photoelectrically converted by the first photoelectric conversion unit; a second floating diffusion region that accumulates charges photoelectrically converted by the second photoelectric conversion unit, The imaging device described in (4), wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of the comparator comparing the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region with the reference signal. (6) When starting imaging, the comparator performs a first comparison process to compare the second pixel signal corresponding to the potential of the second floating diffusion region in a state where the charge in the second floating diffusion region has been discharged with the reference signal, and then performs a second comparison process to compare the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region with the reference signal; The imaging device according to (5), wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of the second comparison process. (7) The comparator determines whether the illuminance at the start of image capture is equal to or greater than the reference level through the second comparison process; The imaging device described in (6), wherein the pixel signal selector selects the second pixel signal when the illuminance is equal to or greater than the reference level, and selects the first pixel signal when the illuminance is less than the reference level. (8) In the imaging device described in (7), when the second comparison process determines that the illuminance is equal to or greater than the reference level, the comparator performs a third comparison process in which the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region is compared with the reference signal, and then performs a fourth comparison process in which the second pixel signal corresponding to the potential of the second floating diffusion region in a state in which the charge in the second floating diffusion region has been drained is compared with the reference signal. (9) The first readout circuit is capable of varying charge-to-voltage conversion efficiency; The imaging device according to (7) or (8), wherein, when the second comparison process determines that the illuminance is less than the reference level, the comparator performs a fifth comparison process in which the first pixel signal corresponding to the potential of the first floating diffusion region in a state in which the charge of the first floating diffusion region has been discharged is compared with the reference signal; then, a sixth comparison process in which the first pixel signal corresponding to the potential of the first floating diffusion region in a state in which the charge of the first floating diffusion region has been discharged with a charge-to-potential conversion efficiency higher than that of the fifth comparison process is compared with the reference signal; then, a seventh comparison process in which the first pixel signal corresponding to the charge photoelectrically converted in the first photoelectric conversion unit with the same charge-to-potential conversion efficiency as that of the sixth comparison process is compared with the reference signal; and then, an eighth comparison process in which the first pixel signal corresponding to the charge photoelectrically converted in the first photoelectric conversion unit with the same charge-to-potential conversion efficiency as that of the fifth comparison process is compared with the reference signal. (10) The comparator a first differential transistor pair that compares the pixel signal selected by the pixel signal selector with the reference signal when the illuminance is determined to be less than the reference level in the second comparison process; The imaging device according to any one of (6) to (9), further comprising: a second differential transistor pair that compares the pixel signal selected by the pixel signal selector with the reference signal when the first comparison process is performed and when the second comparison process determines that the illuminance is equal to or greater than the reference level. (11) The first differential transistor pair includes a first transistor and a second transistor; the second differential transistor pair includes a third transistor and a fourth transistor; The comparator a first switch and a first capacitor connected in series between the gate of the first transistor and an output node of the pixel signal selector; a second switch and a second capacitor connected in series between the gate of the second transistor and the input node of the reference signal; a third switch and a third capacitor connected in series between the gate of the third transistor and the output node of the pixel signal selector; a fourth switch and a fourth capacitor connected in series between the gate of the fourth transistor and the input node of the reference signal; a fifth switch that switches whether or not the gate and drain of the first transistor are short-circuited; a sixth switch that switches whether or not the gate and the drain of the second transistor are short-circuited; a seventh switch that switches whether or not the gate and drain of the third transistor are short-circuited; and an eighth switch that switches whether or not the gate and drain of the fourth transistor are short-circuited. (12) The imaging device described in (11), wherein, when starting imaging at each pixel, the comparator turns off the first switch, the second switch, the third switch, and the fourth switch, turns on the fifth switch and the sixth switch, and turns on the seventh switch and the eighth switch once and then turns them off, thereby accumulating charge corresponding to the second pixel signal selected by the pixel signal selector in the third capacitor and accumulating charge corresponding to the reference signal in the fourth capacitor. (13) A sample and hold circuit includes first and second holding circuits that alternately hold pixel signals selected by the pixel signal selector, and a sample and hold selector that alternately selects and outputs the pixel signals held by the first and second holding circuits, The imaging device according to (1) or (2), wherein the analog-to-digital converter converts the output signal of the sample-and-hold circuit into the digital pixel signal. (14) An imaging device as described in (13), wherein, during a period in which one of the first and second holding circuits inputs the pixel signal it has held to the analog-to-digital converter, the other of the first and second holding circuits holds the pixel signal selected by the pixel signal selector. (15) The analog-to-digital converter a comparator that compares the output signal of the sample-and-hold circuit with the reference signal; a counter that performs a counting operation until a match between the output signal and the reference signal is detected by the comparator, The imaging device according to (13) or (14), wherein the digital pixel signal is generated according to the pixel signal selected by the pixel signal selector based on the count value of the counter. (16) The comparator determines whether the illuminance at the start of imaging is equal to or greater than a predetermined reference level by comparing the output signal of the sample-and-hold circuit with the reference signal; The imaging device described in (15), wherein the pixel signal selector selects the second pixel signal when the illuminance at the start of imaging is equal to or greater than the reference level, and selects the first pixel signal when the illuminance is less than the reference level. (17) a first floating diffusion region that accumulates charges photoelectrically converted by the first photoelectric conversion unit; a second floating diffusion region that accumulates charges photoelectrically converted by the second photoelectric conversion unit, The imaging device described in (16), wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of the comparator comparing the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region with the reference signal. (18) When starting imaging, the first holding circuit holds the second pixel signal corresponding to the potential of the second floating diffusion region in a state where the charge of the second floating diffusion region is discharged, and then inputs the held second pixel signal to the comparator; the second holding circuit holds the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region in synchronization with a timing at which the first holding circuit inputs the second pixel signal to the comparator, and then inputs the held second pixel signal to the comparator; The imaging device described in (17), wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal output from the second holding circuit with the reference signal by the comparator. (19) The sample and hold circuit is capable of outputting at least a part of the pixel signal selected by the pixel signal selector without holding it; The imaging device described in (16), wherein when the comparator determines that the second pixel signal is less than the reference signal, the sample and hold circuit inputs at least a portion of the pixel signal selected by the pixel signal selector to the comparator without holding it. (20) An imaging device that outputs a digital pixel signal corresponding to an imaged pixel signal; a signal processing unit that performs signal processing based on the digital pixel signal, The imaging device is a first photoelectric conversion unit; a first readout circuit that outputs a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit to a first signal line; a second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit; a second readout circuit that outputs a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit to a second signal line; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing it with a reference signal whose potential level changes over time.

[0247] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0248] 1 solid-state imaging device, 11 VSL selector, 12 VSL boost circuit, 13 latch, 14 first signal selector, 15 second signal selector, 16 fourth signal selector, 16 third signal selector, 17 fourth signal selector, 18 first differential transistor pair, 19 second differential transistor pair, 20 current mirror circuit, 21 current source, 22 output circuit, 30 semiconductor chip, 31 first semiconductor region, 32 second semiconductor region, 33 third semiconductor region, 34 on-chip lens, 35 first substrate, 36 second substrate, 37 light-shielding layer, 38 Cu-Cu connection, 100 imaging device, 101 pixel array section, 102 timing control circuit, 103 vertical scanning circuit, 104 charge storage section, 105 ADC group, 106 horizontal transfer scanning circuit, 107 amplifier circuit, 108 signal processing circuit, 109 pixel drive line, 110 vertical signal line, 111 Horizontal transfer line, 114 reference signal line, 121 comparator, 121a input comparison circuit, 121b output circuit, 122 counter, 123 latch circuit, 125 sample hold circuit, 151 first on-chip lens, 152 second on-chip lens, 181 inter-pixel light shielding portion, 310 negative capacitance circuit, 511 semiconductor chip, 512 semiconductor chip, 513 via region, 514 via region, 516 logic circuit, 517 peripheral circuit

Claims

1. a first photoelectric conversion unit; a first readout circuit that outputs a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit to a first signal line; a second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit; a second readout circuit that outputs a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit to a second signal line; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing it with a reference signal whose potential level changes over time.

2. a plurality of pixels arranged in a first direction and a second direction; the first pixel signal and the second pixel signal output from each of two or more pixels arranged in the second direction are output to a common first signal line and a common second signal line, respectively; the analog-to-digital converter is arranged for each pixel column consisting of two or more pixels arranged in the second direction, each of the plurality of pixels includes the first photoelectric conversion unit, the first readout circuit, the second photoelectric conversion unit, and the second readout circuit; The imaging device according to claim 1 , wherein the pixel signal selector is provided for each of the pixel columns arranged in the second direction.

3. The analog-to-digital converter a comparator that compares the pixel signal selected by the pixel signal selector with the reference signal; a counter that performs a counting operation until a match between the pixel signal and the reference signal is detected by the comparator, The imaging device according to claim 1 , wherein the digital pixel signal is generated according to the pixel signal selected by the pixel signal selector based on the count value of the counter.

4. the comparator determines whether or not the illuminance at the start of imaging is equal to or greater than a predetermined reference level by comparing the pixel signal selected by the pixel signal selector with the reference signal; 4. The imaging device according to claim 3, wherein the pixel signal selector selects the second pixel signal when the illuminance at the start of imaging is equal to or greater than the reference level, and selects the first pixel signal when the illuminance is less than the reference level.

5. a first floating diffusion region that accumulates charges photoelectrically converted by the first photoelectric conversion unit; a second floating diffusion region that accumulates charges photoelectrically converted by the second photoelectric conversion unit, 5. The imaging device according to claim 4, wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of a comparison made by the comparator between the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region and the reference signal.

6. the comparator, when starting imaging, performs a first comparison process of comparing the second pixel signal corresponding to the potential of the second floating diffusion region in a state in which the charge of the second floating diffusion region has been discharged with the reference signal, and then performs a second comparison process of comparing the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region with the reference signal; The imaging device according to claim 5 , wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of the second comparison process.

7. the comparator determines whether or not the illuminance at the start of image capture is equal to or greater than the reference level through the second comparison process; 7. The imaging device according to claim 6, wherein the pixel signal selector selects the second pixel signal when the illuminance is equal to or greater than the reference level, and selects the first pixel signal when the illuminance is less than the reference level.

8. 8. The imaging device according to claim 7, wherein, when the second comparison process determines that the illuminance is equal to or greater than the reference level, the comparator performs a third comparison process in which the comparator compares the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region with the reference signal, and then performs a fourth comparison process in which the comparator compares the second pixel signal corresponding to the potential of the second floating diffusion region in a state in which the charge of the second floating diffusion region has been drained with the reference signal.

9. the first readout circuit is capable of varying charge-to-voltage conversion efficiency; 8. The imaging device of claim 7, wherein, when the second comparison process determines that the illuminance is less than the reference level, the comparator performs a fifth comparison process in which the first pixel signal corresponding to the potential of the first floating diffusion region in a state where charge from the first floating diffusion region has been discharged is compared with the reference signal; then, a sixth comparison process in which the first pixel signal corresponding to the potential of the first floating diffusion region in a state where charge from the first floating diffusion region has been discharged is compared with the reference signal with a charge-to-potential conversion efficiency higher than that of the fifth comparison process; then, a seventh comparison process in which the first pixel signal corresponding to charge photoelectrically converted in the first photoelectric conversion unit at the same charge-to-potential conversion efficiency as that of the sixth comparison process is compared with the reference signal; and then, an eighth comparison process in which the first pixel signal corresponding to charge photoelectrically converted in the first photoelectric conversion unit at the same charge-to-potential conversion efficiency as that of the fifth comparison process is compared with the reference signal.

10. The comparator a first differential transistor pair that compares the pixel signal selected by the pixel signal selector with the reference signal when the illuminance is determined to be less than the reference level in the second comparison process; 7. The imaging device according to claim 6, further comprising: a second differential transistor pair that compares the pixel signal selected by the pixel signal selector with the reference signal when the first comparison process is performed and when the second comparison process determines that the illuminance is equal to or greater than the reference level.

11. the first differential transistor pair includes a first transistor and a second transistor; the second differential transistor pair includes a third transistor and a fourth transistor; The comparator a first switch and a first capacitor connected in series between the gate of the first transistor and an output node of the pixel signal selector; a second switch and a second capacitor connected in series between the gate of the second transistor and the input node of the reference signal; a third switch and a third capacitor connected in series between the gate of the third transistor and the output node of the pixel signal selector; a fourth switch and a fourth capacitor connected in series between the gate of the fourth transistor and an input node of the reference signal; a fifth switch that switches whether or not the gate and the drain of the first transistor are short-circuited; a sixth switch that switches whether or not the gate and the drain of the second transistor are short-circuited; a seventh switch that switches whether or not the gate and drain of the third transistor are short-circuited; The imaging device according to claim 10 , further comprising: an eighth switch that switches whether or not the gate and the drain of the fourth transistor are short-circuited.

12. 12. The imaging device according to claim 11, wherein, when starting imaging at each pixel, the comparator turns off the first switch, the second switch, the third switch, and the fourth switch, turns on the fifth switch and the sixth switch, and turns on the seventh switch and the eighth switch once and then turns them off, thereby storing, in the third capacitor, a charge corresponding to the second pixel signal selected by the pixel signal selector, and storing, in the fourth capacitor, a charge corresponding to the reference signal.

13. a sample and hold circuit including first and second holding circuits that alternately hold pixel signals selected by the pixel signal selector, and a sample and hold selector that alternately selects and outputs the pixel signals held by the first and second holding circuits; 2. The imaging device according to claim 1, wherein the analog-to-digital converter converts the output signal of the sample-and-hold circuit into the digital pixel signal.

14. 14. The imaging device according to claim 13, wherein, during a period in which one of the first and second holding circuits inputs the held pixel signal to the analog-to-digital converter, the other of the first and second holding circuits holds the pixel signal selected by the pixel signal selector.

15. The analog-to-digital converter a comparator that compares the output signal of the sample-and-hold circuit with the reference signal; a counter that performs a counting operation until a match between the output signal and the reference signal is detected by the comparator, The imaging device according to claim 13 , wherein the digital pixel signal is generated according to the pixel signal selected by the pixel signal selector based on the count value of the counter.

16. the comparator determines whether the illuminance at the start of imaging is equal to or greater than a predetermined reference level by comparing the output signal of the sample-and-hold circuit with the reference signal; 16. The imaging device according to claim 15, wherein the pixel signal selector selects the second pixel signal when the illuminance at the start of imaging is equal to or greater than the reference level, and selects the first pixel signal when the illuminance is less than the reference level.

17. a first floating diffusion region that accumulates charges photoelectrically converted by the first photoelectric conversion unit; a second floating diffusion region that accumulates charges photoelectrically converted by the second photoelectric conversion unit, 17. The imaging device according to claim 16, wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of a comparison made by the comparator between the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region and the reference signal.

18. the first holding circuit holds the second pixel signal corresponding to the potential of the second floating diffusion region in a state where the charge of the second floating diffusion region has been discharged when starting imaging, and thereafter inputs the held second pixel signal to the comparator; the second holding circuit holds the second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit and accumulated in the second floating diffusion region in synchronization with a timing at which the first holding circuit inputs the second pixel signal to the comparator, and then inputs the held second pixel signal to the comparator; 18. The imaging device according to claim 17, wherein the pixel signal selector selects the first pixel signal or the second pixel signal based on a result of the comparator comparing the second pixel signal output from the second holding circuit with the reference signal.

19. the sample and hold circuit is capable of outputting, without holding, at least a portion of the pixel signal selected by the pixel signal selector; 17. The imaging device according to claim 16, wherein when the comparator determines that the second pixel signal is less than the reference signal, the sample-and-hold circuit inputs at least a portion of the pixel signal selected by the pixel signal selector to the comparator without holding it.

20. an imaging device that outputs a digital pixel signal corresponding to an imaged pixel signal; a signal processing unit that performs signal processing based on the digital pixel signal, The imaging device is a first photoelectric conversion unit; a first readout circuit that outputs a first pixel signal corresponding to the charge photoelectrically converted by the first photoelectric conversion unit to a first signal line; a second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit; a second readout circuit that outputs a second pixel signal corresponding to the charge photoelectrically converted by the second photoelectric conversion unit to a second signal line; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing it with a reference signal whose potential level changes over time.

Images