Discharge circuit for NAND flash memory

The discharge circuit for 3D NAND flash memory uses a MOSFET-based transistor and SL detection to control discharge timing, addressing junction breakdown and reliability issues by maintaining a constant voltage difference.

JP7789853B2Active Publication Date: 2025-12-22YANGTZE MEMORY TECH CO LTD
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Patent Information

Application Number
JP2024104630
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2024-06-28
Publication Date
2025-12-22
Estimated Expiration
2042-02-18

AI Technical Summary

Technical Problem

The challenge in 3D NAND flash memory is the efficient and reliable discharge of high potentials on bit lines and common source lines after erase operations, which can lead to junction breakdown and reduced transistor performance due to improper timing of discharge transistor switching.

Method used

A discharge circuit with a MOSFET-based discharge transistor, a gate discharge circuit, and an SL detection circuit are used to maintain a constant voltage difference, ensuring controlled discharge by comparing the source line potential with predetermined values and regulating the discharge current.

Benefits of technology

This approach prevents junction breakdown and FN stress, maintaining transistor reliability and performance by ensuring precise timing of discharge operations.

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Abstract

To provide a method for discharging a memory device after an erase operation.SOLUTION: This method includes the steps of: grounding a source line of a memory device; and turning on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. This method also includes the steps of: comparing a potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the potential of the source line is less than the first predetermined value.SELECTED DRAWING: Figure 5
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Citation Information

Patent Citations

  • Semiconductor storage device

    JP2019197603A

  • Controlling discharge of a control gate voltage

    US20190206481A1