Package including a substrate and a high density interconnect integrated device coupled to the substrate - Patent Application 20070122997

Abstract

The package includes a substrate, an integrated device, and an interconnected integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is bonded to the substrate. The interconnected integrated device is bonded to a surface of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for electrical signals of the integrated device, the electrical path traveling at least through the substrate, then through the interconnected integrated device, and again through the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Nonprovisional Application No. 17 / 017,361, filed in the United States Patent and Trademark Office on September 10, 2020, and Provisional Application No. 62 / 993,544, filed in the United States Patent and Trademark Office on March 23, 2020, the entire contents of which are incorporated herein by reference as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates. [Background technology]

[0003] FIG. 1 shows a package 100 including a substrate 102, an integrated device 104, an integrated device 106, and an encapsulation layer 108. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. The encapsulation layer 108 encapsulates the integrated device 104 and the integrated device 106. Manufacturing small packages including substrates with high-density interconnects can be difficult. There is a current need to provide more compact packages that can accommodate high-density interconnects and / or high pin counts. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates.

[0005] One example provides a package including a substrate, an integrated device, and an interconnected integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is bonded to the substrate. The interconnected integrated device is bonded to a surface of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and again through the substrate.

[0006] Another example provides an apparatus including a substrate, an integrated device, and a means for integrated device interconnection. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is bonded to the substrate. The means for integrated device interconnection is bonded to a surface of the substrate. The integrated device, the means for integrated device interconnection, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the means for integrated device interconnection, and again through the substrate.

[0007] In another example, a method for manufacturing a package is provided. The method provides a substrate including a first surface and a second surface, the substrate further including a plurality of interconnects. The method bonds an integrated device to the substrate. The method bonds an interconnected integrated device to a surface of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and again through the substrate.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a side view of a package including an integrated device and a substrate. [Figure 2] FIG. 1 is a side view of a package including a high density interconnect integrated device bonded to a substrate. [Figure 3] 1 is a diagram of possible electrical paths within a package including a high density interconnect integrated device bonded to a substrate. [Figure 4] 1 is a diagram of possible electrical paths within a package including a high density interconnect integrated device bonded to a substrate. [Figure 5] 1 is a diagram of possible electrical paths within a package including a high density interconnect integrated device bonded to a substrate. [Figure 6] 1 is a diagram of a possible electrical path for a package-on-package (PoP) including a high density interconnect integrated device bonded to a substrate. [Figure 7] FIG. 1 is a side view of a package including a high density interconnect integrated device bonded to a substrate. [Figure 8A] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 8B] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 8C] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 8D] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 9] 1 is an exemplary flow diagram of a method for manufacturing a high density interconnect integrated device. [Figure 10A] FIG. 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10B] FIG. 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10C] FIG. 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 11] 1 is an exemplary flow diagram of a method for manufacturing a substrate. [Figure 12A]1A-1C illustrate an exemplary sequence for manufacturing a package including a high density interconnect integrated device bonded to a substrate. [Figure 12B] 1A-1C illustrate an exemplary sequence for manufacturing a package including a high density interconnect integrated device bonded to a substrate. [Figure 13] 1 is an exemplary flow diagram of a method for manufacturing a package including a high density interconnect integrated device bonded to a substrate. [Figure 14] 1A-1C illustrate various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (PIDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description, specific details are set forth to enable a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate, an electronic circuit (which may be formed in an integrated device), and an interconnected integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing electrical paths to a board. The integrated device is coupled to the first surface (or the second surface) of the substrate. The interconnected integrated device is coupled to the first surface (or the second surface) of the substrate. The integrated device, the interconnected integrated device, and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, and again through the substrate. The integrated device, the interconnected integrated device, and the substrate are coupled together such that the electrical path for the electrical signal of the integrated device extends (e.g., travels) through the substrate, then through the interconnected integrated device, and again through the substrate. The interconnected integrated device may provide at least one electrical path (e.g., electrical connection) between two integrated devices coupled to the substrate. The interconnect integrated device may be a substrate including at least one dielectric layer and a plurality of interconnects. The interconnect integrated device may be a high-density interconnect integrated device configured with interconnects having a minimum pitch smaller than the minimum pitch of the interconnects from the substrate. The interconnect integrated device may enable a package to have a small and compact form factor while simultaneously providing a high input / output (I / O) pin count. The interconnect integrated device may provide improved voltage drop for the integrated devices, higher capacitance density, shorter paths between the integrated devices, and / or lower inductance.

[0012] Exemplary Package Including a High Density Interconnect Integrated Device Bonded to a Substrate 2 shows a side view of a package 200 containing high-density interconnected integrated devices. Package 200 is coupled to a board 290 (e.g., a printed circuit board (PCB)) through a plurality of solder interconnects 280. Package 200 provides a package with a high input / output pin count while simultaneously having a compact, small form factor. Package 200 offers improved capacitance density, shorter paths between integrated devices, lower inductance, and / or fewer routing constraints.

[0013] 2, package 200 includes substrate 202, first integrated device 204, second integrated device 206, encapsulation layer 208, interconnect integrated device 201, integrated device 205, and integrated device 207. Interconnect integrated device 201 may be configured as a bridge between two or more integrated devices. As described further below, the integrated devices (e.g., 204, 206), interconnect integrated device (e.g., 201), and substrate 202 are coupled together such that when an electrical signal (e.g., a first electrical signal, a second electrical signal) travels between the two integrated devices (e.g., 204, 206) and the board (e.g., 290), the electrical signal travels through at least substrate 202, then through the interconnect integrated device (e.g., 201), and again through substrate 202. This may be achieved by the interconnect integrated device (e.g., 201) providing at least one electrical path between a first electrical contact provided by the substrate 202 and a second electrical contact provided by the substrate 202, the first contact electrically connected to the integrated device (e.g., 204, 206) and the second contact electrically connected to one or more of the interconnects. In the above example, the interconnect integrated device 201 may be configured as a bridge such that at least one electrical signal may travel through the interconnect integrated device 201 when traveling between two integrated devices (e.g., 204, 206) and / or through the board (e.g., 290). The at least one electrical signal may travel through at least one electrical path defined by the package interconnects, the integrated device, the substrate, and / or the interconnect integrated device.

[0014] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The plurality of interconnects 222 may be configured to provide at least one electrical path to and / or from a board (e.g., 290). The plurality of interconnects 222 may provide at least one electrical path to at least one integrated device (e.g., 204, 205, 206, 207). The plurality of interconnects 222 may provide at least one electrical path (e.g., electrical connection) between two or more integrated devices (e.g., 204, 205, 206, 207). The plurality of interconnects 222 may have a first minimum pitch and a first minimum line and spacing (L / S). In some implementations, the first minimum pitch for the plurality of interconnects 222 is approximately in the range of 100 to 200 microns (μm). In some implementations, the first minimum line width and spacing (L / S) for the plurality of interconnects 222 is approximately in the range of 9 / 9 to 12 / 12 microns (μm) (e.g., a minimum line width of approximately 9 to 12 microns (μm) and a minimum spacing of approximately 9 to 12 microns (μm)). Various implementations may use different substrates. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer. In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The at least one dielectric layer 220 may have a dielectric constant approximately in the range of 3.5 to 3.7. The at least one dielectric layer 220 may include glass fiber to reinforce the substrate 202. An example of manufacturing a substrate is further described below in Figures 10A-10C. As described further below, in some implementations, the substrate 202 may be manufactured using a modified semi-adaptive process (mSAP) or a semi-adaptive process (SAP).

[0015] A first integrated device 204 is coupled to a first surface (e.g., a top surface) of the substrate 202. The first integrated device 204 is coupled to the substrate through a plurality of interconnects 240. The plurality of interconnects 240 may include copper pillars and / or solder interconnects. An underfill 243 is located between the substrate 202 and the first integrated device 204. The underfill 243 may surround the plurality of interconnects 240. A second integrated device 206 is coupled to a first surface (e.g., a top surface) of the substrate 202. The second integrated device 206 is coupled to the substrate through a plurality of interconnects 260. The plurality of interconnects 260 may include copper pillars and / or solder interconnects. The underfill 263 is located between the substrate 202 and the second integrated device 206. The underfill 263 may surround the plurality of interconnects 240.

[0016] The integrated device 205 is coupled to a second side (e.g., a bottom side) of the substrate 202. The integrated device 205 is coupled to the substrate through a plurality of interconnects 250. The plurality of interconnects 250 may include copper pillars and / or solder interconnects. An underfill 252 is located between the substrate 202 and the integrated device 205. The underfill 252 may surround the plurality of interconnects 250. The integrated device 207 is coupled to a second side (e.g., a bottom side) of the substrate 202. The integrated device 207 is coupled to the substrate through a plurality of interconnects 270. The plurality of interconnects 270 may include copper pillars and / or solder interconnects. The underfill 272 is located between the substrate 202 and the integrated device 207. The underfill 272 may surround the plurality of interconnects 270. Integrated device 205 and integrated device 207 may be laterally positioned with a plurality of solder interconnects 280 .

[0017] The interconnected integrated device 201 is coupled to a first surface of the substrate 202. As described further below, the interconnected integrated device 201 can be a high-density interconnected integrated device. The interconnected integrated device 201 can be coupled to the substrate 202 through a plurality of solder interconnects 210 and / or pillar interconnects (e.g., copper pillar interconnects). The interconnected integrated device 201 is located between the first integrated device 204 and the second integrated device 206. This configuration helps improve package performance by reducing routing congestion within the substrate 202 and / or by reducing paths for current (e.g., signals) between the integrated devices. The end result is a package with a more compact form factor. Additionally, the interconnected integrated device 201 can help lower the cost of the substrate 202. Because the interconnects of the interconnect integrated device 201 support near-die breakout, the interconnects of the substrate 202 do not need to be as close together (e.g., lower L / S) to achieve near-die breakout. As described further below, at least one interconnect integrated device may be disposed on another surface of the substrate 202. In some implementations, the interconnect integrated device may be integrated or embedded within the substrate 202. The interconnect integrated device may be configured to provide at least one electrical path for at least one electrical signal. As described further below, the interconnect integrated device (e.g., 201, 701) may be configured as a bridge. The interconnect integrated device (e.g., 201, 701) may include a die (e.g., a passive device die). An interconnect integrated device configured as a bridge and / or a passive device die may be free of active devices such as transistors. Thus, an interconnect integrated device configured as a bridge and / or a passive device die may be free of transistors.

[0018] The encapsulation layer 208 is disposed on a first surface (e.g., a top surface) of the substrate 202 such that the encapsulation layer 208 encapsulates the first integrated device 204, the second integrated device 206, and the interconnected integrated device 201. The encapsulation layer 208 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 208 may be a means for encapsulation.

[0019] The integrated devices (e.g., 204, 205, 206, 207) may include a die (e.g., a semiconductor bare die). The integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. The integrated devices (e.g., 204, 205, 206, 207) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0020] Various implementations may couple different components to the substrate 202. Other components (e.g., surface-mounted components) that may be coupled to the substrate 202 include passive devices (e.g., capacitors).

[0021] The interconnect integrated device 201 can be a high-density interconnect integrated device having a second minimum pitch and a second minimum line width and spacing (L / S). In some implementations, the second minimum pitch for the interconnects of the interconnect integrated device (e.g., 201) is approximately in the range of 100 to 200 microns (μm). In some implementations, the second minimum line width and spacing (L / S) for the interconnects of the interconnect integrated device (201, 701) is approximately in the range of 2 1 / 2 to 5 1 / 5 microns (μm) (e.g., approximately 2 to 5 microns (μm) minimum line width, approximately 2 to 5 microns (μm) minimum spacing). For example, as shown in FIG. 7, the interconnect integrated device 201 and the interconnect integrated device 701 can each have interconnects with a respective second minimum pitch that is smaller than the first minimum pitch of the substrate 202. Similarly, interconnected integrated device 201 and interconnected integrated device 701 may each have interconnects with a respective minimum pitch that is smaller than the first minimum line width and spacing (L / S) of substrate 202. The pitch may be defined as the center-to-center distance between two adjacent interconnects. The interconnected integrated devices (e.g., 201, 701) are localized integrated devices configured to be installed in a region close to the integrated device. The size of the interconnected integrated device may vary with various implementations. However, the footprint of the interconnected integrated device is smaller than the footprint of substrate 202.

[0022] As described further below, some electrical signals (e.g., first electrical signal, second electrical signal) to and from the integrated devices (e.g., 204, 206) may be configured to travel through the interconnect integrated device 201. An interconnect integrated device with a higher density of interconnects may allow the package 200 to provide a higher I / O pin count without having to increase the size of the package 200. For example, using the interconnect integrated device 201 may allow the substrate 202 to have a fewer number of metal layers, which may help reduce the overall height of the package 200. One or more interconnect integrated devices 201 may help reduce congestion and / or entanglement in some areas of the substrate 202 (e.g., areas close to the integrated devices) due to a high pin count and / or a large number of netlists. The interconnect integrated device 201 may have a lower height than the first integrated device 204 and / or the second integrated device 206.

[0023] FIG. 2 shows that the interconnect integrated device 201 includes at least one dielectric layer 211, a plurality of interconnects 212, a passivation layer 214, and a substrate 216. The substrate 216 may include silicon (Si), glass, or quartz. The substrate 216 may be a die substrate. The interconnect integrated device 201 may include a front side and a back side. The back side of the interconnect integrated device 201 may be the side that includes the substrate 216. The front side of the interconnect integrated device 201 may be the side that includes the passivation layer 214 and / or the side to which the solder interconnects are bonded to the interconnect integrated device 201. The front side of the interconnect integrated device may be opposite the back side of the interconnect integrated device. As described further below, the interconnect integrated device 201 (and / or any of the interconnect integrated devices described in this disclosure) may be configured as a bridge. The interconnect integrated device 201 may include a die (e.g., a passive device die). An interconnected integrated device configured as a bridge and / or passive device die may be free of active devices such as transistors. Thus, an interconnected integrated device configured as a bridge and / or passive device die may be free of transistors. As described above, the interconnected integrated device interconnects may have a higher density (e.g., a lower minimum pitch and / or a lower minimum L / S) than the interconnects of the substrate 202. A passivation layer 214 is disposed on a first surface of the interconnected integrated device 201. A plurality of solder interconnects 210 are coupled to the first surface of the interconnected integrated device 201.

[0024] As mentioned above, interconnect integrated devices can be components coupled to the substrate 202, which can allow the package 200 to offer higher I / O pin counts and / or shorter paths between integrated devices without having to increase the overall size of the package 200. In some implementations, one or more electrical signals to and from one or more integrated devices can travel through one or more interconnect integrated devices. One or more interconnect integrated devices (e.g., 201) can help reduce congestion and / or entanglement in some areas of the substrate due to high pin counts and / or multiple netlists. A netlist is the arrangement of components of a circuit and how the components are electrically coupled together. One or more interconnect integrated devices 201 can have improved capacitance density, result in shorter paths between integrated devices, facilitate lower inductance, and / or reduce routing constraints.

[0025] In some implementations, the at least one dielectric layer 211 may include a prepreg layer and / or a photosensitive dielectric layer. The at least one dielectric layer 211 may have a dielectric constant in the range of approximately 3.3 to 4.0. In some implementations, the at least one dielectric layer 211 of the interconnect integrated device may include glass fibers. However, the glass fibers are finer than the glass fibers in the at least one dielectric layer 220 of the substrate 202.

[0026] Figure 3 shows a diagram of how electrical signals may be conceptually configured to travel within a package. Figure 3 shows (i) a first electrical path 301 for a first electrical signal, (ii) a second electrical path 302 for a second electrical signal, (iii) a third electrical path 303 for a third electrical signal, and (iv) a fourth electrical path 304 for a fourth electrical signal. The first electrical path 301 may be configured to allow signals to travel between the first integrated device 204 and the interconnect integrated device 201. The second electrical path 302 may be configured to allow signals to travel between the second integrated device 206 and the interconnect integrated device 201. The third electrical path 303 may be configured to allow signals to travel between the first integrated device 204 and the interconnect integrated device 201. The fourth electrical pathway 304 may be configured to allow signals to travel between the second integrated device 206 and the interconnected integrated device 201. The electrical pathway 311 may be coupled to the electrical pathway 301 and the electrical pathway 302. The electrical pathway 313 may be coupled to the electrical pathway 303 and the electrical pathway 304. The electrical pathway 311 may include an interconnect from the interconnected integrated device 201. The electrical pathway 313 may include an interconnect from the interconnected integrated device 201.

[0027] In some implementations, the first integrated device 204 and the second integrated device 206 may be configured to be electrically coupled to one another through the substrate 202 and the interconnected integrated device 201. For example, at least one electrical current (e.g., an electrical signal) between the first integrated device 204 and the second integrated device 206 may travel through the substrate 202, the interconnected integrated device 201, and back through the substrate.

[0028] In one example, the first electrical path 301 and the second electrical path 302 may be configured to be coupled together (e.g., electrically coupled) such that the first integrated device 204 and the second integrated device 206 are configured to be electrically coupled together through the interconnected integrated device 201. Thus, as an example, the first integrated device 204 and the second integrated device 206 are configured to be electrically coupled together such that at least one current (e.g., an electrical signal) between the first integrated device 204 and the second integrated device 206 travels through (i) a first interconnect from the plurality of interconnects 240, (ii) a first interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a first solder interconnect from the plurality of solder interconnects 210, (iv) a first interconnect (e.g., 212) from the interconnect integrated device 201, (v) a second solder interconnect from the plurality of solder interconnects 210, (vi) a second interconnect from the plurality of interconnects 222 of the substrate 202, and (vii) a first solder interconnect from the plurality of interconnects 260.

[0029] The first electrical path 301 may include (i) a first interconnect from the plurality of interconnects 240, (ii) a first interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a first solder interconnect from the plurality of solder interconnects 210, and / or (iv) a first interconnect (e.g., 212) from the interconnect integrated device 201.

[0030] The second electrical path 302 may include (i) a first interconnect from the plurality of interconnects 260, (ii) a second interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a second solder interconnect from the plurality of solder interconnects 210, and / or (iv) a first interconnect (e.g., 212) from the interconnect integrated device 201.

[0031] The third electrical path 303 may include (i) a first interconnect from the plurality of interconnects 240, (ii) a first interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a first solder interconnect from the plurality of solder interconnects 210, and / or (iv) a first interconnect (e.g., 212) from the interconnect integrated device 201.

[0032] The fourth electrical path 304 may include (i) a first interconnect from the plurality of interconnects 260, (ii) a second interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a second solder interconnect from the plurality of solder interconnects 210, and / or (iv) a first interconnect (e.g., 212) from the interconnect integrated device 201.

[0033] It should be noted that two or more of the various electrical pathways described in this disclosure may be configured to be electrically coupled to one another. For example, electrical pathway 303 may be configured to be electrically coupled to electrical pathway 304 (e.g., through electrical pathway 313). In another example, electrical pathway 301 may be configured to be electrically coupled to electrical pathway 302 (e.g., through electrical pathway 311). It should be noted that the electrical pathways for one or more signals may enter or exit through the front face of the interconnect integrated device (e.g., 201). This means that at least one electrical signal traveling through the interconnect integrated device may (i) enter through the front face of the interconnect integrated device, (ii) travel through an interconnect within the interconnect integrated device, and (iii) exit through the front face of the interconnect integrated device. For example, at least one electrical signal may enter through electrical pathway 301, travel through interconnect integrated device 201, and exit through electrical pathway 302, or vice versa. Various implementations may have different numbers of electrical signals traveling to and from different integrated devices. The paths of these electrical signals may vary. The electrical signals may include I / O signals. Instead of I / O signals, the example paths shown in this disclosure may also be applicable to power and / or ground.

[0034] Figure 4 shows another diagram of how an electrical signal may conceptually travel through a package. Figure 4 shows a substrate 402, a first integrated device 204 coupled to the substrate 402, a second integrated device 206 coupled to the substrate 402, and an interconnected integrated device 201 coupled to the substrate 402. The substrate 402 may be similar to the substrate 202 and, therefore, may include similar components as the substrate 202. The substrate 402 may be implemented within any of the packages described in this disclosure.

[0035] 4 shows an interconnected integrated device 201 located between a first integrated device 204 and a second integrated device 206. The first integrated device 204, the second integrated device 206, and the interconnected integrated device 201 are disposed on a surface (e.g., a first surface, a second surface) of a substrate 402.

[0036] The first integrated device 204 includes electrical pathways 410, 411, 412, 440, 441, 442, and 443 for electrical current (e.g., electrical signals) to the first integrated device 204. The electrical pathways 410, 411, 412, 440, 441, 442, and 443 may be conceptual representations of example pathways for electrical current to and from the first integrated device 204. The electrical pathways may include interconnects and / or solder interconnects. The electrical pathways 410, 411, 412, 443, and / or 463 may represent paths by which at least one electrical signal may enter or exit through the front surface of the interconnect integrated device 201.

[0037] The second integrated device 206 includes electrical paths 410, 411, 412, 460, 461, 462, and 463 for electrical current (e.g., electrical signals) to the second integrated device 206. The electrical paths 410, 411, 412, 460, 461, 462, and 463 may be conceptual representations of example paths for electrical current to and from the second integrated device 206. The electrical paths may include interconnects and / or solder interconnects.

[0038] 4, the first integrated device 204 and the second integrated device 206 may be configured to be electrically coupled together through electrical pathways 410, 411, and 412. The electrical pathways 410, 411, and 412 are electrical paths along which current (e.g., signals) travel through the interconnected integrated device 201. The electrical pathways 410, 411, and 412 may include interconnects within the substrate 402 and interconnects within the interconnected integrated device 201. The electrical pathways 410, 411, and / or 412 may be similar to combinations of the electrical pathways (e.g., (301, 302, 311), (303, 304, 313)) of FIG. 3. Each electrical pathway (440, 441, 442, 460, 461, and 463) may include its own respective interconnect from the plurality of interconnects 222 of the substrate 402.

[0039] 4 shows that an electrical path to an integrated device may include the interconnected integrated device 201 even if the electrical path does not provide an electrical path between two integrated devices. For example, a signal traveling through electrical path 443 may mean that a signal to and from the first integrated device 204 may travel through the interconnected integrated device 201 even if the signal does not terminate at the second integrated device 206. Similarly, a signal traveling through electrical path 463 may mean that a signal to and from the second integrated device 206 may travel through the interconnected integrated device 201 even if the signal does not terminate at the first integrated device 204.

[0040] Various implementations may have different numbers of electrical paths and / or different routing of the electrical paths.

[0041] Figure 5 shows another diagram of how electrical signals may conceptually travel through a package. Figure 5 shows a substrate 502, a first integrated device 204 coupled to the substrate 502, a second integrated device 206 coupled to the substrate 502, an interconnected integrated device 201 coupled to the substrate 502, an integrated device 504 coupled to the substrate 502, and an integrated device 506 coupled to the substrate 502. The substrate 502 may be similar to the substrate 202 and, therefore, may include similar components as the substrate 202. The substrate 502 may be implemented within any of the packages described in this disclosure.

[0042] 5 shows that first integrated device 204 includes electrical pathways 530, 531, 540, and 541. Second integrated device 206 includes electrical pathways 530, 532, and 560. Integrated device 504 includes electrical pathways 533, 541, and 542. Integrated device 506 includes electrical pathways 531, 532, 533, and 561. Each electrical pathway (540, 541, 542, 560, and 561) may include its own respective interconnect from the plurality of interconnects 222 of substrate 502. Electrical pathways 530, 531, 532, and / or 533 may represent a path through which at least one electrical signal may enter or exit through the front surface of interconnect integrated device 201.

[0043] The first integrated device 204 is coupled to the integrated device 504 through electrical pathways 541. The first integrated device 204 is coupled to the second integrated device 206 through electrical pathways 530. The electrical pathways 530 include interconnects from the interconnected integrated device 201. Thus, the first integrated device 204 can be coupled to the second integrated device 206 through the substrate 502 and the interconnected integrated device 201. The first integrated device 204 is coupled to the integrated device 506 through electrical pathways 531. The electrical pathways 531 include interconnects from the interconnected integrated device 201. Thus, the first integrated device 204 can be coupled to the integrated device 506 through the substrate 502 and the interconnected integrated device 201.

[0044] The second integrated device 206 is coupled to the integrated device 506 through electrical pathways 532. The electrical pathways 532 include interconnects from the interconnected integrated device 201. Thus, the second integrated device 206 can be coupled to the integrated device 506 through the substrate 502 and the interconnected integrated device 201.

[0045] Integrated device 504 is coupled to integrated device 506 through electrical pathways 533. Electrical pathways 533 include interconnects from interconnected integrated device 201. Thus, integrated device 504 can be coupled to integrated device 506 through substrate 502 and interconnected integrated device 201.

[0046] Figure 6 shows another diagram of how electrical signals may conceptually travel through a package. Figure 6 shows a substrate 602, a first integrated device 204 coupled to the substrate 602, a second integrated device 206 coupled to the substrate 602, an interconnected integrated device 601a coupled to the substrate 602, an interconnected integrated device 601b coupled to the substrate 602, an interconnected integrated device 601c coupled to the substrate 602, an integrated device 504 coupled to the substrate 602, and an integrated device 506 coupled to the substrate 602. The substrate 602 may be similar to the substrate 202 and therefore may include similar components as the substrate 202. The interconnected integrated devices (e.g., 601a, 601b, 601c) may be similar to the interconnected integrated device 201 and therefore may include similar components as the interconnected integrated device 201. The substrate 602 and interconnected integrated devices (eg, 601a, 601b, 601c) may be packaged within any of the packages described in this disclosure.

[0047] 6 shows that the first integrated device 204 is coupled to the second integrated device 206 through an electrical pathway 630. The electrical pathway 630 includes interconnects in the substrate 602 and interconnected integrated device 601a. ​​Thus, the first integrated device 204 can be coupled to the second integrated device 206 through the substrate 602 and the interconnected integrated device 601a.

[0048] The first integrated device 204 is coupled to the integrated device 506 through an electrical pathway 631. The electrical pathway 631 includes interconnects in the substrate 602, interconnects in the interconnected integrated device 601a, and interconnects in the interconnected integrated device 601b. Thus, the first integrated device 204 can be coupled to the integrated device 506 through the substrate 602, the interconnected integrated device 601a, and the interconnected integrated device 601b.

[0049] The second integrated device 206 is coupled to the integrated device 506 through an electrical pathway 632. The electrical pathway 632 includes interconnects in the substrate 602 and interconnected integrated device 601c. Thus, the second integrated device 206 can be coupled to the integrated device 506 through the substrate 602 and the interconnected integrated device 601c.

[0050] Integrated device 504 is coupled to integrated device 506 through electrical pathway 633. Electrical pathway 633 includes interconnects in substrate 602 and interconnected integrated device 601b. Thus, integrated device 504 can be coupled to integrated device 506 through substrate 602 and interconnected integrated device 601b.

[0051] Electrical paths 630, 631, 632, and / or 633 may indicate paths through which at least one electrical signal may enter or exit through the front surface of an interconnected integrated device (e.g., 601a, 601b, 601c). The paths taken by various electrical signals may be similar to the electrical paths shown in FIG. 3 . However, it should be noted that the paths of electrical signals shown in this disclosure are exemplary and / or conceptual. Various implementations may use different paths for electrical signals. Moreover, electrical signals and / or electrical paths may travel through various types of interconnects (e.g., vias, traces, pads, pillars), solder interconnects, and / or components (e.g., passive devices). Thus, for example, in some implementations, electrical signals traveling between an integrated device and an interconnected integrated device may travel through at least one intervening component (e.g., passive device, capacitor) between the integrated device and the interconnected integrated device. The paths shown for electrical signals may also apply to power and / or ground.

[0052] As mentioned above, a package may include different components located on different portions of a substrate and / or different numbers of components. Figure 7 shows a package 700 including interconnected integrated devices. Package 700 is similar to package 200 of Figure 2 and includes similar components to package 200. Package 700 includes first integrated device 204, second integrated device 206, integrated device 705, integrated device 707, interconnected integrated device 201, and interconnected integrated device 701.

[0053] 7, integrated device 705, integrated device 707, and interconnected integrated device 701 are coupled to a second surface (e.g., a bottom surface) of substrate 202. Integrated device 705, integrated device 707, and interconnected integrated device 701 may be positioned laterally relative to a plurality of solder interconnects 280.

[0054] The second interconnected integrated device 701 is similar to the interconnected integrated device 201. The second interconnected integrated device 701 may include the same components and / or materials as the interconnected integrated device 201. The second interconnected integrated device 701 may include a different number of metal layers than the interconnected integrated device 201. The interconnected integrated device may be used to provide at least one electrical path between two or more integrated devices. For example, an electrical signal between a first integrated device and a second integrated device may travel through a substrate (e.g., through a first plurality of interconnects in the substrate), through the interconnected integrated device (e.g., through a plurality of interconnects in the interconnected integrated device), and back through the substrate (e.g., through a second plurality of interconnects in the substrate). The first integrated device and the second integrated device may be located on the same surface of the substrate or on different surfaces of the substrate. The terms "first side" and "second side" of the substrate are arbitrary and may refer to either surface of the substrate. For example, the first side of the substrate can be the bottom side of the substrate, and the second side of the substrate can be the top side of the substrate. In another example, the first side of the substrate can be the top side of the substrate, and the second side of the substrate can be the bottom side of the substrate. The interconnected integrated device (e.g., 201, 701) can be a means for interconnecting integrated devices. One example of a method for fabricating an interconnected integrated device is shown and described in Figures 8A-8D below.

[0055] Interconnected integrated device 701 may be coupled to the plurality of interconnects 222 through a plurality of interconnects 710. The plurality of interconnects 710 may include copper pillars and / or solder interconnects. Integrated device 705 may be coupled to the plurality of interconnects 222 through a plurality of interconnects 750. The plurality of interconnects 750 may include copper pillars and / or solder interconnects. Integrated device 707 may be coupled to the plurality of interconnects 222 through a plurality of interconnects 770. The plurality of interconnects 770 may include copper pillars and / or solder interconnects. Interconnected integrated device 701 is located between integrated device 705 and integrated device 707. Integrated device 705 and integrated device 707 may be configured to be electrically coupled to each other through interconnected integrated device 701.

[0056] Integrated device 705 may be coupled to interconnected integrated device 701 through electrical pathway 702. Integrated device 707 may be coupled to interconnected integrated device 701 through electrical pathway 704. Integrated device 705 may be coupled to integrated device 707 through electrical pathway 702 and electrical pathway 704.

[0057] The electrical pathway 702 may include (i) a first interconnect from the plurality of interconnects 750, (ii) a first interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a first solder interconnect from the plurality of interconnects 710, and / or (iv) a first interconnect (e.g., 212) from the interconnect integrated device 701.

[0058] The electrical pathway 704 may include (i) a first interconnect from the plurality of interconnects 770, (ii) a second interconnect from the plurality of interconnects 222 of the substrate 202, (iii) a second solder interconnect from the plurality of interconnects 710, and / or (iv) a first interconnect (e.g., 212) from the interconnect integrated device 701.

[0059] The first integrated device 204 may be coupled to the integrated device 705 through an electrical pathway 706. The electrical pathway 706 may include (i) a first interconnect from the plurality of interconnects 750, (ii) a first interconnect from the plurality of interconnects 222 of the substrate 202, and / or (iii) a first solder interconnect from the plurality of interconnects 250. It should be noted that two or more of the various electrical pathways described in this disclosure may be configured to be electrically coupled to one another. For example, the electrical pathway 702 may be configured to be electrically coupled to the electrical pathway 704. In another example, the electrical pathway 702 may be configured to be electrically coupled to the electrical pathway 706. It should be noted that the electrical pathway for one or more signals may enter or exit through a front surface of the interconnect integrated device (e.g., 201, 601a, 601b, 601c, 701). That means that electrical signals traveling through the interconnect integrated device may (i) enter through a front surface of the interconnect integrated device, (ii) travel through interconnects within the interconnect integrated device, and (iii) exit through a front surface of the interconnect integrated device. For example, at least one electrical signal may enter through electrical path 702, travel through interconnect integrated device 701, and exit through electrical path 704, or vice versa.

[0060] It should be noted that the configurations and electrical paths described in Figures 4-6 may be applicable to the configuration in Figure 7. Any of the packages described in this disclosure may be part of a package-on-package (PoP). Additionally, the packages described in this disclosure (e.g., 200, 700) may be coupled to an interposer.

[0061] In some implementations, the interconnect integrated device (e.g., 201, 701) may be configured to include or be configured as a passive device (e.g., a capacitor). For example, the interconnect integrated device may be configured as a decoupling integrated device. At least one passive device of the interconnect integrated device may be configured as an electrical decoupler for a power delivery network (PDN) for the package. When the interconnect integrated device includes at least one passive device, such as a capacitor, one or more of the electrical paths described in this disclosure may travel through the at least one passive device of the interconnect integrated device.

[0062] A passive device such as a capacitor may be a metal-insulator-metal (MIM) capacitor formed based on interconnects on two metal layers of an interconnected integrated device. A high-K dielectric layer may be disposed between the interconnects on the two metal layers that define the MIM capacitor. For example, an MIM capacitor in an interconnected integrated device may be defined by interconnects on two metal layers from a plurality of interconnects 212. A high-K dielectric layer (which may be different from dielectric layer 211) may be disposed between the interconnects on the two metal layers that define the MIM capacitor. The capacitor may have a dielectric constant of approximately 25 nanofarads per square millimeter (nF / mm 2 )~1000nF / mm 2 The capacitor may be a high density capacitor having a capacitance density in the range of 0.1 to 1.0 volts, an equivalent series inductance (ESL) of 40 petahenries (pH) or less, and a frequency response of 1 gigahertz (GHz) or greater.

[0063] Exemplary Sequence for Fabricating High Density Interconnect Integrated Devices 8A-8D illustrate an example sequence for providing or manufacturing a high-density interconnect integrated device. In some implementations, the sequence of Figures 8A-8D can be used to provide or manufacture the interconnect integrated device 201 of Figure 2 or any of the interconnect integrated devices described in this disclosure.

[0064] 8A-8D may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing an interconnected integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. Various implementations may manufacture interconnected integrated devices differently.

[0065] 8A, stage 1 represents the state after the substrate 216 is prepared. The substrate 216 may include glass and / or silicon.

[0066] Stage 2 shows the state after a plurality of interconnects 822 have been formed on the substrate 216. The plurality of interconnects 822 may include traces and / or pads. Forming the plurality of interconnects 822 may include forming a seed layer, performing a lithography process, a plating process, a removal process, and / or an etching process. The plurality of interconnects 822 may be part of the plurality of interconnects 212.

[0067] Stage 3 shows the state after a dielectric layer 830 is formed over the plurality of interconnects 822 and the substrate 216. The dielectric layer 830 may be deposited and / or coated over the plurality of interconnects 822 and the dielectric layer 820. The dielectric layer 830 may include a polymer. The dielectric layer 830 may be similar to the dielectric layer 211.

[0068] Stage 4 shows the state after a cavity 831 has been formed in the dielectric layer 830. An etching process may be used to form the cavity 831.

[0069] Stage 5, as shown in FIG. 8B , depicts the state after a plurality of interconnects 832 are formed on the dielectric layer 830. The plurality of interconnects 832 may include vias, traces, and / or pads. Forming the plurality of interconnects 832 may include performing lithography processes, plating processes, removal processes, and / or etching processes. The plurality of interconnects 832 may be part of the plurality of interconnects 212.

[0070] Stage 6 shows the state after a dielectric layer 840 is formed over the plurality of interconnects 832 and the dielectric layer 830. The dielectric layer 840 may be deposited and / or coated over the plurality of interconnects 832 and the dielectric layer 830. The dielectric layer 840 may include a polymer. The dielectric layer 840 may be similar to the dielectric layer 830.

[0071] Stage 7 shows the state after a cavity 841 has been formed in the dielectric layer 840. An etching process may be used to form the cavity 841.

[0072] Stage 8 shows the state after a plurality of interconnects 842 are formed on the dielectric layer 840. The plurality of interconnects 842 may include vias, traces, and / or pads. Forming the plurality of interconnects 842 may include performing lithography processes, plating processes, removal processes, and / or etching processes. The plurality of interconnects 842 may be part of the plurality of interconnects 212.

[0073] Stage 9, as shown in FIG. 8C , depicts the state after a dielectric layer 850 is formed over the plurality of interconnects 842 and the dielectric layer 840. The dielectric layer 850 may be deposited and / or coated over the plurality of interconnects 842 and the dielectric layer 840. The dielectric layer 850 may include a polymer. The dielectric layer 850 may be similar to the dielectric layer 840.

[0074] Stage 10 shows the state after a cavity 851 has been formed in the dielectric layer 850. An etching process may be used to form the cavity 851.

[0075] Stage 11 shows the state after a plurality of interconnects 852 are formed on the dielectric layer 850. The plurality of interconnects 852 may include vias, traces, and / or pads. Forming the plurality of interconnects 852 may include performing lithography processes, plating processes, removal processes, and / or etching processes. The plurality of interconnects 852 may be part of the plurality of interconnects 212.

[0076] Stage 12 depicts the state after passivation layer 214 is formed over at least one dielectric layer 211, as shown in FIG. 8D . At least one dielectric layer 211 may represent dielectric layers 830, 840, and 850. Stage 12 may depict multiple interconnects 212, which may include multiple interconnects 832, 842, and / or 852.

[0077] Stage 13 shows the state after multiple solder interconnects 210 have been bonded to the interconnect integrated device 201. Stage 13 may represent an example of the interconnect integrated device 201 described in FIG. 2. In some implementations, the interconnect integrated device 201 is part of a wafer, and singulation may be performed to cut the wafer into individual interconnect integrated devices. In some implementations, the sequence of FIGS. 8A-8D may be used to fabricate the interconnect integrated device 701.

[0078] As described above, the interconnect integrated device may be configured to include or be configured as at least one passive device. A passive device, such as a capacitor, may be a metal-insulator-metal (MIM) capacitor formed based on interconnects (e.g., 822, 832, 842) from any two metal layers of the interconnect integrated device. A high-K dielectric layer (which may be different from dielectric layers 830, 840, and / or 850) may be formed between the interconnects from the two metal layers of the interconnect integrated device. The high-K dielectric layer may be formed similarly to any of the dielectric layers described above. Other dielectric layers (e.g., 830, 840, 850) may surround the high-K dielectric layer. At least one passive device of the interconnect integrated device may be configured as an electrical decoupler for a power delivery network (PDN) for the package.

[0079] Illustrative flow diagram of a method for fabricating a high density interconnect integrated device In some implementations, manufacturing a package including a high-density interconnect integrated device involves several processes. Figure 9 shows an example flow diagram of a method 900 for providing or manufacturing a high-density interconnect integrated device. In some implementations, the method 900 of Figure 9 may be used to provide or manufacture the high-density interconnect integrated devices (e.g., 201, 701) of Figure 2 and / or Figure 7 described in this disclosure. However, the method 900 may be used to provide or manufacture any of the interconnect integrated devices described in this disclosure.

[0080] It should be noted that the method of FIG. 9 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an interconnect integrated device. In some implementations, the order of the processes may be changed or modified. FIG. 9 is described in terms of manufacturing a redistribution interconnect. However, the method of FIG. 9 may be used to manufacture any type of interconnect.

[0081] The method provides (at 905) a substrate (e.g., 216). The substrate 216 can include glass, quartz, and / or silicon. Stage 1 of Figure 8A shows an example of a substrate.

[0082] The method forms (at 910) a first metal layer by forming a plurality of interconnects 822 over a substrate (e.g., 216). Forming the plurality of interconnects may include performing a lithography process, performing a plating process, performing a removal process, and / or performing an etching process. Stage 2 of Figure 8A illustrates an example of forming a first metal layer for a high-density interconnect integrated device.

[0083] The method forms (at 915) a second metal layer by forming a dielectric layer (e.g., 830) and a plurality of interconnects 832 over the first metal layer. The dielectric layer may include a polymer. Forming the dielectric layer and the plurality of interconnects may include disposing a dielectric layer 830 over the dielectric layer 820 and the interconnects 822, performing a lithography process, performing a plating process, performing a removal process, and / or performing an etching process. Stages 3-5 of FIGS. 8A-8B illustrate an example of forming a second metal layer (e.g., a redistribution layer, a redistribution metal layer) for a high-density interconnect integrated device. The redistribution layer (RDL) may be in the form of a metallization layer. The RDL may include interconnects that include a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side shapes of the interconnects and / or the redistribution interconnects. The U-shaped interconnects and V-shaped interconnects may have a top and a bottom. The bottom of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or V-shaped interconnect). Forming the metal and dielectric layers may include using wiring or back end of line (BEOL) processes.

[0084] The method forms (at 920) an additional metal layer by forming one or more dielectric layers (e.g., 840, 850) and a plurality of interconnects (e.g., 842, 852) over the second metal layer. The dielectric layers may include a polymer. Forming the dielectric layer and the plurality of interconnects may include disposing one or more dielectric layers (e.g., 840, 850) over the dielectric layer 830 and the interconnects 832, performing a lithography process, performing a plating process, performing a removal process, and / or performing an etching process. Stages 7-11 of Figures 8B-8C illustrate an example of forming an additional metal layer for a high-density interconnect integrated device. Forming the additional metal layer and additional dielectric layer may include using wiring or back-end (BEOL) processes.

[0085] The method forms (at 925) a passivation layer (e.g., 214) on the dielectric layer of the interconnect integrated device (e.g., 201). The passivation layer (e.g., 214) may be disposed on the dielectric layer 211. Stage 12 of Figure 8D illustrates one example of a passivation layer formed on the dielectric layer of the interconnect integrated device.

[0086] The method includes (at 930) bonding a plurality of solder interconnects (e.g., 210) to an interconnect integrated device (e.g., 201). Stage 13 of Figure 8D may show an example of solder interconnects bonded to an interconnect integrated device.

[0087] In some implementations, the interconnected integrated device 201 is part of a wafer, and singulation may be performed to cut the wafer into individual interconnected integrated devices. The method 900 may be used to fabricate an interconnected integrated device 201 that includes multiple interconnects 212.

[0088] Exemplary Sequence for Fabricating a Substrate In some implementations, manufacturing a substrate includes several processes. Figures 10A-10C show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of Figures 10A-10C may be used to provide or manufacture substrate 202 of Figure 2. However, the processes of Figures 10A-10C may be used to manufacture any of the substrates described in this disclosure.

[0089] 10A-10C may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0090] 10A, stage 1 shows the state after a carrier 1000 is provided and a metal layer is formed on the carrier 1000. The metal layer may be patterned to form interconnects 1002. Plating and etching processes may be used to form the metal layer and the interconnects.

[0091] Stage 2 shows the state after a dielectric layer 1020 has been formed over the carrier 1000 and interconnects 1002. The dielectric layer 1020 may include polyimide. However, various implementations may use different materials for the dielectric layer.

[0092] Stage 3 shows the state after the plurality of cavities 1010 have been formed in the dielectric layer 1020. The plurality of cavities 1010 may be formed using an etching process (e.g., a photoetching process) or a laser process.

[0093] Stage 4 shows the state after interconnects 1012 have been formed in and on the dielectric layer 1020. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0094] Stage 5 shows the state after another dielectric layer 1022 is formed over dielectric layer 1020. Dielectric layer 1022 can be the same material as dielectric layer 1020. However, various implementations may use different materials for the dielectric layers.

[0095] Stage 6, as shown in Figure 10B, depicts the state after a plurality of cavities 1030 have been formed in the dielectric layer 1022. An etching process or a laser process may be used to form the cavities 1030.

[0096] Stage 7 shows the state after interconnects 1014 have been formed in and on the dielectric layer 1022. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0097] Stage 8 shows the state after another dielectric layer 1024 is formed over dielectric layer 1022. Dielectric layer 1024 can be the same material as dielectric layer 1020. However, various implementations may use different materials for the dielectric layers.

[0098] Stage 9 shows the state after a plurality of cavities 1040 have been formed in the dielectric layer 1024. An etching process or a laser process may be used to form the cavities 1040.

[0099] Stage 10, as shown in Figure 10C, depicts the state after interconnects 1016 have been formed in and on the dielectric layer 1024. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0100] Some or all of the interconnects 1002, 1012, 1014 and / or 1016 may define the plurality of interconnects 222 of the substrate 202. The dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 220.

[0101] Stage 11 shows the state after carrier 1000 has been decoupled (eg, stripped, polished away) from dielectric layer 220 , leaving substrate 202 behind.

[0102] Stage 12 shows the state after a first solder resist layer 224 and a second solder resist layer 226 have been formed on the substrate 202 .

[0103] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0104] 1 is an exemplary flow diagram of a method for manufacturing a substrate; In some implementations, manufacturing a substrate includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or manufacturing a substrate. In some implementations, the method 1100 of Figure 11 can be used to provide or manufacture the substrate of Figure 2. For example, the method of Figure 11 can be used to manufacture the substrate 202.

[0105] 11 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0106] The method provides (at 1105) a carrier 1000. Various implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier tape. Stage 1 of Figure 10A shows the state after the carrier is provided.

[0107] The method forms (at 1110) a metal layer on the carrier 1000. The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and interconnects. Stage 1 of Figure 10A shows the state after the metal layer and interconnects 1002 have been formed.

[0108] The method forms (at 1115) a dielectric layer 1020 over the carrier 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Stages 2-3 of FIG. 10A illustrate forming the dielectric layer and the cavities in the dielectric layer.

[0109] The method forms (at 1120) interconnects in and on the dielectric layer. For example, interconnects 1012 may be formed in and on dielectric layer 1020. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Stage 4 of FIG. 10A shows an example of forming interconnects in and on the dielectric layer.

[0110] The method forms (at 1125) a dielectric layer 1022 over the dielectric layer 1020 and the interconnects. The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Stages 5-6 of Figures 10A-10B illustrate forming the dielectric layer and the cavities in the dielectric layer.

[0111] The method forms (at 1130) interconnects in and / or on the dielectric layer. For example, interconnect 1014 may be formed. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer. Stage 7 of FIG. 10B shows an example of forming interconnects in and on the dielectric layer.

[0112] The method may form additional dielectric layers and additional interconnects as described at 1125 and 1130. Stages 8-10 of Figures 10B-10C show an example of forming interconnects in and on a dielectric layer.

[0113] Once all the dielectric layers and additional interconnects have been formed, the method may decouple (e.g., remove or polish away) the carrier (e.g., 1000) from the dielectric layer 1020, leaving the substrate. In some implementations, the method may form a solder resist layer (e.g., 224, 226) over the substrate.

[0114] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0115] Exemplary Sequence for Manufacturing a Package Including a High Density Interconnect Integrated Device Bonded to a Substrate 12A-12B illustrate an exemplary sequence for providing or manufacturing a package including a high-density interconnect integrated device coupled to a substrate. In some implementations, the sequence of FIG. 12A-12B can be used to provide or manufacture package 200 including substrate 202 and interconnect integrated device 201 of FIG. 2, or any of the packages described in this disclosure.

[0116] It should be noted that the sequence of Figures 12A-12B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. The sequence of Figures 12A-12B may be used to manufacture one package or several packages simultaneously (as part of a wafer).

[0117] As shown in FIG. 12A, stage 1 represents the state after the substrate 202 is prepared. The substrate 202 may be provided by a supplier or may be manufactured. A process similar to that shown in FIGS. 10A-10C may be used to manufacture the substrate 202. However, various implementations may use different processes to manufacture the substrate 202. Examples of processes that may be used to manufacture the substrate 202 include semi-additive processing (SAP) and modified semi-additive processing (mSAP). The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer. In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer.

[0118] Stage 2 shows the state after the integrated device 205 and the integrated device 207 are bonded to a second side (e.g., a bottom side) of the substrate 202. The integrated device 205 is bonded to the substrate 202 through a plurality of interconnects 250. The plurality of interconnects 250 may be bonded to interconnects from the plurality of interconnects 222 of the substrate 202. The integrated device 205 may be bonded to the substrate 202 such that a front side (e.g., an active side) of the integrated device 205 faces the substrate 202. The integrated device 207 is bonded to the substrate 202 through a plurality of interconnects 270. The plurality of interconnects 270 may be bonded to interconnects from the plurality of interconnects 222 of the substrate 202. The integrated device 207 may be bonded to the substrate 202 such that a front side (e.g., an active side) of the integrated device 207 faces the substrate 202.

[0119] Stage 3 shows the state after underfill 252 has been provided between substrate 202 and integrated device 205, and underfill 272 has been provided between substrate 202 and integrated device 207. An underfill may be disposed between substrate 202 and each integrated device.

[0120] Stage 4 shows the state after the plurality of solder interconnects 280 have been bonded to the second side of the substrate 202. The plurality of solder interconnects 280 may be bonded to interconnects from the plurality of interconnects 222 of the substrate 202. A reflow process may be used to bond the plurality of solder interconnects 280 to the substrate 202.

[0121] As shown in FIG. 12B, stage 5 shows the state after the substrate 202 with integrated device 205, integrated device 207 and plurality of solder interconnects 280 has been flipped.

[0122] Stage 6 shows the state after the first integrated device 204, the second integrated device 206, and the interconnected integrated device 201 have been bonded to a first surface (e.g., top surface) of the substrate 202. The first integrated device 204 may be bonded to the substrate 202 through a plurality of interconnects 240. The second integrated device 206 may be bonded to the substrate 202 through a plurality of interconnects 260. The interconnected integrated device 201 may be bonded to the substrate 202 through a plurality of solder interconnects 210.

[0123] Stage 6 also shows the state after underfill has been formed between the integrated device and substrate 202. For example, underfill 243 may be disposed between first integrated device 204 and substrate 202, underfill 263 may be disposed between second integrated device 206 and substrate 202, and underfill 213 may be disposed between interconnect integrated device 201 and substrate 202.

[0124] Stage 7 shows the state after encapsulation layer 208 has been formed on the first side of substrate 202 such that encapsulation layer 208 encapsulates first integrated device 204, second integrated device 206, and interconnected integrated device 201. The process of forming and / or disposing encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 8 may show package 200 including substrate 202, first integrated device 204, second integrated device 206, interconnected integrated device 201, integrated device 205, integrated device 207, and encapsulation layer 208, as at least described in FIG. 2 .

[0125] The packages described in this disclosure (eg, 200, 700) may be fabricated one at a time, or may be fabricated together as part of one or more wafers and then singulated into individual packages.

[0126] 1. An exemplary flow diagram of a method for manufacturing a package including a high density interconnect integrated device bonded to a substrate. In some implementations, manufacturing a package including a high-density interconnect integrated device bonded to a substrate involves several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or manufacturing a package including a high-density interconnect integrated device bonded to a substrate. In some implementations, the method 1300 of Figure 13 may be used to provide or manufacture the package 200 of Figure 2 described in this disclosure. However, the method 1300 may be used to provide or manufacture any of the packages described in this disclosure.

[0127] 13 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package including a high-density interconnect integrated device bonded to a substrate. In some implementations, the order of the processes may be changed or modified.

[0128] The method includes (at 1305) providing a substrate (e.g., 202). The substrate 202 may be provided by a supplier or may be manufactured. The substrate 202 includes a first side and a second side. The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Various implementations may include different substrates. A process similar to that shown in FIGS. 10A-10C may be used to manufacture the substrate 202. However, various implementations may use different processes to manufacture the substrate 202. Stage 1 of FIG. 12A illustrates an example of providing a substrate.

[0129] The method then bonds (at 1310) components to the second side of the substrate 202. Various implementations may bond different components and / or different numbers of components. The components may include integrated devices 205, 207, and / or passive devices (e.g., discrete capacitors). Bonding the components may include providing an underfill between the integrated devices and the substrate. Stages 2-3 of FIG. 12B illustrate examples of various components being bonded to the second side of the substrate.

[0130] The method continues (at 1315) by bonding a plurality of solder interconnects (e.g., 280) to the second side of the substrate (e.g., 202). Stage 4 of Figure 12A illustrates and describes an example of bonding the solder interconnects to the substrate.

[0131] The method includes (at 1320) bonding at least one integrated device (e.g., 204, 206) and an interconnected integrated device (e.g., 201) to a first side of a substrate (e.g., 202). The first integrated device 204 may be coupled to the substrate 202 through a plurality of interconnects 240. The plurality of interconnects 240 may be coupled to interconnects from the plurality of interconnects 222 of the substrate 202. The first integrated device 204 may be coupled to the substrate 202 such that a front side (e.g., active side) of the first integrated device 204 faces the substrate 202. As an example, first integrated device 204 and interconnect integrated device 201 may be coupled to substrate 202 such that the integrated device, interconnect integrated device and substrate are coupled together such that when a first electrical signal travels between the integrated device and the board (e.g., 290), the first electrical signal travels through substrate 202, then through interconnect integrated device 201 and again through substrate 202. Substrate 202 may be inverted before the integrated device is coupled to substrate 202.

[0132] The second integrated device 206 may be coupled to the substrate 202 through a plurality of interconnects 260. The plurality of interconnects 640 may be coupled to interconnects from the plurality of interconnects 222 of the substrate 202. The second integrated device 206 may be coupled to the substrate 202 such that a front surface (e.g., an active surface) of the second integrated device 206 faces the substrate 202.

[0133] As an example, the first integrated device 204, the second integrated device 206, and the interconnected integrated device 201 may be coupled to the substrate 202 such that the integrated devices, the interconnected integrated device, and the substrate are coupled together such that when a first electrical signal travels between the first integrated device 204 and the second integrated device 206, it travels through the interconnected integrated device 201. For example, the first electrical signal between the first integrated device 204 and the second integrated device 206 may travel through the substrate 202, then through the interconnected integrated device 201, and again through the substrate 202. Stage 6 of FIG. 12B illustrates and describes an example of the integrated devices and interconnected integrated devices being coupled to the substrate. Coupling the integrated devices to the substrate may also include providing an underfill (e.g., 213, 243, 263) between each integrated device (e.g., 204, 206) and the substrate 202. Stage 6 of FIG. 12B illustrates and describes an example of the provided underfill.

[0134] The method then (at 1325) forms an encapsulation layer 208 over the second side of the substrate (e.g., 202) such that the encapsulation layer (e.g., 208) encapsulates the first integrated device 204, the second integrated device 206, and the interconnected integrated device 201. The process of forming and / or disposing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 7 of Figure 12B illustrates and describes one example of an encapsulation layer disposed over a substrate to encapsulate the integrated devices.

[0135] Exemplary Electronic Devices 14 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-packages (PoPs), systems-in-packages (SiPs), or systems-on-chips (SoCs). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed location terminal device 1406, a wearable device 1408, or an automobile 1410 may include a device 1400 as described herein. The device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 illustrated in FIG. 14 are merely examples. Other electronic devices may also feature device 1400, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, eyeglasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0136] One or more of the components, processes, features, and / or functions shown in Figures 2-7, 8A-8D, 9, 10A-10C, 11, 12A-12B, and / or 13-14 may be rearranged and / or combined into a single component, process, feature, or function, or may be incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 2-7, 8A-8D, 9, 10A-10C, 11, 12A-12B, and / or 13-14 and their corresponding descriptions in this disclosure are not limited to die and / or ICs. 2-7, 8A-8D, 9, 10A-10C, 11, 12A-12B, and / or 13-14 and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0137] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0138] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the term “aspect” does not require all aspects of the present disclosure to include the described feature, advantage, or mode of operation. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between them. The use of the terms "first," "second," "third," and "fourth" (and / or more than fourth) is arbitrary. Any of the described components may be the first, second, third, or fourth component. For example, a component referred to as a second component may be the first, second, third, or fourth component. The term "encapsulate" means that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located on top may be located above a component located on the bottom. A top component may also be considered a bottom component, and vice versa. As described in this disclosure, a first component located "on" a second component may mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be disposed over (e.g., above) a first surface of a second component, and a third component may be disposed over (e.g., below) a second surface of the second component, with the second surface facing the first surface. It is further noted that the term "over," as used herein in the context of one component being disposed over another component, may be used to refer to a component located on and / or within (e.g., located on the surface of or embedded in) the other component. Thus, for example, a first component being disposed over a second component may mean that (1) the first component is disposed over, but not in direct contact with, the second component, (2) the first component is disposed on (e.g., on the surface of) the second component, and / or (3) the first component is disposed within (e.g., embedded in) the second component. A first component disposed "in" a second component can be disposed partially within the second component or completely within the second component. As used in this disclosure, the term "about the value of X" or "approximately the value of X" means within 10 percent of the "value of X." For example, a value of about 1 or approximately 1 means a value within the range of 0.9 to 1.1.

[0139] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Various implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0140] Also, it should be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0141] In the following, further examples are described to facilitate understanding of the present invention.

[0142] In a first further example, a package is described, the package including a substrate including a plurality of interconnects, an integrated device coupled to the substrate, and an interconnect integrated device coupled to a surface of the substrate, the integrated device, the interconnect integrated device, and the substrate configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path extending (e.g., traveling) at least through the substrate, then through the interconnect integrated device, and again through the substrate. Furthermore, the plurality of interconnects of the substrate may include a first minimum pitch, and the interconnect integrated device may include a plurality of interconnects having a second minimum pitch that is smaller than the first minimum pitch. Similarly, the interconnect integrated device may include a die substrate, at least one dielectric layer, and a plurality of interconnects. Furthermore, the die substrate may include silicon, glass, and / or quartz. Similarly, the interconnect integrated device may include a die without a transistor. Furthermore, the package may include a second integrated device coupled to the surface of the substrate, and the interconnect integrated device may be located between the integrated device and the second integrated device. Similarly, the integrated device, the interconnected integrated device, the second integrated device, and the substrate may be configured to provide a first electrical path for a first electrical signal between the integrated device and the second integrated device, the first electrical path extending at least through the substrate, then through the interconnected integrated device, and again through the substrate, with the interconnected integrated device configured as a bridge between the integrated device and the second integrated device for at least the first electrical signal. Similarly, the integrated device and the interconnected integrated device may be coupled to a first side of the substrate. Further, the integrated device and the interconnected integrated device may be coupled to a second side of the substrate. Similarly, the interconnected integrated device may include a second substrate having a plurality of interconnects. Furthermore, the integrated device, the interconnected integrated device, and the substrate may be configured to provide a first electrical path for a first electrical signal of the integrated device that (i) extends (e.g., enters) through a front surface of the interconnected integrated device, (ii) extends (e.g., enters) through at least one interconnect in the interconnected integrated device, and (iii) extends (e.g., exits) through a front surface of the interconnected integrated device.Entering, going, and / or exiting may be applicable to electrical pathways and / or electrical signals.

[0143] In another further example, an apparatus is described that includes a substrate including a plurality of interconnects, an integrated device coupled to the substrate, and means for integrated device interconnection coupled to a surface of the substrate, wherein the integrated device, the means for integrated device interconnection, and the substrate are configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path extending (e.g., traveling) at least through the substrate, then through the means for integrated device interconnection, and again through the substrate. Furthermore, the plurality of interconnects of the substrate may include a first minimum pitch, and the means for integrated device interconnection may include a plurality of interconnects having a second minimum pitch that is smaller than the first minimum pitch. Similarly, the means for integrated device interconnection may include a die substrate, at least one dielectric layer, and a plurality of interconnects. Furthermore, the die substrate may include silicon, glass, and / or quartz. Similarly, the means for integrated device interconnection may include a die without transistors. The apparatus may further include a second integrated device coupled to the surface of the substrate, with the means for integrated device interconnection disposed between the integrated device and the second integrated device. Similarly, the integrated device, the means for integrated device interconnection, the second integrated device, and the substrate may be configured to provide a first electrical path for a first electrical signal between the integrated device and the second integrated device, the first electrical path passing through at least the substrate, then through the means for integrated device interconnection, and again through the substrate, with the means for integrated device interconnection configured as a bridge between the integrated device and the second integrated device for at least the first electrical signal. Furthermore, the integrated device and the means for integrated device interconnection may be coupled to the first surface of the substrate or the second surface of the substrate. Furthermore, the interconnected integrated device may include a second substrate having a plurality of interconnects.Similarly, the integrated device, the means for integrated device interconnection, and the substrate may be configured to provide a first electrical path for a first electrical signal that (i) extends (e.g., enters) through a front surface of the means for integrated device interconnection, (ii) extends (e.g., goes) through at least one interconnect in the means for integrated device interconnection, and (iii) extends (e.g., exits) through a front surface of the means for integrated device interconnection. Entering, going, and / or exiting may be applicable to electrical path and / or electrical signal.

[0144] In another further example, a method for manufacturing a package is described, the method including providing a substrate including a plurality of interconnects, bonding an integrated device to the substrate, and bonding the interconnect integrated device to a surface of the substrate, wherein the integrated device, the interconnect integrated device, and the substrate are configured to provide a first electrical path for a first electrical signal of the integrated device, the first electrical path extending (e.g., traveling) at least through the substrate, then through the interconnect integrated device, and again through the substrate. Further, the plurality of interconnects of the substrate may include a first minimum pitch, and the interconnect integrated device may include a plurality of interconnects having a second minimum pitch that is smaller than the first minimum pitch. Similarly, the interconnect integrated device may include a die substrate, at least one dielectric layer, and a plurality of interconnects. Additionally, the integrated device, the interconnected integrated device, and the substrate may be configured to provide a first electrical path for a first electrical signal of the integrated device that (i) extends (e.g., in) through a front surface of the interconnected integrated device, (ii) extends (e.g., in) through at least one interconnect in the interconnected integrated device, and (iii) extends (e.g., out) through the front surface of the interconnected integrated device. In, out, and / or out may be applicable to electrical path and / or electrical signal.

[0145] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above-described aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0146] 100 packages 102 Circuit Board 104 Integrated Devices 106 Integrated Devices 108 Encapsulation Layer 120 dielectric layer 122 Interconnection 124 Solder Interconnects 144 Solder Interconnects 164 Solder Interconnects 200 packages 201 Interconnected Integrated Devices 202 Substrate 204 Integrated Devices 205 Integrated Devices 206 Integrated Devices 207 Integrated Devices 208 Encapsulation Layer 210 Solder Interconnects 211 Dielectric layer 212 Interconnection 213 Underfill 214 Passivation Layer 216 Substrate 220 Dielectric Layer 222 Interconnection 224 First solder resist layer 226 Second solder resist layer 240 Interconnection 243 Underfill 250 Interconnection 252 Underfill 260 Interconnection 263 Underfill 270 Interconnection 272 Underfill 280 Solder Interconnects 290 boards 301 First Electrical Path 302 Second Electrical Path 303 Third Electrical Path 304 Fourth Electrical Path 311 Electrical Path 313 Electrical Path 402 board 410 Electrical Path 411 Electrical Path 412 Electrical Path 440 Electrical Path 441 Electrical Path 442 Electrical Path 443 Electrical Path 460 Electrical Path 461 Electrical Path 462 Electrical Path 463 Electrical Path 502 board 504 Integrated Devices 506 Integrated Devices 530 Electrical Path 531 Electrical Path 532 Electrical Path 533 Electrical Path 540 Electrical Path 541 Electrical Path 542 Electrical Path 560 Electrical Path 561 Electrical Path 601a Interconnected Integrated Device 601b Interconnected Integrated Device 601c Interconnected Integrated Device 602 Substrate 630 Electrical Path 631 Electrical Path 632 Electrical Path 633 Electrical Path 700 packages 701 Interconnected Integrated Devices 702 Electrical Path 704 Electrical Path 705 Integrated Devices 706 Electrical Path 707 Integrated Devices 710 Interconnection 750 Interconnect 770 Interconnection 822 Interconnection 830 Dielectric layer 831 Cavity 832 Interconnection 840 Dielectric Layer 841 Cavity 842 Interconnection 850 dielectric layer 851 Cavity 852 Interconnection 1000 Carriers 1002 Interconnection 1010 Cavity 1012 Interconnection Cormorant 1014 Interconnection 1016 Interconnection 1020 dielectric layer 1022 dielectric layer 1024 dielectric layer 1030 Cavity 1040 Cavity 1400 devices 1402 Mobile Phone Devices 1404 Laptop Computer Device 1406 Fixed Location Terminal Device 1408 Wearable Devices 1410 Automobiles

Claims

1. a substrate including a plurality of interconnects; a first integrated device coupled to the plurality of interconnects of the substrate; a second integrated device coupled to the plurality of interconnects of the substrate; and an interconnected integrated device coupled to a surface of the substrate via the plurality of interconnects, the interconnected integrated device including a die substrate, at least one dielectric layer, a plurality of interconnects, and a plurality of metal layers; the interconnect integrated device includes a high-K dielectric layer disposed between two adjacent metal layers of the plurality of metal layers and having a different material than the dielectric layers, the two metal layers and the high-K dielectric layer forming a metal-insulator-metal capacitor; the interconnected integrated device and the substrate are configured to provide an electrical path for an electrical signal of the first integrated device, the electrical path extending at least through the substrate, then through the interconnected integrated device, then through the substrate again to the second integrated device; A package, wherein the glass fibers in the at least one dielectric layer included in the interconnect integrated device are finer than the glass fibers in the at least one dielectric layer included in the substrate.

2. The package of claim 1 , wherein the die substrate comprises silicon, glass, and / or quartz.

3. The package of claim 1 , wherein the interconnect integrated device comprises a transistor-less die.

4. The package of claim 1 , wherein the interconnect integrated device is located between the first integrated device and the second integrated device.

5. the first integrated device, the interconnected integrated device, the second integrated device, and the substrate are configured to provide a second electrical path for a second electrical signal between the first integrated device and the second integrated device, the second electrical path extending at least through the substrate, then through the interconnected integrated device, and again through the substrate; The package of claim 4 , wherein the interconnect integrated device is configured as a bridge between the first integrated device and the second integrated device for at least the electrical signal and the second electrical signal.

6. The package of claim 1 , wherein the first integrated device and the interconnect integrated device are bonded to a first side of the substrate.

7. 2. The package of claim 1, wherein the interconnect integrated device and the substrate are configured to provide an electrical path for the electrical signal of the first integrated device such that the electrical path for the electrical signal (i) enters through a front surface of the interconnect integrated device, (ii) travels through at least one interconnect within the interconnect integrated device, and (iii) exits through the front surface of the interconnect integrated device.

8. 10. The package of claim 1, wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things, IoT, device, and a device in an automotive vehicle.

9. 1. A method for manufacturing a package, comprising: providing a substrate including a plurality of interconnects; coupling a first integrated device to the plurality of interconnects of the substrate; coupling a second integrated device to the plurality of interconnects of the substrate; coupling an interconnected integrated device to a surface of the substrate via the plurality of interconnects of the substrate, the interconnected integrated device including a die substrate, at least one dielectric layer, a plurality of interconnects, and a plurality of metal layers; the interconnect integrated device includes a high-K dielectric layer disposed between two adjacent metal layers of the plurality of metal layers and having a different material than the dielectric layers, the two metal layers and the high-K dielectric layer forming a metal-insulator-metal capacitor; the interconnected integrated device and the substrate are configured to provide an electrical path for an electrical signal of the first integrated device, the electrical path passing through at least the substrate, then through the interconnected integrated device, then through the substrate again, to the second integrated device; The method, wherein the glass fibers in the at least one dielectric layer included in the interconnect integrated device are finer than the glass fibers in the at least one dielectric layer included in the substrate.

10. 10. The method of claim 9, wherein the first integrated device, the interconnected integrated device, and the substrate are configured to provide the electrical path for the electrical signal of the first integrated device such that the electrical path for the electrical signal (i) enters through a front surface of the interconnected integrated device, (ii) travels through at least one interconnect within the interconnected integrated device, and (iii) exits through the front surface of the interconnected integrated device.

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