Photoelectric conversion device

Abstract

To provide a photoelectric conversion device corresponding to a phenomenon generated when a switch that controls a voltage of an APD is turned off.SOLUTION: A photoelectric conversion device includes an avalanche photodiode including a first terminal and a second terminal, a first power source connected to the first terminal, a second power source connected to the second terminal, and a switch that switches a resistance value between the first power source and the first terminal. The first terminal of the avalanche photodiode is connected to a gate of each of a first PMOS transistor and a first NMOS transistor connected in series between a third power source and a fourth power source. First disconnecting means that disconnects an electric route between the third power source and the fourth power source is provided in the photoelectric conversion device.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Photoelectric conversion devices are known that have pixels each including a plurality of avalanche photodiodes (hereinafter referred to as APDs). By utilizing the avalanche multiplication of photocharges generated when photons are incident on the APD, each pixel is capable of detecting light at the single-photon level. Patent Document 1 describes a photodetector that can suppress noise while also suppressing a decrease in light detection efficiency. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-064086 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 does not fully consider the phenomenon that occurs when the switch that controls the voltage of the APD is turned off. Therefore, an object of the present invention is to provide a photoelectric conversion device that addresses the phenomenon that occurs when the switch that controls the voltage of the APD is turned off. [Means for solving the problem]

[0005] One aspect of the present invention is a photoelectric conversion device, comprising: an avalanche photodiode having a first terminal and a second terminal; a first power supply connected to the first terminal; a second power supply connected to the second terminal; and a switch for switching a resistance value between the first power supply and the first terminal. a third power supply, a fourth power supply, a first PMOS transistor and a first NMOS transistor connected in series between the third power supply and the fourth power supply, a first interrupting means for interrupting an electrical path between the third power supply and the fourth power supply, a first chip on which the avalanche photodiode is disposed, and a second chip on which the first interrupting means is disposed; and the first terminal of the avalanche photodiode is The aforementioned a first PMOS transistor; The aforementionedconnected to the gates of the first NMOS transistor and the second NMOS transistor; before The second chip and the first chip are stacked. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a photoelectric conversion device that can deal with the phenomenon that occurs when a switch that controls the voltage of an APD is turned off. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating a configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing the arrangement of sensor chips in the photoelectric conversion device according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing the configuration of a circuit chip of the photoelectric conversion device according to the first embodiment. [Figure 4] FIG. 4 is a block diagram of one pixel of a sensor chip and a circuit chip of a comparative example according to the first embodiment. [Figure 5] FIG. 2 is a block diagram of one pixel of the sensor chip and the circuit chip of the photoelectric conversion device according to the first embodiment. [Figure 6] 3A and 3B are diagrams illustrating a relationship between the operation of an APD and an output signal of the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 10 is a driving timing diagram of one pixel of a comparative example according to the first embodiment. [Figure 8] FIG. 2 is a drive timing chart for one pixel of the photoelectric conversion device according to the first embodiment. [Figure 9] FIG. 10 is a logic circuit diagram of one pixel of the sensor chip and the circuit chip of the photoelectric conversion device according to the second embodiment. [Figure 10] FIG. 10 is a block diagram of one pixel of a sensor chip and a circuit chip of a photoelectric conversion device according to a second embodiment. [Figure 11] FIG. 10 is a logic circuit diagram of one pixel of the sensor chip and the circuit chip of the photoelectric conversion device according to the third embodiment. [Figure 12]FIG. 10 is a block diagram of one pixel of a sensor chip and a circuit chip of a photoelectric conversion device according to a third embodiment. [Figure 13] FIG. 10 is a block diagram of one pixel of a sensor chip and a circuit chip of a photoelectric conversion device according to a fourth embodiment. [Figure 14] FIG. 10 is a block diagram of one pixel of a sensor chip and a circuit chip of a photoelectric conversion device according to a fifth embodiment. [Figure 15] FIG. 11 is a drive timing chart for one pixel of a photoelectric conversion device according to a fifth embodiment. [Figure 16] FIG. 10 is a functional block diagram of a photoelectric conversion system according to a sixth embodiment. [Figure 17] FIG. 13 is a functional block diagram of a photoelectric conversion system according to a seventh embodiment. [Figure 18] FIG. 13 is a functional block diagram of a photoelectric conversion system according to an eighth embodiment. [Figure 19] FIG. 13 is a functional block diagram of a photoelectric conversion system according to a ninth embodiment. [Figure 20] FIG. 20 is a functional block diagram of a photoelectric conversion system according to a tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] (First embodiment) The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0010] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0011] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and a signal is extracted from the cathode side. Therefore, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is an N-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is a P-type semiconductor region. The present invention also applies when the cathode of the APD is set to a fixed potential and a signal is extracted from the anode side. In this case, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is a P-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is an N-type semiconductor region. While the following description focuses on a case where one node of the APD is set to a fixed potential, the potentials of both nodes may fluctuate.

[0012] In this specification, when the term "impurity concentration" is used simply, it means the net impurity concentration minus the amount compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET doping concentration. A region where the P-type doped impurity concentration is higher than the N-type doped impurity concentration is a P-type semiconductor region. Conversely, a region where the N-type doped impurity concentration is higher than the P-type doped impurity concentration is an N-type semiconductor region.

[0013] 1 is a diagram showing the configuration of a stacked photoelectric conversion device according to an embodiment of the present invention. The photoelectric conversion device 100 is configured by stacking and electrically connecting two chips: a sensor chip 11 and a circuit chip 21.

[0014] The sensor chip 11 has a pixel region 12 arranged thereon, and the circuit chip 21 has a circuit region 22 arranged thereon for processing signals detected in the pixel region 12 .

[0015] 2 is a layout diagram of the sensor chip 11. Pixels 101, each having a photoelectric conversion unit 102 including an avalanche photodiode (hereinafter, referred to as APD), are arranged two-dimensionally to form a pixel region 12.

[0016] The pixel 101 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. In other words, the pixel 101 may be a pixel for measuring the time and amount of light that arrives.

[0017] 3 is a configuration diagram of the circuit chip 21. It has a signal processing unit 103 that processes charges photoelectrically converted by the photoelectric conversion unit 102 in FIG. 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, signal lines 113, and a vertical scanning circuit unit 110. The signal processing unit 103 outputs the photoelectrically converted electrical signal to the readout circuit 112. The readout circuit 112 stores the signal output from the signal processing unit 103 on a row-by-row basis.

[0018] The photoelectric conversion unit 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 are electrically connected via connection wiring provided for each pixel.

[0019] In this embodiment, a configuration in which two chips, the sensor chip 11 and the circuit chip 21, are stacked is shown, but a configuration in which the pixel region 12 of the sensor chip 11 and the circuit region 22 of the circuit chip 21 are arranged on a single chip may also be used.

[0020] The vertical scanning circuit unit 110 receives a control pulse supplied from the control pulse generating unit 115 and supplies the control pulse to each pixel. The vertical scanning circuit unit 110 uses logic circuits such as a shift register and an address decoder.

[0021] The signal output from the photoelectric conversion unit 102 of each pixel is processed by the signal processing unit 103. The signal processing unit 103 is provided with a counter, a memory, etc., and digital values ​​are held in the memory.

[0022] The horizontal scanning circuit unit 111 inputs a control pulse to the signal processing unit 103 to sequentially select each column in order to read out the signal from the memory of each pixel in which the digital signal is held.

[0023] A signal is output to the signal line 113 from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 for the selected column.

[0024] The signal output to the signal line 113 is output to a recording unit or a signal processing unit outside the photoelectric conversion device 100 via a read circuit 112 and an output circuit 114 .

[0025] 2, the pixels 101 may be arranged one-dimensionally in the pixel region 12. The function of the signal processing unit 103 does not necessarily need to be provided for each pixel 101, and for example, one signal processing unit 103 may be shared by multiple pixels 101, and signal processing may be performed sequentially.

[0026] 4 is an example of a block diagram including an equivalent circuit for one pixel of the comparative example shown in FIGS. 2 and 3. FIG. 5 is an example of a block diagram including an equivalent circuit for one pixel of the photoelectric conversion device according to the present embodiment shown in FIGS. 2 and 3. In each of FIGS. 4 and 5, the photoelectric conversion unit 102 having the APD 201 is provided on the sensor chip 11, and the other components are provided on the circuit chip 21. The photoelectric conversion device according to the present embodiment shown in FIG. 5 differs from the photoelectric conversion device of the comparative example shown in FIG. 4 in that a blocking unit 205 is provided.

[0027] The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage higher than the voltage supplied to the anode is supplied to the cathode of the APD 201 from a power supply VH (first power supply). A voltage is also supplied to the anode of the APD 201 from a power supply VL (second power supply). A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With this voltage supplied, the charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0028] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the potential difference between the anode and cathode is greater than the breakdown voltage, and linear mode, in which the potential difference between the anode and cathode is close to or less than the breakdown voltage. APDs operating in Geiger mode are called SPADs. For example, the power supply VL is -30V and the power supply VH is 1V.

[0029] The anode or cathode of the APD 201 is connected to node A (first terminal), which is also connected to the gate of the first PMOS transistor 206, the gate of the first NMOS transistor 207, and the switch 202.

[0030] The switch 202 is provided between the power supply VH and the APD 201 and switches the resistance between the power supply VH and the APD 201. The switch 202 has a function of converting a change in avalanche current generated in the APD 201 into a voltage signal. The switch 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation). The switch 202 is controlled between a standby state in which the switch 202 is non-conductive and the potential of the cathode is maintained, and a recharge state in which the switch 202 is conductive and a potential that causes avalanche multiplication is applied to the cathode of the APD 201. The standby state and the recharge state are controlled by a control signal Pctrl via a first control line 215. For example, when the control signal Pctrl is at a high level, the switch 202 is turned off and the APD 201 is controlled to be in a standby state, and when the control signal Pctrl is at a low level, the switch 202 is turned on and the APD 201 is controlled to be in a recharge state.

[0031] The signal processing unit 103 shown in FIG. 4 includes a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212, and the signal processing unit 103 shown in FIG.

[0032] The waveform shaping unit 210 shapes the potential change at the cathode of the APD 201 obtained upon photon detection and outputs a pulse signal. The waveform shaping unit 210 uses an inverter circuit configured with a first PMOS transistor 206 and a first NMOS 207. The drains of the first PMOS transistor 206 and the first NMOS 207 are connected to node B. The source of the first NMOS transistor 207 is connected to GND (ground potential). For example, GND is 0 V. Node B is also connected to the input of a counter circuit 221. This inverter circuit determines whether the signal output from the APD 201 exceeds a determination threshold and outputs a signal in which the magnitude relationship of the input signal with respect to the threshold is inverted. The output of the inverter circuit is a pulse wave in which the voltage change at the cathode is shaped. In other words, the inverter circuit performs a waveform shaping function by shaping the continuous signal output from the APD into a pulse shape and outputting it.

[0033] Here, the through current flowing through the inverter circuit, which is the waveform shaping unit 210, will be described with reference to FIG. 4. As described above, this inverter circuit determines whether the signal output from the APD 201 exceeds the determination threshold. The determination threshold is the potential at which the first PMOS transistor 206 and the first NMOS 207 alternate between ON and OFF. For example, when the signal input to the inverter circuit is low, the first PMOS transistor 206 constituting the inverter circuit turns ON and the first NMOS 207 constituting the inverter circuit turns OFF. The nodeB output goes high as the parasitic capacitance is charged by VDD. When the signal input to the inverter circuit is high, the first PMOS transistor 206 constituting the inverter circuit turns OFF and the first NMOS 207 constituting the inverter circuit turns ON. The parasitic capacitance is discharged to GND, causing the nodeB output to go low.

[0034] When the input signal is in a transition state between High and Low, it transitions near a potential (decision threshold) at which the first PMOS transistor 206 and the first NMOS 207 switch between ON and OFF. At this time, the input signal may reach an intermediate potential at which both the first PMOS transistor 206 and the first NMOS 207 are turned on. When the input signal reaches the intermediate potential, both the first PMOS transistor 206 and the first NMOS 207, which are connected in series between VDD and GND, are turned on, causing a through current to flow between VDD and GND.

[0035] Although an example in which one inverter is used as the waveform shaping section 210 is shown in FIGS. 4 and 5, the waveform shaping section 210 may be configured with a logic circuit including an inverter.

[0036] 5, the cutoff means 205 is provided between a power supply VDD (third power supply) and GND (fourth power supply) and cuts off the path between the power supplies VDD and GND. The cutoff means 205 is composed of a second PMOS transistor 208. The source of the second PMOS transistor 208 is connected to the power supply VDD. For example, the power supply VDD is 1V.

[0037] 5 shows a configuration in which the power supply VH and the power supply VDD are provided separately. However, the power supply VH and the power supply VDD may be a common power supply. By using a common power supply, it is possible to reduce the number of power supplies required for the photoelectric conversion device 100.

[0038] The cutoff means 205 is controlled to be ON (operating state) or OFF (cutoff state). The cutoff means 205 is controlled by a control signal Pcutoff via a second control line 216. For example, the cutoff means 205 is controlled to be ON when the control signal Pcutoff is at a low level, and to be OFF when the control signal Pcutoff is at a high level. Although FIG. 5 shows an example in which a PMOS transistor is used as the cutoff means 205, an NMOS transistor or other circuit having a current cutoff effect may also be used. Furthermore, the cutoff means 205 may be provided between GND and the first NMOS transistor 207.

[0039] The counter circuit 211 counts the pulse signal output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter circuit 211 is reset.

[0040] A control pulse pSEL is supplied to the selection circuit 212 from the vertical scanning circuit unit 110 in Fig. 3 via a drive line 214 (not shown in Fig. 3) in Fig. 5, and switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0041] The electrical connection may be switched by disposing a switch such as a transistor between the switch 202 and the APD 201 or between the photoelectric conversion unit 102 and the signal processing unit 103. Similarly, the supply of voltage to the photoelectric conversion unit 102 may be electrically switched using a switch such as a transistor.

[0042] In this embodiment, a configuration using the counter circuit 211 has been described. However, instead of the counter circuit 211, the photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0043] FIG. 6 is a diagram showing the relationship between the operation of the APD and the output signal. FIG. 6(a) is a diagram showing the APD 201, switch 202, waveform shaping unit 210, node A, and node B from FIG. 4. FIG. 6(b), FIG. 6(c), and FIG. 6(d) show the relationship between the operation of the APD and the output signal when switch 202 is always in a conductive state. FIG. 6(e), FIG. 6(f), and FIG. 6(g) show the relationship between the operation of the APD and the output signal when switch 202 is controlled between a conductive state and a non-conductive state. FIG. 6(b) and FIG. 6(e) show the waveform change of node A in FIG. 6(a), FIG. 6(c) and FIG. 6(f) show the waveform change of node B in FIG. 6(a), and FIG. 6(d) and FIG. 6(g) show the waveform change of Pctrl in FIG. 6(a).

[0044] The relationship between the operation of the APD and the output signal when the switch 202 in FIG. 6(a) is always ON will be described with reference to FIGS. 6(b) to 6(d).

[0045] Between times t0 and t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 6(a).

[0046] 6(b), when a photon is incident at time t1, an avalanche multiplication current flows through switch 202, causing the voltage at node A to drop. As the voltage drop increases further and the potential difference applied to APD 201 decreases, avalanche multiplication by APD 201 stops, and at time t2 the voltage level at node A no longer drops below a certain value. After that, a current flows through node A to compensate for the voltage drop, and at time t3, node A stabilizes at its original potential level.

[0047] At this time, as shown in FIG. 6(c), the portion of the output waveform at node A that exceeds a certain threshold is waveform-shaped by the waveform shaping section 210 and is output as a signal to node B.

[0048] Next, with reference to FIGS. 6(e) to 6(g), the relationship between the operation of the APD 201 and the output signal when the switch 202 in FIG. 6(a) is controlled to be ON or OFF will be described.

[0049] In FIG. 6(e), the switch 202 is OFF between times t0 and t3. Therefore, between times t2 and t3, node A cannot compensate for (recover) the voltage drop caused by avalanche multiplication. At time t3, the switch 202 is turned ON. Thereafter, the voltage drop at node A is compensated for, and at time t4, node A returns to its original potential level and becomes static. At time t5, the switch 202 is turned OFF, and the APD 201 returns to the standby state.

[0050] FIG. 7 shows an example of the drive timing of one pixel according to the comparative example shown in FIG. 4, and FIG. 8 shows an example of the drive timing of one pixel according to the present embodiment shown in FIG.

[0051] In both Figures 7 and 8, the period from time t1 to t4 is a non-exposure period of (n-1) frames. The period from time t4 to time t12 is an exposure period of n frames. The period from time t12 to time t14 is a non-exposure period of n frames. The period from time t14 to time t16 and onwards is an exposure period of (n+1) frames. When the exposure period is set shorter than the maximum exposure period of one frame, a non-exposure period occurs as a period other than the exposure period within one frame. Here, the exposure period is a period during which the APD 210 detects photons, and a photon detection signal corresponding to the photons detected during this period is output from the APD 210. The non-exposure period is a period during which the APD 210 is controlled not to detect light by shutter operation or the like. The period during which photon detection or output is stopped due to a cropping operation that stops the photon detection operation of a pixel area among a plurality of pixels during the exposure period, or a thinning operation that periodically thins out pixels, such as every other row or every third row, is also considered a non-exposure period.

[0052] Furthermore, a control signal EN that defines the exposure period may be input to the counter 211, and the exposure period may be linked to the operation of the counter 211. That is, when the control signal EN transitions from low level to high level, the exposure period starts, and when the control signal EN transitions from high level to low level, the exposure period ends and the counter 211 enters a stopped state.

[0053] First, FIG. 7 will be described.

[0054] At time t1 during the non-exposure period of the (n-1)th frame, the control signal Pctrl changes from high level to low level, the switch 202 turns on, and the APD 201 enters a recharge state.

[0055] At time t2, the potential of node A exceeds the determination threshold of the waveform shaping unit 210. At this time, a through current flows from the power supply VDD to GND. Thereafter, the potential of node A settles to a potential level at which avalanche multiplication is possible.

[0056] At time t3, the control signal Pctrl changes from low level to high level, the switch 202 turns off, and the APD 201 goes into a standby state.

[0057] At time t4, the non-exposure period of (n-1) frames ends and the exposure period of n frames begins.

[0058] At time t5, a photon is incident on the APD 201, an avalanche multiplication current flows, and the potential of nodeA drops.

[0059] At time t6, the potential of node A exceeds the determination threshold of the waveform shaping unit 210. At this time, a through current flows from the power supply VDD to GND.

[0060] At time t7, the control signal Pctrl changes from high to low, the switch 202 turns on, and the APD 201 enters a recharge state.

[0061] At time t8, the potential at nodeA exceeds the determination threshold of the waveform shaping unit 210. At this time, a through current flows from the power supply VDD to GND. Thereafter, the potential at nodeA settles to a potential level at which avalanche multiplication is possible.

[0062] At time t9, the control signal Pctrl changes from low level to high level, the switch 202 turns off, and the APD 201 goes into a standby state.

[0063] At time t10, a photon is incident on the APD 201, an avalanche multiplication current flows, and the potential of nodeA drops.

[0064] At time t11, the signal at node A exceeds the determination threshold of the waveform shaping unit 210. At this time, a through current flows from the power supply VDD to GND. During the subsequent exposure period, the operation is the same as from time t4 to time t11, depending on the operation of the control signal Pctrl.

[0065] At time t12, the exposure period of n frames ends and the non-exposure period of n frames begins. At this time, Pctrl is at a high level and switch 202 is in an OFF state. Therefore, node A is floating. If a reverse current flows through APD 201 while node A is floating, the potential of node A drops. At this time, APD 210 is in a standby state, so node A cannot compensate for (recover) the voltage drop caused by avalanche multiplication, and the potential of node A continues to drop as the reverse current occurs.

[0066] At time t13, the potential at node A reaches an intermediate potential at which both the first PMOS transistor 206 and the first NMOS transistor 207, which constitute the downstream waveform shaping unit 210, are turned on. A larger through-current flows through the waveform shaping unit 210 than the through-currents that flow at times t2 and t6. In addition, the signal at node A exceeds the decision threshold of the waveform shaping unit 210.

[0067] The reason why the through current flowing at t13 is larger than the through current flowing at t2 and t6 is explained below. During the exposure period, the APD 210 operates in response to the control signal Pctrl, repeatedly decreasing the potential of node A due to avalanche multiplication and increasing the potential of node A due to recharge. Therefore, both when the potential of node A decreases due to avalanche multiplication and when the potential of node A increases due to recharge, the period during which node A is at an intermediate potential is very short. On the other hand, during the non-exposure period, the potential of node A changes depending on the current generated by the APD 210 operating in linear mode, so the period during which node A is held at an intermediate potential is relatively long. Therefore, if a through current flows during the non-exposure period, the period during which the through current flows is longer than during the exposure period, raising concerns about increased power consumption.

[0068] At time t14, the non-exposure period of n frames ends, and the exposure period of (n+1) frames begins.

[0069] At time t15, the control signal Pctrl changes from high to low, the switch 202 turns on, and the APD 201 enters a recharge state.

[0070] At time t16, the potential of node A exceeds the determination threshold of the waveform shaping unit 210. Thereafter, node A settles to a potential level at which avalanche multiplication is possible. After time t14, the operation is the same as that during the exposure period of the nth frame.

[0071] Next, FIG. 8 will be described.

[0072] At time t1, the control signal Pctrl changes from high to low, turning on the switch 202 and recharging the APD 201. After that, the potential at node A settles to a potential level that allows avalanche multiplication.

[0073] At time t2, the potential of nodeA exceeds the determination threshold of the waveform shaping unit 210. Since Pcutoff is at a high level and the cutoff means 205 is in a cutoff state, the electrical path from the power supply VDD to GND is cut off and no through current flows.

[0074] At time t3, the control signal Pctrl changes from low level to high level, the switch 202 turns on, and the APD 201 goes into a standby state.

[0075] At time t4, the control signal Pcutoff changes from high level to low level, and the cutoff means 205 enters an operating state.

[0076] At time t5, a photon is incident on the APD 201, an avalanche multiplication current flows, and the potential of nodeA drops.

[0077] At time t6, the potential of node A exceeds the determination threshold of the waveform shaping unit 210. At this time, the cutoff means 205 is in an operating state and the electrical path from the power supply VDD to GND is in a conductive state, so that a through current flows from the power supply VDD to GND.

[0078] At time t7, the control signal Pctrl changes from high to low, the switch 202 turns off, and the APD 201 enters a recharge state.

[0079] At time t8, the potential of nodeA exceeds the determination threshold of the waveform shaping unit 210. At this time, a through current flows from the power supply VDD to GND. Thereafter, nodeA settles to a potential level at which avalanche multiplication is possible.

[0080] At time t9, the control signal Pctrl changes from low level to high level, the switch 202 turns off, and the APD 201 goes into a standby state.

[0081] At time t10, a photon is incident on the APD 201, an avalanche multiplication current flows, and the potential of nodeA drops.

[0082] At time t11, the potential of node A exceeds the determination threshold of the waveform shaping unit 210. At this time, a through current flows from the power supply VDD to GND. The subsequent exposure period operates in the same manner as from time t4 to time t11.

[0083] At time t12, the control signal Pcutoff changes from low to high, and the cutoff means 205 enters a cutoff state. Also, Pctrl is at high level, the switch 202 is turned on, and the APD 201 enters a standby state.

[0084] Therefore, node A is floating. During the period when node A is floating, a reverse current flows through the APD 201, and the potential of node A drops.

[0085] At time t13, the potential at node A reaches an intermediate potential at which both the first PMOS transistor 206 and the first NMOS transistor 207, which constitute the downstream waveform shaping unit 210, are turned on. However, in this embodiment, the cutoff means 205 is in a cutoff state, so that a through current flowing from the power supply VDD to GND can be prevented. In addition, the signal at node A exceeds the determination threshold of the waveform shaping unit 210.

[0086] At time t14, the control signal Pcutoff changes from high level to low level, and the cutoff means 205 enters an operating state.

[0087] At time t15, the control signal Pctrl changes from high level to low level, and the switch 202 enters a recharge state.

[0088] At time t16, the signal at node A exceeds the decision threshold of the waveform shaping unit 210. After that, node A settles to its original potential level at which avalanche multiplication is possible. After time t14, the operation is the same as that during the exposure period of the nth frame.

[0089] As described above, according to this embodiment, by blocking the path between the power supplies VDD and GND during the non-exposure period, it is possible to prevent a through current from flowing through the waveform shaping unit 206. While this embodiment describes a pixel having an exposure period and a non-exposure period, the present invention is also applicable to, for example, a light-shielded dummy pixel that functions as a so-called OPB (Optical Black) pixel. Even in such a dummy pixel, a through current occurs due to the period during which the switch 202 is turned off.

[0090] In the configuration shown in FIG. 5 , when the cutoff means 205 is OFF (cutoff state), the output of the waveform shaping unit 210 may become floating. However, it is undesirable for the input signal of the counter circuit 211 to become floating because a shoot-through current may flow between the power supply and GND in the elements constituting the counter circuit. Therefore, a switch may be added between the output of the waveform shaping unit 210 and the power supply or GND so that the output of the waveform shaping unit 210 becomes high or low when the cutoff means 205 is cutoff. That is, a first terminal of the switch is connected to a node between the output terminal of the waveform shaping unit 210 and the input terminal of the counter circuit 211, and a second terminal of the switch is connected to the power supply or GND. With this configuration, when the cutoff means 205 is cutoff, the output of the waveform shaping unit 210 is fixed to high or low depending on the switch. Therefore, it is possible to prevent the input signal of the counter circuit from becoming floating and a shoot-through current from occurring in the counter circuit.

[0091] (Second embodiment) A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 9 and 10. Components common to the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0092] In this embodiment, a case will be described in which the waveform shaping unit 210 and the cutoff means 205 are configured by a logic circuit 203 including the cutoff means 205 .

[0093] 9 and 10 are a logic circuit diagram including an equivalent circuit for one pixel of the photoelectric conversion device according to this embodiment shown in FIGS. 2 and 3, and a block diagram thereof.

[0094] 9, the logic circuit 203 is a NOR circuit having inputs connected to the cathode node A of the APD 201 and the second control line 216, and an output connected to the counter circuit 211. A specific configuration of this NOR circuit is shown in FIG.

[0095] The logic circuit 203 is composed of a first PMOS transistor 206, a second PMOS transistor 208, a first NMOS transistor 207, and a second NMOS transistor 209. The cutoff means 205 is composed of the second PMOS transistor 208 and is included in the logic circuit 203.

[0096] 10, the source of the first PMOS transistor 206 is connected to VDD, and the source of the first NMOS transistor 207 is connected to GND. Furthermore, the drain of the first PMOS transistor 206 is connected to the source of the second PMOS transistor 208. The drain of the second PMOS transistor 208, the drain of the first NMOS transistor 207, and the drain of the second NMOS transistor 209 are connected. The source of the first NMOS transistor is connected to the source of the second NMOS transistor 209.

[0097] One of the inputs constituting the NOR circuit, input A, is controlled by the control signal Pcutoff, and the other input B is controlled by the potential of node A, which is the cathode of APD 201. Cutoff means 205 is conductive when input A is low level and non-conductive when input A is high level. When input A is high level, the output of the logic circuit is low level.

[0098] According to this embodiment, by using the logic circuit 203 (NOR circuit) including the cutoff means 205, it is possible to prevent a through current from flowing through the waveform shaping unit 206 during the non-exposure period.

[0099] (Third embodiment) A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 11 and 12. Components common to the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted or simplified.

[0100] In this embodiment, a case where the logic circuit 203 is configured by a NAND circuit will be described.

[0101] 11 and 12 are a logic circuit diagram including an equivalent circuit for one pixel of the photoelectric conversion device according to this embodiment shown in FIGS. 2 and 3, and a block diagram thereof.

[0102] 11, the logic circuit 203 is a NAND circuit having inputs connected to the cathode node A of the APD 201 and the third control line 217, and an output connected to the counter circuit 211. A specific configuration of this NAND circuit is shown in FIG.

[0103] The logic circuit 203 is composed of a first PMOS transistor 206, a second PMOS transistor 208, a first NMOS transistor 207, and a second NMOS transistor 209. The cutoff means 205 is composed of the second NMOS transistor 209 and is included in the logic circuit 203.

[0104] 12, the source of the first PMOS transistor 206 is connected to VDD, and the source of the first NMOS transistor 207 is connected to GND. The drain of the first PMOS transistor 206, the drain of the second PMOS transistor 208, and the drain of the second NMOS transistor 209 are connected, and the source of the first PMOS transistor 206 and the source of the second PMOS transistor 208 are connected. The drain 207 of the first NMOS is connected to the source of the second NMOS 209.

[0105] One of the inputs constituting the NAND circuit, input A, is controlled by control signal PcutoffB, which is an inverted signal of control signal Pcutoff, and the other input B is controlled by the potential of node A, which is the cathode of APD 201. Cutoff means 205 is in a conductive state when input A is at a high level and in a non-conductive state when input A is at a low level. Furthermore, when input A is at a low level, the output of the logic circuit is at a high level.

[0106] According to this embodiment, by using the logic circuit 203 (NAND circuit) including the cutoff means 205, it is possible to prevent a through current from flowing through the waveform shaping unit 206 during the non-exposure period.

[0107] (Fourth embodiment) A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Fig. 13. Components common to the photoelectric conversion device according to the first embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted or simplified.

[0108] In this embodiment, a case will be described in which the logic circuit 203 is configured by a three-state buffer circuit.

[0109] FIG. 13 is a block diagram including an equivalent circuit for one pixel of FIGS. 2 and 3 according to this embodiment.

[0110] The inverter circuit 220 receives the control signal Pcutoff and outputs an inverted signal, a control signal Pcutoff B. The inverter circuit 229 has the control line 216 connected to its input and the control line 217 connected to its output.

[0111] The logic circuit 203 is a three-state buffer circuit whose inputs are connected to the cathode of the APD 201, a second control line 216, and a third control line 217, and whose output is connected to the counter circuit 211. The cutoff means 205 is composed of a second PMOS transistor 208 and a second NMOS transistor 209, and is included in the logic circuit 203.

[0112] 13, the source of a first PMOS transistor 206 is connected to VDD, and the source of a first NMOS transistor 207 is connected to GND. The source of a second PMOS transistor 208 is connected to the drain of the first PMOS transistor 206, and the source of a second NMOS transistor 209 is connected to the drain of the first NMOS transistor 207. The drain of the second PMOS transistor 208 is connected to the drain of the second NMOS transistor 209.

[0113] One of the inputs constituting the three-state buffer circuit, input A, is controlled by a control signal Pcutoff, and the other input B is controlled by the potential of node A, which is the cathode of APD 201. Cutoff means 205 is conductive when input A is at a low level and is non-conductive when input A is at a high level. According to the operation of the three-state buffer circuit, power supplies VDD and GND are cut off and the output becomes high impedance.

[0114] According to this embodiment, by using the logic circuit 203 (three-state buffer circuit) including the cutoff means 205, it is possible to prevent a through current from flowing through the waveform shaping unit 206 during the non-exposure period.

[0115] (Fifth embodiment) A photoelectric conversion device according to a fifth embodiment of the present invention will be described with reference to Figures 14 and 15. Components common to the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted or simplified.

[0116] In this embodiment, an example of drive timing when the logic circuit 203 is configured by a NOR circuit will be described.

[0117] FIG. 12 is a block diagram including an equivalent circuit for one pixel of FIGS. 2 and 3 according to this embodiment.

[0118] The pixel of the photoelectric conversion device according to this embodiment is obtained by adding an inverter circuit 220 and a NAND circuit 221 to the pixel of the photoelectric conversion device according to the second embodiment.

[0119] The inverter circuit 220 receives the control signal Pctrl and outputs an inverted control signal PctrlB. The inverter circuit 220 has an input connected to the first control line 215 and an output connected to the fifth control line 219. The control signal PctrlB is input to the inverter circuit 220 via the fifth control line 219.

[0120] The NAND circuit 221 receives the control signals Pcnten and PctrlB as inputs and outputs a control signal Pcutoff. The fourth control line 218 and the fifth control line 219 are connected to the inputs of the NAND circuit 221, and the control signal Pcutoff is connected to the output. The control signal Pcnten is input to the NAND circuit 221 via the fourth control line 218. The control signal PctrlB is input to the NAND circuit 221 via the fifth control line 219.

[0121] The control signal Pcnten controls whether the input to the counter circuit 211 is enabled or disabled. When the control signal Pcnten is at a high level, the input to the counter circuit 211 changes depending on the photon incidence and the control line signal Pctrl. Therefore, the input to the counter circuit 211 is enabled, enabling counting. On the other hand, when the control signal Pcnten is at a low level, the input to the counter circuit 211 is fixed at a low level. Therefore, the input to the counter circuit is disabled, and the count circuit 211 does not perform counting. For example, when the control signal Pcnten is at a high level, it is an exposure period, and when the control signal Pcnten is at a low level, it is a non-exposure period.

[0122] 15 is a diagram showing an example of the drive timing of one pixel according to this embodiment. The period from time t1 to t3 is a non-exposure period of (n-1) frames. The period from time t3 to time t16 is an exposure period of n frames. The period from time t16 onwards is a non-exposure period of n frames.

[0123] At time t1, the control signal Pctrl changes from high to low, the switch 202 turns on, and the APD 201 enters a recharge state. After that, the node A settles to a potential level that allows avalanche multiplication.

[0124] At time t2, the control signal Pctrl changes from low level to high level, the switch 202 turns off, and the APD 201 goes into a standby state.

[0125] At time t3, the control signal Pcnten changes from low level to high level, and the input to the counter circuit 211 becomes valid.

[0126] At time t4, a photon is incident on the APD 201, an avalanche multiplication current flows, and the voltage at node A drops.

[0127] At time t5, the potential of node A exceeds the decision threshold of the logic circuit 203.

[0128] At time t6, the control signal Pctrl changes from high to low, the switch 202 turns on, and the APD 201 enters a recharge state. Also, the control signal Pcutoff changes from high to low, and the cutoff means 205 enters an operating state.

[0129] At time t7, the signal at node A exceeds the decision threshold of the logic circuit 203. At this time, a through current flows from the power supply VDD to GND. After that, node A settles to a potential level at which avalanche multiplication is possible.

[0130] At time t8, the control signal Pctrl changes from low to high, the switch 202 turns off, and the APD 201 enters a standby state. The control signal Pcutoff also changes from low to high, and the cutoff means 205 enters a cutoff state. Therefore, node A becomes floating. If the floating period is long, the potential of node A decreases due to the reverse current generated in the APD 201, even during the exposure period.

[0131] At time t9, the signal at node A exceeds the decision threshold of the logic circuit 203. At this time, the potential at node A becomes the intermediate potential of the transistors constituting the subsequent logic circuit 203, but in this embodiment, the cutoff means 205 is in the cutoff state even during the exposure period, making it possible to prevent a through current.

[0132] At time t10, the control signal Pctrl changes from high to low, the switch 202 turns on, and the APD 201 enters a recharge state. Also, the control signal Pcutoff changes from high to low, and the cutoff means 205 enters an operating state.

[0133] At time t11, the signal at node A exceeds the decision threshold of the logic circuit 203. At this time, a through current flows from the power supply VDD to GND. After that, the cathode node A settles to a potential level that allows avalanche multiplication.

[0134] At time t12, the control signal Pctrl changes from low to high, the switch 202 turns off, and the APD 201 enters a standby state. Also, the control signal Pcutoff changes from low to high, and the cutoff means 205 enters a cutoff state. As a result, nodeA becomes floating.

[0135] At time t13, a photon is incident on the APD 201, an avalanche multiplication current flows, and the voltage at node A drops.

[0136] At time t14, the signal at node A exceeds the decision threshold of the logic circuit 203.

[0137] At time t15, Pcnten changes from high level to low level, and the input to the counter circuit 211 becomes invalid.

[0138] As described above, according to this embodiment, during the exposure period, it is possible to prevent a through current from flowing through the waveform shaping unit 206 when the cathode is floating by performing a logical operation on the control signals Pctrl and Pcnten.

[0139] 15 shows an example of the drive timing in which the cutoff unit 205 is put into the cutoff state when the control signal Pctrl goes high during the exposure period, the switch 202 is turned off, and the APD 210 is in the standby state. The drive timing is not limited to this, and for example, the switch 202 may be controlled to be in the standby state when the count value of the counter circuit 211 reaches a maximum.

[0140] (Sixth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 16. Fig. 16 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0141] The photoelectric conversion devices described in the first to sixth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Also included in the photoelectric conversion system is a camera module equipped with an optical system such as a lens and an imaging device. Fig. 16 illustrates a block diagram of a digital still camera as an example of such systems.

[0142] 16 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. The system further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0143] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary to output image data. The signal processing unit 1007 may be formed on the same semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004.

[0144] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0145] The photoelectric conversion system further includes an overall control and calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0146] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0147] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0148] (Seventh embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 17. Fig. 17 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0149] FIG. 17(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 1300 includes an image capture device 1310. The image capture device 1310 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 1300 includes an image processing unit 1312 that performs image processing on multiple pieces of image data acquired by the image capture device 1310, and a parallax acquisition unit 1314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 1318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0150] The photoelectric conversion system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to a control ECU 1330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 1318. The photoelectric conversion system 1300 is also connected to an alarm device 1340 that issues an alarm to the driver based on the determination result of the collision determination unit 1318. For example, if the determination result of the collision determination unit 1318 indicates a high possibility of a collision, the control ECU 1330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0151] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 1300. Fig. 20 and Fig. 17(b) show a photoelectric conversion system for imaging the area in front of the vehicle (imaging range 1350). A vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0152] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0153] (Eighth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 18. Fig. 18 is a block diagram showing an example of the configuration of a range image sensor which is the photoelectric conversion system of this embodiment.

[0154] 18, the range image sensor 401 is configured to include an optical system 407, a photoelectric conversion device 408, an image processing circuit 404, a monitor 405, and a memory 406. The range image sensor 401 can obtain a range image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected toward the subject from a light source device 409 and reflected from the surface of the subject.

[0155] The optical system 407 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photoelectric conversion device 408, forming an image on the light receiving surface (sensor section) of the photoelectric conversion device 408.

[0156] The photoelectric conversion device 408 is the photoelectric conversion device of each of the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photoelectric conversion device 408 is supplied to the image processing circuit 404.

[0157] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 408. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording).

[0158] In the range image sensor 401 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0159] (Ninth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 19. Fig. 19 is a diagram showing an example of a schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system of this embodiment.

[0160] 19 shows an operator (doctor) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1150. As shown in the figure, the endoscopic surgery system 1150 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0161] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the example shown, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0162] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0163] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is sent to a camera control unit (CCU) 1135 as RAW data.

[0164] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0165] Under the control of the CCU 1135 , the display device 1136 displays an image based on the image signal that has been subjected to image processing by the CCU 1135 .

[0166] The light source device 1203 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0167] The input device 1137 is an input interface for the endoscopic surgery system 1150. A user can input various information and instructions to the endoscopic surgery system 1150 via the input device 1137.

[0168] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0169] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 1203. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0170] Furthermore, the light source device 1203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0171] The light source device 1203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, by irradiating light with a narrower band than the light (i.e., white light) used during normal observation, specific tissues such as blood vessels on the surface of the mucous membrane can be photographed with high contrast. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained from fluorescence generated by irradiating excitation light onto a body tissue. Fluorescence observation can involve irradiating excitation light onto a body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 can be configured to supply narrowband light and / or excitation light compatible with such special light observation.

[0172] (Tenth embodiment) The photoelectric conversion system of this embodiment will be described with reference to FIGS. 20(a) and (b). FIG. 20(a) illustrates glasses 1600 (smart glasses) which are the photoelectric conversion system of this embodiment. The glasses 1600 have a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the above embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 20(a).

[0173] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0174] FIG. 20(b) illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612, which includes a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0175] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0176] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0177] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0178] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0179] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first and second field-of-view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0180] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0181] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0182] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0183] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0184] Furthermore, the photoelectric conversion systems shown in the sixth and seventh embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 16 to 20. The same applies to the ToF system shown in the eighth embodiment, the endoscope shown in the ninth embodiment, and the smart glasses shown in the tenth embodiment.

[0185] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0186] 201 APD 202 Switch 205 Cut-off means 206 first PMOS transistor 207 First NMOS transistor VH First power supply VL Second power supply VDD Third power supply GND Fourth power supply nodeA 1st terminal

Claims

1. an avalanche photodiode having a first terminal and a second terminal; a first power supply connected to the first terminal; a second power supply connected to the second terminal; a switch that switches a resistance value between the first power supply and the first terminal; a third power source; and a fourth power source; and a first PMOS transistor and a first NMOS transistor connected in series between the third power supply and the fourth power supply; a first interrupting means for interrupting an electrical path between the third power source and the fourth power source; a first chip on which the avalanche photodiode is disposed; a second chip on which the first interrupting means is disposed, the first terminal of the avalanche photodiode is connected to the gates of the first PMOS transistor and the first NMOS transistor; The photoelectric conversion device is characterized in that the second chip and the first chip are stacked.

2. 2. The photoelectric conversion device according to claim 1, wherein the switch, the first PMOS transistor, and the first NMOS transistor are arranged on the second chip.

3. 3. The photoelectric conversion device according to claim 2, wherein the switch is turned off while a reverse bias voltage is supplied to the avalanche photodiode, and the first interrupting means interrupts the electrical path during a period in which the off state is maintained.

4. the switch is a MOS transistor, and a gate of the switch is connected to a first control line; 4. The photoelectric conversion device according to claim 3, wherein a state in which the voltage applied to the avalanche photodiode exceeds a breakdown voltage and a state in which the voltage applied to the avalanche photodiode does not exceed the breakdown voltage are controlled.

5. the switch is a MOS transistor, and a gate of the switch is connected to a first control line; 4. The photoelectric conversion device according to claim 3, wherein a standby state in which avalanche multiplication by the avalanche photodiode is possible and a recharge state in which the avalanche photodiode is restored to a state in which avalanche multiplication by the avalanche photodiode is possible are controlled.

6. the first cutoff means is a MOS transistor, and a gate of the first cutoff means is connected to a second control line; The photoelectric conversion device according to claim 5, characterized in that the electrical path is controlled between a conductive state and a non-conductive state by a second signal input from the second control line of the first interruption means.

7. the second signal is generated by a logical operation of a first signal input from the first control line and a third signal; 7. The photoelectric conversion device according to claim 6, wherein the first cutoff means is controlled by the second signal.

8. 2. The photoelectric conversion device according to claim 1, wherein the first PMOS transistor and the first NMOS transistor have a waveform shaping function for generating a pulse from the output signal of the avalanche photodiode.

9. 9. The photoelectric conversion device according to claim 8, wherein an output terminal of the logic circuit including the first cutoff means is connected to a counter circuit.

10. the logic circuit has a second PMOS transistor and a second NMOS transistor; the source of the first PMOS transistor is connected to the third power supply; the source of the first NMOS transistor is connected to the fourth power supply; the drain of the first PMOS transistor and the source of the second PMOS transistor are connected together; a drain of the second PMOS transistor, a drain of the first NMOS transistor, and a drain of the second NMOS transistor are connected together; 10. The photoelectric conversion device according to claim 9, wherein the source of the first NMOS transistor and the source of the second NMOS transistor are connected together.

11. the logic circuit has a second PMOS transistor and a second NMOS transistor; the source of the first PMOS transistor is connected to a third power supply; the source of the first NMOS transistor is connected to a fourth power supply; the drain of the first PMOS transistor, the drain of the second PMOS transistor, and the drain of the second NMOS transistor are connected together; the source of the first PMOS transistor and the source of the second PMOS transistor are connected together; 10. The photoelectric conversion device according to claim 9, wherein the drain of the first NMOS is connected to the source of the second NMOS.

12. the logic circuit has a second PMOS transistor and a second NMOS transistor; the source of the first PMOS transistor is connected to a third power supply; the source of the first NMOS transistor is connected to a fourth power supply; the source of the second PMOS transistor is connected to the drain of the first PMOS transistor; the drain of the first NMOS transistor is connected to the source of the second NMOS transistor; 10. The photoelectric conversion device according to claim 9, wherein the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected together.

13. the photoelectric conversion device has a second blocking means, The photoelectric conversion device according to claim 9, characterized in that a first terminal of the second cutoff means is connected between the output terminal of the logic circuit and the input terminal of the counter circuit, and a second terminal of the second cutoff means is connected to a power supply or ground potential.

14. 2. The photoelectric conversion device according to claim 1, wherein the avalanche photodiode outputs a photon detection signal in response to detection of a photon during an exposure period.

15. 15. The photoelectric conversion device according to claim 14, wherein the first cutoff means controls the electrical path to be in a cutoff state during periods other than the exposure period.

16. 2. The photoelectric conversion device according to claim 1, wherein the first power supply and the third power supply are power supplies that supply a common voltage.

17. The photoelectric conversion device according to any one of claims 1 to 16, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

18. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 16, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

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