solid-state imaging device

Abstract

Provided is a solid-state imaging device capable of improving the electric characteristics of a transistor of a pixel circuit while achieving a finer pixel pattern. The solid-state imaging device comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a plurality of pixels arranged in a matrix along the planar direction, the pixel including a photoelectric conversion element. The second semiconductor layer is stacked on the first semiconductor layer on the opposite side to the light incident side of the pixels. A first transistor electrically connected to the pixel is disposed on the second semiconductor layer. The first transistor has the gate length direction tilted with respect to the array direction of the pixels.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device. [Background technology]

[0002] Patent Document 1 discloses an imaging element. In the imaging element, a second substrate is stacked on a first substrate. Pixels (sensor pixels) that perform photoelectric conversion are arranged on the first substrate. Pixel circuits (readout circuits) that output pixel signals based on charges output from the pixels are arranged on the second substrate. In an image sensor, the pixels and pixel circuits are arranged on separate substrates, which allows sufficient space to be secured for the arrangement of pixel circuits even as pixels become increasingly miniaturized. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. WO2019 / 131965A1 Summary of the Invention

[0004] The trend in image sensors is toward further miniaturization of pixels. As pixels become smaller, the layout area of ​​transistors in pixel circuits arranged corresponding to the pixels becomes smaller. Therefore, there is room for improvement in preventing the occurrence of short channel effects, effectively suppressing the effects of noise, and improving transistor characteristics.

[0005] The present disclosure provides a solid-state imaging device that can improve the electrical characteristics of transistors in pixel circuits while realizing miniaturization of pixels.

[0006] A solid-state imaging device according to an embodiment of the present disclosure includes a first semiconductor layer in which a plurality of pixels, each having a photoelectric conversion element, are arranged in a matrix along a surface direction, and a second semiconductor layer electrically connected to the pixels, having a first transistor whose gate length direction is inclined with respect to the pixel arrangement direction, and stacked on the first semiconductor layer on the side opposite to the light incident side of the pixels. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic plan view of a pixel circuit of a solid-state imaging device according to a first embodiment of the present disclosure. [Figure 2] 2 is a schematic cross-sectional view of a solid-state imaging device including the pixel circuit shown in FIG. [Figure 3] 3 is a circuit diagram including pixels and pixel circuits of the solid-state imaging device shown in FIGS. 1 and 2. FIG. [Figure 4] 10 is a circuit diagram corresponding to FIG. 3 of a solid-state imaging device according to a second embodiment of the present disclosure. FIG. [Figure 5] 5 is a schematic plan view of a pixel circuit of the solid-state imaging device shown in FIG. 4, corresponding to FIG. [Figure 6] 10 is a schematic cross-sectional view of a main part corresponding to FIG. 2, showing a pixel and a pixel circuit of a solid-state imaging device according to a third embodiment of the present disclosure. [Figure 7] 1. FIG. 9 is a schematic plan view corresponding to FIG. 1 of a pixel circuit of a solid-state imaging device according to a fourth embodiment of the present disclosure. [Figure 8] 10 is a schematic plan view of a pixel circuit of a solid-state imaging device according to a fifth embodiment of the present disclosure, the plan view corresponding to FIG. [Figure 9] FIG. 11 is a schematic cross-sectional view of a main part corresponding to FIG. 2, showing a pixel and a pixel circuit of a solid-state imaging device according to a sixth embodiment of the present disclosure. [Figure 10] FIG. 13 is a schematic cross-sectional view of a capacitor mounted on a solid-state imaging device according to a seventh embodiment of the present disclosure. [Figure 11] FIG. 19 is a schematic cross-sectional view of a resistor mounted on a solid-state imaging device according to an eighth embodiment of the present disclosure. [Figure 12] FIG. 13 is a schematic cross-sectional view of a memory element mounted on a solid-state imaging device according to a ninth embodiment of the present disclosure. [Figure 13] 1 is a block diagram illustrating an example of a schematic configuration of a vehicle control system according to a first application example of an embodiment of the present disclosure. FIG. [Figure 14] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 15] FIG. 10 is a diagram illustrating a second application example according to an embodiment of the present disclosure, which is an example of a schematic configuration of an endoscopic surgery system. [Figure 16] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First embodiment In the first embodiment, an example in which the present technology is applied to a solid-state imaging device will be described. 2. Second embodiment The second embodiment will explain an example in which a plurality of amplifying transistors are arranged in one pixel circuit in the solid-state imaging device according to the first embodiment. 3. Third embodiment The third embodiment will explain an example in which the bonding method between the first semiconductor layer and the second semiconductor layer in the solid-state imaging device according to the first embodiment is changed. 4. Fourth embodiment The fourth embodiment will describe an example in which the planar shape of the pixel circuit is changed in the solid-state imaging device according to the first embodiment. 5. Fifth Embodiment The fifth embodiment describes a modification of the transistor arrangement layout of the pixel circuit in the solid-state imaging device according to the first embodiment. 6. Sixth Embodiment The sixth embodiment describes an example in which the crystal orientation of the second semiconductor layer in which the pixel circuits are disposed is changed in the solid-state imaging device according to the third embodiment. 7. Seventh Embodiment The seventh embodiment will explain an example in which a capacitor is provided in the second semiconductor layer in the solid-state imaging device according to the first embodiment. 8. Eighth Embodiment The eighth embodiment describes an example in which a resistor is provided in the second semiconductor layer in the solid-state imaging device according to the first embodiment. 9. Ninth Embodiment The ninth embodiment describes an example in which a memory element is provided in the second semiconductor layer in the solid-state imaging device according to the first embodiment. 10. Mobile application examples This section explains an example of applying this technology to a vehicle control system, which is an example of a mobile object control system. 11. Application to an endoscopic surgery system An example of applying this technology to an endoscopic surgery system will be described. 12. Other embodiments

[0009] <1. First embodiment> A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described with reference to FIGS.

[0010] Here, the arrow X direction shown as appropriate in the drawings indicates one planar direction of the solid-state imaging device 1 placed on a flat surface for convenience. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates an upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly coincide with the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are shown to facilitate understanding of the description and are not intended to limit the directions of the present technology.

[0011] [Configuration of solid-state imaging device 1] (1) Circuit configuration of pixel 100 and pixel circuit 200 of solid-state imaging device 1 FIG. 3 shows an example of the circuit configuration of the pixel 100 and the pixel circuit 200 that constitute the solid-state imaging device 1. One pixel 100 is composed of a photoelectric conversion element (photodiode) 101 and a transfer transistor 102 connected in series. The anode terminal of the photoelectric conversion element 101 is connected to a reference potential GND, and the cathode terminal is connected to one terminal of the transfer transistor 102. The photoelectric conversion element 101 converts light incident from outside the solid-state imaging device 1 into an electric signal. The other terminal of the transfer transistor 102 is connected to the pixel circuit 200. The control terminal of the transfer transistor 102 is connected to a horizontal signal line 103.

[0012] The pixel circuit 200 includes a floating diffusion (FD) conversion gain switching transistor 201, a reset transistor 202, an amplification transistor 203, and a selection transistor 204. The other terminal of the transfer transistor 102 is connected to one terminal of the FD conversion gain switching transistor 201 and a control terminal of the amplification transistor 203. The other terminal of the FD conversion gain switching transistor 201 is connected to one terminal of the reset transistor 202. The other terminal of the reset transistor 202 is connected to a power supply potential VDD. One terminal of the amplification transistor 203 is connected to one terminal of the selection transistor 204. The other terminal of the amplification transistor 203 is connected to a power supply potential VDD. The other terminal of the selection transistor 204 is connected to a vertical signal line 205. In the solid-state imaging device 1 according to the first embodiment, one pixel circuit 200 is provided for every four pixels 100.

[0013] (2) Vertical cross-sectional structure of the solid-state imaging device 1 FIG. 2 shows an example of a vertical cross-sectional configuration of the solid-state imaging device 1. Here, the solid-state imaging device 1 is configured as a back-illuminated image sensor. When viewed in the direction of arrow Y (hereinafter simply referred to as "side view"), the solid-state imaging device 1 is configured by sequentially stacking a first base 10, a second base 20, and a third base 30. That is, the second base 20 is stacked on the first base 10, and the second base 20 is bonded to the first base 10. The third base 30 is stacked on the second base 20, and the third base 30 is bonded to the second base 20.

[0014] The first base substrate 10 includes a first semiconductor layer 11 and a first wiring layer 12 disposed on the second base substrate 20 side of the first semiconductor layer 11. The first semiconductor layer 11 is made of single crystal silicon (Si).

[0015] The pixels 100 are formed in the first semiconductor layer 11. Although the detailed structure of the photoelectric conversion element 101 of the pixel 100 is omitted, it has an n-type semiconductor region and a p-type semiconductor region, and is formed by a pn junction between the two. A light-receiving lens 13 is disposed on the light incident side of the photoelectric conversion element 101, with a charge fixing film and an insulating film (not shown) interposed therebetween. The light-receiving lens 13 is disposed for each pixel 100. The light-receiving lens 13 can condense light incident on the photoelectric conversion element 101. Here, the light incident side is the side of the first semiconductor layer 11 opposite to the second base 20 side.

[0016] The transfer transistor 102 of the pixel 100, whose detailed structure is similarly omitted, is configured on the surface portion of the first semiconductor layer 11 on the second substrate 20 side. The transfer transistor 102 is formed of an n-channel insulated gate field effect transistor (IGFET). The transfer transistor 102 includes a pair of main electrodes (terminals) that are a source region and a drain region, a channel formation region, a gate insulating film, and a gate electrode (control terminal). Here, the IGFET includes at least a metal oxide semiconductor field effect transistor (MOSFET) and a metal insulator semiconductor field effect transistor (MISFET).

[0017] Furthermore, a pixel isolation region 14 is disposed between adjacent pixels 100. The pixel isolation region 14 optically and electrically isolates the adjacent pixels 100 from each other. The arrangement layout of the pixels 100 and the arrangement layout of the pixel isolation region 14 will be described in detail later together with the arrangement layout of the amplification transistors 203 and the like that constitute the pixel circuit 200.

[0018] The first wiring layer 12 includes a wiring 121, a multilayer wiring 122, a first terminal 123, and an insulator . One end of the wiring 121 is connected to the transfer transistor 102, and the other end of the wiring 121 is connected to the multilayer wiring 122. The wiring 121 is configured as a through wiring that penetrates the first wiring layer 12 in the thickness direction, and is made of a wiring material such as tungsten (W). Although there is no limitation on the number of layers, the multilayer wiring 122 is configured with a three-layer wiring structure. The wiring of each layer of the multilayer wiring 122 is connected through connection holes. The multilayer wiring 122 is formed of a wiring material such as aluminum (Al). One end of the first terminal 123 is connected to the multilayer wiring 122, and the other end of the first terminal 123 is exposed from the surface of the first wiring layer 12 on the second base 20 side. The first terminal 123 is made of, for example, copper (Cu). The insulator 124 is formed by burying the wiring 121, the multilayer wiring 122, and the first terminal 123. The insulator 124 is actually formed by stacking multiple insulating films. The insulator 124 is formed of a silicon oxide film (SiO), a silicon nitride film (SiN), or a combination of both.

[0019] The second base 20 includes a second semiconductor layer 21 and a second wiring layer 22 disposed on the first base 10 side of the second semiconductor layer 21. The second semiconductor layer 21 is made of single crystal silicon. A pixel circuit 200 is configured in the second semiconductor layer 21. That is, an FD conversion gain switching transistor 201, a reset transistor 202, an amplification transistor 203, and a selection transistor 204 are configured in the second semiconductor layer 21 (see FIG. 3). The FD conversion gain switching transistor 201, the reset transistor 202, the amplification transistor 203, and the selection transistor 204 that configure the pixel circuit 200 each correspond to a "first transistor" according to the present technology.

[0020] The pixel circuit 200 is disposed on the main surface of the second semiconductor layer 21 on the first substrate 10 side. The term "main surface portion" is used to mean the main surface portion where transistors, capacitors, resistors, etc. are formed.

[0021] The reset transistor 202 is disposed on the main surface of the second semiconductor layer 21 in a region surrounded by an element isolation region 28. Although the structure is not particularly limited, a trench-structured element isolation region 28 is used here, thereby improving the degree of integration. The reset transistor 202 includes a pair of main electrodes 23, a channel formation region, a gate insulating film 25, and a gate electrode 26. The pair of main electrodes 23 are a source region and a drain region, and are formed by n-type semiconductor regions. The channel formation region is formed by the second semiconductor layer 21 between the pair of main electrodes 23. The gate insulating film 25 is disposed along the channel formation region, and is formed by, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof. The gate electrode 26 is disposed along the gate insulating film 25, and is formed by, for example, polycrystalline silicon. Like the transfer transistor 102, the reset transistor 202 is configured by an n-channel IGFET.

[0022] Here, the gate length direction of the first transistor according to the present technology, including the reset transistor 202, is the direction in which carriers flow between the pair of main electrodes 23, and is the same direction as the channel length direction.

[0023] Similar to the reset transistor 202, the select transistor 204 is disposed on the main surface of the second semiconductor layer 21 within a region surrounded by the element isolation region 28. The select transistor 204 includes a pair of main electrodes 23, a channel formation region, a gate insulating film 25, and a gate electrode 26. The select transistor 204 is configured by an n-channel IGFET. Although not shown in Fig. 2, the FD conversion gain switching transistor 201, like the reset transistor 202, is disposed on the main surface of the second semiconductor layer 21 in a region surrounded by an element isolation region 28 (see Fig. 1). The FD conversion gain switching transistor 201 includes a pair of main electrodes 23, a channel formation region, a gate insulating film 25, and a gate electrode 26. The FD conversion gain switching transistor 201 is configured by an n-channel IGFET.

[0024] Similar to the reset transistor 202, the amplifier transistor 203 is disposed on the main surface of the second semiconductor layer 21 in a region surrounded by the element isolation region 28. The amplifier transistor 203 includes a pair of main electrodes 23, a channel formation region, a gate insulating film 25, and a gate electrode 26. The amplifier transistor 203 is configured by an n-channel IGFET. Here, the amplification transistor 203 has a fin structure. The fin structure is a structure in which both ends of the gate electrode 26 (and the gate insulating film 25) in the gate width direction extend in the depth direction from the main surface of the second semiconductor layer 21, thereby expanding the gate width dimension in the depth direction. When the fin structure is adopted, the amount of current of the amplification transistor 203 can be increased.

[0025] The second wiring layer 22 includes a wiring 221 , a multilayer wiring 222 , a second terminal 223 , and an insulator 224 . One end of the wiring 221 is connected to the amplification transistor 203, and the other end of the wiring 221 is connected to the multi-layer wiring 222. Similar to the wiring 121, the wiring 221 is configured as a through wiring that penetrates the second wiring layer 22 in the thickness direction. Although there is no limitation on the number of layers, the multilayer wiring 222 is configured to have a three-layer wiring structure, similar to the multilayer wiring 122. One end of the second terminal 223 is connected to the multilayer wiring 222, and the other end of the second terminal 223 is connected to the first terminal Similar to the first terminal 123, the second terminal 223 is disposed so as to be exposed from the surface of the second wiring layer 22 on the first substrate 10 side. The second terminal 223 is disposed at a position corresponding to the first terminal 123, and is joined to and electrically connected to the first terminal 123. The insulator 224 is formed by embedding the wiring 221, the multilayer wiring 222, and the second terminal 223. The insulator 224 is made of the same material as the insulator 124.

[0026] In the solid-state imaging device 1 according to the first embodiment, the first terminal 123 of the first base body 10 and the second terminal 223 of the second base body 20 are joined facing each other. That is, the first base body 10 and the second base body 20 are connected by a face-to-face connection structure.

[0027] The third base 30 includes a third semiconductor layer 31 and a third wiring layer 32 disposed on the second base 20 side of the third semiconductor layer 31. The third semiconductor layer 31 is made of single crystal silicon. A peripheral circuit 300 that controls the operation of the pixel circuit 200 is disposed on the third semiconductor layer 31. Although detailed description will be omitted, the peripheral circuit 300 includes, for example, an input section, a timing control section, a row driving section, a column signal processing section, an image signal processing section, and an output section. The peripheral circuit 300 includes a complementary IGFET including an n-channel IGFET 301 and a p-channel IGFET 302. The complementary IGFET corresponds to the "second transistor" according to the present technology.

[0028] The n-channel IGFET 301 is disposed on the main surface of the third semiconductor layer 31 in a region surrounded by the element isolation region 38. Like the element isolation region 28, the element isolation region 38 has a trench structure. The n-channel IGFET 301 includes a pair of main electrodes 33, a channel formation region, a gate insulating film 35, and a gate electrode 36. The pair of main electrodes 33 are a source region and a drain region, and are formed by n-type semiconductor regions. The channel formation region is formed by a third semiconductor layer 31 between the pair of main electrodes 33. The gate insulating film 35 is disposed along the channel formation region and is formed, for example, from the same material as the gate insulating film 25. The gate electrode 36 is disposed along the gate insulating film 35 and is formed, for example, from the same material as the gate electrode 26. The p-channel IGFET 302 includes a pair of main electrodes 34, a channel formation region, a gate insulating film 35, and a gate electrode 36. The pair of main electrodes 34 are a source region and a drain region, and are formed by p-type semiconductor regions. The channel formation region is formed by a third semiconductor layer 31 between the pair of main electrodes 34. Although not shown, the n-channel IGFET 301 is formed in a p-type well region disposed on the main surface of the third semiconductor layer 31. The p-channel IGFET 302 is formed in an n-type well region disposed on the main surface of the third semiconductor layer 31.

[0029] The third wiring layer 32 includes a wiring 321 , a multilayer wiring 322 , and an insulator 324 . One end of the wiring 321 is connected to the complementary IGFET, and the other end of the wiring 321 is connected to the multi-layer wiring 322. Like the wiring 121, the wiring 321 is configured as a through wiring that penetrates the third wiring layer 32 in the thickness direction. Although there is no limitation on the number of layers, the multilayer wiring 322 is configured to have a three-layer wiring structure, similar to the multilayer wiring 122. The multilayer wiring 322 is connected to the multilayer wiring 222 of the second base 20 via through wiring (not shown). The insulator 324 is formed by burying the wiring 321 and the multilayer wiring 322. The insulator 324 is made of the same material as the insulator 124.

[0030] (3) Planar Configuration of the Pixel 100 and the Pixel Circuit 200 FIG. 1 shows an example of an arrangement layout of pixels 100 and an arrangement layout of pixel circuits 200 when the solid-state imaging device 1 is viewed in the direction of arrow Z from the light incident side (hereinafter simply referred to as "planar view"). It represents.

[0031] A plurality of pixels 100 are arranged in a matrix along a plane direction parallel to the surface of the first semiconductor layer 11 of the first substrate 10. That is, the pixels 100 are arranged at regular intervals in the directions of arrow X and arrow Y. A pixel isolation region 14 is disposed between adjacent pixels 100 in the direction of arrow X and between adjacent pixels 100 in the direction of arrow Y. In the first embodiment, the pixels 100 are formed in a rectangular shape, more specifically, a square shape, in a plan view.

[0032] In the pixel circuit 200, the FD conversion gain switching transistor 201 and the reset transistor 202 are arranged in a line along the main surface of the second semiconductor layer 21, with their gate length directions aligned. Here, the gate length direction is the direction of the arrows labeled "Lg." Furthermore, the gate width direction is the direction of the arrows labeled "Lw." One main electrode 23 of the FD conversion gain switching transistor 201 is formed integrally with one main electrode 23 of the reset transistor 202. The gate length directions of the FD conversion gain switching transistor 201 and the reset transistor 202 are inclined with respect to the arrangement direction of the pixels 100 (the direction of the arrow X or the direction of the arrow Y). In the first embodiment, the FD conversion gain switching transistor 201 and the reset transistor 202 are arranged aligned with the diagonal direction of the rectangular pixel 100, i.e., with their gate length directions parallel to the diagonal direction.

[0033] Furthermore, in the pixel circuit 200, the amplification transistor 203 and the selection transistor 204 have their gate length directions aligned and are arranged in a line along the major surface of the second semiconductor layer 21. One main electrode 23 of the amplification transistor 203 is formed integrally with one main electrode 23 of the selection transistor 204. As with the FD conversion gain switching transistor 201 and the reset transistor 202, the gate length directions of the amplification transistor 203 and the selection transistor 204 are inclined with respect to the arrangement direction of the pixels 100 (the direction of arrow X or the direction of arrow Y). The gate length directions of the amplification transistor 203 and the selection transistor 204 are parallel to the FD conversion gain switching transistor 201 and the reset transistor 202, and they are spaced apart in the gate width direction.

[0034] Furthermore, one pixel circuit 200 is arranged for four pixels 100. An FD conversion gain switching transistor 201 of one pixel circuit 200 is arranged so that its gate length direction coincides with the diagonal direction of one of the four pixels 100. Similarly, a reset transistor 202 of one pixel circuit 200 is arranged so that its gate length direction coincides with the diagonal direction of one of the four pixels 100. An amplification transistor 203 of one pixel circuit 200 is arranged so that its gate length direction coincides with the diagonal direction of one of the four pixels 100. And a selection transistor 204 of one pixel circuit 200 is arranged so that its gate length direction coincides with the diagonal direction of one of the four pixels 100.

[0035] Although not limited to these values, the dimension of one side of one pixel 100 is set to, for example, 0.4 μm or more and 2.0 μm or less. Meanwhile, the gate length dimensions of each of the FD conversion gain switching transistor 201, reset transistor 202, and selection transistor 204 of the pixel circuit 200 are set to, for example, 150 nm or more and 300 nm or less. Furthermore, the gate length dimension of the amplification transistor 203 is longer than the gate length dimensions of the reset transistor 202, etc., and is set to, for example, 300 nm or more and 600 nm or less.

[0036] In other words, pixel isolation regions 14 are disposed between the pixels 100, and the pixel isolation regions 14 are formed in a grid pattern in plan view. That is, the pixel isolation regions 14 are configured with first isolation walls 141 that extend in the direction of arrow X and are arranged at regular intervals in the direction of arrow Y, and second isolation walls 142 that extend in the direction of arrow Y and are arranged at regular intervals in the direction of arrow X. Therefore, the gate length direction of the FD conversion gain switching transistor 201 and the like of the pixel circuit 200 is inclined with respect to the extension direction of the first isolation wall 141 or the second isolation wall 142.

[0037] Although not shown, the gate length direction of each of the n-channel IGFET 301 and p-channel IGFET 302 that constitute the peripheral circuit 300 is parallel to the arrangement direction of the pixels 100.

[0038] [Action and effect] As shown in Fig. 2, the solid-state imaging device 1 according to the first embodiment includes a first semiconductor layer 11 and a second semiconductor layer 21. As shown in Fig. 1, the first semiconductor layer 11 has a plurality of pixels 100, each having a photoelectric conversion element 101, arranged in a matrix along the surface direction. The second semiconductor layer 21 is stacked on the first semiconductor layer 11 on the side opposite to the light incident side of the pixels 100. The second semiconductor layer 21 has first transistors disposed therein that are electrically connected to the pixels 100 and have gate length directions inclined with respect to the arrangement direction of the pixels 100. The first transistors are an FD conversion gain switching transistor 201, a reset transistor 202, an amplification transistor 203, or a selection transistor 204 that constitute a pixel circuit 200. The pixels 100 are disposed in the first semiconductor layer 11, and the first transistors are disposed in the second semiconductor layer 21 independently of the pixels 100. Therefore, even if the pixels 100 are miniaturized and the number of arranged pixels 100 is increased, an area for disposing the first transistors in the second semiconductor layer 21 can be secured. In addition, because the gate length direction of the first transistor is inclined with respect to the arrangement direction of the pixels 100, the gate length dimension of the first transistor can be increased. This effectively suppresses or prevents the occurrence of short channel effects or noise in the first transistor, thereby improving the electrical characteristics of the first transistor. In particular, the amplification transistor 203 as the first transistor can effectively suppress or prevent the occurrence of RTS (Random Telegraph Signal) noise. This improves the electrical characteristics of the pixel circuit 200. In addition, because the gate length direction of the first transistor is inclined with respect to the arrangement direction of the pixels 100, the gate width dimension of the first transistor can be expanded. In particular, the gate width dimensions of each of the amplifying transistor 203 and the selecting transistor 204 can be expanded. This makes it possible to improve the mutual conductance (gm) of each of the amplifying transistor 203 and the selecting transistor 204, and effectively suppress or prevent thermal noise. Furthermore, because the mutual conductance is improved, the operating speed of the pixel circuit 200 can be increased.

[0039] 1, in the solid-state imaging device 1, the pixel 100 is formed in a rectangular shape in a plan view. The gate length direction of the first transistor is parallel to the diagonal direction of the pixel 100 in a plan view. This allows the gate length dimension of the first transistor to be maximized. Specifically, the gate length dimension of the first transistor can be approximately 1.4 times longer than when the gate length direction is parallel to the arrangement direction of the pixels 100. Therefore, the electrical characteristics of the first transistor can be further improved.

[0040] Furthermore, in the solid-state imaging device 1, the first transistor constitutes a pixel circuit 200 connected to the pixel 100, as shown in Fig. 3. That is, as shown in Fig. 2, the pixel 100 is disposed in the first semiconductor layer 11, and the pixel circuit 200 is disposed in the second semiconductor layer 21. Therefore, the pixel 100 can be miniaturized independently of the layout area of ​​the pixel circuit 200, and the number of pixels 100 arranged can be increased.

[0041] 1, in the solid-state imaging device 1, the gate length of the amplifying transistor 203 serving as the first transistor is longer than the gate length of the selecting transistor 204 or the reset transistor 202. Therefore, in the amplifying transistor 203, the occurrence of RTS noise can be more effectively suppressed or prevented, and the electrical characteristics can be further improved.

[0042] 2, the solid-state imaging device 1 further includes a first terminal 123 and a second terminal 223. The first terminal 123 is disposed on the second semiconductor layer 21 side of the first semiconductor layer 11 and is electrically connected to the pixel 100 via the first wiring layer 12. The second terminal 223 is disposed on the first semiconductor layer 11 side of the second semiconductor layer 21 and is electrically connected to the first transistor via the second wiring layer 22 and is joined to the first terminal 123. That is, the first base 10 having the first semiconductor layer 11 and the second base 20 having the second semiconductor layer 21 are connected by a face-to-face connection structure. In the face-to-face connection structure, a second wiring layer 222 is disposed in the connection path between the pixel 100 and the first transistor, and in the connection path between the second terminal 223 and the first transistor. Therefore, wiring can be routed in the second wiring layer 22, and the position of the first transistor can be freely laid out.

[0043] 2, the solid-state imaging device 1 also includes a third semiconductor layer 31. The third semiconductor layer 31 is stacked on the second semiconductor layer 21 on the opposite side to the first semiconductor layer 11. The third semiconductor layer 31 has a second transistor, and the second transistor forms a peripheral circuit 300 that controls the pixel circuit 200. The second transistor is, for example, a complementary IGFET. That is, the pixel 100 is disposed in the first semiconductor layer 11, the pixel circuit 200 is disposed in the second semiconductor layer 21, and the peripheral circuit 300 is disposed in the third semiconductor layer 31. Therefore, the first semiconductor layer 11 can be mainly composed of pixels 100, and the number of pixels 100 that can be arranged can be increased.

[0044] 2 is parallel to the arrangement direction of the pixels 100. In other words, the gate length direction of the first transistor constituting the pixel circuit 200 is inclined with respect to the gate length direction of the second transistor. Therefore, the electrical characteristics of the first transistor can be optimized independently of the second transistor.

[0045] <2. Second embodiment> A solid-state imaging device 2 according to a second embodiment of the present disclosure will be described with reference to Figures 4 and 5. In the second embodiment and the embodiments described thereafter, components that are the same as or substantially the same as components of the solid-state imaging device 1 according to the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0046] [Configuration of solid-state imaging device 2] FIG. 4 shows an example of the circuit configuration of the pixel 100 and the pixel circuit 200 that constitute the solid-state imaging device 2. In the solid-state imaging device 2 according to the second embodiment, a pixel circuit 200 includes an FD conversion gain switching transistor 201, a reset transistor 202, two amplification transistors 203, and a selection transistor 204. That is, one pixel circuit 200 is provided with two amplification transistors 203. The two amplification transistors 203 are electrically connected in parallel.

[0047] FIG. 5 shows an example of an array layout of the pixels 100 and the pixel circuits 200 of the solid-state imaging device 2 in a plan view. In the pixel circuit 200, the FD conversion gain switching transistor 201 and the reset transistor 202 are arranged in a line along the main surface of the second semiconductor layer 21, with their gate length directions aligned. One main electrode 23 of the FD conversion gain switching transistor 201 is formed integrally with one main electrode 23 of the reset transistor 202. The gate length directions of the FD conversion gain switching transistor 201 and the reset transistor 202 are inclined with respect to the array direction of the pixels 100. In the second embodiment, similar to the solid-state imaging device 1 according to the first embodiment, the FD conversion gain switching transistor 201 and the reset transistor 202 are arranged with their gate length directions aligned with the diagonal direction of the rectangular shape of the pixel 100.

[0048] The selection transistor 204 is arranged on an extension of the gate length direction of the FD conversion gain switching transistor 201 and the reset transistor 202 so that the gate length direction is aligned with the extension of the gate length direction of the FD conversion gain switching transistor 201 and the reset transistor 202 .

[0049] Furthermore, in the pixel circuit 200, two amplification transistors 203 are arranged in a line along the major surface of the second semiconductor layer 21, with their gate length directions aligned. One main electrode 23 of each of the two amplification transistors 203 is integrally formed. Like the FD conversion gain switching transistor 201, the reset transistor 202, and the selection transistor 204, the gate length directions of the two amplification transistors 203 are inclined with respect to the arrangement direction of the pixels 100. The two amplification transistors 203 are spaced apart in the gate width direction, with their gate length directions parallel to the FD conversion gain switching transistor 201, the reset transistor 202, and the selection transistor 204.

[0050] The components other than the pixel circuit 200 are the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0051] [Action and effect] According to the solid-state imaging device 2 of the second embodiment, it is possible to obtain the same effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0052] 4 and 5, in the solid-state imaging device 2, a plurality of amplification transistors 203 are electrically connected in parallel to one pixel circuit 200. Here, two amplification transistors 203 are electrically connected in parallel. Therefore, the generation of RTS noise can be more effectively suppressed or prevented in the amplification transistor 203, and the electrical characteristics can be further improved.

[0053] 3. Third Embodiment A solid-state imaging device 3 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0054] [Configuration of solid-state imaging device 3] FIG. 6 shows an example of a longitudinal cross-sectional configuration of a main part showing the pixel 100 and the pixel circuit 200 of the solid-state imaging device 3. As shown in FIG. Similar to the solid-state imaging device 1 according to the first embodiment, the solid-state imaging device 3 according to the third embodiment is configured by sequentially stacking a first base 10, a second base 20, and a third base 30 (not shown) in side view. Here, the second base 20 has a second semiconductor layer 21 disposed on the first base 10 side and a second wiring layer 22 disposed on the third base 30 side. The main surface of the second semiconductor layer 21 faces the third base 30, and an amplifying transistor 203 and the like that constitute a pixel circuit 200 (see FIG. 3 or 4) are configured on the main surface portion of the second semiconductor layer 21.

[0055] The pixels 100 and the pixel circuits 200 are electrically connected to each other using through-wires 125. One end of the through-wires 125 is connected to the transfer transistors 102 of the pixels 100. The other end of the through-wires 125 passes through the second semiconductor layer 21 in the thickness direction and is connected to the second wiring layer 22. The second wiring layer 22 is connected to the amplification transistor 203 and the FD conversion gain switching transistor 201 (not shown). That is, the first substrate 10 and the second substrate 20 are connected by a face-to-back connection structure.

[0056] The components other than the above-mentioned connection structure are the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0057] [Action and effect] According to the solid-state imaging device 3 of the third embodiment, it is possible to obtain the same effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0058] 6, in the solid-state imaging device 3, the first base 10 having the first semiconductor layer 11 and the second base 21 having the second semiconductor layer 21 are connected by a face-to-back connection structure. The pixels 100 and the pixel circuits 200 are connected by through-wires 125. Therefore, compared to the solid-state imaging device 1 according to the first embodiment, for example, the length of the signal path connecting the pixel 100 and the pixel circuit 200 is shorter, and therefore the signal-to-noise ratio (SN ratio) can be reduced.

[0059] 4. Fourth Embodiment A solid-state imaging device 4 according to a fourth embodiment of the present disclosure will be described with reference to FIG.

[0060] [Configuration of solid-state imaging device 4] FIG. 7 shows an example of the arrangement layout of the pixels 100 and the arrangement layout of the pixel circuits 200 of the solid-state imaging device 4. In FIG. In the solid-state imaging device 4 according to the fourth embodiment, in a plan view, the pixel 100 is formed in a rectangular shape in which the sides parallel to the direction of the arrow Y are longer than the sides parallel to the direction of the arrow X. The first transistors such as the amplifying transistor 203 that constitute the pixel circuit 200 are arranged with their gate length directions parallel to the diagonal direction of the pixel 100.

[0061] [Action and effect] The solid-state imaging device 4 according to the fourth embodiment can provide the same effects as those provided by the solid-state imaging device 1 according to the first embodiment.

[0062] <5. Fifth Embodiment> A solid-state imaging device 5 according to a fifth embodiment of the present disclosure will be described with reference to FIG.

[0063] [Configuration of solid-state imaging device 5] FIG. 8 shows an example of the arrangement layout of the pixels 100 and the arrangement layout of the pixel circuits 200 of the solid-state imaging device 5. In FIG. The solid-state imaging device 5 according to the fifth embodiment includes a plurality of pixel regions in a plan view. For ease of explanation, the solid-state imaging device 5 includes two pixel regions: a first pixel region 15 and a second pixel region 16.

[0064] In the first pixel region 15, first transistors are arranged in the same manner as in the solid-state imaging device 1 according to the first embodiment. That is, the FD conversion gain switching transistor 201, reset transistor 202, amplification transistor 203, and selection transistor 204 that constitute the pixel circuit 200 are arranged with their gate length directions inclined with respect to the arrangement direction of the pixels 100. The gate length directions of the amplification transistor 203 etc. are parallel to the diagonal direction of the pixels 100. The gate length direction of the amplification transistor 203 and the like is set at an angle α1 counterclockwise with respect to a boundary line CC that is virtually set at the boundary between the first pixel region 15 and the second pixel region 16. In this example, the angle α1 is 45 degrees.

[0065] In the second pixel region 16, an FD conversion gain switching transistor 201, a reset transistor 202, an amplification transistor 203, and a selection transistor 204 that constitute a pixel circuit 200 are arranged with their gate length directions inclined with respect to the arrangement direction of the pixels 100. The gate length directions of the amplification transistor 203 and the like are parallel to the diagonal direction of the pixels 100. In the second pixel region 16, the gate length direction of the amplification transistor 203 and the like is set at an angle α2 clockwise with respect to the boundary line CC. In this example, the angle α2 is 45 degrees.

[0066] That is, the gate length direction of the first pixel region 15 is set to be perpendicular to the gate length direction of the second pixel region 16. In other words, the gate length direction of the second pixel region 16 is set to be parallel to the gate width direction of the first pixel region 15.

[0067] [Action and effect] The solid-state imaging device 5 according to the fifth embodiment can provide the same effects as those provided by the solid-state imaging device 1 according to the first embodiment.

[0068] 6. Sixth Embodiment A solid-state imaging device 6 according to a sixth embodiment of the present disclosure will be described with reference to FIG.

[0069] [Configuration of solid-state imaging device 6] 9 shows an example of a vertical cross-sectional configuration of a main part showing the pixel 100 and the pixel circuit 200 of the solid-state imaging device 6. Here, a modification of the solid-state imaging device 3 according to the third embodiment will be described.

[0070] The solid-state imaging device 6 according to the sixth embodiment includes a second semiconductor layer 21N instead of the second semiconductor layer 21 of the second substrate 20 of the solid-state imaging device 3 according to the third embodiment. The second semiconductor layer 21N is diced from a semiconductor wafer (single crystal silicon substrate) having a 0 (zero) degree notch, which is used in the manufacturing process of the solid-state imaging device 6. The diced side of the second semiconductor layer 21N is <110> It is a crystal plane.

[0071] The amplification transistor 203 disposed on the main surface of the second semiconductor layer 21N employs a fin structure as described above, and the gate length direction is inclined at 45 degrees with respect to the arrangement direction of the pixels 100. Therefore, the sidewall of the channel formation region (second semiconductor layer 21N) of the amplification transistor 203 is <100> It is set on a crystal plane.

[0072] [Action and effect] The solid-state imaging device 6 according to the sixth embodiment can achieve the same effects as those achieved by the solid-state imaging device 3 according to the third embodiment.

[0073] The solid-state imaging device 6 also includes a second semiconductor layer 21N diced from a semiconductor wafer having a 0-degree notch. The second semiconductor layer 21N includes an amplifying transistor 203 having a fin structure whose gate length direction is parallel to the arrangement direction of the pixels 100. Therefore, the side surface of the channel forming region of the amplifying transistor 203 is <100> This is the crystal plane. In single crystal silicon, <100> On the crystal plane, <110> The interface state that worsens noise is lower than that of the crystal plane, so noise in the amplifier transistor 203 can be effectively suppressed or prevented. In addition, even if the second semiconductor layer 21 is replaced with the second semiconductor layer 21N in the solid-state imaging device 1 of the first embodiment, the same effects as those obtained by the solid-state imaging device 6 of the sixth embodiment can be obtained.

[0074] 7. Seventh Embodiment A solid-state imaging device 7 according to a seventh embodiment of the present disclosure will be described with reference to FIG.

[0075] [Configuration of solid-state imaging device 7] FIG. 10 shows an example of a vertical cross-sectional configuration of the capacitor 206 mounted on the second substrate 20 of the solid-state imaging device 7. In FIG. The solid-state imaging device 7 includes a capacitor (capacitive element) 206 in a region inside the pixel circuit 200 or outside the pixel circuit 200 in the second semiconductor layer 21 of the second substrate 20. The capacitor 206 includes the second semiconductor layer 21 as a second electrode, a dielectric 25A disposed on the second semiconductor layer 21, and a metal body 26A disposed on the dielectric 25A and as a first electrode. That is, the capacitor 206 is configured as a metal body / dielectric / semiconductor type capacitor.

[0076] The second semiconductor layer 21 of the capacitor 206 is made of single crystal silicon. The dielectric 25A is made of the same material as the gate insulating film 25 (see FIG. 2) of the selection transistor 204 or the like that constitutes the pixel circuit 200. The metal body 26A is made of the same material as the gate electrode 26 of the selection transistor 204 or the like. When the dielectric 25A is made of silicon oxide, the capacitor 206 is configured as a MOS (Metal Oxide Semiconductor) type capacitor. When the dielectric 25A is made of an insulator other than silicon oxide, such as silicon nitride, the capacitor 206 is configured as a MIS (Metal Insulator Semiconductor) type capacitor.

[0077] The capacitor 206 is disposed in the second semiconductor layer 21 with the center line Lc along the surface direction of the metal body 26A being parallel to the gate length direction of the select transistor 204, for example.

[0078] [Action and effect] The solid-state imaging device 7 according to the seventh embodiment can provide the same effects as those provided by the solid-state imaging device according to the first embodiment.

[0079] 10, the solid-state imaging device 7 includes a capacitor 206 in the second semiconductor layer 21 of the second base 20. This allows for effective use of the second semiconductor layer 21. For example, a circuit including the capacitor 206 can be mounted on the second semiconductor layer 21.

[0080] Furthermore, in the solid-state imaging device 7, the center line Lc of the metal body 26A serving as the first electrode is parallel to the gate length direction of the select transistor 204, etc., and the capacitor 206 is disposed in the second semiconductor layer 21. Therefore, the dimensions of the capacitor 206 can be lengthened along the center line Lc and in the direction orthogonal to the center line Lc, and the capacitance area can be increased, so that the capacitance value of the capacitor 206 can be increased.

[0081] 8. Eighth Embodiment A solid-state imaging device 8 according to an eighth embodiment of the present disclosure will be described with reference to FIG.

[0082] [Configuration of solid-state imaging device 8] FIG. 11 shows an example of a vertical cross-sectional configuration of a resistor 207 mounted on the second substrate 20 of the solid-state imaging device 8. In FIG. The solid-state imaging device 8 includes a resistor (resistance element) 207 in a region inside the pixel circuit 200 or outside the pixel circuit 200 in the second semiconductor layer 21 of the second base 20. The resistor 207 is formed by a semiconductor region (diffusion layer) 23A disposed on the main surface portion of the second semiconductor layer 21. In other words, the resistor 207 is a diffusion layer resistor.

[0083] The semiconductor region 23A is formed with the same structure as the main electrode 23 of, for example, the selection transistor 204 that constitutes the pixel circuit 200. Here, the semiconductor region 23A is an n-type semiconductor region. The semiconductor region 23A may be formed of a p-type semiconductor region, or a p-type well region or an n-type well region (not shown). Furthermore, the resistor 207 may be formed of the same material as the gate electrode 26 of the select transistor 204. If the gate electrode 26 is formed of polycrystalline silicon, for example, the resistor 207 becomes a polysilicon resistor.

[0084] The resistor 207 is disposed in the second semiconductor layer 21 with the resistor length direction Lr parallel to the gate length direction of the select transistor 204 or the like, for example.

[0085] [Action and effect] The solid-state imaging device 8 according to the eighth embodiment can achieve the same effects as those achieved by the solid-state imaging device according to the first embodiment.

[0086] 11, the solid-state imaging device 8 includes a resistor 207 in the second semiconductor layer 21 of the second base 20. This allows for effective use of the second semiconductor layer 21. For example, a circuit including the resistor 207 can be mounted on the second semiconductor layer 21.

[0087] Furthermore, in the solid-state imaging device 8, the resistor 207 is disposed in the second semiconductor layer 21 with its resistor length direction Lr parallel to the gate length direction of the select transistor 204, etc. Therefore, the resistor length dimension of the resistor 207 can be increased, and the resistance value of the resistor 207 can be increased.

[0088] The solid-state imaging device 8 according to the eighth embodiment may be combined with the solid-state imaging device 7 according to the seventh embodiment and may include a resistor 207 and a capacitor 206 in the second semiconductor layer 21.

[0089] 9. Ninth Embodiment A solid-state imaging device 9 according to a ninth embodiment of the present disclosure will be described with reference to FIG.

[0090] [Configuration of solid-state imaging device 9] FIG. 12 shows an example of a vertical cross-sectional configuration of a memory element 208 mounted on the second substrate 20 of the solid-state imaging device 9. In FIG. The solid-state imaging device 9 includes a memory element 208 in a region inside the pixel circuit 200 or outside the pixel circuit 200 in the second semiconductor layer 21 of the second substrate 20. In the ninth embodiment, the memory element 208 is a memory cell that employs a one-transistor structure of a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory). Although only one memory element 208 is shown in the figure, in reality, a plurality of memory elements 208 are arranged in a matrix.

[0091] The memory element 208 includes a pair of main electrodes 23B, which are a source region and a drain region, a channel forming region, a ferroelectric substance 25B, and a gate electrode 26B. The main electrode 23B has the same structure as the main electrodes 23 of, for example, the selection transistor 204 that constitutes the pixel circuit 200. That is, the main electrode 23B is an n-type semiconductor region. Although not shown, sidewall spacers are formed on the sidewalls of the gate electrode 26B. Using the sidewall spacers, the main electrode 23B is formed in an LDD (Lightly Doped Drain) structure. The channel formation region is formed by the second semiconductor layer 21 between the pair of main electrodes 23B. The ferroelectric 25B is formed on the channel formation region. For example, a high-k insulator having a higher dielectric constant than silicon dioxide is used for the ferroelectric 25B. As a specific example, the ferroelectric 25B is formed of hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), hafnium oxide (HfO), or the like. The gate electrode 26B is formed on the ferroelectric layer 25B. The gate electrode 26B is formed of the same material as the gate electrode 26 of the select transistor 204, for example.

[0092] The memory element 208 is disposed on the second semiconductor layer 21 with the gate length direction of the memory element 208 parallel to the gate length direction of the select transistor 204 and the like.

[0093] [Action and effect] The solid-state imaging device 9 according to the ninth embodiment can provide the same effects as those provided by the solid-state imaging device according to the first embodiment.

[0094] 12, the solid-state imaging device 9 includes a memory element 208 in the second semiconductor layer 21 of the second base 20. This allows for effective use of the second semiconductor layer 21. For example, the second semiconductor layer 21 can be equipped with a circuit including a ferroelectric memory.

[0095] Furthermore, in the solid-state imaging device 9, the gate length direction of the memory element 208 is parallel to the gate length direction (see FIG. 1) of the selection transistor 204 and the like that constitute the pixel circuit 200, and the memory element 208 is disposed in the second semiconductor layer 21. Therefore, it is possible to effectively suppress or prevent the occurrence of short channel effects and noise in the memory element 208, thereby improving electrical reliability. In addition, since the dimension in the gate width direction of the memory element 208 can be expanded, the transconductance can be improved.

[0096] In addition, the solid-state imaging device 9 of the ninth embodiment may be combined with the solid-state imaging device 7 of the seventh embodiment or the solid-state imaging device 8 of the eighth embodiment, and may include a memory element 208 and a capacitor 206 or a resistor 207 in the second semiconductor layer 21. Furthermore, the solid-state imaging device 9 according to the ninth embodiment may be combined with the solid-state imaging device 7 according to the seventh embodiment and the solid-state imaging device 8 according to the eighth embodiment, and may include a memory element 208, a capacitor 206, and a resistor 207 in the second semiconductor layer 21.

[0097] <10. Mobile Application Examples> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0098] FIG. 13 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0099] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 13, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0100] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0101] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0102] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0103] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0104] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0105] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0106] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0107] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0108] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 13, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0109] FIG. 14 is a diagram showing an example of the installation position of the imaging unit 12031.

[0110] In FIG. 14, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0111] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0112] 14 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0113] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0114] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0115] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0116] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0117] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the components described above. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to realize an imaging unit 12031 with a simpler configuration.

[0118] <11. Application example to endoscopic surgery system> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0119] FIG. 15 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0120] 15 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0121] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0122] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0123] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0124] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0125] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0126] The light source device 11203 is configured from a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0127] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0128] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0129] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0130] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0131] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0132] FIG. 16 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0133] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0134] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0135] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0136] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0137] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0138] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0139] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0140] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0141] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0142] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0143] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0144] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0145] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0146] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0147] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0148] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0149] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the above-described configurations, the technology according to the present disclosure can be applied to, for example, the image capturing unit 11402 of the camera head 11102. By applying the technology according to the present disclosure to the image capturing unit 11402, it is possible to obtain good images of the surgical site while achieving a simplified structure.

[0150] Although an endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0151] <12. Other embodiments> The present technology is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the technology. For example, among the solid-state imaging devices according to the first to ninth embodiments, the solid-state imaging devices according to two or more of the embodiments may be combined. In addition, although this technology is applied to a solid-state imaging device having two layers, a first semiconductor layer and a second semiconductor layer, on a third substrate, it can also be applied to a device having three or more semiconductor layers on a third substrate.

[0152] In the present disclosure, a solid-state imaging device includes a first semiconductor layer and a second semiconductor layer. In the first semiconductor layer, a plurality of pixels each having a photoelectric conversion element are arranged in a matrix along a surface direction. The second semiconductor layer is stacked on the first semiconductor layer on the side opposite to the light incident side of the pixels. The second semiconductor layer includes first transistors electrically connected to the pixels and having a gate length direction tilted with respect to the pixel arrangement direction. This allows the first transistor to be disposed in the second semiconductor layer independently of the pixel arrangement, thereby enabling pixel miniaturization in the first semiconductor layer. In addition, the gate length direction of the first transistor can be tilted relative to the pixel arrangement direction, thereby increasing the gate length of the first transistor, thereby improving the electrical characteristics of the first transistor.

[0153] <Configuration of this technology> This technology has the following configuration. (1) a first semiconductor layer in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix along a surface direction; a second semiconductor layer that is electrically connected to the pixel and has a first transistor whose gate length direction is inclined with respect to the arrangement direction of the pixels, and is stacked on the first semiconductor layer on the side opposite to the light incident side of the pixel; A solid-state imaging device comprising: (2) The pixel is formed in a rectangular shape in a plan view, A gate length direction of the first transistor is parallel to a diagonal direction of the pixel in a plan view. The solid-state imaging device according to (1) above. (3) The first transistor constitutes a pixel circuit connected to the pixel. The solid-state imaging device according to (1) or (2). (4) The first transistor is an amplification transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor that constitutes the pixel circuit. The solid-state imaging device according to (3) above. (5) The gate length of the amplification transistor is longer than the gate length of the selection transistor or the reset transistor. The solid-state imaging device according to (4) above. (6) A plurality of the amplifying transistors are electrically connected in parallel to one of the pixel circuits. The solid-state imaging device according to (4) or (5) above. (7) a first terminal disposed on the second semiconductor layer side of the first semiconductor layer and electrically connected to the pixel via a first wiring layer; a second terminal disposed on the second semiconductor layer side of the first semiconductor layer, electrically connected to the first transistor via a second wiring layer, and joined to the first terminal. The solid-state imaging device according to any one of (1) to (6). (8) The semiconductor device further includes a through-wiring that penetrates from the first semiconductor layer to the second semiconductor layer and electrically connects the pixel and the first transistor. The solid-state imaging device according to any one of (1) to (6). (9) The pixel circuit further includes a third semiconductor layer stacked on the opposite side of the second semiconductor layer from the first semiconductor layer, the third semiconductor layer having a second transistor and a peripheral circuit for controlling the pixel circuit. The solid-state imaging device according to any one of (3) to (8). (10) The gate length direction of the second transistor is parallel to the arrangement direction of the pixels. The solid-state imaging device according to (9) above. (11) The second semiconductor layer further includes one or more elements selected from a metal / dielectric / semiconductor type capacitor, resistor, and memory element. The solid-state imaging device according to any one of (1) to (10) above. (12) The metal body / dielectric / semiconductor type capacitor is configured with a metal body formed in a rectangular shape in a plan view as a first electrode and a semiconductor as a second electrode, The center line of the first electrode is parallel to the gate length direction of the first transistor. The solid-state imaging device according to (11) above. (13) The resistor length direction of the resistor is parallel to the gate length direction of the first transistor. The solid-state imaging device according to (11) or (12). (14) The memory element has a pair of main electrodes, a channel formation region disposed between the main electrodes, a ferroelectric disposed on the channel formation region, and a gate electrode disposed on the ferroelectric, The gate length direction of the memory element is parallel to the gate length direction of the first transistor. The solid-state imaging device according to any one of (11) to (13) above.

[0154] This application claims priority based on Japanese Patent Application No. 2021-041892, filed on March 15, 2021, with the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0155] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a first semiconductor layer in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix along a surface direction; a plurality of pixel circuits, each of which is provided for one or more of the pixels and electrically connected to the corresponding one or more of the pixels; a second semiconductor layer stacked on the first semiconductor layer on the side opposite to the light incident side of the pixel; Equipped with each of the pixel circuits includes a plurality of first transistors whose gate length directions are inclined with respect to an arrangement direction of the plurality of pixels; the first transistors included in the pixel circuits have gate length directions that are aligned with each other; a plurality of third transistors that are part of the plurality of first transistors are arranged in a line along a gate length direction, each said third transistor includes a source region and a drain region; In two adjacent third transistors, either the source region or the drain region of one of the third transistors and either the source region or the drain region of the other third transistor are formed integrally with each other. Solid-state imaging device.

2. The pixel is formed in a rectangular shape in a plan view, A gate length direction of the first transistor is parallel to a diagonal direction of the pixel in a plan view. The solid-state imaging device according to claim 1 .

3. The first transistor is an amplification transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor. The solid-state imaging device according to claim 1 .

4. The gate length of the amplification transistor is longer than the gate length of the selection transistor or the reset transistor. The solid-state imaging device according to claim 3 .

5. A plurality of the amplification transistors are electrically connected in parallel to one of the pixel circuits. The solid-state imaging device according to claim 3 .

6. a first terminal disposed on the second semiconductor layer side of the first semiconductor layer and electrically connected to the pixel via a first wiring layer; a second terminal disposed on the second semiconductor layer side of the first semiconductor layer, electrically connected to the first transistor via a second wiring layer, and joined to the first terminal. The solid-state imaging device according to claim 1 .

7. The pixel and the first transistor are electrically connected to each other by a through-wiring that penetrates from the first semiconductor layer to the second semiconductor layer. The solid-state imaging device according to claim 1 .

8. a third semiconductor layer stacked on the second semiconductor layer opposite to the first semiconductor layer, having a second transistor and on which a peripheral circuit for controlling the pixel circuit is mounted; The solid-state imaging device according to claim 1 .

9. The gate length direction of the second transistor is parallel to the arrangement direction of the pixels. The solid-state imaging device according to claim 8 .

10. The second semiconductor layer further includes one or more elements selected from a metal / dielectric / semiconductor type capacitor, a resistor, and a memory element. The solid-state imaging device according to claim 1 .

11. The metal body / dielectric / semiconductor type capacitor is configured with a metal body formed in a rectangular shape in a plan view as a first electrode and a semiconductor as a second electrode, The center line of the first electrode is parallel to the gate length direction of the first transistor. The solid-state imaging device according to claim 10.

12. The resistor length direction of the resistor is parallel to the gate length direction of the first transistor. The solid-state imaging device according to claim 10.

13. the memory element has a pair of main electrodes, a channel formation region disposed between the main electrodes, a ferroelectric substance disposed on the channel formation region, and a gate electrode disposed on the ferroelectric substance; The gate length direction of the memory element is parallel to the gate length direction of the first transistor. The solid-state imaging device according to claim 10.

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