More than two states to achieve high aspect ratio dielectric etching

Abstract

To provide several systems and methods for applying three or more states for achieving a high aspect ratio dielectric etch operation.SOLUTION: A system has a source radio frequency (RF) generator and a bias radio frequency (RF) generator, supplies an RF signal to a capacitively coupled plasma chamber, and processes a dielectric etch operation. In the system, a processing method comprises introducing a middle state S2 to between a high state S1 and a low state S3 of radio frequency (RF) power applied to a substrate, where the middle state is applied to both the source radio frequency (RF) generator and the bias radio frequency (RF) generator. The RF power in the middle state is maintained to be between a high amount of RF power associated with the high state and a low amount of RF power associated with the low state in order to achieve high aspect ratio dielectric etch.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present embodiments relate to systems and methods for generating three or more states to achieve high aspect ratio dielectric etching. [Background technology]

[0002] The background description provided herein is intended to present the contents of the present disclosure generally. Work by the presently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] The plasma tool includes a radio frequency (RF) generator, an impedance matcher, and a plasma chamber. The RF generator is coupled to the impedance matcher, which is further coupled to the plasma chamber. A wafer is placed in the plasma chamber.

[0004] The RF generator generates an RF signal, which is fed to an impedance matcher. The impedance matcher includes components that reduce the power reflected from the plasma chamber back to the RF generator. The RF signal passes through these components to modify the RF signal. The modified RF signal is then provided from the impedance matcher to the plasma chamber for processing wafers.

[0005] It is in this context that the embodiments described in this disclosure arise. Summary of the Invention

[0006]

[0006] Embodiments of the present disclosure provide systems, apparatuses, methods, and computer programs for generating three or more states to achieve high aspect ratio dielectric etching. It should be appreciated that the present embodiments can be embodied in numerous forms (e.g., a process, an apparatus, a system, a device, or a method on a computer-readable medium). Several embodiments are described below.

[0007] In some embodiments, a method is described for applying an intermediate state between a high state and a low state. During the intermediate state, a lower level of radio frequency (RF) power is applied to the substrate than during the high state. Applying such a level of RF power during the intermediate state increases the critical dimension of the neck of a mask layer of the substrate. Additionally, mask material deposited on the mask layer during the high state is sputtered toward the substrate layer of the substrate, reducing the likelihood of bowing of the substrate layer.

[0008] In various embodiments, a method for reducing bowing without affecting capping margins and mask selectivity in high aspect ratio (HAR) etching is described. An example of bowing reduction is a reduction in the bow growth rate relative to etch depth, and an example of capping margin is a reduction in the neck critical dimension (CD). The method includes implementing a multi-state pulse with a medium-power RF pulse during a dielectric etch operation. The method helps minimize lateral etching while maintaining a vertical etch rate without damaging the capping or causing neck clogging under mask facet regions of a mask layer of a substrate. Lateral etching causes bowing in a substrate layer of a substrate that resides below the mask layer. The clogging is caused by excessive mask layer deposition due to a passivation process under the mask facet regions.

[0009] In various embodiments, the method includes applying State S2 between States S1 and S3 to balance mask redeposition and neck removal to widen the critical dimension of the neck. State S2 is introduced between States S1 and S3 to perform a sputter passivation process (e.g., deposition of a mask material) from the neck to the substrate layer to promote neutral passivation at the bend location. By way of example, the RF power in State S2 is between the RF power in State S1 and the RF power in State S3. By way of example, the target ion energy in State S2 is in the range of 1.0 kiloelectronvolt (keV) to 5 keV.

[0010] In some embodiments, a method for processing a dielectric etch operation in a capacitively coupled plasma (CCP) chamber is described. The CCP chamber has a substrate support electrode and an upper electrode defining a process volume. The method includes providing a bias RF signal applied to the substrate support electrode. The bias RF signal is controlled to include a first plurality of parameter levels during a repeating period. The first plurality of parameter levels includes a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state. The method further includes providing a source RF signal applied to the upper electrode and transmitting a second plurality of parameter levels to the upper electrode during a repeating period. The second plurality of parameter levels includes a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state. The second parameter level of the bias RF signal during the second state is set to be different from the first parameter level of the bias RF signal during the first state, and the third parameter level of the bias RF signal during the third state is set to be different from the first and second parameter levels of the bias RF signal. A second parameter level of the source RF signal during the second state is set to be different from the first parameter level of the source RF signal during the first state, and a third parameter level of the source RF signal during the third state is set to be different from the first and second parameter levels of the source RF signal.

[0011] In various embodiments, the above-described method of processing a dielectric etch operation in a CCP chamber is performed except for applying a source RF signal and a bias RF signal to a substrate support electrode.

[0012] In some embodiments, a method for processing a dielectric etch operation in a CCP chamber is described. The CCP chamber includes a first electrode and a second electrode With do The CCP chamber is coupled to an impedance matching circuit. The method includes providing a bias RF signal to the impedance matching circuit. The bias RF signal includes a first plurality of parameter levels during a repeating period. The first plurality of parameter levels includes a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state. The method further includes providing a source RF signal to the impedance matching circuit to communicate a second plurality of parameter levels during a repeating period. The second plurality of parameter levels includes a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state. The bias RF signal and the source RF signal are used to control a dielectric etching operation in the CCP chamber. The first, second, and third parameter levels of the bias RF signal are different from one another. The first, second, and third parameter levels of the source RF signal are different from one another.

[0013] In some embodiments, a system is described. The system includes a plasma chamber having a first electrode and a second electrode. The system further includes an impedance matching circuit coupled to the plasma chamber and a bias RF generator coupled to the impedance matching circuit. The bias RF generator is configured to supply a bias RF signal to the impedance matching circuit. The bias RF signal includes a first plurality of parameter levels during a repeating period. The first plurality of parameter levels includes a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state. The system further includes a source RF generator coupled to the impedance matching circuit. The source RF generator supplies the source RF signal to the impedance matching circuit. The source RF signal includes a second plurality of parameter levels during a repeating period. The second plurality of parameter levels includes a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state. The first, second, and third parameter levels of the bias RF signal are different from one another. The first, second, and third parameter levels of the source RF signal are different from one another.

[0014] Some advantages of the systems and methods described herein include applying a medium power level to the substrate in state S2. In one embodiment, the medium power level is between the high power level of state S1 and the low power level of state S3. The medium power level generates plasma ions that sputter mask material downward to protect the substrate layer. The mask material can be deposited on the mask layer during state S1. The sputtered mask material protects the substrate layer during state S1, where the etching operation is performed. Sputtering the mask material downward also increases the critical dimension at the neck. The increased critical dimension at the neck reduces the likelihood of lateral etching of the substrate layer and increases the likelihood of vertical etching of the substrate layer, increasing the selectivity and etch rate when etching the substrate. During state S3, material is deposited on the mask layer.

[0015] Some additional advantages of the systems and methods described herein include improved trade-off between bowed CD and unopened defects with post-etch inspection, improved trade-off between bowed CD and unopened defects with post-develop inspection, improved trade-off between etch selectivity and unopened defects, and improved aspect ratio dependent etching (ARDE).

[0016] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0017] The embodiments may be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0018] [Figure 1A] FIG. 1A is a diagram of one embodiment of a system illustrating the generation of three states to achieve high aspect ratio dielectric etching.

[0019] [Figure 1B] FIG. 1B is a diagram of another system embodiment illustrating the generation of more than two states to achieve high aspect ratio dielectric etching.

[0020] [Figure 2A] FIG. 2A shows an embodiment of a plurality of graphs illustrating parameters of a radio frequency (RF) signal generated by the bias generator of FIGS. 1A and 1B and parameters of another RF signal generated by the source generator of FIGS. 1A and 1B.

[0021] [Figure 2B] FIG. 2B is a diagram illustrating an embodiment of a plurality of graphs illustrating parameters of an RF signal generated by the bias generator of FIGS. 1A and 1B and another parameter of an RF signal generated by the source generator of FIGS. 1A and 1B.

[0022] [Figure 3A] FIG. 3A is a diagram of one embodiment of a system illustrating the generation of four states to achieve high aspect ratio dielectric etching.

[0023] [Figure 3B] FIG. 3B is a diagram of another system embodiment illustrating the generation of four states to achieve high aspect ratio dielectric etching.

[0024] [Figure 4A] FIG. 4A shows an embodiment of a plurality of graphs illustrating parameters of an RF signal generated by the bias generator of FIGS. 3A and 3B and parameters of another RF signal generated by the source generator of FIGS. 3A and 3B.

[0025] [Figure 4B] FIG. 4B shows an embodiment of a plurality of graphs illustrating parameters of an RF signal generated by the bias generator of FIGS. 3A and 3B and another parameter of an RF signal generated by the source generator of FIGS. 3A and 3B.

[0026] [Figure 4C] FIG. 4C is an embodiment of a plurality of graphs illustrating parameters of an RF signal generated by the bias generator of FIGS. 3A and 3B and another parameter of an RF signal generated by the source generator of FIGS. 3A and 3B.

[0027] [Figure 5A] FIG. 5A is one embodiment of a substrate being processed by applying a two-state pulse.

[0028] [Figure 5B] FIG. 5B is an embodiment of a substrate being processed by applying a two-state pulse.

[0029] [Figure 5C]FIG. 5C is an embodiment of a substrate illustrating the effect of state S1 of a three-state pulse on a substrate.

[0030] [Figure 5D] FIG. 5D is an embodiment of a substrate illustrating the effect of state S2 of a three-state pulse on a substrate.

[0031] [Figure 5E] FIG. 5E is an embodiment of a substrate illustrating the effect of state S3 of a three-state pulse on a substrate.

[0032] [Figure 6] FIG. 6 is one embodiment of a graph illustrating a plot of maximum critical dimension (CD) versus minimum critical dimension.

[0033] [Figure 7A] FIG. 7A is one embodiment of a graph illustrating a plot showing the relationship between post-etch inspection (AEI) curvature CD plotted on the x-axis and unopened defects plotted on the y-axis.

[0034] [Figure 7B] FIG. 7B is one embodiment of a graph illustrating a plot showing the relationship between curved CD by after develop inspection (ADI) plotted on the x-axis and unopened defects plotted on the y-axis.

[0035] [Figure 7C] FIG. 7C is one embodiment of a graph illustrating a plot showing the relationship between etch selectivity (sel) plotted on the x-axis and unopened defects plotted on the y-axis.

[0036] [Figure 7D] FIG. 7D is one embodiment of a graph illustrating a plot showing the relationship between aspect ratio and differential etch rate plotted on the y-axis. DETAILED DESCRIPTION OF THE INVENTION

[0037] The following embodiments describe systems and methods for generating three or more states to achieve high aspect ratio dielectric etching. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments.

[0038] FIG. 1A is a diagram of an embodiment of a system 100 illustrating the generation of three states to achieve high-aspect-ratio dielectric etching. The system 100 includes a source generator 102 and a bias generator 104. The source generator 102 is an example of a source RF generator, and the bias generator 104 is an example of a bias RF generator. The system 100 further includes an impedance matching circuit (IMCS) 106 for the source generator 102 and another impedance matching circuit (IMCB) 108 for the bias generator 104. The impedance matching circuit IMCS 106 is an example of a source impedance matching circuit, and the impedance matching circuit IMCB 108 is an example of a bias impedance matching circuit. The impedance matching circuit IMCS 106 is coupled to the source generator 102 via a radio frequency (RF) cable 120A, and the impedance matching circuit IMCB 108 is coupled to the bias generator 104 via another RF cable 120B. Additionally, the system 100 includes a plasma chamber 110 that is a capacitively coupled plasma (CCP) chamber. An impedance matching circuit IMCS 106 is coupled to the plasma chamber 110 via an RF transmission line 122A, and an impedance matching circuit IMCB 108 is coupled to the plasma chamber 110 via another RF transmission line 122B.

[0039] The source generator 102 includes a digital signal processor (DSPS), multiple parameter controllers PRS1S, PRS2S, and PRS3S, a driver system 124A, and multiple frequency controllers FCS1S, FCS2S, and FCS3S. A parameter, as used herein, refers to voltage or power. The source generator 102 also includes a source RF power supply. The digital signal processor of the source generator 102 is coupled to a host computer processor (P) via a transfer cable TCS. The digital signal processor of the source generator 102 is further coupled to the parameter controllers PRS1S, PRS2S, and PRS3S, as well as the frequency controllers FCS1S, FCS2S, and FCS3S. The parameter controllers PRS1S, PRS2S, and PRS3S, as well as the frequency controllers FCS1S, FCS2S, and FCS3S, are coupled to the driver system 124A, which is coupled to the source RF power supply. The host computer further includes a memory device (M) coupled to the processor of the host computer.

[0040] Similarly, the bias generator 104 includes a digital signal processor (DSPB), multiple parameter controllers PRS1B, PRS2B, and PRS3B, a driver system 124B, and multiple frequency controllers FCS1B, FCS2B, and FCS3B. The bias generator 104 also includes a bias RF power supply. The digital signal processor of the bias generator 104 is coupled to a processor of a host computer via a transfer cable TCB. The digital signal processor of the bias generator 104 is further coupled to the parameter controllers PRS1B, PRS2B, and PRS3B and the frequency controllers FCS1B, FCS2B, and FCS3B. The parameter controllers PRS1B, PRS2B, and PRS3B and the frequency controllers FCS1B, FCS2B, and FCS3B are coupled to the driver system 124B, which is coupled to the bias RF power supply.

[0041] The plasma chamber 110 includes a substrate support 112 (e.g., a chuck) with an embedded lower electrode 114. The lower electrode 114 is an example of a substrate support electrode. Examples of chucks include electrostatic chucks (ESCs) and magnetic chucks. A substrate S is placed on the substrate support 112. The substrates described herein are used to fabricate one or more semiconductor chips, which are used in one or more electronic devices, such as mobile phones, tablets, processors, memory devices, televisions, devices that apply artificial intelligence, or devices that are part of the Internet of Things (IoT). Furthermore, an upper electrode 116 of the plasma chamber 110 faces the substrate support 112. A gap 118, such as a processing volume, is formed between the upper electrode 116 and the substrate support 112. Each of the lower electrode 114 and the upper electrode 116 is made of a metal, such as aluminum or an aluminum alloy.

[0042] Examples of host computers include desktop computers, controllers, tablets, servers, laptop computers, and smartphones. A processor, as used herein, is an application-specific integrated circuit (ASIC), digital signal processor, programmable logic device (PLD), central processing unit (CPU), microprocessor, or microcontroller. A controller, as used herein, includes an ASIC, PLD, CPU, microprocessor, microcontroller, processor, or digital signal processor, and further includes a memory device. Examples of memory devices, as used herein, include random access memory (RAM) and read-only memory (ROM). Illustratively, memory devices include flash memory, hard disks, and storage devices. A memory device is an example of a computer-readable medium. An example of a driver system, as used herein, includes one or more transistors. Another example of a driver system, as used herein, includes one or more transistors coupled to an amplifier. An example of an RF power source, as used herein, includes an RF oscillator that generates a sine wave signal at a radio frequency (e.g., in the range of 100 kHz to 100 MHz).

[0043] An example of the bias generator 104 is an X RF generator, where X is in the range of 100 kilohertz (kHz) to 13 megahertz (MHz). For example, the bias generator 104 is a 400 kHz generator. For another example, the bias generator 104 is a 2 MHz RF generator. For yet another example, the bias generator 104 has a frequency in the range of 100 kHz to 3 MHz. For example, the source generator 102 is a Y RF generator, where Y is in the range of 13 MHz to 170 MHz. For example, the source generator 102 has a frequency in the range of 40 MHz to 70 MHz. For another example, the source generator 102 is a 70 MHz RF generator, or a 60 MHz RF generator, or a 50 MHz RF generator, or a 27 MHz RF generator, or a 13.56 MHz RF generator. For a further example, the Y RF generator has an operating range of 57 MHz to 63 MHz.

[0044] The impedance matching circuit described herein is a network of one or more components (such as one or more resistors, one or more capacitors, one or more inductors, or a combination thereof) that matches the impedance of a load coupled to the output of the impedance matching circuit to the impedance of a source coupled to the input of the impedance matching circuit. Two or more of these components are coupled to each other in a parallel or series configuration. The impedance matching circuit matches the impedance of a load coupled to the output of the impedance matching circuit to the impedance of a source coupled to one or more inputs of the impedance matching circuit. For example, the impedance matching circuit IMCS 106 matches the impedance of the RF transmission line 122A and the plasma chamber 110 to the impedance of the source generator 102 and the RF cable 120A. As another example, the impedance matching circuit IMCB 108 matches the impedance of the RF transmission line 122B and the plasma chamber 110 to the impedance of the bias generator 104 and the RF cable 120B. The impedance matching circuits described herein may be referred to herein as a matching box, an RF matching section, an impedance matching network, or a matching section.

[0045] The processor of the host computer generates a digital pulse signal DPS1 and transmits the digital pulse signal DPS1 to the digital signal processor of the source generator 102 via a transfer cable TCS, and also transmits the digital pulse signal DPS1 to the digital signal processor of the bias generator 104 via a transfer cable TCB. The digital pulse signal DPS1 has a plurality of states S1, S2, and S3, and periodically transitions between the states S1, S2, and S3.

[0046] Additionally, the processor of the host computer transmits the parameter level of the RF signal 116A in state S1, the parameter level of the RF signal 116A in state S2, and the parameter level of the RF signal 116A in state S3 to the digital signal processor of the source generator 102 via the transfer cable TCS. The RF signal 116A is generated by the source generator 102 and is an example of a source RF signal. Furthermore, the processor of the host computer transmits the frequency level of the RF signal 116A in state S1, the frequency level of the RF signal 116A in state S2, and the frequency level of the RF signal 116A in state S3 to the digital signal processor of the source generator 102 via the transfer cable TCS. The parameter levels and frequency levels of states S1 to S3 transmitted to the digital signal processor of the source generator 102 are identified by the processor of the host computer from the memory device of the host computer. Upon receiving the parameter levels and frequency levels for states S1-S3, the digital signal processor of the source generator 102 sends the parameter level for state S1 to parameter controller PRS1S to store it in a memory device of the parameter controller PRS1S, sends the parameter level for state S2 to parameter controller PRS2S to store it in a memory device of the parameter controller PRS2S, sends the parameter level for state S3 to parameter controller PRS3S to store it in a memory device of the parameter controller PRS3S, sends the frequency level for state S1 to frequency controller FCS1S to store it in a memory device of the frequency controller FCS1S, sends the frequency level for state S2 to frequency controller FCS2S to store it in a memory device of the frequency controller FCS2S, and sends the frequency level for state S3 to frequency controller FCS3S to store it in a memory device of the frequency controller FCS3S.

[0047] Similarly, the processor of the host computer transmits the parameter level of the RF signal 116B in state S1, the parameter level of the RF signal 116B in state S2, and the parameter level of the RF signal 116B in state S3 to the digital signal processor of the bias generator 104 via the transfer cable TCB. The RF signal 116B is generated by the bias generator 104 and is an example of a bias RF signal. Furthermore, the processor of the host computer transmits the frequency level of the RF signal 116B in state S1, the frequency level of the RF signal 116B in state S2, and the frequency level of the RF signal 116B in state S3 to the digital signal processor of the bias generator 104 via the transfer cable TCB. The parameter levels and frequency levels of states S1 to S3 transmitted to the digital signal processor of the bias generator 104 are identified by the processor of the host computer from a memory device of the host computer. Upon receiving the parameter levels and frequency levels for states S1-S3, the digital signal processor of bias generator 104 sends the parameter level for state S1 to parameter controller PRS1B to store it in a memory device of parameter controller PRS1B, sends the parameter level for state S2 to parameter controller PRS2B to store it in a memory device of parameter controller PRS2B, sends the parameter level for state S3 to parameter controller PRS3B to store it in a memory device of parameter controller PRS3B, sends the frequency level for state S1 to frequency controller FCS1B to store it in a memory device of frequency controller FCS1B, sends the frequency level for state S2 to frequency controller FCS2B to store it in a memory device of frequency controller FCS2B, and sends the frequency level for state S3 to frequency controller FCS3B to store it in a memory device of frequency controller FCS3B.

[0048] Each of the digital signal processors of the source generator 102 and the bias generator 104 determines whether the digital pulse signal DPS1 has a state S1, S2, or S3. For example, each of the digital signal processors of the source generator 102 and the bias generator 104 determines whether the logic level of the digital pulse signal DPS1 is greater than, equal to, or less than a predetermined threshold. If the digital signal processors of the source generator 102 and the bias generator 104 determine that the logic level of the digital pulse signal DPS1 is greater than the predetermined threshold, they identify the occurrence of the state of the digital pulse signal DPS1 as S1. On the other hand, if the digital signal processors of the source generator 102 and the bias generator 104 determine that the logic level of the digital pulse signal DPS1 is less than the predetermined threshold, they identify the occurrence of the state of the digital pulse signal DPS1 as S3. Also, upon determining that the logic level of digital pulse signal DPS1 is equal to the predetermined threshold, each of the digital signal processors of source generator 102 and bias generator 104 identifies the occurrence of the state of digital pulse signal DPS1 as S2. As another example, each of the digital signal processors of source generator 102 and bias generator 104 determines whether the logic level of digital pulse signal DPS1 is zero, one, or two. Upon determining that the logic level of digital pulse signal DPS1 is two, each of the digital signal processors of source generator 102 and bias generator 104 identifies the occurrence of the state of digital pulse signal DPS1 as S1. Similarly, upon determining that the logic level of digital pulse signal DPS1 is one, each of the digital signal processors of source generator 102 and bias generator 104 identifies the occurrence of the state of digital pulse signal DPS1 as S2. DPS1 Upon determining that the logic level of digital pulse signal DPS1 is zero, each of the digital signal processors of source generator 102 and bias generator 104 identifies the occurrence of the state of digital pulse signal DPS1 as S3.

[0049] During the period when digital pulse signal DPS1 is generating state S1, the digital signal processor of source generator 102 sends a signal indicative of state S1 to each of parameter controller PRS1S and frequency controller FCS1S. Furthermore, during the period when digital pulse signal DPS1 is generating state S2, the digital signal processor of source generator 102 sends a signal indicative of state S2 to each of parameter controller PRS2S and frequency controller FCS2S. Furthermore, during the period when digital pulse signal DPS1 is generating state S3, the digital signal processor of source generator 102 sends a signal indicative of state S3 to each of parameter controller PRS3S and frequency controller FCS3S.

[0050] Furthermore, during a period in which the digital pulse signal DPS1 is generating state S1, upon receiving a signal indicative of state S1, the parameter controller PRS1S accesses the parameter level for state S1 from the memory device of the parameter controller PRS1S and transmits the parameter level for state S1 to the driver system 124A of the source generator 102. Similarly, during a period in which the digital pulse signal DPS1 is generating state S1, upon receiving a signal indicative of state S1, the frequency controller FCS1S accesses the frequency level for state S1 from the memory device of the frequency controller FCS1S and transmits the frequency level for state S1 to the driver system 124A of the source generator 102.

[0051] Furthermore, during the period when the digital pulse signal DPS1 is generating the state S2, upon receiving a signal indicative of the state S2, the parameter controller PRS2S accesses the parameter level for the state S2 from the memory device of the parameter controller PRS2S and transmits the parameter level for the state S2 to the driver system 124A of the source generator 102. Similarly, during the period when the digital pulse signal DPS1 is generating the state S2, upon receiving a signal indicative of the state S2, the frequency controller FCS2S accesses the frequency level for the state S2 from the memory device of the frequency controller FCS2S and transmits the frequency level for the state S2 to the driver system 124A of the source generator 102.

[0052] Furthermore, during the period when the digital pulse signal DPS1 is generating state S3, upon receiving a signal indicating state S3, the parameter controller PRS3S accesses the parameter level for state S3 from the memory device of the parameter controller PRS3S and transmits the parameter level for state S3 to the driver system 124A of the source generator 102. Similarly, during the period when the digital pulse signal DPS1 is generating state S3, upon receiving a signal indicating state S3, the frequency controller FCS3S accesses the frequency level for state S3 from the memory device of the frequency controller FCS3S and transmits the frequency level for state S3 to the driver system 124A of the source generator 102.

[0053] During the period when digital pulse signal DPS1 is generating state S1, driver system 124A of source generator 102 receives the parameter level and the frequency level of state S1, generates a current signal based on the parameter level and the frequency level of state S1, and provides the current signal to the source RF power supply. Also, during the period when digital pulse signal DPS1 is generating state S1, the source RF power supply generates a portion of state S1 RF signal 116A upon receiving the current signal from driver system 124A of source generator 102. The portion of state S1 RF signal 116A has the parameter level and frequency level of state S1 during the generation of state S1 of digital pulse signal DPS1.

[0054] Similarly, during the period when digital pulse signal DPS1 is generating state S2, driver system 124A of source generator 102 receives the parameter level and the frequency level of state S2, generates a current signal based on the parameter level and the frequency level of state S2, and provides the current signal to the source RF power supply. Also, during the period when digital pulse signal DPS1 is generating state S2, the source RF power supply generates a portion of state S2 RF signal 116A upon receiving the current signal from driver system 124A of source generator 102. The portion of state S2 RF signal 116A has the parameter level and frequency level of state S2 during the generation of state S2 of digital pulse signal DPS1.

[0055] Additionally, during the period when digital pulse signal DPS1 is generating state S3, driver system 124A of source generator 102 receives the parameter level and the frequency level of state S3, generates a current signal based on the parameter level and the frequency level of state S3, and provides the current signal to the source RF power supply. Additionally, during the period when digital pulse signal DPS1 is generating state S3, the source RF power supply generates a portion of RF signal 116A for state S3 when it receives the current signal from driver system 124A of source generator 102. The portion of RF signal 116A for state S3 has the parameter level and frequency level of state S3 during the generation of digital pulse signal DPS1 in state S3.

[0056] Impedance matching circuit IMCS 106 receives RF signal 116A via RF cable 120A and matches the impedance of a load coupled to the output of impedance matching circuit IMCS 106 to the impedance of a source coupled to the input of impedance matching circuit IMCS 106 to generate modified RF signal 126A. Modified RF signal 126A is an example of an output of impedance matching circuit IMCS 106. Modified RF signal 126A is provided from the output of impedance matching circuit IMCS 106 to upper electrode 116.

[0057] Similarly, during a period when digital pulse signal DPS1 is generating state S1, the digital signal processor of bias generator 104 sends a signal indicative of state S1 to each of parameter controller PRS1B and frequency controller FCS1B of bias generator 104. Furthermore, during a period when digital pulse signal DPS1 is generating state S2, the digital signal processor of bias generator 104 sends a signal indicative of state S2 to each of parameter controller PRS2B and frequency controller FCS2B. Furthermore, during a period when digital pulse signal DPS1 is generating state S3, the digital signal processor of bias generator 104 sends a signal indicative of state S3 to each of parameter controller PRS3B and frequency controller FCS3B.

[0058] Furthermore, during the period when the digital pulse signal DPS1 is generating the state S1, upon receiving a signal indicating the state S1, the parameter controller PRS1B accesses the parameter level for the state S1 from the memory device of the parameter controller PRS1B and transmits the parameter level for the state S1 to the driver system 124B of the bias generator 104. Similarly, during the period when the digital pulse signal DPS1 is generating the state S1, upon receiving a signal indicating the state S1, the frequency controller FCS1B accesses the frequency level for the state S1 from the memory device of the frequency controller FCS1B and transmits the frequency level for the state S1 to the driver system 124B of the bias generator 104. Bias Generator 104 The driver system 124B then transmits the received signal to the driver system 124B.

[0059] Furthermore, during the period when the digital pulse signal DPS1 is generating the state S2, upon receiving a signal indicating the state S2, the parameter controller PRS2B accesses the parameter level for the state S2 from the memory device of the parameter controller PRS2B and transmits the parameter level for the state S2 to the driver system 124B of the bias generator 104. Similarly, during the period when the digital pulse signal DPS1 is generating the state S2, upon receiving a signal indicating the state S2, the frequency controller FCS2B accesses the frequency level for the state S2 from the memory device of the frequency controller FCS2B and transmits the frequency level for the state S2 to the driver system 124B of the bias generator 104.

[0060] Furthermore, during the period when the digital pulse signal DPS1 is generating the state S3, upon receiving a signal indicating the state S3, the parameter controller PRS3B accesses the parameter level for the state S3 from the memory device of the parameter controller PRS3B and transmits the parameter level for the state S3 to the driver system 124B of the bias generator 104. Similarly, during the period when the digital pulse signal DPS1 is generating the state S3, upon receiving a signal indicating the state S3, the frequency controller FCS3B accesses the frequency level for the state S3 from the memory device of the frequency controller FCS3B and transmits the frequency level for the state S3 to the driver system 124B of the bias generator 104.

[0061] During the period when the digital pulse signal DPS1 is generating the state S1, the driver system 124B of the bias generator 104 receives the parameter level and the frequency level of the state S1, generates a current signal based on the parameter level and the frequency level of the state S1, and provides the current signal to the bias RF power supply. Also, during the period when the digital pulse signal DPS1 is generating the state S1, the bias RF power supply generates a portion of the state S1 RF signal 116B upon receiving the current signal from the driver system 124B of the bias generator 104. The portion of the state S1 RF signal 116B has the parameter level and the frequency level of the state S1 during the generation of the state S1 of the digital pulse signal DPS1.

[0062] Similarly, during the period when digital pulse signal DPS1 is generating state S2, driver system 124B of bias generator 104 receives the parameter level and the frequency level of state S2, generates a current signal based on the parameter level and the frequency level of state S2, and provides the current signal to the bias RF power supply. Also, during the period when digital pulse signal DPS1 is generating state S2, the bias RF power supply generates a portion of state S2 RF signal 116B when it receives the current signal from driver system 124B of bias generator 104. The portion of state S2 RF signal 116B has the parameter level and frequency level of state S2 during the generation of state S2 of digital pulse signal DPS1.

[0063] Additionally, during the period when digital pulse signal DPS1 is generating state S3, driver system 124B of bias generator 104 receives the parameter level and frequency level of state S3, generates a current signal based on the parameter level and frequency level of state S3, and provides the current signal to the bias RF power supply. Additionally, during the period when digital pulse signal DPS1 is generating state S3, the bias RF power supply generates a portion of RF signal 116B for state S3 when it receives the current signal from driver system 124B of bias generator 104. The portion of RF signal 116B for state S3 has the parameter level and frequency level of state S3 during the generation of digital pulse signal DPS1 in state S3.

[0064] The impedance matching circuit IMCB 108 receives the RF signal 116B via the RF cable 120B and matches the impedance of a load coupled to the output of the impedance matching circuit IMCB 108 to the impedance of a source coupled to the input of the impedance matching circuit IMCB 108 to generate a modified RF signal 126B. The modified RF signal 126B is an example of an output of the impedance matching circuit IMCB 108. The modified RF signal 126B is provided from the output of the impedance matching circuit IMCB 108 to the lower electrode 114 of the substrate support 112 to control (e.g., manage) processing of the substrate S. Examples of processing of the substrate S include performing an etching operation on the substrate S, or depositing material on the substrate S, or sputtering the substrate S, or cleaning the substrate S, or a combination of two or more thereof.

[0065] In addition to providing the modified RF signals 126A and 126B, one or more process gases are provided to the plasma chamber 110, whereby a plasma is struck or maintained in the gap 118 of the plasma chamber 110 to process the substrate S. The processing of the substrate S is controlled, for example, by including a parameter level for the RF signal 116A in State S2 and including a parameter level for the RF signal 116B in State S2. During State S2, the RF signals 116A and 116B have parameter levels to generate plasma ions that sputter mask material downward on the substrate S to protect the substrate layer of the substrate S. Sputtering the mask material downward increases the critical dimension at the neck of the substrate S. Examples of the one or more process gases include an oxygen-containing gas, such as O. Other examples of the one or more process gases include a fluorine-containing gas (e.g., tetrafluoromethane (CF), sulfur hexafluoride (SF), hexafluoroethane (CF), etc.). Examples of processing a substrate described herein include depositing a material onto a substrate, etching a substrate, cleaning a substrate, and sputtering a substrate.

[0066] In some embodiments, any number of RF generators are coupled to an impedance matching circuit described herein, such as the IMCS 106 or the IMCB 108. For example, an additional RF generator is coupled to another input of the impedance matching circuit via another RF cable to generate and transmit an RF signal to the other input of the impedance matching circuit.

[0067] In some embodiments, the parameter levels of states S1-S3 sent to the digital signal processor of the source generator 102 and the parameter levels of states S1-S3 sent to the digital signal processor of the bias generator 104 are received from a user via an input device (such as a keyboard, mouse, or stylus) connected to the processor of the host computer via an input / output interface, instead of or in addition to being identified by the processor of the host computer. Similarly, in some embodiments, the frequency levels of states S1-S3 sent to the digital signal processor of the source generator 102 and the frequency levels of states S1-S3 sent to the digital signal processor of the bias generator 104 are received from a user via an input device, instead of or in addition to being identified by the processor of the host computer.

[0068] In some embodiments, each parameter level described herein with respect to an RF signal is the envelope of the RF signal, e.g., the parameter level described herein with respect to an RF signal is the zero-to-peak magnitude of the RF signal or the peak-to-peak magnitude of the RF signal.

[0069] Also, in various embodiments, a parameter level of a parameter of the RF signal includes one or more magnitudes (e.g., amplitudes or values) of the parameter of the RF signal, which magnitudes exclude one or more magnitudes of another parameter level of the parameter of the RF signal. For example, the parameter level transmitted to the digital signal processor of the source generator 102 for state S2 has one or more values, none of which are the same as one or more values ​​of the parameter level transmitted to the digital signal processor of the source generator 102 for state S1. Further, the parameter level transmitted to the digital signal processor of the source generator 102 for state S3 has one or more values, none of which are the same as one or more values ​​of the parameter level transmitted to the digital signal processor of the source generator 102 for state S2. Further, the parameter level transmitted to the digital signal processor of the source generator 102 for state S3 has one or more values, none of which are the same as one or more values ​​of the parameter level transmitted to the digital signal processor of the source generator 102 for state S1. As another example, the parameter levels sent to the digital signal processor of the bias generator 104 for state S2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the bias generator 104 for state S1. Further, the parameter levels sent to the digital signal processor of the bias generator 104 for state S3 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the bias generator 104 for state S2. Also, the parameter levels sent to the digital signal processor of the bias generator 104 for state S3 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the bias generator 104 for state S1.

[0070] In various embodiments, a single frequency controller is used to control the source RF power supply instead of the multiple frequency controllers FCS1S, FCS2S, and FCS3S of the source generator 102 to generate a single frequency level of the RF signal instead of the multiple frequency levels of states S1-S3. The single frequency level includes one or more values ​​of the frequency of the RF signal. The single frequency level represents a continuous wave of frequencies. The processor of the host computer transmits the value of the single frequency level of the RF signal to the digital signal processor of the source generator 102. Upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS1 is S1, S2, or S3, the digital signal processor of the source generator 102 transmits the value of the single frequency level to the frequency controller for storage in the memory device of the frequency controller. Furthermore, upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS1 is S1, S2, or S3, the frequency controller transmits the value to the driver system 124A. The driver system 124A generates a current signal based on the value of the single frequency level and provides the current signal to the source RF power supply. Upon receiving the current signal, the source RF power supply generates an RF signal having a single frequency level and multiple parameter levels for states S1-S3.

[0071] Similarly, in some embodiments, a single frequency controller is used to control the bias RF power supply instead of the multiple frequency controllers FCS1B, FCS2B, and FCS3B of the bias generator 104 to generate a single frequency level of the RF signal instead of the multiple frequency levels of states S1-S3. The single frequency level includes one or more values ​​of the frequency of the RF signal and represents a continuous wave of frequencies. The processor of the host computer transmits the value of the single frequency level of the RF signal to the digital signal processor of the bias generator 104. Upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS1 is S1, S2, or S3, the digital signal processor of the bias generator 104 transmits the value to the frequency controller for storage in the memory device of the frequency controller. Furthermore, upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS1 is S1, S2, or S3, the frequency controller transmits the value of the single frequency level to the driver system 124B. The driver system 124B generates a current signal based on the value of the single frequency level and provides the current signal to the bias RF power supply. Upon receiving the current signal, the bias RF power supply generates an RF signal having a single frequency level and multiple parameter levels for states S1-S3.

[0072] In various embodiments, one or more functions described herein as being performed by a host computer processor are instead performed by a digital signal processor of source generator 102. For example, instead of the host computer processor providing the parameter levels and frequency levels for states S1-S3 to the digital signal processor of source generator 102, the parameter levels and frequency levels are stored in a memory device coupled to the digital signal processor of source generator 102, accessed from the memory device by the digital signal processor of source generator 102, and sent to parameter controllers PRS1S, PRS2S, and PRS3S and frequency controllers FCS1S, FCS2S, and FCS3S based on whether the state of digital pulse signal DPS1 received from the host computer processor is S1, S2, or S3. As another example, instead of digital pulse signal DPS1 being generated by the host computer's processor, digital pulse signal DPS1 may be generated by the digital signal processor of source generator 102 and transmitted to the digital signal processor of bias generator 104 via a transfer cable coupling the two digital signal processors of source generator 102 and bias generator 104. As a further example, instead of the host computer's processor providing the parameter levels and frequency levels for states S1-S3 to the digital signal processor of bias generator 104, the parameter levels and frequency levels may be stored in a memory device coupled to the digital signal processor of bias generator 104, accessed from the memory device by the digital signal processor of bias generator 104, and transmitted to parameter controllers PRS1B, PRS2B, and PRS3B and frequency controllers FCS1B, FCS2B, and FCS3B based on whether the state of digital pulse signal DPS1 received from the host computer's processor is S1, S2, or S3.As another example, instead of the digital pulse signal DPS1 being generated by the processor of the host computer, the digital pulse signal DPS1 is generated by the digital signal processor of the bias generator 104 and transmitted to the digital signal processor of the source generator 102 via a transfer cable connecting the two digital signal processors of the source generator 102 and the bias generator 104.

[0073] In various embodiments, one or more functions described herein as being performed by the digital signal processor of the source generator 102 and the controllers PRS1S, PRS2S, PRS3S, FCS1S, FCS2S, and FCS3S of the source generator 102 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to the driver system 124A without being coupled to the digital signal processor of the source generator 102. The functions described herein as being performed by the digital signal processor of the source generator 102 and the controllers PRS1S, PRS2S, PRS3S, FCS1S, FCS2S, and FCS3S of the source generator 102 are computer programs or computer modules executed by the processor of the host computer.

[0074] Similarly, in some embodiments, one or more of the functions described herein as being performed by the digital signal processor of bias generator 104 and controllers PRS1B, PRS2B, PRS3B, FCS1B, FCS2B, and FCS3B of bias generator 104 may instead be performed by a host computer. Ta'sFor example, the processor of the host computer is coupled to the driver system 124B without being coupled to the digital signal processor of the bias generator 104. The functions described herein as being performed by the digital signal processor of the bias generator 104 and the controllers PRS1B, PRS2B, PRS3B, FCS1B, FCS2B, and FCS3B of the bias generator 104 are computer programs or computer modules executed by the processor of the host computer.

[0075] In various embodiments, one or more functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S, FCS1S, FCS2S, and FCS3S of the source generator 102 are instead performed by a digital signal processor of the source generator 102. For example, the digital signal processor of the source generator 102 is coupled to the driver system 124A without being coupled to the controllers PRS1S, PRS2S, PRS3S, FCS1S, FCS2S, and FCS3S. The functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S, FCS1S, FCS2S, and FCS3S of the source generator 102 are computer programs or computer modules executed by the digital signal processor of the source generator 102.

[0076] Similarly, in some embodiments, one or more functions described herein as being performed by controllers PRS1B, PRS2B, PRS3B, FCS1B, FCS2B, and FCS3B of bias generator 104 are instead performed by a digital signal processor of bias generator 104. For example, the digital signal processor of bias generator 104 is coupled to driver system 124B without being coupled to controllers PRS1B, PRS2B, PRS3B, FCS1B, FCS2B, and FCS3B. The functions described herein as being performed by controllers PRS1B, PRS2B, PRS3B, FCS1B, FCS2B, and FCS3B of bias generator 104 are computer programs or computer modules executed by the digital signal processor of bias generator 104.

[0077] In various embodiments, one or more functions described herein as being performed by the digital signal processor of source generator 102, the controllers PRS1S, PRS2S, PRS3S of source generator 102, and the controller used to generate the single frequency levels of source generator 102 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to driver system 124A without being coupled to the digital signal processor of source generator 102. The functions described herein as being performed by the digital signal processor of source generator 102, the controllers PRS1S, PRS2S, PRS3S of source generator 102, and the controller used to generate the single frequency levels of source generator 102 are computer programs or computer modules executed by the processor of the host computer.

[0078] Similarly, in some embodiments, one or more functions described herein as being performed by the digital signal processor of bias generator 104, the controllers PRS1B, PRS2B, and PRS3B of bias generator 104, and the controller used to generate the single frequency level of bias generator 104 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to driver system 124B without being coupled to the digital signal processor of bias generator 104. The functions described herein as being performed by the digital signal processor of bias generator 104, the controllers PRS1B, PRS2B, and PRS3B of bias generator 104, and the controller used to generate the single frequency level of bias generator 104 are computer programs or computer modules executed by the processor of the host computer.

[0079] In various embodiments, one or more functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S of the source generator 102 and the controller used to generate the single frequency levels of the source generator 102 are instead performed by a digital signal processor of the source generator 102. For example, the digital signal processor of the source generator 102 is coupled to the driver system 124A without being coupled to the controllers PRS1S, PRS2S, PRS3S of the source generator 102 and without being coupled to the controller used to generate the single frequency levels of the source generator 102. The functions described herein as being performed by the controllers PRS1S, PRS2S, and PRS3S of the source generator 102 and the controller used to generate the single frequency levels of the source generator 102 are computer programs or computer modules executed by the digital signal processor of the source generator 102.

[0080] Similarly, in some embodiments, one or more functions described herein as being performed by the controllers PRS1B, PRS2B, and PRS3B of bias generator 104 and the controller used to generate the single frequency level of bias generator 104 are instead performed by a digital signal processor of bias generator 104. For example, the digital signal processor of bias generator 104 is coupled to driver system 124B without being coupled to the controllers PRS1B, PRS2B, and PRS3B of bias generator 104 and without being coupled to the controller used to generate the single frequency level of bias generator 104. The functions described herein as being performed by the controllers PRS1B, PRS2B, and PRS3B of bias generator 104 and the controller used to generate the single frequency level of bias generator 104 are computer programs or computer modules executed by the digital signal processor of bias generator 104.

[0081] 1B is a diagram of one embodiment of a system 150 illustrating the generation of three or more states to achieve high-aspect-ratio dielectric etching. System 150 includes source generator 102, bias generator 104, a host computer, RF cables 120A and 120B, impedance matching circuit IMC 152, RF transmission line 122B, and plasma chamber 110. Impedance matching circuit IMC 152 is coupled to RF cables 120A and 120B and also to RF transmission line 122B. Upper electrode 116 is coupled to ground potential (e.g., grounded).

[0082] Impedance matching circuit IMC 152 receives RF signal 116A generated by source generator 102 and RF signal 116B generated by bias generator 104 and matches the impedance of a load coupled to the output of impedance matching circuit IMC 152 to the impedance of a source coupled to the input of impedance matching circuit IMC 152 to generate modified RF signal 154. For example, impedance matching circuit IMC 152 matches the impedance of RF transmission line 122B and plasma chamber 110 to the impedance of RF cables 120A and 120B, source generator 102, and bias generator 104. Modified RF signal 154 is an example of an output of impedance matching circuit IMC 152. Lower electrode 114 receives the modified RF signal 152. When one or more process gases are supplied to the plasma chamber 110 along with the modified RF signal 152, a plasma is struck or sustained within the gap 118 of the plasma chamber 110 to process the substrate S.

[0083] In various embodiments, instead of the top electrode 116 being grounded, the bottom electrode 112 is grounded and the top electrode 116 is coupled to RF transmission line 122B to receive modified RF signal 154.

[0084] 2A shows embodiments of graphs 202, 204, and 206 illustrating a parameter 208A of an RF signal 116B generated by the bias generator 104 of FIGS. 1A and 1B and a parameter 208B of an RF signal 116A generated by the source generator 102 of FIGS. 1A and 1B. Graph 202 plots parameters 208A and 208B versus time t. Additionally, graph 204 plots the logic level of a digital pulse signal 210 versus time t, and graph 206 plots the logic level of a clock signal 212 versus time t. Digital pulse signal 210 is an example of digital pulse signal DPS1 of FIG. 1.

[0085] Clock signal 212 is generated by the processor of the host computer of FIG. 1. For example, clock signal 212 is generated by a clock signal source, such as a crystal oscillator, within the processor of the host computer. Clock signal 212 alternates between logic level 1 and logic level 0. For example, clock signal 212 is at logic level 1 during the period between time t3 and time t0. The period between time t3 and time t0 includes time t1 and time t2. Clock signal 212 transitions from logic level 1 to logic level 0 at time t3 and remains at logic level 0 during the period between time t6 and time t3. The period between time t6 and t3 includes time t4 and time t5. Clock signal 212 transitions from logic level 0 to logic level 1 at time t6 and remains at logic level 1 during the period between time t9 and time t6. The period between time t9 and time t6 includes time t7 and time t8. Clock signal 212 transitions from logic level 1 to logic level 0 at time t9 and is at logic level 0 for the period between time t12 and time t9. The period between time t12 and t9 includes time t10 and time t11. Clock signal 212 transitions from logic level 0 to logic level 1 at time t12.

[0086] Digital pulse signal 210 transitions from logic level 0 to logic level 2 at time t0 and remains at logic level 2 while state S1 occurs (i.e., the period between time t3 and time t0). Digital pulse signal 210 transitions from logic level 2 to logic level 1 at time t3 and remains at logic level 1 while state S2 occurs (i.e., the period between time t4 and time t3). Digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t4 and remains at logic level 0 while state S3 occurs (i.e., the period between time t6 and time t4). Digital pulse signal 210 transitions from logic level 0 to logic level 2 at time t6 and remains at logic level 2 while state S1 again occurs (i.e., the period between time t6 and time t9). Digital pulse signal 210 transitions from logic level 2 to logic level 1 at time t9 and remains at logic level 1 while state S2 reoccurs (i.e., the period between time t9 and time t10). Digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 while state S3 reoccurs (i.e., between time t10 and time t12). Digital pulse signal 210 transitions from logic level 0 to logic level 2 at time t12.

[0087] Note that during the period between times t3 and t0, digital pulse signal 210 generates state S1, during the period between times t3 and t4, digital pulse signal 210 generates state S2, and during the period between times t4 and t6, digital pulse signal 210 generates state S3. Similarly, during the period between times t6 and t9, digital pulse signal 210 again generates state S1, during the period between times t9 and t10, digital pulse signal 210 again generates state S2, and during the period between times t10 and t12, digital pulse signal 210 again generates state S3.

[0088] Parameter 208A is at parameter level PR7 during the time period between t0 and t3 when digital pulse signal 210 has state S1. Parameter 208A transitions from parameter level PR7 to parameter level PR3 substantially at time t3 and remains at parameter level PR3 during the time period between t3 and t4 when digital pulse signal 210 has state S2. Parameter 208A transitions from parameter level PR3 to parameter level PR0.1 substantially at time t4 and remains at parameter level PR0.1 during the time period between t4 and t6 when digital pulse signal 210 has state S3. Parameter 208A transitions from parameter level PR0.1 to parameter level PR7 substantially at time t6 and remains at parameter level PR7 during the time period between t6 and t9 when digital pulse signal 210 has state S1.

[0089] Parameter 208A transitions from parameter level PR7 to parameter level PR3 substantially at time t9 and remains at parameter level PR3 during the period between t9 and t10 when digital pulse signal 210 has state S2. Parameter 208A transitions from parameter level PR3 to parameter level PR0.1 substantially at time t10 and remains at parameter level PR0.1 during the period between t10 and t12 when digital pulse signal 210 has state S3. Parameter 208A transitions from parameter level PR0.1 to parameter level PR7 substantially at time t12.

[0090] Parameter 208B is at parameter level PR4 during the time period between t0 and t3 when digital pulse signal 210 has state S1. Parameter 208B transitions from parameter level PR4 to parameter level PR2 substantially at time t3 and remains at parameter level PR2 during the time period between t3 and t4 when digital pulse signal 210 has state S2. Parameter 208B transitions from parameter level PR2 to parameter level PR0.1 substantially at time t4 and remains at parameter level PR0.1 during the time period between t4 and t6 when digital pulse signal 210 has state S3. Parameter 208B transitions from parameter level PR0.1 to parameter level PR4 substantially at time t6 and remains at parameter level PR4 during the time period between t6 and t9 when digital pulse signal 210 has state S1.

[0091] Parameter 208B transitions from parameter level PR4 to parameter level PR2 substantially at time t9 and remains at parameter level PR2 during the period between t9 and t10 when digital pulse signal 210 has state S2. Parameter 208B transitions from parameter level PR2 to parameter level PR0.1 substantially at time t10 and remains at parameter level PR0.1 during the period between t10 and t12 when digital pulse signal 210 has state S3. Parameter 208B transitions from parameter level PR0.1 to parameter level PR4 substantially at time t12.

[0092] Note that in some embodiments, a transition from one parameter level to another parameter level that occurs substantially at a time t occurs within a predetermined time period from that time. For example, when a transition from a first parameter level to a second parameter level occurs within a predetermined microsecond or a predetermined fraction of a millisecond from time t, the transition occurs substantially at time t. As another example, when a transition from a first parameter level to a second parameter level occurs at time t, the transition occurs substantially at time t.

[0093] Additionally, note that parameter level PR0.1 is greater than parameter level PR0 (e.g., the zero parameter level). Parameter level PR1 is greater than parameter level PR0.1, and parameter level PR2 is greater than parameter level PR1. Parameter level PR3 is greater than parameter level PR2, and parameter level PR4 is greater than parameter level PR3. Parameter level PR5 is greater than parameter level PR4, and parameter level PR6 is greater than parameter level PR5. Parameter level PR7 is greater than parameter level PR6.

[0094] Also note that time t of clock signal 212 is divided into equal segments. For example, the period between times t1 and t2 is equal to the period between times t0 and t1. Similarly, the period between times t2 and t3 is equal to the period between times t1 and t2, the period between times t3 and t4 is equal to the period between times t2 and t3, the period between times t4 and t5 is equal to the period between times t3 and t4, and the period between times t5 and t6 is equal to the period between times t 4 and t 5 The period between times t6 and t7 is equal to the period between times t5 and t6, the period between times t7 and t8 is equal to the period between times t6 and t7, the period between times t8 and t9 is equal to the period between times t7 and t8, and the period between times t9 and t10 is equal to the period between times t8 and t9. 10 and t 11 The period between is time t 9 and t 10 and the period between times t11 and t12 is equal to the period between times t10 and t11.

[0095] In various embodiments, parameter 208A transitions from parameter PR7 to another parameter level between parameter levels PR0.1 and PR7 at substantially time t3 or substantially time t9, and remains at the transitioned parameter level during state S2. Also, parameter 208A transitions from parameter PR3 to another parameter level (e.g., between parameter levels PR0.1 and PR3, or parameter level PR0) at substantially time t4 or substantially time t10, and remains at the transitioned parameter level during state S3.

[0096] In some embodiments, parameter 208B transitions from parameter PR4 to another parameter level between parameter levels PR0.1 and PR4 at substantially time t3 or substantially time t9 and remains at the transitioned parameter level during state S2. Also, parameter 208B transitions from parameter PR2 to another parameter level (e.g., between parameter levels PR0.1 and PR2, or parameter level PR0) at substantially time t4 or substantially time t10 and remains at the transitioned parameter level during state S3.

[0097] In some embodiments, the host computer processor modifies the digital pulse signal 210 to change the duration of state S2 of the digital pulse signal 210. For example, the host computer processor modifies the digital pulse signal 210 so that the period of logic level 1 is longer or shorter than the period between times t4 and t3. For example, the host computer processor modifies the digital pulse signal 210 so that the period of logic level 1 is from time t3 to the period between times t4 and t5.5. Time t5.5 is less than time t6 and greater than time t5. State S3 of the digital pulse signal 210 is shortened to the period between times t5.5 and t6. For another example, the host computer processor modifies the digital pulse signal 210 so that the period of logic level 1 is from the period between times t1.5 and t3 to time t4. Time t1.5 is less than time t2 and greater than time t1. State S1 of digital pulse signal 210 is shortened to the period between times t0 and t1.5. As yet another example, the host computer processor modifies digital pulse signal 210 so that the period of logic level 1 is the period from time t1.5 to time t5.5. As another example, the duration during which digital pulse signal DPS1 has state S2 is at most 30% of the period between times t0 and t6 and the period between times t6 and t12. As a further example, the duration during which digital pulse signal DPS1 has state S2 is in the range of 1% to 30% of the period between times t0 and t6 and the period between times t6 and t12. As another example, the duration during which digital pulse signal DPS1 has state S2 is in the range of 1% to 20% of the period between times t0 and t6 and the period between times t6 and t12.

[0098] FIG. 2B illustrates one embodiment of graph 250 and one embodiment of graph 252. Graph 250 illustrates another digital pulse signal 254, and graph 252 illustrates a parameter 256A of RF signal 116B generated by bias generator 104 of FIGS. 1A and 1B and another parameter 256B of RF signal 116A generated by source generator 102 of FIGS. 1A and 1B. Graph 250 plots the logic level of digital pulse signal 254 versus time t. Digital pulse signal 254 is an example of digital pulse signal DPS1 of FIG. 1. Graph 252 plots parameters 256A and 256B versus time t. Parameter 256A is synchronized to clock signal 212 and digital pulse signal 254 of FIG. 2A. Similarly, parameter 256B is synchronized to clock signal 212 (FIG. 2A) and digital pulse signal 254.

[0099] Digital pulse signal 254 transitions from logic level 0 to logic level 2 at time t0 and remains at logic level 2 while state S1 of digital pulse signal 254 occurs (i.e., the period between time t3 and time t0). Digital pulse signal 254 transitions from logic level 1 to logic level 0 at time t3 and remains at logic level 1 while state S2 of digital pulse signal 254 occurs (i.e., the period between time t5 and time t3). Digital pulse signal 254 transitions from logic level 1 to logic level 0 at time t5 and remains at logic level 0 while state S3 of digital pulse signal 254 occurs (i.e., the period between time t6 and time t5). Digital pulse signal 254 transitions from logic level 0 to logic level 2 at time t6 and remains at logic level 2 while state S1 of digital pulse signal 254 occurs again (i.e., the period between time t6 and time t9). Digital pulse signal 254 transitions from logic level 2 to logic level 1 at time t9 and remains at logic level 1 while state S2 of digital pulse signal 254 reoccurs (i.e., the period between time t9 and time t11). Digital pulse signal 254 transitions from logic level 1 to logic level 0 at time t11 and remains at logic level 0 while state S3 of digital pulse signal 254 reoccurs (i.e., the period between time t11 and time t12). Digital pulse signal 254 transitions from logic level 0 to logic level 2 at time t12.

[0100] Note that during the period between times t3 and t0, digital pulse signal 254 causes state S1 to occur, during the period between times t3 and t5, digital pulse signal 254 causes state S2 to occur, and during the period between times t5 and t6, digital pulse signal 254 causes state S3 to occur. Similarly, during the period between times t6 and t9, digital pulse signal 254 again causes state S1 to occur, during the period between times t9 and t11, digital pulse signal 254 again causes state S2 to occur, and during the period between times t11 and t12, digital pulse signal 254 again causes state S3 to occur.

[0101] Parameter 256A is at parameter level PR7 during the time period between t0 and t3 when digital pulse signal 254 has state S1. Parameter 256A transitions from parameter level PR7 to parameter level PR0.1 substantially at time t3 and remains at parameter level PR0.1 during the time period between t3 and t5 when digital pulse signal 254 has state S2. Parameter 256A transitions from parameter level PR0.1 to parameter level PR3 substantially at time t5 and remains at parameter level PR3 during the time period between t5 and t6 when digital pulse signal 254 has state S3. Parameter 256A transitions from parameter level PR3 to parameter level PR7 substantially at time t6 and remains at parameter level PR7 during the time period between t6 and t9 when digital pulse signal 254 has state S1.

[0102] Parameter 256A transitions from parameter level PR7 to parameter level PR0.1 substantially at time t9 and remains at parameter level PR0.1 during the period between t9 and t11 when digital pulse signal 254 has state S2. Parameter 256A transitions from parameter level PR0.1 to parameter level PR3 substantially at time t11 and remains at parameter level PR3 during the period between t11 and t12 when digital pulse signal 254 has state S3. Parameter 256A transitions from parameter level PR3 to parameter level PR7 substantially at time t12.

[0103] Parameter 256B is at parameter level PR4 during the time period between t0 and t3 when digital pulse signal 254 has state S1. Parameter 256B transitions from parameter level PR4 to parameter level PR0.1 substantially at time t3 and remains at parameter level PR0.1 during the time period between t3 and t5 when digital pulse signal 254 has state S2. Parameter 256B transitions from parameter level PR0.1 to parameter level PR2 substantially at time t5 and remains at parameter level PR2 during the time period between t5 and t6 when digital pulse signal 254 has state S3. Parameter 256B transitions from parameter level PR2 to parameter level PR4 substantially at time t6 and remains at parameter level PR4 during the time period between t6 and t9 when digital pulse signal 254 has state S1.

[0104] Parameter 256B transitions from parameter level PR4 to parameter level PR0.1 substantially at time t9 and remains at parameter level PR0.1 during the period between t9 and t11 when digital pulse signal 254 has state S2. Parameter 256B transitions from parameter level PR0.1 to parameter level PR2 substantially at time t11 and remains at parameter level PR2 during the period between t11 and t12 when digital pulse signal 254 has state S3. Parameter 256B transitions from parameter level PR2 to parameter level PR4 substantially at time t12.

[0105] In various embodiments, parameter 256A transitions from parameter PR7 to another parameter level (e.g., between parameter levels PR0.1 and PR3, or to parameter level PR0) substantially at time t3 or substantially at time t9 and remains at the transitioned parameter level during state S2. Also, parameter 256A transitions from parameter PR0.1 to another parameter level between parameter levels PR0.1 and PR7 substantially at time t5 or substantially at time t11 and remains at the transitioned parameter level during state S3.

[0106] In some embodiments, parameter 256B transitions from parameter PR4 to another parameter level (e.g., between parameter levels PR0.1 and PR4, or at parameter level PR0) substantially at time t3 or substantially at time t9 and remains at the transitioned parameter level during state S2. Also, parameter 256B transitions from parameter PR0.1 to another parameter level between parameter levels PR0.1 and PR4 substantially at time t5 or substantially at time t11 and remains at the transitioned parameter level during state S3.

[0107] In some embodiments, the host computer processor modifies the digital pulse signal 254 to change the duration of the state S2 of the digital pulse signal 254. For example, the host computer processor modifies the digital pulse signal 254 so that the period of logic level 1 is longer or shorter than the period between times t3 and t5. Illustratively, the host computer processor modifies the digital pulse signal 254 so that the period of logic level 1 is the period from time t3 to between time t5 and time t5.5. Time t5.5 is less than time t6 and greater than time t5. State S3 of the digital pulse signal 254 is shortened to the period between times t5.5 and t6. Illustratively, the host computer processor modifies the digital pulse signal 254 so that the period of logic level 1 is the period from the period between time t0.5 and time t3 to time t5. Time t0.5 is less than time t1 and greater than time t0. Digital pulse signal 254 State S1 is reduced to the period between times t0 and t0.5. As yet another example, the host computer processor modifies digital pulse signal 254 so that the period of logic level 1 is from time t0.5 to time t5.5.

[0108] In various embodiments, when digital pulse signal DPS1 is in state S1, the parameter level of each of RF signals 116A and 116B is greater than 1 kilowatt (kW), and the ion energy of ions in plasma chamber 110 is greater than 2.5 kiloelectronvolts (keV). Also, when digital pulse signal DPS1 is in state S1, the pressure in plasma chamber 110 is less than 30 milliTorr (mTorr) to obtain a narrow ion angular distribution function. Also, during state S2, the ion energy of ions in plasma chamber 110 is between 1.5 keV and 2.5 keV. Also, during state S3, the parameter level of each of RF signals 116A and 116B is less than 1 kilowatt, and the ion energy of ions in plasma chamber 110 is less than 100 eV.

[0109] In some embodiments, the various power level ranges of the source generator 102 and bias generator 104 for states S1-S3 of the digital pulse signal DPS1 are illustrated in the table below. [Table 1] As shown in Table 1, the parameter level of RF signal 116B generated by bias generator 104 during state S1 of digital pulse signal DPS1 ranges from 5 kW to 100 kW. The parameter level of RF signal 116A generated by source generator 102 during state S1 of digital pulse signal DPS1 ranges from 2 kW to 20 kW. The parameter level of RF signal 116B generated by bias generator 104 during state S3 of digital pulse signal DPS1 ranges from 0 kW to less than 2 kW. The parameter level of RF signal 116A generated by source generator 102 during state S3 of digital pulse signal DPS1 ranges from 0 kW to 2 kW. The parameter level of RF signal 116B generated by bias generator 104 during state S2 of digital pulse signal DPS1 ranges between the parameter level value of RF signal 116B during state S1 and the parameter level value of RF signal 116B during state S3. Also, the parameter level of the RF signal 116A generated by the source generator 102 during state S2 of the digital pulse signal DPS1 ranges from zero to the value of the parameter level of the RF signal 116A during state S1.

[0110] 3A is a diagram of one embodiment of a system 300 illustrating the generation of four states to achieve high aspect ratio dielectric etching. The system 300 includes a source generator 302 and a bias generator 304. The source generator 302 is an example of a source RF generator, and the bias generator 304 is an example of a bias RF generator. The system 300 further includes a host computer, a source impedance match circuit IMCS 106, a bias impedance match circuit IMCB 108, and a plasma chamber 110.

[0111] The source generator 302 includes a digital signal processor (DSPS), parameter controllers PRS1S, PRS2S, and PRS3S, frequency controllers FCS1S, FCS2S, and FCS3S, a driver system 306A, and a source RF power supply. The source generator 302 also includes a parameter controller PRS4S and a frequency controller FCS4S. The digital signal processor of the source generator 302 is coupled to the parameter controllers PRS1S, PRS2S, PRS3S, and PRS4S and is also coupled to the frequency controllers FCS1S, FCS2S, FCS3S, and FCS4S. The parameter controllers PRS1S, PRS2S, PRS3S, and PRS4S and the frequency controllers FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302 are further coupled to the driver system 306A. The driver system 306A is coupled to the source RF power supply of the source generator 302 .

[0112] 1A and 1B, and bias generator 304 has the same operating frequency as bias generator 104 of FIGURES 1A and 1B. For example, source generator 302 is an X RF generator and bias generator 304 is a Y RF generator. Both the X RF generator and the Y RF generator have been previously described.

[0113] Similarly, bias generator 304 includes a digital signal processor (DSPB), parameter controllers PRS1B, PRS2B, and PRS3B, frequency controllers FCS1B, FCS2B, and FCS3B, a driver system 306B, and a bias RF power supply. Bias generator 304 also includes a parameter controller PRS4B and a frequency controller FCS4B. The digital signal processor of bias generator 304 is coupled to the parameter controllers PRS1B, PRS2B, PRS3B, and PRS4B, and is also coupled to the frequency controllers FCS1B, FCS2B, FCS3B, and FCS4B. Furthermore, parameter controllers PRS1B, PRS2B, PRS3B, and PRS4B and frequency controllers FCS1B, FCS2B, FCS3B, and FCS4B are coupled to driver system 306B. Driver system 306B is coupled to the bias RF power supply of bias generator 304. The digital signal processor of the source generator 302 is coupled to the processor of the host computer via a transfer cable TCS, and the digital signal processor 304 of the bias generator 304 is coupled to the processor of the host computer via a transfer cable TCB.

[0114] The source coupled to the input of impedance matching circuit IMCS 106 includes RF cable 120A and source generator 302. The load coupled to the output of impedance matching circuit IMCS 106 includes RF transmission line 122A and plasma chamber 110. Additionally, the source coupled to the input of impedance matching circuit IMCB 108 includes RF cable 120B and bias generator 304. The load coupled to the output of impedance matching circuit IMCB 108 includes RF transmission line 122B and plasma chamber 110.

[0115] The processor of the host computer generates a digital pulse signal DPS2 and transmits the digital pulse signal DPS2 to the digital signal processor of the source generator 302 via a transfer cable TCS, and also transmits the digital pulse signal DPS2 to the digital signal processor of the bias generator 304 via a transfer cable TCB. The digital pulse signal DPS2 has a plurality of states S1, S2, S3, and S4, and periodically transitions among the states S1, S2, S3, and S4.

[0116] In addition to transmitting the multiple parameter levels for states S1-S3 of digital pulse signal DPS2 to the digital signal processors of source generator 302 and bias generator 304 in the same manner as transmitting the parameter levels for states S1-S3 of digital signal pulse DPS1, the processor of the host computer also transmits the parameter level for state S4 of digital pulse signal DPS2 to the digital signal processor of source generator 302 and transmits the parameter level for state S4 of digital pulse signal DPS2 to the digital signal processor of bias generator 304. Furthermore, in addition to transmitting the multiple frequency levels for states S1-S3 of digital pulse signal DPS2 to the digital signal processors of source generator 302 and bias generator 304 in the same manner as transmitting the frequency levels for states S1-S3 of digital signal pulse DPS1, the processor of the host computer also transmits the frequency level for state S4 of digital pulse signal DPS2 to the digital signal processor of source generator 302 and transmits the frequency level for state S4 of digital pulse signal DPS2 to the digital signal processor of bias generator 304.

[0117] The parameter levels and frequency levels of states S1-S4 of digital pulse signal DPS2 that are transmitted to the digital signal processors of source generator 302 and bias generator 304 are identified by the processor of the host computer from a memory device of the host computer. Upon receiving the parameter levels and frequency levels of states S1-S4 of digital pulse signal DPS2, in addition to transmitting the parameter levels of states S1-S3 of digital pulse signal DPS2 to corresponding parameter controllers PRS1S-PRS3S of source generator 302 and transmitting the frequency levels of states S1-S3 of digital pulse signal DPS2 to corresponding frequency controllers FCS1S-FCS3S of source generator 302, the digital signal processor of source generator 302 transmits the parameter level of state S4 to parameter controller PRS4S for storage in its memory device and transmits the frequency level of state S4 to frequency controller FCS4S for storage in its memory device. Similarly, upon receiving the parameter levels and frequency levels of states S1-S4 of digital pulse signal DPS2, in addition to transmitting the parameter levels of states S1-S3 of digital pulse signal DPS2 to corresponding parameter controllers PRS1B-PRS3B of bias generator 302 and transmitting the frequency levels of states S1-S3 of digital pulse signal DPS2 to corresponding frequency controllers FCS1B-FCS3B of bias generator 302, the digital signal processor of bias generator 304 transmits the parameter level of state S4 to parameter controller PRS4B to be stored in the memory device of parameter controller PRS4B and transmits the frequency level of state S4 to frequency controller FCS4B to be stored in the memory device of frequency controller FCS4B.

[0118] Each of the digital signal processors of the source generator 302 and the bias generator 304 determines whether the digital pulse signal DPS2 has the state S1, S2, S3, or S4. eachdetermine whether the logic level of digital pulse signal DPS2 is greater than, equal to, a second predetermined threshold, or less than a first predetermined threshold. The second predetermined threshold is less than the first predetermined threshold. If the logic level of digital pulse signal DPS2 is determined to be greater than the first predetermined threshold, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S1. On the other hand, if the logic level of digital pulse signal DPS2 is determined to be equal to the first predetermined threshold, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S2. Also, if the logic level of digital pulse signal DPS2 is determined to be equal to the second predetermined threshold, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S3.

[0033] Upon determining that the logic level of digital pulse signal DPS2 is less than the second predetermined threshold, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S4. As another example, each of the digital signal processors of source generator 302 and bias generator 304 determines whether the logic level of digital pulse signal DPS2 is 3. Upon determining that the logic level of digital pulse signal DPS2 is 3, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S1. Similarly, upon determining that the logic level of digital pulse signal DPS2 is 2, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S2. Additionally, upon determining that the logic level of digital pulse signal DPS2 is 1, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S3.Upon determining that the logic level of digital pulse signal DPS2 is zero, each of the digital signal processors of source generator 302 and bias generator 304 identifies the occurrence of the state of digital pulse signal DPS2 as S4.

[0119] During the period when digital pulse signal DPS2 is generating states S1, S2, and S3, the digital signal processor of source generator 302 sends a plurality of signals indicative of states S1, S2, and S3 of digital pulse signal DPS2 to corresponding parameter controllers PRS1S, PRS2S, and PRS3S of source generator 302, and to corresponding frequency controllers FCS1S, FCS2S, and FCS3S of source generator 302, in the manner described above with reference to the digital signal processor of source generator 102 of FIGURE 1A. Additionally, during the period when digital pulse signal DPS2 is generating state S4 of digital pulse signal DPS2, the digital signal processor of source generator 302 sends a signal indicative of state S4 to parameter controller PRS4S of source generator 302, and sends a signal indicative of state S4 to frequency controller FCS4S of source generator 302.

[0120] Similarly, during the period when digital pulse signal DPS2 is generating states S1, S2, and S3 of digital pulse signal DPS2, the digital signal processor of bias generator 304 sends a plurality of signals indicative of states S1, S2, and S3 of digital pulse signal DPS2 to corresponding parameter controllers PRS1B, PRS2B, and PRS3B of bias generator 304, and to corresponding frequency controllers FCS1B, FCS2B, and FCS3B of bias generator 304, in the manner described above with reference to the digital signal processor of bias generator 104 of FIG. 1A. Furthermore, during the period when digital pulse signal DPS2 is generating state S4 of digital pulse signal DPS2, the digital signal processor of bias generator 304 sends a signal indicative of state S4 to parameter controller PRS4B of bias generator 304, and sends a signal indicative of state S4 to frequency controller FCS4B of bias generator 304.

[0121] During the period when digital pulse signal DPS2 is generating states S1-S3, upon receiving signals indicating states S1-S3 of digital pulse signal DPS2, parameter controllers PRS1S, PRS2S, and PRS3S of source generator 302 access the corresponding parameter levels for states S1-S3 of digital pulse signal DPS2 from the corresponding memory devices of parameter controllers PRS1S, PRS2S, and PRS3S of source generator 302, in the manner described above with reference to source generator 102 of FIG. 1A, and transmit the parameter levels for states S1-S3 of digital pulse signal DPS2 to driver system 306A of source generator 302. Similarly, during the period when digital pulse signal DPS2 is generating states S1-S3, situation Upon receiving the signals indicating S1-S3, frequency controllers FCS1S, FCS2S, and FCS3S of source generator 302 access the corresponding frequency levels of states S1-S3 of digital pulse signal DPS2 from corresponding memory devices of frequency controllers FCS1S, FCS2S, and FCS3S of source generator 302, in the manner described above with reference to source generator 102 of FIG. 1A, and transmit the frequency levels of states S1-S3 of digital pulse signal DPS2 to driver system 306A of source generator 302.

[0122] Additionally, during the period when the digital pulse signal DPS2 is generating state S4, upon receiving a signal indicating state S4, the parameter controller PRS4S accesses the parameter level for state S4 from the corresponding memory device of the parameter controller PRS4S and transmits the parameter level for state S4 to the driver system 306A of the source generator 302. Similarly, during the period when the digital pulse signal DPS2 is generating state S4, upon receiving a signal indicating state S4, the frequency controller FCS4S accesses the frequency level for state S4 from the corresponding memory device of the frequency controller FCS4S and transmits the frequency level for state S4 to the driver system 306A of the source generator 302.

[0123] During the period when digital pulse signal DPS2 is generating states S1-S3, driver system 306A of source generator 302 receives the parameter levels of digital pulse signal DPS2 for states S1-S3 and the frequency levels of digital pulse signal DPS2 for states S1-S3 in the same manner as described above in which driver system 124A of source generator 102 receives the parameter levels of digital pulse signal DPS1 for states S1-S3 and the frequency levels of digital pulse signal DPS1 for states S1-S3. Additionally, during the period when digital pulse signal DPS2 is generating state S4, driver system 306A of source generator 302 receives the parameter levels of state S4 and the frequency level of state S4.

[0124] Upon receiving the parameter level of state S1 of digital pulse signal DPS2 and the frequency level of state S1 of digital pulse signal DPS2, driver system 306A of source generator 302 generates a current signal based on the parameter level of state S1 of digital pulse signal DPS2 and the frequency level of state S1 of digital pulse signal DPS2 and provides the current signal to the source RF power supply of source generator 302. During the period when digital pulse signal DPS2 is generating state S1 of digital pulse signal DPS2, the source RF power supply of source generator 302 generates a portion of RF signal 308A for state S1 of digital pulse signal DPS2 upon receiving the current signal from driver system 306A of source generator 302. RF signal 308A is an example of a source RF signal. The portion of RF signal 308A for state S1 of digital pulse signal DPS2 has the parameter level of state S1 of digital pulse signal DPS2 and the frequency level of state S1 of digital pulse signal DPS2 during the generation of state S1 of digital pulse signal DPS2.

[0125] Similarly, upon receiving the parameter level for state S2 of digital pulse signal DPS2 and the frequency level for state S2 of digital pulse signal DPS2, driver system 306A of source generator 302 generates a current signal based on the parameter level for state S2 of digital pulse signal DPS2 and the frequency level for state S2 of digital pulse signal DPS2, and provides the current signal to the source RF power supply of source generator 302. During the period when digital pulse signal DPS2 is generating state S2, the source RF power supply of source generator 302 generates a portion of RF signal 308A for state S2 of digital pulse signal DPS2 upon receiving the current signal from driver system 306A of source generator 302. The portion of RF signal 308A for state S2 of digital pulse signal DPS2 has the parameter level for state S2 of digital pulse signal DPS2 and the frequency level for state S2 of digital pulse signal DPS2 during the generation of state S2 of digital pulse signal DPS2.

[0126] Furthermore, upon receiving the parameter level of digital pulse signal DPS2 for state S3 and the frequency level of digital pulse signal DPS2 for state S3, driver system 306A of source generator 302 generates a current signal based on the parameter level of digital pulse signal DPS2 for state S3 and the frequency level of digital pulse signal DPS2 for state S3, and provides the current signal to the source RF power supply of source generator 302. During the period when digital pulse signal DPS2 is generating state S3, the source RF power supply of source generator 302 generates a portion of RF signal 308A for state S3 of digital pulse signal DPS2 upon receiving the current signal from driver system 306A of source generator 302. The portion of RF signal 308A for state S3 of digital pulse signal DPS2 has the parameter level of state S3 of digital pulse signal DPS2 and the frequency level of state S3 of digital pulse signal DPS2 during the generation of state S3 of digital pulse signal DPS2.

[0127] Furthermore, upon receiving the state S4 parameter level and the state S4 frequency level, driver system 306A of source generator 302 generates a current signal based on the state S4 parameter level and the state S4 frequency level and provides the current signal to the source RF power supply of source generator 302. During the period when digital pulse signal DPS2 is generating state S4, the source RF power supply of source generator 302 generates a portion of state S4 RF signal 308A of digital pulse signal DPS2 upon receiving the current signal from driver system 306A of source generator 302. The portion of state S4 RF signal 308A of digital pulse signal DPS2 has the state S4 parameter level and the state S4 frequency level during the generation of state S4 of digital pulse signal DPS2.

[0128] Furthermore, during the period when the digital pulse signal DPS2 is generating the states S1-S3, upon receiving a signal indicating the states S1-S3 of the digital pulse signal DPS2, the parameter controllers PRS1B, PRS2B, and PRS3B of the bias generator 304 access the corresponding parameter levels of the states S1-S3 of the digital pulse signal DPS2 from the corresponding memory devices of the parameter controllers PRS1B, PRS2B, and PRS3B in the manner described above with reference to the bias generator 104 of FIG. 1A, and transmit the parameter levels of the states S1-S3 of the digital pulse signal DPS2 to the driver system 306B of the bias generator 304. Similarly, during the period when digital pulse signal DPS2 is generating states S1-S3, upon receiving a signal indicating states S1-S3 of digital pulse signal DPS2, frequency controllers FCS1B, FCS2B, and FCS3B of bias generator 304 access the corresponding frequency levels of states S1-S3 of digital pulse signal DPS2 from their corresponding memory devices in the manner described above with reference to bias generator 104 of FIG. 1A, and transmit the frequency levels of states S1-S3 of digital pulse signal DPS2 to driver system 306B of bias generator 304.

[0129] Additionally, during the period when the digital pulse signal DPS2 is generating the state S4, upon receiving a signal indicating the state S4, the parameter controller PRS4B accesses the parameter level for the state S4 from the corresponding memory device of the parameter controller PRS4B and transmits the parameter level for the state S4 to the driver system 306B of the bias generator 304. Similarly, during the period when the digital pulse signal DPS2 is generating the state S4, upon receiving a signal indicating the state S4, the frequency controller FCS4B accesses the frequency level for the state S4 from the corresponding memory device of the frequency controller FCS4B and transmits the frequency level for the state S4 to the driver system 306B of the bias generator 304.

[0130] During the period when digital pulse signal DPS2 is generating states S1-S3, driver system 306B of bias generator 304 receives the parameter levels of digital pulse signal DPS2 for states S1-S3 and the frequency levels of digital pulse signal DPS2 for states S1-S3 in the same manner as described above in which driver system 124B of bias generator 104 receives the parameter levels of digital pulse signal DPS1 for states S1-S3 and the frequency levels of digital pulse signal DPS1 for states S1-S3. Additionally, during the period when digital pulse signal DPS2 is generating state S4, driver system 306B of bias generator 304 receives the parameter levels of state S4 and the frequency level of state S4.

[0131] Upon receiving the parameter level and frequency level of state S1 of digital pulse signal DPS2, driver system 306B of bias generator 304 generates a current signal based on the parameter level and frequency level of state S1 of digital pulse signal DPS2 and provides the current signal to the source RF power supply of bias generator 304. During the period when digital pulse signal DPS2 is generating state S1, the bias RF power supply of bias generator 304 generates a portion of RF signal 308B of state S1 of digital pulse signal DPS2 upon receiving the current signal from driver system 306B of bias generator 304. RF signal 308B is an example of a bias RF signal. The portion of RF signal 308B of state S1 of digital pulse signal DPS2 has the parameter level and frequency level of state S1 of digital pulse signal DPS2 during the generation of state S1 of digital pulse signal DPS2.

[0132] Similarly, upon receiving the parameter level and frequency level of state S2 of digital pulse signal DPS2, driver system 306B of bias generator 304 generates a current signal based on the parameter level and frequency level of state S2 of digital pulse signal DPS2 and provides the current signal to the bias RF power supply of bias generator 304. During the period when digital pulse signal DPS2 is generating state S2, the bias RF power supply of bias generator 304 generates a portion of state S2 RF signal 308B of digital pulse signal DPS2 upon receiving the current signal from driver system 306B of bias generator 304. The portion of state S2 RF signal 308B of digital pulse signal DPS2 has the parameter level and frequency level of state S2 of digital pulse signal DPS2 during the generation of state S2 of digital pulse signal DPS2.

[0133] Furthermore, upon receiving the parameter levels and frequency levels of state S3 of digital pulse signal DPS2, driver system 306B of bias generator 304 generates a current signal based on the parameters and frequency levels of state S3 of digital pulse signal DPS2 and provides the current signal to the bias RF power supply of bias generator 304. During the period when digital pulse signal DPS2 is generating state S3, the bias RF power supply of bias generator 304 generates a portion of RF signal 308B of state S3 of digital pulse signal DPS2 upon receiving the current signal from driver system 306B of bias generator 304. The portion of RF signal 308B of state S3 of digital pulse signal DPS2 has the parameter levels and frequency levels of state S3 of digital pulse signal DPS2 during the generation of state S3 of digital pulse signal DPS2.

[0134] Furthermore, upon receiving the parameter level and frequency level for state S4, driver system 306B of bias generator 304 generates a current signal based on the parameter level and frequency level for state S4 and provides the current signal to the bias RF power supply of bias generator 304. During the period when digital pulse signal DPS2 is generating state S4, the bias RF power supply of bias generator 304 generates a portion of RF signal 308B for state S4 of digital pulse signal DPS2 upon receiving the current signal from driver system 306B of bias generator 304. The portion of RF signal 308B for state S4 of digital pulse signal DPS2 has the parameter level and frequency level for state S4 during the generation of state S4 of digital pulse signal DPS2.

[0135] Impedance matching circuit IMCS 106 receives RF signal 308A via RF cable 120A and matches the impedance of a load coupled to the output of impedance matching circuit IMCS 106 to the impedance of a source coupled to the input of impedance matching circuit IMCS 106 to generate modified RF signal 310A. Modified RF signal 310A is provided from the output of impedance matching circuit IMCS 106 to upper electrode 116.

[0136] Similarly, impedance match circuit IMCB 108 receives RF signal 308B via RF cable 120B and matches the impedance of a load coupled to the output of impedance match circuit IMCB 108 to the impedance of a source coupled to the input of impedance match circuit IMCB 108 to generate modified RF signal 310B. Modified RF signal 310B is provided from the output of impedance match circuit IMCB 108 to the lower electrode 114. In addition to providing modified RF signals 310A and 310B, one or more process gases are provided to the plasma chamber 110, and a plasma is struck or sustained in gap 118 of the plasma chamber 110 to process the substrate S.

[0137] In some embodiments, the parameter levels of states S1-S4 of digital pulse signal DPS2 that are sent to the digital signal processor of source generator 302 and bias generator 304 are received from a user via an input device connected to the processor of the host computer via an input / output interface, instead of being identified by the processor of the host computer. Similarly, in some embodiments, the frequency levels of states S1-S4 that are sent to the digital signal processor of source generator 302 and bias generator 304 are received from a user via an input device, instead of being identified by the processor of the host computer.

[0138] Also, in various embodiments, as described above, a parameter level of an RF signal includes one or more magnitudes (e.g., amplitudes or values) of a parameter of the RF signal, which magnitudes exclude one or more magnitudes of another parameter level of the parameter of the RF signal. For example, the parameter level transmitted to the digital signal processor of source generator 302 for state S2 of digital pulse signal DPS2 has one or more values, none of which is the same as one or more values ​​of the parameter level transmitted to the digital signal processor of source generator 302 for state S1 of digital pulse signal DPS2. Furthermore, the parameter level transmitted to the digital signal processor of source generator 302 for state S3 of digital pulse signal DPS2 has one or more values, none of which is the same as one or more values ​​of the parameter level transmitted to the digital signal processor of source generator 302 for state S2 of digital pulse signal DPS2. Additionally, the parameter levels sent to the digital signal processor of source generator 302 for state S3 of digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of source generator 302 for state S1 of digital pulse signal DPS2. The parameter levels sent to the digital signal processor of source generator 302 for state S4 of digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of source generator 302 for state S3 of digital pulse signal DPS2. Additionally, the parameter levels sent to the digital signal processor of source generator 302 for state S4 of digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of source generator 302 for state S2 of digital pulse signal DPS2.The parameter levels sent to the digital signal processor of the source generator 302 for state S4 of the digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the source generator 302 for state S1 of the digital pulse signal DPS2.

[0139] As another example, the parameter levels sent to the digital signal processor of bias generator 304 for state S2 of digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of bias generator 304 for state S1 of digital pulse signal DPS2. Further, the parameter levels sent to the digital signal processor of bias generator 304 for state S3 of digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of bias generator 304 for state S2 of digital pulse signal DPS2. Also, the parameter levels sent to the digital signal processor of bias generator 304 for state S3 of digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of bias generator 304 for state S1 of digital pulse signal DPS2. The parameter levels sent to the digital signal processor of the bias generator 304 for state S4 of the digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the bias generator 304 for state S3 of the digital pulse signal DPS2. Also, the parameter levels sent to the digital signal processor of the bias generator 304 for state S4 of the digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the bias generator 304 for state S2 of the digital pulse signal DPS2. The parameter levels sent to the digital signal processor of the bias generator 304 for state S4 of the digital pulse signal DPS2 have one or more values, none of which are the same as the one or more values ​​of the parameter levels sent to the digital signal processor of the bias generator 304 for state S1 of the digital pulse signal DPS2.

[0140] In various embodiments, a single frequency controller is used to control the source RF power supply of the source generator 302 instead of the multiple frequency controllers FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302 to generate a single frequency level of the RF signal instead of the multiple frequency levels of states S1-S4. The single frequency level is described above with reference to the source generator 102. The processor of the host computer transmits the value of the single frequency level of the RF signal to the digital signal processor of the source generator 302. Upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS2 is S1, S2, S3, or S4, the digital signal processor of the source generator 302 transmits the value to the frequency controller for storage in the memory device of the frequency controller. Furthermore, upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS2 is S1, S2, S3, or S4, the frequency controller transmits the value to the driver system 306A. The driver system 306A generates a current signal based on the value of the single frequency level, and the current signal to the source RF power supply of source generator 302. Upon receiving the current signal, the source RF power supply of source generator 302 generates an RF signal having a single frequency level and multiple parameter levels in states S1 to S4.

[0141] Similarly, in some embodiments, a single frequency controller is used to control the bias RF power supply instead of the multiple frequency controllers FCS1B, FCS2B, FCS3B, and FCS4B of the bias generator 304 to generate a single frequency level of the RF signal instead of the multiple frequency levels of states S1-S4. The single frequency level is described above with reference to the bias generator 104. The processor of the host computer transmits the value of the single frequency level of the RF signal to the digital signal processor of the bias generator 304. Upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS2 is S1, S2, S3, or S4, the digital signal processor of the bias generator 304 transmits the value to the frequency controller for storage in the memory device of the frequency controller. Furthermore, upon receiving the value of the single frequency level, regardless of whether the state of the digital pulse signal DPS2 is S1, S2, S3, or S4, the frequency controller transmits the value to the driver system 306B. The driver system 306B generates a current signal based on the value of the single frequency level, and the current signal to the bias RF power supply of the bias generator 304. Upon receiving the current signal, the bias RF power supply of the bias generator 304 generates an RF signal having a single frequency level and multiple parameter levels for the states S1 to S4 of the digital pulse signal DPS2.

[0142] In various embodiments, one or more functions described herein as being performed by a host computer processor are instead performed by a digital signal processor of source generator 302. For example, instead of the host computer processor providing the parameter levels and frequency levels for states S1-S4 to the digital signal processor of source generator 302, the parameter levels and frequency levels are stored in a memory device coupled to the digital signal processor of source generator 302, accessed from the memory device by the digital signal processor of source generator 302, and sent to parameter controllers PRS1S, PRS2S, PRS3S, and PRS4S and frequency controllers FCS1S, FCS2S, FCS3S, and FCS4S based on whether the state of digital pulse signal DPS2 received from the host computer processor is S1, S2, S3, or S4. As another example, instead of digital pulse signal DPS2 being generated by a processor of the host computer, digital pulse signal DPS2 is generated by a digital signal processor of source generator 302 and transmitted to the digital signal processor of bias generator 304 via a transfer cable coupling the two digital signal processors of source generator 302 and bias generator 304. As yet another example, instead of the processor of the host computer providing the parameter levels and frequency levels for states S1-S4 to the digital signal processor of bias generator 304, the parameter levels and frequency levels are stored in a memory device coupled to the digital signal processor of bias generator 304, accessed from the memory device by the digital signal processor of bias generator 304, and transmitted to parameter controllers PRS1B, PRS2B, PRS3B, and PRS4B and frequency controllers FCS1B, FCS2B, FCS3B, and FCS4B based on whether the state of digital pulse signal DPS2 received from the processor of the host computer is S1, S2, S3, or S4.As another example, instead of the digital pulse signal DPS2 being generated by the processor of the host computer, the digital pulse signal DPS2 is generated by a digital signal processor of the bias generator 304 and transmitted to the source generator 302 via a transfer cable coupling the two digital signal processors of the source generator 302 and the bias generator 304.

[0143] 3B is a diagram of one embodiment of a system 350 illustrating the generation of four states to achieve high-aspect ratio dielectric etching. System 350 includes a source generator 302, a bias generator 304, a host computer, RF cables 120A and 120B, an impedance matching circuit IMC 152, an RF transmission line 122B, and a plasma chamber 110. System 350 is the same as system 150 of FIG. 1B except that in system 350, a four-state source generator 302 and a bias generator 304 are used instead of the three-state source generator 102 and bias generator 104. Sources coupled to the inputs of impedance matching circuit IMC 152 include RF cables 120A and 120B, and the source generator 302 and bias generator 304.

[0144] Impedance matching circuit IMC152 receives RF signal 308A generated by source generator 302 and RF signal 308B generated by bias generator 304 and matches the impedance of a load coupled to the output of impedance matching circuit IMC152 to the impedance of a source coupled to the input of impedance matching circuit IMC152 to generate modified RF signal 354. For example, impedance matching circuit IMC152 matches the impedance of RF transmission line 122B and plasma chamber 110 to the impedance of RF cables 120A and 120B, source generator 302, and bias generator 304. Lower electrode 114receives a modified RF signal 354 to control processing of the substrate S. When one or more process gases are supplied to the plasma chamber 110 with the modified RF signal 354, a plasma is struck or sustained in the gap 118 of the plasma chamber 110 to process the substrate S. The processing of the substrate S is controlled, for example, by including a parameter level for the RF signal 308A in state S2 and including a parameter level for the RF signal 308B in state S2. During state S2, the RF signal 308A and the RF signal 308B have parameter levels to generate plasma ions that sputter mask material of the substrate S downward to protect a substrate layer of the substrate S.

[0145] In various embodiments, instead of the top electrode 116 being coupled to ground potential, the bottom electrode 112 is coupled to ground potential and the top electrode 116 is coupled to RF transmission line 122B to receive modified RF signal 354.

[0146] In various embodiments, one or more functions described herein as being performed by the digital signal processor of the source generator 302 and the controllers PRS1S, PRS2S, PRS3S, PRS4S, FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to the driver system 306A without being coupled to the digital signal processor of the source generator 302. The functions described herein as being performed by the digital signal processor of the source generator 302 and the controllers PRS1S, PRS2S, PRS3S, PRS4S, FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302 are computer programs or computer modules executed by the processor of the host computer.

[0147] Similarly, in some embodiments, one or more functions described herein as being performed by the digital signal processor of bias generator 304 and controllers PRS1B, PRS2B, PRS3B, PRS4B, FCS1B, FCS2B, FCS3B, and FCS4B of bias generator 304 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to driver system 306B without being coupled to the digital signal processor of bias generator 304. The functions described herein as being performed by the digital signal processor of bias generator 304 and controllers PRS1B, PRS2B, PRS3B, PRS4B, FCS1B, FCS2B, FCS3B, and FCS4B of bias generator 304 are computer programs or computer modules executed by the processor of the host computer.

[0148] In various embodiments, one or more functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S, PRS4S, FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302 are instead performed by a digital signal processor of the source generator 302. For example, the digital signal processor of the source generator 302 is coupled to the driver system 306A without being coupled to the controllers PRS1S, PRS2S, PRS3S, PRS4S, FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302. The functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S, PRS4S, FCS1S, FCS2S, FCS3S, and FCS4S of the source generator 302 are computer programs or computer modules executed by the digital signal processor of the source generator 302.

[0149] Similarly, in some embodiments, one or more functions described herein as being performed by controllers PRS1B, PRS2B, PRS3B, PRS4B, FCS1B, FCS2B, FCS3B, and FCS4B of bias generator 304 are instead performed by a digital signal processor of bias generator 304. For example, the digital signal processor of bias generator 304 is coupled to driver system 306B without being coupled to controllers PRS1B, PRS2B, PRS3B, PRS4B, FCS1B, FCS2B, FCS3B, and FCS4B of bias generator 304. The functions described herein as being performed by controllers PRS1B, PRS2B, PRS3B, PRS4B, FCS1B, FCS2B, FCS3B, and FCS4B of bias generator 304 are computer programs or computer modules executed by the digital signal processor of bias generator 304.

[0150] In various embodiments, one or more functions described herein as being performed by the digital signal processor of source generator 302, the controllers PRS1S, PRS2S, PRS3S, and PRS4S of source generator 302, and the controller used to generate the single frequency levels of source generator 302 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to driver system 306A without being coupled to the digital signal processor of source generator 302. The functions described herein as being performed by the digital signal processor of source generator 302, the controllers PRS1S, PRS2S, PRS3S, and PRS4S of source generator 302, and the controller used to generate the single frequency levels of source generator 302 are computer programs or computer modules executed by the processor of the host computer.

[0151] Similarly, in some embodiments, one or more functions described herein as being performed by the digital signal processor of bias generator 304, the controllers PRS1B, PRS2B, PRS3B, and PRS4B of bias generator 304, and the controller used to generate the single frequency levels of bias generator 304 are instead performed by a processor of a host computer. For example, the processor of the host computer is coupled to driver system 306B without being coupled to the digital signal processor of bias generator 304. The digital signal processor of bias generator 304, the bias generator 304 The functions described herein as being performed by the controllers PRS1B, PRS2B, PRS3B, and PRS4B, as well as the controller used to generate the single frequency level of the bias generator 304, are computer programs or computer modules that are executed by a processor of a host computer.

[0152] In various embodiments, one or more functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S, and PRS4S of the source generator 302 and the controller used to generate the single frequency levels of the source generator 302 are instead performed by a digital signal processor of the source generator 302. For example, the digital signal processor of the source generator 302 is coupled to the driver system 306A without being coupled to the controllers PRS1S, PRS2S, PRS3S, and PRS4S of the source generator 302 and without being coupled to the controller used to generate the single frequency levels of the source generator 302. The functions described herein as being performed by the controllers PRS1S, PRS2S, PRS3S, and PRS4S of the source generator 302 and the controller used to generate the single frequency levels of the source generator 302 are computer programs or computer modules executed by the digital signal processor of the source generator 302.

[0153] Similarly, in some embodiments, one or more functions described herein as being performed by the controllers PRS1B, PRS2B, PRS3B, and PRS4B of bias generator 304 and the controller used to generate the single frequency level of bias generator 304 are instead performed by a digital signal processor of bias generator 304. For example, the digital signal processor of bias generator 304 is coupled to driver system 306B without being coupled to the controllers PRS1B, PRS2B, PRS3B, and PRS4B of bias generator 304 and without being coupled to the controller used to generate the single frequency level of bias generator 304. The functions described herein as being performed by the controllers PRS1B, PRS2B, PRS3B, and PRS4B of bias generator 304 and the controller used to generate the single frequency level of bias generator 304 are computer programs or computer modules executed by the digital signal processor of bias generator 304.

[0154] 4A shows an embodiment of graph 206, as well as additional graphs 402 and 404, illustrating parameters 408A of RF signal 308B generated by bias generator 304 of FIGS. 3A and 3B and parameters 408B of RF signal 308A generated by source generator 302 of FIGS. 3A and 3B. Graph 404 plots parameters 408A and 408B versus time t, and graph 402 plots the logic levels of digital pulse signal 406 versus time t. Digital pulse signal 406 is an example of digital pulse signal DPS2 of FIG. 3A.

[0155] Digital Pulse Signal 406 transitions from logic level 0 to logic level 3 at time t0 and remains at logic level 3 while state S1 occurs (i.e., the period between time t0 and time t3).406 transitions from logic level 3 to logic level 2 at time t3 and remains at logic level 2 while state S2 occurs (i.e., the period between time t3 and time t3.5). 406 transitions from logic level 2 to logic level 1 at time t3.5 and remains at logic level 1 while state S3 occurs (i.e., the period between time t3.5 and time t5.5). 406 transitions from logic level 1 to logic level 0 at time t5.5 and remains at logic level 0 while state S4 occurs (ie, the period between time t5.5 and time t6).

[0156] Digital Pulse Signal 406 transitions from logic level 0 to logic level 3 at time t6 and remains at logic level 3 while state S1 reoccurs (i.e., the period between time t6 and time t9). 406 transitions from logic level 3 to logic level 2 at time t9 and remains at logic level 2 while state S2 reoccurs (i.e., the period between time t9 and time t9.5). 406 transitions from logic level 2 to logic level 1 at time t9.5 and remains at logic level 1 while state S3 occurs again (i.e., the period between time t9.5 and time t11.5). 406 transitions from logic level 1 to logic level 0 at time t11.5 and remains at logic level 0 while state S4 occurs again (i.e., the period between time t11.5 and time t12). 406 transitions from logic level 0 to logic level 3 at time t12.

[0157] Note that during the period between times t3 and t0, digital pulse signal 406 causes state S1, during the period between times t3 and t3.5, digital pulse signal 406 causes state S2, during the period between times t3.5 and t5.5, digital pulse signal 406 causes state S3, and during the period between times t5.5 and t6, digital pulse signal 406 causes state S4. Similarly, during the period between times t6 and t9, digital pulse signal 406 causes state S1 to occur again, during the period between times t9 and t9.5, digital pulse signal 406 causes state S2 to occur again, during the period between times t9.5 and t11.5, digital pulse signal 406 causes state S3 to occur again, and during the period between times t11.5 and t12, digital pulse signal 406 causes state S4 to occur again.

[0158] Parameter 408A is at parameter level PR7 during the time period between t0 and t3 when digital pulse signal 406 has state S1. Parameter 408A transitions from parameter level PR7 to parameter level PR5.5 substantially at time t3 and remains at parameter level PR5.5 during the time period between t3 and t3.5 when digital pulse signal 406 has state S2. Parameter 408A transitions from parameter level PR5.5 to parameter level PR0.1 substantially at time t3.5 and remains at parameter level PR0.1 during the time period between t3.5 and t5.5 when digital pulse signal 406 has state S3. Parameter 408A transitions from parameter level PR0.1 to parameter level PR3 substantially at time t5.5 and remains at parameter level PR3 during the time period between t5.5 and t6 when digital pulse signal 406 has state S4.

[0159] Parameter 408A transitions from parameter level PR3 to parameter level PR7 substantially at time t6 and remains at parameter level PR7 for the period between times t6 and t9 when digital pulse signal 406 has state S1. Parameter 408A transitions from parameter level PR7 to parameter level PR5.5 substantially at time t9 and remains at parameter level PR5.5 for the period between times t9 and t9.5 when digital pulse signal 406 has state S2. Parameter 408A transitions from parameter level PR5.5 to parameter level PR0.1 substantially at time t9.5 and remains at parameter level PR0.1 for the period between times t9.5 and t11.5 when digital pulse signal 406 has state S3. Parameter 408A transitions from parameter level PR0.1 to parameter level PR3 substantially at time t11.5 and remains at parameter level PR3 for the period between times t11.5 and t12 when digital pulse signal 406 has state S4. Parameter 408A transitions from parameter level PR3 to parameter level PR7 substantially at time t12.

[0160] Parameter 408B is at parameter level PR4 during the time period between t0 and t3 when digital pulse signal 406 has state S1. Parameter 408B transitions from parameter level PR4 to parameter level PR3.5 substantially at time t3 and remains at parameter level PR3.5 during the time period between t3 and t3.5 when digital pulse signal 406 has state S2. Parameter 408B transitions from parameter level PR3.5 to parameter level PR0.1 substantially at time t3.5 and remains at parameter level PR0.1 during the time period between t3.5 and t5.5 when digital pulse signal 406 has state S3. Parameter 408B transitions from parameter level PR0.1 to parameter level PR2 substantially at time t5.5 and remains at parameter level PR2 during the time period between t5.5 and t6 when digital pulse signal 406 has state S4.

[0161] Parameter 408B transitions from parameter level PR2 to parameter level PR4 substantially at time t6 and remains at parameter level PR4 for the period between times t6 and t9 when digital pulse signal 406 has state S1. Parameter 408B transitions from parameter level PR4 to parameter level PR3.5 substantially at time t9 and remains at parameter level PR3.5 for the period between times t9 and t9.5 when digital pulse signal 406 has state S2. Parameter 408B transitions from parameter level PR3.5 to parameter level PR0.1 substantially at time t9.5 and remains at parameter level PR0.1 for the period between times t9.5 and t11.5 when digital pulse signal 406 has state S3. Parameter 408B transitions from parameter level PR0.1 to parameter level PR2 substantially at time t11.5 and remains at parameter level PR2 for the period between times t11.5 and t12 when digital pulse signal 406 has state S4. Parameter 408B transitions from parameter level PR2 to parameter level PR4 substantially at time t12.

[0162] It is further noted that parameter level PR3.5 is greater than parameter level PR3 but less than parameter level PR4, and parameter level PR5.5 is greater than parameter level PR5 but less than parameter level PR6.

[0163] In various embodiments, parameter 408A transitions from parameter PR7 to another parameter level (e.g., between parameter levels PR3 and PR7) substantially at time t3 or substantially at time t9 and remains at the transitioned parameter level during state S2. Also, parameter 408A transitions from parameter PR5.5 to another parameter level (i.e., between parameter levels PR0.1 and PR3, or parameter level PR0) substantially at time t3.5 or substantially at time t9.5 and remains at the transitioned parameter level during state S3. Parameter 408A transitions from parameter PR0.1 to another parameter level (i.e., between parameter levels PR0.1 and PR5.5) substantially at time t5.5 or substantially at time t11.5 and remains at the transitioned parameter level during state S4.

[0164] In some embodiments, parameter 408B transitions from parameter PR4 to another parameter level (i.e., between parameter levels PR2 and PR4) substantially at time t3 or substantially at time t9 and remains at the transitioned parameter level during state S2. Also, parameter 408B transitions from parameter PR3.5 to another parameter level (i.e., between parameter levels PR0.1 and PR2, or parameter level PR0) substantially at time t3.5 or substantially at time t9.5 and remains at the transitioned parameter level during state S3. Parameter 408B transitions from parameter PR0.1 to another parameter level (i.e., between parameter levels PR0.1 and PR3.5) substantially at time t5.5 or substantially at time t11.5 and remains at the transitioned parameter level during state S4.

[0165] In some embodiments, the host computer processor modifies the digital pulse signal 406 to change the duration of state S2 of the digital pulse signal 406 and / or the duration of state S3 of the digital pulse signal 406. For example, the host computer processor modifies the digital pulse signal 406 so that the period of logic level 2 is longer or shorter than the period between times t3 and t3.5. As another example, the host computer processor modifies the digital pulse signal 406 so that the period of logic level 1 is longer or shorter than the period between times t3.5 and t5.5. As another example, the duration during which the digital pulse signal DPS2 has states S2 and S3 is at most 30% of the period between times t0 and t6. As a further example, the duration during which the digital pulse signal DPS2 has states S2 and S3 is in the range of 1% to 30% of the period between times t0 and t6. As another example, the duration during which the digital pulse signal DPS2 has states S2 and S3 is in the range of 1% to 20% of the period between times t0 and t6.

[0166] FIG. 4B illustrates one embodiment of graph 450 and one embodiment of graph 452. Graph 450 illustrates another digital pulse signal 454, and graph 452 illustrates a parameter 456A of RF signal 308B generated by bias generator 304 of FIGS. 3A and 3B and another parameter 456B of RF signal 308A generated by source generator 302 of FIGS. 3A and 3B. Graph 450 plots the logic level of digital pulse signal 454 versus time t. Digital pulse signal 454 is an example of digital pulse signal DPS2 of FIGS. 3A and 3B. Graph 452 plots parameters 456A and 456B versus time t. Parameter 456A is synchronized to clock signal 212 and digital pulse signal 454 of FIG. 4A. Similarly, parameter 456B is synchronized to clock signal 212 (FIG. 4A) and digital pulse signal 454.

[0167] Digital pulse signal 454 transitions from logic level 0 to logic level 3 at time t0 and remains at logic level 3 while state S1 of digital pulse signal DPS2 occurs (i.e., the period between time t0 and time t3). Digital pulse signal 454 transitions from logic level 3 to logic level 2 at time t3 and remains at logic level 2 while state S2 of digital pulse signal DPS2 occurs (i.e., the period between time t3 and time t3.5). Digital pulse signal 454 transitions from logic level 2 to logic level 1 at time t3.5 and remains at logic level 1 while state S3 of digital pulse signal DPS2 occurs (i.e., the period between time t3.5 and time t4). Digital pulse signal 454 transitions from logic level 1 to logic level 0 at time t4 and remains at logic level 0 while state S4 of digital pulse signal DPS2 occurs (i.e., the period between time t4 and t6).

[0168] Digital pulse signal 454 transitions from logic level 0 to logic level 3 at time t6 and remains at logic level 3 while state S1 of digital pulse signal DPS2 reoccurs (i.e., the period between time t6 and time t9). Digital pulse signal 454 transitions from logic level 3 to logic level 2 at time t9 and remains at logic level 2 while state S2 of digital pulse signal DPS2 reoccurs (i.e., the period between time t9 and time t9.5). Digital pulse signal 454 transitions from logic level 2 to logic level 1 at time t9.5 and remains at logic level 1 while state S3 of digital pulse signal DPS2 reoccurs (i.e., the period between time t9.5 and time t10). Digital pulse signal 454 transitions from logic level 1 to logic level 0 at time t10 and remains at logic level 0 while state S4 of digital pulse signal DPS2 reoccurs (i.e., the period between time t10 and time t12). Digital pulse signal 454 transitions from logic level 0 to logic level 3 at time t12.

[0169] Note that during the period between times t3 and t0, digital pulse signal 454 causes state S1, during the period between times t3 and t3.5, digital pulse signal 454 causes state S2, during the period between times t3.5 and t4, digital pulse signal 454 causes state S3, and during the period between times t4 and t6, digital pulse signal 454 causes state S4. Similarly, during the period between times t6 and t9, digital pulse signal 454 again causes state S1, during the period between times t9 and t9.5, digital pulse signal 454 again causes state S2, during the period between times t9.5 and t10, digital pulse signal 454 again causes state S3, and during the period between times t10 and t12, digital pulse signal 454 again causes state S4.

[0170] Parameter 456A is at parameter level PR7 during the time period between t0 and t3 when digital pulse signal 454 has state S1. Parameter 456A transitions from parameter level PR7 to parameter level PR5 substantially at time t3 and remains at parameter level PR5 during the time period between t3 and t3.5 when digital pulse signal 454 has state S2. Parameter 456A transitions from parameter level PR5 to parameter level PR3 substantially at time t3.5 and remains at parameter level PR3 during the time period between t3.5 and t4 when digital pulse signal 454 has state S3. Parameter 456A transitions from parameter level PR3 to parameter level PR0.1 substantially at time t4 and remains at parameter level PR0.1 during the time period between t4 and t6 when digital pulse signal 454 has state S4.

[0171] Parameter 456A transitions from parameter level PR0.1 to parameter level PR7 substantially at time t6 and remains at parameter level PR7 for the period between times t6 and t9 when digital pulse signal 454 has state S1. Parameter 456A transitions from parameter level PR7 to parameter level PR5 substantially at time t9 and remains at parameter level PR5 for the period between times t9 and t9.5 when digital pulse signal 454 has state S2. Parameter 456A transitions from parameter level PR5 to parameter level PR3 substantially at time t9.5 and remains at parameter level PR3 for the period between times t9.5 and t10 when digital pulse signal 454 has state S3. Parameter 456A transitions from parameter level PR3 to parameter level PR0.1 substantially at time t10 and remains at parameter level PR0.1 for the period between times t10 and t12 when digital pulse signal 454 has state S4. Parameter 456A transitions from parameter level PR0.1 to parameter level PR7 substantially at time t12.

[0172] Parameter 456B is at parameter level PR4 during the time period between t0 and t3 when digital pulse signal 454 has state S1. Parameter 456B transitions from parameter level PR4 to parameter level PR3 substantially at time t3 and remains at parameter level PR3 during the time period between t3 and t3.5 when digital pulse signal 454 has state S2. Parameter 456B transitions from parameter level PR3 to parameter level PR2 substantially at time t3.5 and remains at parameter level PR2 during the time period between t3.5 and t4 when digital pulse signal 454 has state S3. Parameter 456B transitions from parameter level PR2 to parameter level PR0.1 substantially at time t4 and remains at parameter level PR0.1 during the time period between t4 and t6 when digital pulse signal 454 has state S4.

[0173] Parameter 456B transitions from parameter level PR0.1 to parameter level PR4 substantially at time t6 and remains at parameter level PR4 for the period between times t6 and t9 when digital pulse signal 454 has state S1. Parameter 456B transitions from parameter level PR4 to parameter level PR3 substantially at time t9 and remains at parameter level PR3 for the period between times t9 and t9.5 when digital pulse signal 454 has state S2. Parameter 456B transitions from parameter level PR3 to parameter level PR2 substantially at time t9.5 and remains at parameter level PR2 for the period between times t9.5 and t10 when digital pulse signal 454 has state S3. Parameter 456B transitions from parameter level PR2 to parameter level PR0.1 substantially at time t10 and remains at parameter level PR0.1 for the period between times t10 and t12 when digital pulse signal 454 has state S4. Parameter 456B transitions from parameter level PR0.1 to parameter level PR4 substantially at time t12.

[0174] In various embodiments, parameter 456A is set to a value substantially at time t3 or substantially at time t9, where parameter level The digital pulse signal 454 transitions from parameter level PR7 to another parameter level (e.g., between parameter levels PR3 and PR7) and remains at the transitioned parameter level during state S2. Also, the digital pulse signal 454 transitions from parameter level PR7 to parameter level PR8 at substantially time t3.5 or substantially time t9.5. level The digital pulse signal 454 transitions from PR0.1 to another parameter level (i.e., between parameter levels PR0.1 and PR5) and remains at the transitioned parameter level during state S3. The digital pulse signal 454 transitions from PR0.1 to PR5 at substantially time t4 or substantially time t10 ... level It transitions from PR3 to another parameter level (ie, between parameter levels PR0.1 and PR3, or to parameter level PR0) and remains at the transitioned parameter level during state S4.

[0175] In some embodiments, parameter 456B transitions from parameter PR4 to another parameter level (e.g., between parameter levels PR2 and PR4) substantially at time t3 or substantially at time t9, and digital pulse signal 454 remains at the transitioned parameter level during state S2. Also, parameter 456B transitions from parameter PR3 to another parameter level (i.e., between parameter levels PR0.1 and PR3) substantially at time t3.5 or substantially at time t9.5, and digital pulse signal 454 remains at the transitioned parameter level during state S3. Parameter 456B transitions from parameter PR2 to another parameter level (i.e., between parameter levels PR0.1 and PR2, or parameter level PR0) substantially at time t4 or substantially at time t10, and remains at the transitioned parameter level during state S4.

[0176] In some embodiments, the host computer processor modifies digital pulse signal 454 to change the duration of state S2 of digital pulse signal 454 and / or the duration of state S3 of digital pulse signal 454. For example, the host computer processor modifies digital pulse signal 454 so that the period of logic level 2 is longer or shorter than the period between times t3 and t3.5, and / or modifies digital pulse signal 454 so that the period of logic level 1 is longer or shorter than the period between times t3.5 and t4.

[0177] FIG. 4C illustrates one embodiment of graph 470 and one embodiment of graph 472. Graph 470 illustrates another digital pulse signal 474, and graph 472 illustrates a parameter 476A of RF signal 308B generated by bias generator 304 of FIGS. 3A and 3B and another parameter 476B of RF signal 308A generated by source generator 302 of FIGS. 3A and 3B. Graph 470 plots the logic level of digital pulse signal 474 versus time t. Digital pulse signal 474 is an example of digital pulse signal DPS2 of FIGS. 3A and 3B. Graph 472 plots parameters 476A and 476B versus time t. Parameter 476A is synchronized to clock signal 212 and digital pulse signal 474 of FIG. 4A. Similarly, parameter 476B is synchronized to clock signal 212 and digital pulse signal 474 of FIG. 4A.

[0178] Digital pulse signal 474 transitions from logic level 0 to logic level 3 at time t0 and remains at logic level 3 while state S1 occurs (i.e., the period between time t0 and time t3). Digital pulse signal 474 transitions from logic level 3 to logic level 2 at time t3 and remains at logic level 2 while state S2 occurs (i.e., the period between time t3 and t5). Digital pulse signal 474 transitions from logic level 2 to logic level 1 at time t5 and remains at logic level 1 while state S3 occurs (i.e., the period between time t5 and time t5.5). Digital pulse signal 474 transitions from logic level 1 to logic level 0 at time t5.5 and remains at logic level 0 while state S4 occurs (i.e., the period between time t5.5 and time t6).

[0179] Digital pulse signal 474 transitions from logic level 0 to logic level 3 at time t6 and remains at logic level 3 while state S1 reoccurs (i.e., the period between time t6 and time t9). Digital pulse signal 474 transitions from logic level 3 to logic level 2 at time t9 and remains at logic level 2 while state S2 reoccurs (i.e., the period between time t9 and time t11). Digital pulse signal 474 transitions from logic level 2 to logic level 1 at time t11 and remains at logic level 1 while state S3 reoccurs (i.e., the period between time t11 and time t11.5). Digital pulse signal 474 transitions from logic level 1 to logic level 0 at time t11.5 and remains at logic level 0 while state S4 reoccurs (i.e., the period between time t11.5 and time t12). Digital pulse signal 474 transitions from logic level 0 to logic level 3 at time t12.

[0180] During the time period between times t3 and t0, digital pulse signal 474 generates state S1; during the time period between times t3 and t5, digital pulse signal 474 generates state S2; during the time period between times t5 and t5.5, digital pulse signal 474 generates state S3; and during the time period between times t5.5 and t6, digital pulse signal 474 generates state S4. 474 Similarly, during the period between times t6 and t9, digital pulse signal 474 causes state S1 to occur again, during the period between times t9 and t11, digital pulse signal 474 causes state S2 to occur again, during the period between times t11 and t11.5, digital pulse signal 474 causes state S3 to occur again, and during the period between times t11.5 and t12, digital pulse signal 474 causes state S4 to occur again.

[0181] Parameter 476A is at parameter level PR6 during the time period between t0 and t3 when digital pulse signal 474 has state S1. Parameter 476A transitions from parameter level PR6 to parameter level PR0.1 substantially at time t3 and remains at parameter level PR0.1 during the time period between t3 and t5 when digital pulse signal 474 has state S2. Parameter 476A transitions from parameter level PR0.1 to parameter level PR5 substantially at time t5 and remains at parameter level PR5 during the time period between t5 and t5.5 when digital pulse signal 474 has state S3. Parameter 476A transitions from parameter level PR5 to parameter level PR3 substantially at time t5.5 and remains at parameter level PR3 during the time period between t5.5 and t6 when digital pulse signal 474 has state S4.

[0182] Parameter 476A transitions from parameter level PR3 to parameter level PR6 substantially at time t6 and remains at parameter level PR6 for the period between times t6 and t9 when digital pulse signal 474 has state S1. Parameter 476A transitions from parameter level PR6 to parameter level PR0.1 substantially at time t9 and remains at parameter level PR0.1 for the period between times t9 and t11 when digital pulse signal 474 has state S2. Parameter 476A transitions from parameter level PR0.1 to parameter level PR5 substantially at time t11 and remains at parameter level PR5 for the period between times t11 and t11.5 when digital pulse signal 474 has state S3. Parameter 476A transitions from parameter level PR5 to parameter level PR3 substantially at time t11.5 and remains at parameter level PR3 for the period between times t11.5 and t12 when digital pulse signal 474 has state S4. Parameter 476A transitions from parameter level PR3 to parameter level PR6 substantially at time t12.

[0183] Parameter 476B is at parameter level PR4 during the time period between t0 and t3 when digital pulse signal 474 has state S1. Parameter 476B transitions from parameter level PR4 to parameter level PR0.1 substantially at time t3, and remains at parameter level PR0.1 during the time period between t3 and t5 when digital pulse signal 474 has state S2. PR0.1 Parameter 476B transitions from parameter level PR0.1 to parameter level PR3.5 substantially at time t5 and remains at parameter level PR3.5 for the period between times t5 and t5.5 when digital pulse signal 474 has state S3. Parameter 476B transitions from parameter level PR3.5 to parameter level PR2 substantially at time t5.5 and remains at parameter level PR2 for the period between times t5.5 and t6 when digital pulse signal 474 has state S4.

[0184] Parameter 476B transitions from parameter level PR2 to parameter level PR4 substantially at time t6 and remains at parameter level PR4 for the period between times t6 and t9 when digital pulse signal 474 has state S1. Parameter 476B transitions from parameter level PR4 to parameter level PR0.1 substantially at time t9 and remains at parameter level PR0.1 for the period between times t9 and t11 when digital pulse signal 474 has state S2. Parameter 476B transitions from parameter level PR0.1 to parameter level PR3.5 substantially at time t11 and remains at parameter level PR3.5 for the period between times t11 and t11.5 when digital pulse signal 474 has state S3. Parameter 476B transitions from parameter level PR3.5 to parameter level PR2 substantially at time t11.5 and remains at parameter level PR2 for the period between times t11.5 and t12 when digital pulse signal 474 has state S4. Parameter 476B transitions from parameter level PR2 to parameter level PR4 substantially at time t12.

[0185] In various embodiments, parameter 476A transitions from parameter PR6 to another parameter level (e.g., between parameter levels PR0.1 and PR3, or at parameter level PR0) substantially at time t3 or substantially at time t9 and remains at the transitioned parameter level during state S2. Also, parameter 476A transitions from parameter level PR0.1 to another parameter level (i.e., between parameter levels PR3 and PR6) substantially at time t5 or substantially at time t11 and remains at the transitioned parameter level during state S3. Parameter 476A transitions from parameter level PR5 to another parameter level (i.e., between parameter levels PR0.1 and PR5) substantially at time t5.5 or substantially at time t11.5 and remains at the transitioned parameter level during state S4.

[0186] In some embodiments, parameter 476B transitions from parameter PR4 to another parameter level (e.g., between parameter levels PR0.1 and PR2) substantially at time t3 or substantially at time t9 and remains at the transitioned parameter level during state S2. Also, parameter 476B transitions from parameter level PR0.1 to another parameter level (i.e., between parameter levels PR2 and PR4) substantially at time t5 or substantially at time t11 and remains at the transitioned parameter level during state S3. Parameter 476B transitions from parameter level PR3.5 to another parameter level (i.e., between parameter levels PR0.1 and PR3.5) substantially at time t5.5 or substantially at time t11.5 and remains at the transitioned parameter level during state S4.

[0187] In some embodiments, the host computer processor modifies digital pulse signal 474 to change the duration of state S2 of digital pulse signal 474 and / or the duration of state S3 of digital pulse signal 474. For example, the host computer processor modifies digital pulse signal 474 so that the period of logic level 2 is longer or shorter than the period between times t3 and t5, and / or modifies digital pulse signal 474 so that the period of logic level 1 is longer or shorter than the period between times t5 and t5.5.

[0188] Figure 5A is one embodiment of a substrate 500 that is processed by applying a two-state pulse. 500 is an example of the substrate S in FIGS. 1A, 1B, 3A, and 3B. 500 includes a portion 504A of the substrate layer and another portion 504B of the substrate layer. 500 The mask layer further includes a mask layer portion 502 A and a mask layer portion 502 B. The mask layer is laminated on top of the substrate layer.

[0189] In the two-state pulse, sputtering of the mask layer occurs during the first state, depositing mask layer material on portions 502A and 502B and reducing the width of the neck between the vertical layers of portions 502A and 502B. This deposition of mask layer material on the mask layer is sometimes referred to herein as passivation. In FIG. 5A , the mask layer material is shown as a circle. Because of the reduced neck width, when plasma ions from the plasma in plasma chamber 110 are used to etch substrate 500 during the first state, a bow is formed in the vertical layers of portions 504A and 504B of the substrate layer.

[0190] 5B illustrates an embodiment of a substrate 500 being processed using a two-state pulse in which a deposition material (such as copper or another metal, or an oxide) is deposited on a mask layer during the second state. The deposition material deposited on the mask layer is indicated by an x ​​on portions 502A and 502B.

[0191] FIG. 5C is an embodiment of a substrate 500 illustrating the effect of State S1 of digital pulse signal DPS1 on substrate 500. While digital pulse signal DPS1 or DPS2 is in State S1, a substrate layer is etched by applying RF signals 116A and 116B of FIGS. 1A and 1B. For example, a high aspect ratio etch is performed during State S1 of digital pulse signal DPS1. The high aspect ratio etch of substrate 500 performed during State S1 is an example of a dielectric etch operation. During etching of the substrate layer, sputtering and deposition of mask layer particles occurs on the top of the mask layer, reducing the width of the neck between portions 502A and 502B. However, compared to the first state of the two-state pulse, State S1 of digital pulse signal DPS1 occurs for a shorter period of time, resulting in a smaller amount of mask layer particles being deposited on the mask layer.

[0192] FIG. 5D illustrates an embodiment of a substrate 500 illustrating the effect of state S2 of the digital pulse signal DPS1 on the substrate 500. While the digital pulse signal DPS1 is in state S2, or while the digital pulse signal DPS2 is in states S2 and S3, particles of the mask layer deposited on the mask layer are sputtered downward by the plasma in the plasma chamber 110. For example, particles of the mask layer deposited on top of the mask layer are sputtered downward toward the substrate layer, enlarging the critical dimension of the neck of the mask layer and promoting increased neutral passivation at the location of curvature in the substrate layer. The increased critical dimension of the neck increases the likelihood of vertical etching of the substrate layer and decreases the likelihood of lateral etching. The increased neutral passivation at the location of curvature reduces the likelihood of curvature forming in the substrate layer due to lateral etching. Illustratively, when the three-state or four-state pulse described herein is applied to process the substrate 500, curvature in the substrate layer is reduced by 10% to 20% compared to when a two-state pulse is applied. The reduced curvature helps achieve a vertical profile in the substrate layer. As a result, there is minimal or no curvature of the substrate layer.

[0193] 5E is an embodiment of a substrate 500 illustrating the effect of State S3 of the digital pulse signal DPS1 on the substrate 500. While the digital pulse signal DPS1 is in State S3, particles of deposition material are deposited on the mask layer. For example, while the digital pulse signal DPS1 is in State S3, direct ion deposition occurs on the mask layer, reducing sputter redeposition of mask layer material at the neck of the mask layer. The deposition of particles of deposition material during State S3 is an example of a deposition operation.

[0194] While digital pulse signal DPS1 is in state S2, or while digital pulse signal DPS2 is in states S2 and S3, particles from the mask layer are sputtered downward from the mask layer to the substrate layer, widening the neck of the mask layer and increasing the etch rate and selectivity of the substrate layer during state S1. The increased etch rate facilitates achieving high aspect ratio dielectric etches.

[0195] 6 is one embodiment of a graph 600 illustrating plots 602 and 604 of the maximum (max) critical dimension (CD) of the curvature of a substrate layer versus the minimum (min) critical dimension of the curvature. Each critical dimension is measured in nanometers (nm). Plot 602 plots the maximum CD on the y-axis versus the minimum CD on the x-axis when a two-state pulse is applied to the plasma chamber 110 of FIGS. 1A, 1B, 3A, and 3B. Furthermore, plot 604 plots the maximum CD on the y-axis versus the minimum CD on the x-axis when a two-state pulse is applied to the plasma chamber 110 of FIGS. 1A, 1B, 3A, and 3B. 604 1 plots the maximum CD on the y-axis against the minimum CD on the x-axis when a multi-state pulse (such as a three-state pulse or a four-state pulse) is applied to the plasma chamber 110. Along the x-axis are numbers X', X'+2, X'+4, X'+6, and X'+8. Note that X', as used herein, is a real number greater than or equal to 0. Also along the y-axis are numbers X'+11, X'+12, X'+13, X'+14, X'+15, and X'+16.

[0196] For three-state pulsing, RF signals 116A and 116B of FIGS. 1A and 1B are generated and provided. Additionally, for four-state pulsing, RF signals 308A and 308B of FIGS. 3A and 3B are generated and provided. Note that applying multi-state pulsing increases the minimum CD for the same amount of maximum CD, and decreases the maximum CD for the same amount of minimum CD. The critical dimension of the curvature of the substrate layer described herein is the width of the curvature of the substrate layer (e.g., the width between the curvature of substrate portion 504A and the curvature of substrate portion 504B in FIGS. 5C-5E). Similarly, the critical dimension of the mask layer described herein is the width of the mask layer (e.g., the width between the curvature of substrate portion 504A and the curvature of substrate portion 504B in FIGS. 5C-5E). Section minute 502A and department The width between minutes 502B.

[0197] Additionally, the parameter level of RF signal 116A while digital pulse signal DPS1 is in state S2 and / or the parameter level of RF signal 116B while digital pulse signal DPS1 is in state S2 are adjusted (e.g., increased or decreased) to move plot 604 further vertically down along the y-axis of graph 600, moving plot 604 closer to the target region. The parameter level of RF signal 116A and / or the parameter level of RF signal 116B are adjusted by the host computer processor. The host computer processor sends the parameter level adjustments, such as increasing or decreasing the parameter level PR3 of parameter 208A of FIG. 2A, increasing or decreasing the parameter level PR2 of parameter 208B of FIG. 2A, increasing or decreasing the parameter level PR0.1 of parameter 256A of FIG. 2B, increasing or decreasing the parameter level PR0.1 of parameter 256B of FIG. 2B, or the adjusted parameter levels, to the digital signal processors of source generator 102 and bias generator 104 of FIGS. 1A and 1B, which adjust the parameter levels.

[0198] Also, for a four-state pulse, the parameter levels of RF signal 308A while digital pulse signal DPS2 is in state S2, the parameter levels of RF signal 308B while digital pulse signal DPS2 is in state S2, the parameter levels of RF signal 308A while digital pulse signal DPS2 is in state S3, and / or the parameter levels of RF signal 308B while digital pulse signal DPS2 is in state S3 are adjusted (e.g., increased or decreased) to move plot 604 further vertically down along the y-axis of graph 600, closer to the target region. The parameter levels of RF signal 308A and / or the parameter levels of RF signal 308B are adjusted by the host computer processor. The processor of the host computer sends the parameter level adjustments, such as increasing or decreasing the parameter level PR5.5 of parameter 408A of FIG. 4A, increasing or decreasing the parameter level PR3.5 of parameter 408B of FIG. 4A, increasing or decreasing the parameter level PR0.1 of parameter 408A of FIG. 4A, increasing or decreasing the parameter level PR0.1 of parameter 408B of FIG. 4A, or the adjusted parameter levels, to the digital signal processors of source generator 302 and bias generator 304 of FIGS. 3A and 3B, which adjust the parameter levels.

[0199] Other examples of parameter level adjustments include increasing or decreasing parameter level PR5 of parameter 456A in FIG. 4B, increasing or decreasing parameter level PR3 of parameter 456A, increasing or decreasing parameter level PR3 of parameter 456B, increasing or decreasing parameter level PR2 of parameter 456B, Figure 4C These include an increase or decrease in parameter level PR0.1 of parameter 476A, an increase or decrease in parameter level PR5 of parameter 476A, an increase or decrease in parameter level PR4 of parameter 476A, an increase or decrease in parameter level PR0.1 of parameter 476B, and an increase or decrease in parameter level PR3.5 of parameter 476B.

[0200] 7A is one embodiment of a graph 700 illustrating a plot 702 showing the relationship between post-etch inspection (AEI) curvature CD plotted on the x-axis and unopened defects plotted on the y-axis. Graph 700 also includes a plot 704. Plot 702 is generated when a two-state pulse is applied, and plot 704 is generated when a multi-state pulse is applied. An example of an unopened defect described herein is a large number of channels (e.g., holes) formed in a substrate S that reach the bottom of the substrate layer. For the same amount of holes reaching the bottom of the substrate layer, applying a multi-state pulse reduces the critical dimension of the curvature of the substrate layer after performing an etching operation on the substrate S.

[0201] 7B is an embodiment of a graph 706 illustrating a plot 708 showing the relationship between the post-develop inspection (ADI) curvature CD plotted on the x-axis and the unopened defects plotted on the y-axis. The ADI inspection is an inspection performed before applying an etch operation to the substrate S. Graph 706 also includes a plot 710. Plot 708 is generated when a two-state pulse is applied, and plot 710 is generated when a multi-state pulse is applied. As shown in graph 706, for the same amount of holes reaching the bottom of the substrate layer, applying a multi-state pulse reduces the critical dimension of the curvature of the substrate layer before performing an etch operation on the substrate S.

[0202] 7C is one embodiment of a graph 712 illustrating a plot 714 showing the relationship between etch selectivity (sel) plotted on the x-axis and unopened defects plotted on the y-axis. The etch selectivity is the selectivity of a substrate layer compared to a mask layer. Graph 712 also includes a plot 716. Plot 714 is generated when a two-state pulse is applied to the substrate S, and plot 716 is generated when a multi-state pulse is applied to the substrate S. As shown in graph 712, when the amount of holes reaching the bottom of the substrate layer is the same, applying a multi-state pulse results in a higher etch selectivity to the substrate layer.

[0203] FIG. 7D is one embodiment of a graph 718 illustrating a plot 720 showing the relationship between aspect ratio and differential etch rate plotted on the y-axis. The aspect ratio is the ratio of the etch depth of a substrate layer to the critical dimension of the curvature of the substrate layer. The aspect ratio is plotted on the x-axis. The differential etch rate is the etch rate of a substrate layer at a particular level of depth of the substrate layer. Graph 718 also includes plot 722. Plot 720 is generated when a two-state pulse is applied, and plot 722 is generated when a multi-state pulse is applied. As shown in graph 718, applying a multi-state pulse results in a higher aspect ratio for the same differential etch rate.

[0204] The embodiments described herein may be practiced with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0205] In some embodiments, the controller is part of a system, and such a system may be part of the examples described above. A system includes semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling system operation before, during, and after semiconductor wafer or substrate processing. Such electronics are referred to as a "controller" and may control various components or subcomponents of the system. The controller is programmed to control any of the processes disclosed herein, depending on the processing requirements and / or type of system. Such processes include process gas supply, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and motion settings, wafer transfer to and from the tool, and wafer transfer to and from other transfer tools and / or load locks coupled or interfaced with the system.

[0206] Broadly, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, coefficients, variables, etc. for performing a particular process on or for a semiconductor wafer or system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0207] The controller, in some embodiments, is part of, coupled to, or a combination of a computer that is integrated with, coupled to, or otherwise networked to the system. For example, the controller may be in the "cloud" or all or part of a fab host computer, thereby enabling remote access of wafer processing. The computer provides remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set up processing steps following the current process, or initiate a new process.

[0208] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a network. Such a network includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters, coefficients, and / or variables for each processing step to be performed during one or more operations. It should be understood that the parameters, coefficients, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more individual controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein). One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0209] In various embodiments, exemplary systems to which the method is applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0210] It is further noted that in some embodiments, the above-described operations apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, and electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a flat coil, and the like.

[0211] As described above, depending on the one or more process steps being performed by the tool, the host computer communicates with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in the semiconductor fabrication factory.

[0212] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0213] Some of the embodiments also relate to hardware units or apparatus for performing these operations. The apparatus is specially constructed for use as a special purpose computer. When defined as a special purpose computer, the computer is operable for its dedicated purpose, while also performing other processes, program execution, or routines that are not part of its dedicated purpose.

[0214] In some embodiments, operations may be processed by a computer selectively activated or configured by one or more computer programs stored in computer memory, cache, or obtained over a computer network. If data is obtained over a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computational resources).

[0215] One or more embodiments may also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit (e.g., a memory device, etc.) that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a computer-readable tangible medium distributed over network-coupled computer systems so that the computer-readable code is stored and executed in a distributed manner.

[0216] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between each operation, or each method operation is coordinated to occur at slightly different times, or is distributed across a system that allows each method operation to occur at various intervals, or is performed in an order other than that set forth above.

[0217] It is further noted that in one embodiment, one or more features of any of the above-described embodiments may be combined with one or more features of any of the other embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0218] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments should not be limited to the details set forth herein. The present disclosure may be realized in the following forms. [Form 1] 1. A method of processing a dielectric etch operation in a capacitively coupled plasma (CCP) chamber, the CCP chamber having a first electrode and a second electrode, the CCP chamber coupled to an impedance matching circuit, the method comprising: providing a bias radio frequency (RF) signal to the impedance matching circuit, the bias RF signal comprising a first plurality of parameter levels during a repeating period, the first plurality of parameter levels comprising a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state; providing a source RF signal to the impedance matching circuit to deliver a second plurality of parameter levels during the repeating period, the second plurality of parameter levels including a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state; Including, the bias RF signal and the source RF signal are used to control the dielectric etch operation in the CCP chamber; the first, second, and third parameter levels of the bias RF signal are different from one another; the first, second, and third parameter levels of the source RF signal are different from one another; method. [Form 2] 2. The method of claim 1, The impedance matching circuit includes a bias impedance matching circuit and a source impedance matching circuit, and the method includes: receiving the source RF signal using the source impedance match circuit and providing an output to the first electrode; receiving the bias RF signal using the bias impedance matching circuit and providing an output to the second electrode; The method further comprises: [Form 3] 3. The method of claim 2, further comprising: The method, wherein the first electrode is a top electrode and the second electrode is a substrate support electrode. [Form 4] 2. The method of claim 1, The method further comprising using the impedance matching circuit to provide an output based on the bias RF signal and the source RF signal. [Form 5] 5. The method of claim 4, The method further comprising providing the output from the impedance matching circuit to the first electrode. [Form 6] 6. The method of claim 5, The method wherein the first electrode is a substrate support electrode. [Form 7] 6. The method of claim 5, The method wherein the first electrode is a top electrode. [Form 8] 2. The method of claim 1, wherein the second parameter level of the bias RF signal and source RF signal during the second state is set lower than the first parameter level of the bias RF signal and source RF signal during the first state and higher than the third parameter level of the bias RF signal and source RF signal during the third state. [Form 9] 2. The method of claim 1, wherein the third parameter level of the bias RF signal and source RF signal during the third state is set lower than the first parameter level of the bias RF signal and source RF signal during the first state and higher than the second parameter level of the bias RF signal and source RF signal during the second state. [Form 10] 2. The method of claim 1, the second parameter level of the source RF signal is maintained during the second state, and the second parameter level of the bias RF signal is maintained during the second state. [Form 11] 2. The method of claim 1, The method, wherein the second parameter levels of the bias RF signal and the source RF signal are maintained for up to 30 percent of the repetition period. [Form 12] 2. The method of claim 1, the second parameter level at which the source RF signal is maintained during the second state; and the second parameter level at which the bias RF signal is maintained during the second state. [Form 13] 2. The method of claim 1, The method wherein the dielectric etch operation is performed during the first state and the deposition operation is performed during the third state. [Form 14] 2. The method of claim 1, the first plurality of parameter levels includes a fourth parameter level, providing the first plurality of parameter levels includes providing the fourth parameter level of the bias RF signal during a fourth state, the second plurality of parameter levels includes the fourth parameter level, providing the second plurality of parameter levels includes providing the fourth parameter level of the source RF signal during the fourth state, the fourth parameter level of the bias RF signal being different from each of the first, second, and third parameter levels of the bias RF signal, and the fourth parameter level of the source RF signal being different from each of the first, second, and third parameter levels of the source RF signal. [Form 15] a plasma chamber having a first electrode and a second electrode; an impedance matching circuit coupled to the plasma chamber; a bias radio frequency (RF) generator coupled to the impedance matching circuit, the bias RF generator configured to provide a bias radio frequency (RF) signal to the impedance matching circuit, the bias RF signal including a first plurality of parameter levels during a repeating period, the first plurality of parameter levels including a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state; a source RF generator coupled to the impedance matching circuit, the source RF generator configured to provide a source RF signal to the impedance matching circuit, the source RF signal including a second plurality of parameter levels during the repeating period, the second plurality of parameter levels including a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state; Equipped with the first, second, and third parameter levels of the bias RF signal are different from one another; the first, second, and third parameter levels of the source RF signal are different from one another; system. [Form 16] 16. The system according to claim 15, the impedance matching circuit includes a bias impedance matching circuit and a source impedance matching circuit, the source impedance matching circuit configured to receive the source RF signal and provide an output to the first electrode, and the bias impedance matching circuit configured to receive the bias RF signal and provide an output to the second electrode. [Form 17] 17. The system according to claim 16, The system wherein the first electrode is a top electrode and the second electrode is a substrate support electrode. [Form 18] 16. The system according to claim 15, The system, wherein the impedance matching circuit is configured to provide an output based on the bias RF signal and the source RF signal. [Form 19] 19. The system according to claim 18, The output from the impedance matching circuit is provided to the first electrode. [Form 20] 20. The system according to claim 19, The system wherein the first electrode is a substrate support electrode. [Form 21] 20. The system according to claim 19, The system wherein the first electrode is a top electrode. [Form 22] 16. The system according to claim 15, the source RF generator is configured to set the second parameter level of the source RF signal during the second state lower than the first parameter level of the source RF signal during the first state and higher than the third parameter level of the source RF signal during the third state, and the bias RF generator is configured to set the second parameter level of the bias RF signal during the second state lower than the first parameter level of the bias RF signal during the first state and higher than the third parameter level of the bias RF signal during the third state. [Form 23] 16. The system according to claim 15, the source RF generator is configured to set the third parameter level of the source RF signal during the third state lower than the first parameter level of the source RF signal during the first state and higher than the second parameter level of the source RF signal during the second state, and the bias RF generator is configured to set the third parameter level of the bias RF signal during the third state lower than the first parameter level of the bias RF signal during the first state and higher than the second parameter level of the bias RF signal during the second state. [Form 24] 16. The system according to claim 15, the source RF generator is configured to vary a duration for which the second parameter level of the source RF signal is maintained during the second state, and the bias RF generator is configured to vary a duration for which the second parameter level of the bias RF signal is maintained during the second state. [Form 25] 16. The system according to claim 15, the source RF generator is configured to vary the second parameter level at which the source RF signal is maintained during the second state, and the bias RF generator is configured to vary the second parameter level at which the bias RF signal is maintained during the second state. [Form 26] 16. The system according to claim 15, The system wherein an etching operation is performed during the first state and a deposition operation is performed during the third state.

Claims

1. 1. A method of conducting an etching operation in a plasma chamber having a first electrode and a second electrode, comprising: generating a first radio frequency (RF) signal; providing the first RF signal to a first impedance matching circuit coupled to the first electrode, the first RF signal comprising a first plurality of parameter levels during a repeating period, the first plurality of parameter levels comprising a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state; generating a second RF signal; providing the second RF signal to a second impedance matching circuit coupled to the second electrode, the second RF signal including a second plurality of parameter levels during the repeating period, the second plurality of parameter levels including a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state; Including, the first, second, and third parameter levels of the first RF signal are different from one another; the first, second, and third parameter levels of the second RF signal are different from one another; the first RF signal and the second RF signal are used to control the etching operation in the plasma chamber; The method wherein the etching operation is performed during the first state and the deposition operation is performed during the third state.

2. 10. The method of claim 1, The method, wherein the first electrode is a top electrode of the plasma chamber and the second electrode is a bottom electrode of the plasma chamber.

3. 10. The method of claim 1, the second parameter level of the first RF signal is lower than the first parameter level of the first RF signal, the third parameter level of the first RF signal is lower than the second parameter level of the first RF signal, the second parameter level of the second RF signal is lower than the first parameter level of the second RF signal, and the third parameter level of the second RF signal is lower than the second parameter level of the second RF signal.

4. 10. The method of claim 1, the first, second, and third parameter levels of the first RF signal occur during the repeating period of a clock signal, and the first, second, and third parameter levels of the second RF signal occur during the repeating period of the clock signal.

5. 10. The method of claim 1, the second parameter level of the first RF signal is lower than the first parameter level of the first RF signal, the third parameter level of the first RF signal is higher than the second parameter level of the first RF signal and lower than the first parameter level of the first RF signal, the second parameter level of the second RF signal is lower than the first parameter level of the second RF signal, and the third parameter level of the second RF signal is higher than the second parameter level of the second RF signal and lower than the first parameter level of the second RF signal.

6. 6. The method of claim 5, The method, wherein the second parameter level of the first RF signal is equal to the second parameter level of the second RF signal.

7. 10. The method of claim 1, The method, wherein the first plurality of parameter levels are voltage levels and the second plurality of parameter levels are voltage levels.

8. 10. The method of claim 1, A method, wherein the first plurality of parameter levels are power levels and the second plurality of parameter levels are power levels.

9. 1. A controller for processing an etching operation in a plasma chamber having a first electrode and a second electrode, comprising:

1. A processor, comprising: configured to control a first radio frequency (RF) generator to generate a first RF signal and provide the first RF signal to a first impedance matching circuit, the first impedance matching circuit coupled to the first electrode, the first RF signal comprising a first plurality of parameter levels during a repetitive period, the first plurality of parameter levels comprising a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state; a processor configured to control a second RF generator to generate a second RF signal and provide the second RF signal to a second impedance matching circuit, the second impedance matching circuit coupled to the second electrode, the second RF signal including a second plurality of parameter levels during the repeating period, the second plurality of parameter levels including a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state; a memory device coupled to the processor; the first, second, and third parameter levels of the first RF signal are different from one another; the first, second, and third parameter levels of the second RF signal are different from one another; the first RF signal and the second RF signal are used to control the etching operation in the plasma chamber; The controller wherein the etching operation is performed during the first state and the deposition operation is performed during the third state.

10. 10. The controller of claim 9, The first electrode is a top electrode of the plasma chamber and the second electrode is a bottom electrode of the plasma chamber.

11. 10. The controller of claim 9, the second parameter level of the first RF signal is lower than the first parameter level of the first RF signal, the third parameter level of the first RF signal is lower than the second parameter level of the first RF signal, the second parameter level of the second RF signal is lower than the first parameter level of the second RF signal, and the third parameter level of the second RF signal is lower than the second parameter level of the second RF signal.

12. 10. The controller of claim 9, the first, second, and third parameter levels of the first RF signal occur during the repeating period of a clock signal, and the first, second, and third parameter levels of the second RF signal occur during the repeating period of the clock signal.

13. 10. The controller of claim 9, the second parameter level of the first RF signal is lower than the first parameter level of the first RF signal, the third parameter level of the first RF signal is higher than the second parameter level of the first RF signal and lower than the first parameter level of the first RF signal, the second parameter level of the second RF signal is lower than the first parameter level of the second RF signal, and the third parameter level of the second RF signal is higher than the second parameter level of the second RF signal and lower than the first parameter level of the second RF signal.

14. 14. The controller of claim 13, The second parameter level of the first RF signal is equal to the second parameter level of the second RF signal.

15. 10. The controller of claim 9, The first plurality of parameter levels are voltage levels and the second plurality of parameter levels are voltage levels.

16. 10. The controller of claim 9, The first plurality of parameter levels are power levels and the second plurality of parameter levels are power levels.

17. 1. A plasma system for processing an etching operation in a plasma chamber having a first electrode and a second electrode, comprising: a first radio frequency (RF) generator configured to generate a first RF signal, the first RF signal including a first plurality of parameter levels during a repeating period, the first plurality of parameter levels including a first parameter level during a first state, a second parameter level during a second state, and a third parameter level during a third state, the first, second, and third parameter levels of the first RF signal being different from one another; a first impedance matching circuit coupled to the first RF generator and the first electrode, the first impedance matching circuit configured to receive the first RF signal and output a first modified RF signal to the first electrode; a second RF generator configured to generate a second RF signal, the second RF signal including a second plurality of parameter levels during the repeating period, the second plurality of parameter levels including a first parameter level during the first state, a second parameter level during the second state, and a third parameter level during the third state, the first, second, and third parameter levels of the second RF signal being different from one another; a second impedance matching circuit coupled to the second RF generator and the second electrode, the second impedance matching circuit configured to receive the second RF signal and output a second modified RF signal to the second electrode; the first RF signal and the second RF signal are used to control the etching operation in the plasma chamber; The plasma system wherein the etching operation is performed during the first state and the deposition operation is performed during the third state.

18. 18. The plasma system of claim 17, The plasma system, wherein the first electrode is a top electrode of the plasma chamber and the second electrode is a bottom electrode of the plasma chamber.

19. 18. The plasma system of claim 17, the second parameter level of the first RF signal is lower than the first parameter level of the first RF signal, the third parameter level of the first RF signal is lower than the second parameter level of the first RF signal, the second parameter level of the second RF signal is lower than the first parameter level of the second RF signal, and the third parameter level of the second RF signal is lower than the second parameter level of the second RF signal.

20. 18. The plasma system of claim 17, the first, second, and third parameter levels of the first RF signal occur during the repeating period of a clock signal, and the first, second, and third parameter levels of the second RF signal occur during the repeating period of the clock signal.

21. 18. The plasma system of claim 17, the second parameter level of the first RF signal is lower than the first parameter level of the first RF signal, the third parameter level of the first RF signal is higher than the second parameter level of the first RF signal and lower than the first parameter level of the first RF signal, the second parameter level of the second RF signal is lower than the first parameter level of the second RF signal, and the third parameter level of the second RF signal is higher than the second parameter level of the second RF signal and lower than the first parameter level of the second RF signal.

22. 22. The plasma system of claim 21, The plasma system, wherein the second parameter level of the first RF signal is equal to the second parameter level of the second RF signal.

23. 18. The plasma system of claim 17, The plasma system, wherein the first plurality of parameter levels are voltage levels and the second plurality of parameter levels are voltage levels.

24. 18. The plasma system of claim 17, A plasma system, wherein the first plurality of parameter levels are power levels and the second plurality of parameter levels are power levels.

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