Decoders for Analog Neural Memories in Deep Learning Artificial Neural Networks

Abstract

To provide a word line driver, a bit line decoder circuit, a current-voltage circuit, and an analog neuromorphic memory system used in a vector matrix multiplication (VMM) array in an artificial neural network.SOLUTION: In a VMM array, a word line driver 2000 has a plurality of select transistors 2002, each of which has a first terminal, a second terminal, and a gate, in which each gate is coupled to a common control line 2001, each first terminal is coupled to a different word line WL0 to WL3,..., and each second terminal is coupled to one or more bias transistors 2003 and 2004. A bias transistor coupled to each of the plurality of select transistors provides a bias voltage to a single select transistor or to all of the select transistors.SELECTED DRAWING: Figure 20

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 642,884, filed March 14, 2018, entitled "Decoders for Analog Neuromorphic Memory in Artificial Neural Network," and U.S. Patent Application No. 15 / 991,890, filed May 29, 2018, entitled "Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network."

[0002] FIELD OF THE INVENTION Numerous embodiments of a decoder for use with vector matrix multiplication (VMM) arrays in artificial neural networks are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain), which can rely on a large number of inputs and are used to estimate or approximate functions that are largely unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 illustrates an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the neural network's output. At each level, neurons make decisions, individually or collectively, based on the data received from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons and therefore a very high degree of computational parallelism. In principle, such complexity could be achieved by digital supercomputers or specialized graphics processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses are too bulky for the large number of neurons and synapses required.

[0006] The applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0007] Each non-volatile memory cell used in an analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge in its floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, and 64.

[0008] Prior art decoding circuits (such as bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders) are not suitable for use with VMMs in analog neuromorphic memory systems. One reason for this is that in VMM systems, the program and verify portion of the verify operation (which is a read operation) operates on a single selected memory cell, while the read operation operates on all memory cells in the array.

[0009] What is needed is an improved decoding circuit suitable for use with a VMM in an analog neuromorphic memory system. Summary of the Invention

[0010] A number of embodiments are disclosed for use with vector matrix multiplication (VMM) arrays in artificial neural networks.

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[0054] [Brief explanation of the drawings]

[0055] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 is a cross-sectional view of a conventional two-gate nonvolatile memory cell. [Figure 3] 1 is a cross-sectional view of a conventional four-gate nonvolatile memory cell. [Figure 4] 1 is a side cross-sectional view of a conventional three-gate nonvolatile memory cell. [Figure 5] FIG. 2 is a cross-sectional view of another conventional two-gate nonvolatile memory cell. [Figure 6] FIG. 1 illustrates an exemplary artificial neural network at different levels utilizing a non-volatile memory array. [Figure 7] FIG. 2 is a block diagram illustrating a vector multiplier matrix. [Figure 8] FIG. 2 is a block diagram illustrating various levels of a vector multiplier matrix. [Figure 9] 1 illustrates one embodiment of a vector multiplier matrix. [Figure 10] 10 illustrates another embodiment of a vector multiplier matrix. [Figure 11] 10 illustrates another embodiment of a vector multiplier matrix. [Figure 12] 10 illustrates another embodiment of a vector multiplier matrix. [Figure 13] 10 illustrates another embodiment of a vector multiplier matrix. [Figure 14] 1 illustrates one embodiment of a bit line decoder for a vector multiplier matrix. [Figure 15] 10 illustrates another embodiment of a bit line decoder for a vector multiplier matrix. [Figure 16] 10 illustrates another embodiment of a bit line decoder for a vector multiplier matrix. [Figure 17] 1 shows a system for operating a vector multiplier matrix. [Figure 18] 1 illustrates another system for operating a vector multiplier matrix. [Figure 19] 1 illustrates another system for operating a vector multiplier matrix. [Figure 20] 1 illustrates one embodiment of a word line driver for use with a vector multiplier matrix. [Figure 21] 10 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 22] 10 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 23] 10 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 24] 10 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 25] 10 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 26] 10 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 27]1 shows a source line decoder circuit for use with a vector multiplier matrix. [Figure 28] 1 shows a word line decoder circuit, a source line decoder circuit, and a high voltage level shifter for use with a vector multiplier matrix. [Figure 29] 1 shows an erase gate decoder circuit, a control gate decoder circuit, a source line decoder circuit, and a high voltage level shifter for use with a vector multiplier matrix. [Figure 30] 1 illustrates a word line decoder circuit for use with a vector multiplier matrix. [Figure 31] 1 shows a control gate decoder circuit for use with a vector multiplier matrix. [Figure 32] 10 illustrates another control gate decoder circuit for use with a vector multiplier matrix. [Figure 33] 10 illustrates another control gate decoder circuit for use with a vector multiplier matrix. [Figure 34] 1 shows a current-voltage circuit for controlling word lines in a vector multiplier matrix. [Figure 35] 10 shows another current-voltage circuit for controlling word lines in a vector multiplier matrix. [Figure 36] 1 shows a current-voltage circuit for controlling the control gate lines in a vector multiplier matrix. [Figure 37] 10 shows another current-voltage circuit for controlling the control gate lines in a vector multiplier matrix. [Figure 38] 10 shows another current-voltage circuit for controlling the control gate lines in a vector multiplier matrix. [Figure 39] 10 shows another current-voltage circuit for controlling word lines in a vector multiplier matrix. [Figure 40] 10 shows another current-voltage circuit for controlling word lines in a vector multiplier matrix. [Figure 41]10 shows another current-voltage circuit for controlling word lines in a vector multiplier matrix. [Figure 42] 10 shows the operating voltages of the vector multiplier matrix of FIG. [Figure 43] 11 shows the operating voltages of the vector multiplier matrix of FIG. [Figure 44] 12 shows the operating voltages of the vector multiplier matrix of FIG. [Figure 45] 13 shows the operating voltages of the vector multiplier matrix of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0056] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. Nonvolatile Memory Cell

[0057] Digital nonvolatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent") discloses an array of split-gate nonvolatile memory cells and is incorporated herein by reference for all purposes. Such a memory cell is shown in FIG. 2. Each memory cell 210 is formed in a semiconductor substrate 12 and includes a source region 14 and a drain region 16 having a channel region 18 therebetween. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is also formed above a portion of the source region 16. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending above and above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0058] The memory cell 210 is erased (where electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, thereby causing electrons in the floating gate 20 to tunnel through the intermediate insulator from the floating gate 20 to the word line terminal 22 by Fowler-Nordheim tunneling.

[0059] The memory cell 210 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source 16 (where electrons are applied to the floating gate). An electron current will flow from the source 16 towards the drain 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, they accelerate and heat up. Some of the heated electrons are injected into the floating gate 20 through the gate oxide 26 due to electrostatic attraction from the floating gate 20.

[0060] The memory cell 210 is read by applying a positive read voltage to the drain 14 and word line terminal 22 (turning on the channel region under the word line terminal). If the floating gate 20 is positively charged (i.e., erased of electrons and positively coupled to the drain 16), then the portion of the channel region under the floating gate 20 will also be turned on and current will flow through the channel region 18, which is sensed as an erased or "1" state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region under the floating gate 20 will be mostly or completely off and no (or only a small) current will flow through the channel region 18, which is sensed as a programmed or "0" state.

[0061] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1]

[0062] Other split-gate memory cell configurations are known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a select gate 28 (typically coupled to a word line) above a second portion of the channel region 18, a control gate 22 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is indicated by heated electrons from the channel region 18 injecting themselves into the floating gate 20. Erasing is indicated by electrons tunneling from the floating gate 20 to the erase gate 30.

[0063] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0064] Figure 4 shows a split-gate tri-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase operations (erase through the erase gate) and read operations are similar to those of Figure 3, except there is no control gate bias. Programming operations are also performed without a control gate bias, so the program voltage on the source line is higher to compensate for the lack of control gate bias.

[0065] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0066] Figure 5 shows a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the channel region 18 and the control gate 22 extends over the floating gate 20 separated by an insulating layer. Erase, programming, and read operations operate in a similar manner as described above for memory cell 210.

[0067] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0068] To utilize a memory array containing one of the types of non-volatile memory cells in an artificial neural network, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, continuous (analog) programming of the memory cells is provided.

[0069] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state independently and continuously with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully programmed state to a fully erased state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage is analog, or at a minimum, can store one of many distinct values ​​(such as 16 or 64 different values), which allows for very precise and individual tuning of every cell in the memory array and makes the memory array ideal for storing and fine-tuning the synaptic weights of a neural network. Neural networks using nonvolatile memory cell arrays

[0070] 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural net for a face recognition application, although any other suitable application can be implemented using a non-volatile memory array-based neural network.

[0071] S0 is the input, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from S0 to C1 has both a set of distinct and shared weights, scans the input image with overlapping 3x3 pixel filters (kernels), and shifts the filters by one pixel (or two or more pixels, as determined by the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of that multiplication, a single output value is determined and provided by the first neuron of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right (i.e., adding a column of 3 pixels to the right and dropping a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, which multiplies them by the same weight to determine a second single output value by the associated neuron. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image for all three colors and all bits (the precision value). The process is then repeated using different sets of weights to generate different feature maps for C1 until all of layer C1's feature maps have been calculated.

[0072] In C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, synapses CB1 constitute 16 layers of two-dimensional arrays. (Note that the neuron layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0073] Activation function P1 (pooling) is applied before going from C1 to S1 to pool values ​​from consecutive, non-overlapping 2x2 regions in each feature map. The purpose of the pooling step is to average to nearby locations (or a max function can also be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). The synapses and associated neurons in CB2 going from S1 to C2 scan the maps in S1 with a 4x4 filter using a 1-pixel filter shift. In C2, there are 22 12x12 feature maps. Activation function P2 (pooling) is applied before going from C2 to S2 to pool values ​​from consecutive, non-overlapping 2x2 regions in each feature map. In S2, there are 22 6x6 feature maps. The activation function is applied at synapse CB3 going from S2 to C3, where all neurons in C3 connect to all maps in S2. There are 64 neurons in C3. Synapse CB4 going from C3 to output S3 fully connects S3 to C3. The output at S3 contains 10 neurons, where the highest output neuron determines the class. This output can indicate, for example, the identity or classification of the content of the original image.

[0074] Each level of synapses is implemented using an array or portion of an array of non-volatile memory cells. FIG. 7 is a block diagram of a vector matrix multiplication (VMM) array containing non-volatile memory cells and utilized as a synapse between an input layer and the next layer. Specifically, the VMM 32 includes an array 33 of non-volatile memory cells, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the inputs to the memory array 33. The source line decoder 37 in this example also decodes the output of the memory cell array. Alternatively, the bit line decoder 36 can decode the output of the memory array. The memory array serves two purposes. First, it stores the weights used by the VMM. Second, the memory array effectively multiplies the inputs by the weights stored in the memory array and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic and is also power efficient due to in-place memory computation.

[0075] The output of the memory array is fed to a differential adder (e.g., summing op-amp) 38, which sums the outputs of the memory cell array to generate a single value for the convolution. The differential adder is such that a positive input implements the sum of positive and negative weights. The summed output value is then fed to an activation function circuit 39, which rectifies the output. Activation functions may include sigmoid, tanh, or ReLU functions. The rectified output value becomes an element of a feature map for the next layer (e.g., C1 in the above description) and is then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the memory array constitutes multiple synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summing op-amp 38 and activation function circuit 39 constitute multiple neurons.

[0076] FIG. 8 is a block diagram of the various levels of VMMs. As shown in FIG. 14, inputs are converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM 32a. The output generated by the input VMM 32a is provided as input to the next VMM (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM (hidden level 2) 32b, and so on. The various layers of the VMMs 32 function as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM can be a standalone non-volatile memory array, or multiple VMMs can utilize different portions of the same non-volatile memory array, or multiple VMMs can utilize overlapping portions of the same non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may alternatively include more than two hidden layers and more than two fully connected layers. Vector Matrix Multiplication (VMM) Array

[0077] FIG. 9 shows a neuron VMM 900 particularly suited for memory cells of the type shown in FIG. 2, utilized as part of synapses and neurons between an input layer and the next layer. VMM 900 comprises a memory array 903 of non-volatile memory cells, a reference array 901, and a reference array 902. Reference arrays 901 and 902 serve to convert current inputs flowing into terminals BLR0-3 into voltage inputs WL0-3. The illustrated reference arrays 901 and 902 are in a column direction. Generally, the reference array direction is perpendicular to the input lines. In practice, the reference memory cells are diode-connected via multiplexers (multiplexer 914, which includes one multiplexer and one cascode transistor VBLR for biasing the reference bit line), and the current inputs flow into them. The reference cells are adjusted to a target reference level.

[0078] The memory array 903 serves two purposes. First, it stores the weights used by the VMM 900. Second, the memory array 903 effectively multiplies the inputs (current inputs provided to terminals BLR0-3, which the reference arrays 901 and 902 convert to input voltages and provide to word lines WL0-3) with the weights stored in the memory array to produce an output that becomes the input to the next layer or the input to the final layer. By performing a multiplication function, the memory array eliminates the need for separate multiplication logic and is also power efficient. Here, voltage inputs are provided to word lines and outputs appear on bit lines during read (inference) operations. The current on the bit lines performs a function of the sum of all the currents from the memory cells connected to the bit lines.

[0079] Figure 42 shows the operating voltages of the VMM 900. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations.

[0080] FIG. 10 shows a neuron VMM1000 that is particularly suited for memory cells of the type shown in FIG. 2, which are used as part of synapses and neurons between the input layer and the next layer. VMM1000 comprises a memory array 1003 of non-volatile memory cells, a reference array 1001, and a reference array 1002. VMM1000 is similar to VMM900, except that the word lines run vertically in VMM1000. There are two reference arrays: 1001 (at the top, providing reference conversion input currents to voltages on even rows) and 1002 (at the bottom, providing reference conversion input currents to voltages on odd rows). Here, inputs are provided to word lines, and outputs appear on source lines during read operations. The current on the source line performs a function of the sum of all currents from memory cells connected to the source line.

[0081] Figure 43 shows the operating voltages of the VMM 1000. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations.

[0082] FIG. 11 shows a neuron VMM1100 that is particularly suited for memory cells of the type shown in FIG. 3, used as part of a synapse and neuron between an input layer and the next layer. VMM1100 comprises a memory array 1101 of non-volatile memory cells, a reference array 1102 (which provides a reference conversion input current for the input voltages of the even rows), and a reference array 1103 (which provides a reference conversion input current for the input voltages of the odd rows). VMM1100 is similar to VMM900, except for VMM1100. VMM1100 further comprises a control line 1106 coupled to the control gates of a row of memory cells and a control line 1107 coupled to the erase gates of an adjacent row of memory cells, where the word lines, control gate lines, and erase gate lines are in the same direction. The VMM further comprises a reference bitline select transistor 1104 (part of mux 1114) that selectively couples to the bitline contact of a selected reference memory cell and a switch 1105 (part of mux 1114) that selectively couples the reference bitline to a control line 1106 for a particular selected reference memory cell, where inputs are provided to wordlines (of memory array 1101) and outputs appear on bitlines, such as bitline 1109, during a read operation. The current on the bitline performs a function of the sum of all the currents from the memory cells connected to the bitline.

[0083] Figure 44 shows the operating voltages of the VMM 1100. The columns in the table indicate the voltages of the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations.

[0084] Figure 12 shows a neuron VMM1200 that is particularly suited to memory cells of the type shown in Figure 3, used as part of a neuron and synapse between an input layer and the next layer. VMM1200 is similar to VMM1100, except that in VMM1200, erase gate lines, such as erase gate line 1201, run vertically. Here, inputs are provided on word lines and outputs appear on source lines. The current on a bit line performs a sum function of all the currents from the memory cells connected to the bit line.

[0085] Figure 45 shows the operating voltages of VMM1200. The columns in the table indicate the voltages of the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations.

[0086] FIG. 13 shows a neuron VMM 1300 that is particularly suited for memory cells of the type shown in FIG. 3, which are utilized as part of synapses and neurons between the input layer and the next layer. VMM 1300 comprises a memory array 1301 of nonvolatile memory cells and a reference array 1302 (at the top of the array). Alternatively, a separate reference array can be located at the bottom, similar to that of FIG. 10. In other respects, VMM 1300 is similar to VMM 1200, except that in VMM 1300, control gate lines, such as control gate line 1303, run vertically (thus the row-oriented reference array 1302 is orthogonal to the input control gate lines), and erase gate lines, such as erase gate line 1304, run horizontally. Here, inputs are provided to the control gate lines, and outputs appear on the source lines. In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current in the source line is a function of the sum of all currents from the memory cells connected to the source line.

[0087] As described herein for neural networks, the flash cells are preferably configured to operate in the sub-threshold region.

[0088] The memory cells described herein are biased in weak inversion. Ids=Io * e (Vg-Vth) / kVt =w * Io * e (Vg) / kVt w=e (-Vth) / kVt

[0089] Regarding the I-V log converter, which uses a memory cell to convert an input current to an input voltage: Vg=k * Vt * log[Ids / wp * Io]

[0090] For a memory array used as a vector matrix multiplier VMM, the output current is: Iout=wa * Io * e (Vg) / kVt , i.e. Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / kVt

[0091] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0092] Alternatively, the flash memory cells can be configured to operate in the linear region. Ids=β * (Vgs-Vth) * Vds;β=u * Cox * W / L W α(Vgs-Vth)

[0093] In an IV linear converter, memory cells operating in the linear region can be used to linearly convert input / output currents to input / output voltages.

[0094] Other embodiments of the ESF vector matrix multiplier are described in U.S. Patent Application No. 15 / 826,345, which is incorporated herein by reference. The source lines or bit lines can be used as neuron outputs (current sum outputs).

[0095] 14 shows one embodiment of a bit line decoder circuit 1400. The bit line decoder circuit 1400 comprises a column decoder 1402 and an analog neuromorphic neuron ("ANN") column decoder 1403, each of which is coupled to a VMM array 1401. The VMM array can be based on any of the VMM designs discussed above (such as VMMs 900, 1000, 1100, 1200, and 1300) or other VMM designs.

[0096] One challenge with analog neuromorphic systems is that the system must be able to program and verify (which involves a read operation) and perform ANN reads where every cell in the array is selected and read. In other words, the bit line decoder must select only one bit line in some cases and all bit lines in other cases.

[0097] Bit line decoder circuit 1400 achieves this objective. Column decoder 1402 is a conventional column decoder (program and erase, or PE, decode path) that can be used to select individual bit lines for programming and program verify (sense operations). The output of column decoder 1402 is coupled to a program / erase (PE) column driver circuit (not shown in FIG. 14) for controlling programming, PE verify, and erasing. ANN column decoder 1403 is a column decoder specifically designed to enable read operations on all bit lines at once. ANN column decoder 1403 includes exemplary select transistors 1405 coupled to a bit line (here, BL0) and output circuitry (e.g., current adders and activation functions such as tanh, sigmoid, ReLU, etc.) 1406. The same set of devices is attached to each of the other bit lines. All of the select transistors, such as select transistors 1405, are coupled to select line 1404. During an ANN read operation, select line 1404 is enabled, turning on each of the select transistors, such as select transistor 1405, and then current from each bit line is received by an output circuit, such as circuit 1406 and output.

[0098] 15 shows one embodiment of a bit line decoder circuit 1500. The bit line decoder circuit 1500 is coupled to a VMM array 1501. The VMM array can be based on any of the VMM designs discussed above (such as VMMs 900, 1000, 1100, 1200, and 1300) or other VMM designs.

[0099] Select transistors 1502 and 1503 are controlled by a pair of complementary control signals (V0 and VB_0) and are coupled to a bit line (BL0). Select transistors 1504 and 1505 are controlled by another pair of complementary control signals (V1 and VB_1) and are coupled to another bit line (BL1). Select transistors 1502 and 1504 are coupled to the same output for enable programming, and select transistors 1503 and 1505 are coupled to the same output for inhibit programming, etc. The output lines (program and erase PE decode paths) of transistors 1502 / 1503 / 1504 / 1505 are such that they are coupled to PE column driver circuits for controlling program, PE verify, and erase (not shown).

[0100] The select transistor 1506 is coupled to a bit line (BL0) and to an output and activation function circuit 1507 (e.g., a current summation and activation function such as tanh, sigmoid, ReLU, etc.) The select transistor 1506 is controlled by a control line 1508.

[0101] When only BL0 is activated, control line 1508 is deasserted and signal V0 is asserted, thus reading only BL0. During an ANN read operation, control line 1508 is asserted, turning on select transistor 1506 and similar transistors, and all bit lines are read for all neuron processing.

[0102] 16 shows one embodiment of a bit line decoder circuit 1600. The bit line decoder circuit 1600 is coupled to a VMM array 1601. The VMM array can be based on any of the VMM designs discussed above (such as VMMs 900, 1000, 1100, 1200, and 1300) or other VMM designs.

[0103] Select transistor 1601 is coupled to bit line (BL0) and to output and activation function circuit 1603. Select transistor 1602 is coupled to bit line (BL0) and to common output (PE decode path).

[0104] When only BL0 is activated, select transistor 1602 is activated and connects BL0 to the common output. During an ANN read operation, select transistor 1601 and similar transistors are turned on and all bit lines are read.

[0105] 14, 15, and 16, unselected transistors can be negatively biased to reduce transistor leakage from affecting memory cell performance. Alternatively, a negative bias can be applied to the PE decode path while the array is in ANN operation. The negative bias can be −0.1V to −0.5V or greater.

[0106] 17 shows a VMN 1700. The VMM system 1700 includes a VMM array 1701 and a reference array 1720 (which can be based on any of the VMM designs described above, such as VMMs 900, 1000, 1100, 1200, and 1300, or other VMM designs), a low-voltage row decoder 1702, a high-voltage row decoder 1703, a reference cell low-voltage column decoder 1704 (shown for the reference array in the column direction, meaning it provides inputs for outputting conversions in the row direction), bit line PE drivers 1712, bit line multiplexers 1706, activation function circuits and adders 1707, control logic 1705, and analog bias circuits 1708.

[0107] As shown, the reference cell low-voltage column decoder 1704 is meant to be for a column-wise reference array 1720, providing inputs for outputting conversions row-wise. If the reference array were row-wise, then the reference decoders would need to be at the top and / or bottom of the array, providing inputs for outputting conversions column-wise.

[0108] The low-voltage row decoder 1702 provides bias voltages for read and program operations and provides decode signals for the high-voltage row decoder 1703. The high-voltage row decoder 1703 provides high-voltage bias signals for program and erase operations. The reference cell low-voltage column decoder 1704 provides the decode function for the reference cells. The bit line PE driver 1712 provides the control function for the bit lines in program, verify, and erase. The bias circuit 1705 is a shared bias block that provides multiple voltages required for the various program, erase, program verify, and read operations.

[0109] FIG. 18 shows a VMM system 1800. The VMM system 1800 is similar to the VMM system 1700, except that the VMM system 1800 further includes a red array 1801, a bit line PE driver BLDRV 1802, a high voltage column decoder 1803, an NVR sector 1804, and a reference array 1820. The high voltage column decoder 1803 provides high voltage bias for the vertical decode lines. The red array 1802 provides array redundancy for replacing defective array portions. The NVR (non-volatile register aka information sector) sector 1804 is an array sector used to store user information, device ID, passwords, security keys, trim bits, configuration bits, manufacturing information, etc.

[0110] 19 shows a VMM system 1900. The VMM system 1900 is similar to the VMM system 1800, except that the VMM system 1900 further comprises a reference system 1999. The reference system 1999 comprises a reference array 1901, a reference array low-voltage row decoder 1902, a reference array high-voltage row decoder 1903, and a reference array low-voltage column decoder 1904. The reference system can be shared across multiple VMM systems. The VMM system further comprises an NVR sector 1905.

[0111] The reference array low voltage row decoder 1902 provides bias voltages for read and programming operations involving the reference array 1901 and also provides decode signals for the reference array high voltage row decoder 1903. The reference array high voltage row decoder 1903 provides high voltage biases for programming and operations involving the reference array 1901. The reference array low voltage column decoder 1904 provides the decode function for the reference array 1901. The reference array 1901 is such that it provides a reference target or cell margin for program verify (searching for edge cells).

[0112] FIG. 20 illustrates a word line driver 2000. The word line driver 2000 selects a word line (such as the exemplary word lines WL0, WL1, WL2, and WL3 shown herein) and provides a bias voltage to that word line. Each word line is attached to a select transistor, such as a select iso (isolation) transistor 2002, which is controlled by a control line 2001. The iso transistor 2002 is used to isolate high voltages, such as erase (e.g., 8-12V), from the word line decode transistors, which can be implemented with IO transistors (e.g., 1.8V, 3.3V). Here, during any operation, the control line 2001 is activated, turning on all select transistors similar to selecting the iso transistors 2002. Exemplary bias transistor 2003 (part of the word line decode circuit) selectively couples the word lines to a first bias voltage (e.g., 3V), and exemplary bias transistor 2004 (part of the word line decode circuit) selectively couples the word lines to a second bias voltage (a bias lower than the first bias voltage, including ground, and a negative voltage bias to reduce leakage from unused memory rows). During an ANN read operation, all used word lines are selected and tied to the first bias voltage. All unused word lines are tied to the second bias voltage. During other operations, such as program operations, only one word line is selected while the other word line is tied to the second bias voltage, which may be a negative bias (e.g., −0.3 to −0.5V or higher) to reduce array leakage.

[0113] 21 shows word line driver 2100. Word line driver 2100 is similar to word line driver 2000, except that top transistors such as bias transistor 2103 can be individually coupled to bias voltages, rather than all such transistors being tied together as in word line driver 2000. This allows all word lines to have different independent voltages simultaneously.

[0114] Figure 22 shows word line driver 2200. Word line driver 2200 is similar to word line driver 2100, except that bias transistors 2103 and 2104 are coupled to decoder circuit 2201 and inverter 2202. Thus, Figure 22 shows decode subcircuit 2203 within word line driver 2200.

[0115] 23 shows word line driver 2300. Word line driver 2300 is similar to word line driver 2100, except that bias transistors 2103 and 2104 are coupled to the output of stage 2302 of shift register 2301. Shift register 1301 allows for independent control of each column by serially shifting data (serial clocking the register), allowing one or more rows to be enabled simultaneously as the data pattern shifts.

[0116] FIG. 24 shows word line driver 2400. Word line driver 2400 is similar to word line driver 2000, except that each select transistor is further coupled to a capacitor, such as capacitor 2403. Capacitor 2403 can provide a precharge or bias to the word line at the beginning of operation, enabled by transistor 2401 to sample the voltage on line 2440. Capacitor 2403 acts to sample and hold (S / H) the input voltage for each word line. Transistor 2401 is off during ANN operation (array current adder and activation function) of the VMM array, meaning the voltage on the S / H capacitor acts as a (floating) voltage source for the word line. Alternatively, capacitor 2403 can be provided by the word line capacitance from the memory array.

[0117] 25 shows word line driver 2500. Word line driver 2500 is similar to the previously described word line drivers, except that bias transistors 2501 and 2502 are connected to switches 2503 and 2504, respectively. Switch 2503 receives the output of opa (operational amplifier) ​​2505 and switch 2504, which provides a reference input to the negative input of opa 2505, thereby essentially providing the voltage stored by capacitor 2403 due to the closed loop action provided by opa 2505, transistor 2501, and switches 2503 and 2504. In this way, when switches 2503 and 2504 are closed, the voltage at input 2506 is superimposed on capacitor 2403 by transistor 2501. Alternatively, capacitor 2403 may be provided by word line capacitance from the memory array.

[0118] 26 shows a word line driver. Word line driver 2600 is similar to the word line drivers described above, except for the addition of amplifier 2601, which acts as a voltage buffer for the voltage on capacitor 2604 to drive a voltage onto word line WL0, meaning that the voltage on the S / H capacitor acts as a (floating) voltage source for the word line. This is to avoid, for example, word line-to-word line coupling from affecting the capacitor voltage.

[0119] FIG. 27 illustrates a high voltage source line decoder circuit 2700. The high voltage source line decoder circuit includes transistors 2701, 2702, and 2703 configured as shown. Transistor 2703 is used to deselect the source line to a low voltage. Transistor 2702 is used to drive a high voltage to the source line of the array, and transistor 2701 is used to monitor the voltage on the source line. Transistors 2702, 2701 and a driver circuit (e.g., opa) are configured in a closed loop manner (force / sense) to maintain PVT (process, voltage, temperature) and varying current load conditions. The SLE (driving source line node) and SLB (monitored source line node) can be at one end of the source line. Alternatively, SLE can be at one end of the source line and SLN at the other end.

[0120] FIG. 28 shows a VMM high voltage decode circuit comprising a word line decoder circuit 2801, a source line decoder circuit 2804 and a high voltage level shifter 2808 suitable for use with memory cells of the type shown in FIG.

[0121] Word line decoder circuit 2801 comprises a PMOS select transistor 2802 (controlled by signal HVO_B) and an NMOS select transistor 2803 (controlled by signal HVO_B) configured as shown.

[0122] Source line decoder circuit 2804 comprises an NMOS monitor transistor 2805 (controlled by signal HVO), a drive transistor 2806 (controlled by signal HVO), and a transistor 2807 (controlled by signal HVO_B) configured as shown.

[0123] A high voltage level shifter 2808 receives a valid signal EN and outputs a high voltage signal HV and its complement HVO_B.

[0124] FIG. 29 shows a VMM high voltage decode circuit comprising an erase gate decoder circuit 2901, a control gate decoder circuit 2904, a source line decoder circuit 2907 and a high voltage level shifter 2911 suitable for use with memory cells of the type shown in FIG.

[0125] The erase gate decoder circuit 2901 and the control gate decoder circuit 2904 use the same design as the word line decoder circuit 2801 of FIG.

[0126] The source line decoder circuit 2907 uses the same design as the source line decoder circuit 2804 of FIG.

[0127] High voltage level shifter 2911 uses the same design as high voltage level shifter 2808 in FIG.

[0128] Figure 30 shows a word line decoder 300 for exemplary word lines WL0, WL1, WL2, and WL3. Exemplary word line WL0 is coupled to pull-up transistor 3001 and pull-down transistor 3002. When pull-up transistor 3001 is activated, WL0 is enabled. When pull-down transistor 3002 is activated, WL0 is disabled. The function of Figure 30 is similar to Figure 21 without the isolation transistors.

[0129] Figure 31 shows a control gate decoder 3100 for exemplary control gate lines CG0, CG1, CG2, and CG3. Exemplary control gate line CG0 is coupled to pull-up transistor 3101 and pull-down transistor 3102. When pull-up transistor 3101 is activated, CG0 is enabled. When pull-down transistor 3102 is activated, CG0 is disabled. The select and deselect functions of Figure 31 are similar to the select and deselect functions of Figure 30 for the control gates.

[0130] 32 shows an exemplary control gate decoder 3200 for control gate lines CG0, CG1, CG2, and CG3. Control gate decoder 3200 is similar to control gate decoder 3100, except that control gate decoder 3200 includes capacitors, such as capacitor 3203, coupled to each control gate line. These sample and hold (S / H) capacitors can provide a precharge bias to each control gate line prior to operation, meaning that the voltage on the S / H capacitor acts as a (floating) voltage source for the control gate line. The S / H capacitors can be provided by control gate capacitance from the memory cells.

[0131] 33 shows an exemplary control gate decoder 3300 for control gate lines CG0, CG1, CG2, and CG3. Control gate decoder 3300 is similar to control gate decoder 3200, except that control gate decoder 3300 further comprises a buffer 3301 (such as an opa).

[0132] 34 shows a current-to-voltage circuit 3400. The circuit comprises a diode-connected reference cell circuit 3450 and a sample-and-hold circuit 3460 configured. Circuit 3450 comprises an input current source 3401, an NMOS transistor 3402, a cascoding bias transistor 3403, and a reference memory cell 3404. The sample-and-hold circuit comprises a switch 3405 and an S / H capacitor 3406. Memory 3404 is biased in a diode-connected configuration with the bias of the bit line to convert an input current into a voltage, such as to supply a word line.

[0133] 35 shows a current-to-voltage circuit 3500, which is similar to current-to-voltage circuit 3400, but adds an amplifier 3501 after the S / H capacitor. The current-to-voltage circuit 3500 includes a configured diode-connected reference cell circuit 3550, a sample-and-hold circuit 3470, and an amplifier stage 3562.

[0134] 36 shows a current-voltage circuit 3600 that is the same design as the control gate current-voltage circuit 3400 in a diode-connected configuration. The current-voltage circuit 3600 comprises a diode-connected reference cell circuit 3650 and a sample-and-hold circuit 3660 configured.

[0135] FIG. 37 shows a current-to-voltage circuit 3700 in which a buffer 3790 is placed between a reference circuit 3750 and an S / H circuit 3760 .

[0136] Figure 38 shows a current-to-voltage circuit 3800 similar to Figure 35 with the control gates connected in a diode-connected configuration. The current-to-voltage circuit 3800 includes a diode-connected reference cell circuit 3550 configured, a sample-and-hold circuit 3870, and an amplifier stage 3862.

[0137] Figure 39 shows a current-voltage circuit 3900 similar to Figure 34 applied to the memory cell of Figure 2. The current-voltage circuit 3900 comprises a diode-connected reference cell circuit 3950 and a sample-and-hold circuit 3960 configured.

[0138] FIG. 40 shows a current-voltage circuit 4000 similar to FIG. 37 applied to the memory cell of FIG. 2, with a buffer 4090 disposed between the reference circuit 4050 and the S / H circuit 4060.

[0139] Figure 41 shows a current-voltage circuit 4100 similar to Figure 38 applied to the memory cell of Figure 2. The current-voltage circuit 4100 comprises a diode-connected reference cell circuit 4150 configured, a sample-and-hold circuit 4170, and an amplifier stage 4162.

[0140] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (without any intermediate material, element, or space disposed between them) and "indirectly on" (with an intermediate material, element, or space disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (without any intermediate material, element, or space disposed between them) and "indirectly adjacent" (with an intermediate material, element, or space disposed between them); "attached" includes "directly attached" (without any intermediate material, element, or space disposed between them) and "indirectly attached to" (with an intermediate material, element, or space disposed between them); and "electrically coupled" includes "directly electrically coupled" (without any intermediate material or element electrically coupling the elements together) and "indirectly electrically coupled to" (with an intermediate material or element electrically coupling the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate, without any intermediate materials / elements therebetween, and forming the element indirectly on the substrate, with one or more intermediate materials / elements therebetween.

Claims

1. A word line driver coupled to a vector matrix multiplication array, the vector matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, each row coupled to a word line, each word line coupled to the word line driver, the word line driver comprising: a plurality of select transistors, each of the plurality of select transistors having a first terminal, a second terminal, and a gate, the gate of each of the plurality of select transistors being coupled to a common control line, the first terminal of each of the plurality of select transistors being coupled to different word lines, and the second terminal of each of the plurality of select transistors being coupled to one or more bias transistors; The bias transistor coupled to each of the plurality of select transistors may provide a bias voltage to a single select transistor or to all of the select transistors.

2. 2. The word line driver of claim 1, wherein each of said bias transistors is coupled to circuitry for decoding a word line address.

3. 2. The word line driver of claim 1, wherein the bias transistor is coupled to a shift register.

4. 2. The word line driver of claim 1, wherein each select transistor is coupled to a capacitor.

5. 2. The word line driver of claim 1, wherein each bias transistor is coupled to a comparator.

6. 1. An analog neuromorphic memory system, comprising: a vector matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, each column connected to a bit line, each memory cell having a word line terminal and a source line terminal; a word line decoder circuit coupled to the word line terminals of the non-volatile memory cells, the word line decoder circuit being capable of applying a low voltage via a low voltage transistor or a high voltage via a high voltage transistor to the coupled word line terminal, the word line decoder circuit comprising an isolation transistor coupled to each word line to isolate the high voltage transistor from the low voltage transistor.

7. 7. The system of claim 6, wherein a negative bias is applied to the word line of each unselected memory cell during a program and verify operation or during a read operation.

8. 7. The system of claim 6, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

9. 7. The system of claim 6, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

10. The system of claim 6 , wherein each of the non-volatile memory cells is configured to operate in a sub-threshold region.

11. The system of claim 6 , wherein each of the non-volatile memory cells is configured to operate in a linear region.

12. 1. An analog neuromorphic memory system, comprising: a vector matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, each column connected to a bit line, each memory cell having a word line terminal and a source line terminal; a word line decoder circuit coupled to the word line terminal of the non-volatile memory cell, the word line decoder circuit being capable of applying a low voltage or a high voltage to the coupled word line terminal; a sample and hold capacitor coupled to each word line.

13. 13. The system of claim 12, wherein a negative bias is applied to the word line of each unselected memory cell during a program and verify operation or during a read operation.

14. 13. The system of claim 12, wherein the capacitance in the sample and hold capacitor is provided by the intrinsic capacitance of a word line.

15. 13. The system of claim 12, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

16. 13. The system of claim 12, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

17. 13. The system of claim 12, wherein each of the non-volatile memory cells is configured to operate in a sub-threshold region.

18. 13. The system of claim 12, wherein each of the non-volatile memory cells is configured to operate in a linear region.

19. The system of claim 12 , wherein the sample and hold capacitor provides a voltage source for the word line.

20. 1. An analog neuromorphic memory system, comprising: a vector matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, each column connected to a bit line, each memory cell having a word line terminal and a source line terminal; a control gate decoder circuit coupled to a control gate line terminal of the non-volatile memory cell, the control gate decoder circuit being capable of applying a low voltage or a high voltage to the coupled control gate terminal; a sample and hold capacitor coupled to each word line.

21. 21. The system of claim 20, wherein a negative bias is applied to the word line of each unselected memory cell during a program and verify operation or during a read operation.

22. 21. The system of claim 20, wherein the sample and hold capacitor comprises a control gate capacitance.

23. 21. The system of claim 20, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

24. 21. The system of claim 20, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

25. 21. The system of claim 20, wherein each of the non-volatile memory cells is configured to operate in a sub-threshold region.

26. 21. The system of claim 20, wherein each of the non-volatile memory cells is configured to operate in a linear region.

27. 21. The system of claim 20, wherein the sample and hold capacitor provides a voltage source for the control gate line.

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