field-effect transistor

Abstract

This electric field effect transistor (10) comprises, on a surface in the following order, a source electrode (111), a first gate electrode (112), and a drain electrode (113), and comprises, in a direction perpendicular to the surface, in the following order: a first barrier layer (104); a second gate electrode (103) disposed inside the first barrier layer; a first channel layer (105) composed of a semiconductor; a second barrier layer (106) composed of a semiconductor having a larger energy gap than the first channel layer, and including a δ-doped layer; a second channel layer (107) composed of a semiconductor having a smaller energy gap than the second barrier layer; a third barrier layer (108); and the first gate electrode.　Consequently, the present invention is able to provide a field effect transistor that is capable of high output and high frequency operation.

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor capable of high-power and high-frequency operation. [Background technology]

[0002] The terahertz frequency band (0.3 to 3.0 THz) is expected to have a wide range of applications, including next-generation high-speed wireless communications, non-destructive testing using terahertz wave imaging, security applications using transmission imaging, and material analysis using absorption spectra. Therefore, attention is being focused on electronic devices and integrated circuits that can directly handle the terahertz frequency band. Generally, field-effect transistors (FETs) using compound semiconductors with high electron mobility are used as electronic devices with excellent high-frequency characteristics.

[0003] A high-frequency field-effect transistor generally has a structure in which a barrier layer including a buffer layer, a channel layer, and a carrier supply layer is stacked on a semiconductor substrate, an ohmic cap layer and ohmic electrodes, i.e., a source electrode and a drain electrode, are formed thereon, and a gate electrode is formed between the source electrode and the drain electrode.

[0004] In this stacked structure, the materials and composition are determined taking into account the spatial band structure. The carrier supply layer is heavily doped with impurities. Carriers generated by ionization of these impurities accumulate in the channel layer, which has a smaller band gap than the barrier layer, forming a two-dimensional electron gas.

[0005] The two-dimensional electron gas in the channel layer is spatially separated from the ionized impurities by the barrier layer, allowing it to travel between the source and drain at high speed without suffering mobility degradation due to impurity scattering.

[0006] In a high-frequency field-effect transistor, applying a voltage to the gate electrode modulates the energy band structure of the channel layer directly below the gate electrode, thereby controlling the two-dimensional electron gas concentration in the channel layer and the amount of current flowing between the source and drain. Therefore, in a configuration where the source electrode is grounded, by inputting an amplified high-frequency signal to the gate electrode, the amplified signal can be output from the drain electrode.

[0007] In particular, when using high-frequency field-effect transistors to configure circuits where high output is important, such as power amplifiers, it is necessary to increase the current driving force of the field-effect transistor itself, that is, to extract more output from the drain electrode for any input to the gate electrode.

[0008] As shown in FIGS. 6A and 6B, a typical field effect transistor 60 includes a source electrode 603, a gate electrode 604, and a drain electrode 605 on the surface of a channel layer 602 on a substrate 601.

[0009] 7, a structure has been disclosed in which a single channel layer 704 is sandwiched between a front gate 708 and a back gate 703 in order to improve threshold voltage control and gate controllability in a field effect transistor 70 (Non-Patent Document 1). Here, the field effect transistor 70 includes a buffer layer 702 on a substrate 701, and a source electrode 707 and a drain electrode 709 on the surface of the channel layer 704 via ohmic cap layers 705 and 706.

[0010] In order to achieve a high current driving force in such a field effect transistor, the width of the gate electrode is generally increased.

[0011] Furthermore, as shown in FIG. 8, in order to increase the current driving force in a field-effect transistor 80, a so-called multi-finger structure has been disclosed in which a source electrode 802, a drain electrode 804, and a gate electrode 803 each have multiple finger portions formed in parallel on an active region (channel layer) 801, and these are bundled together to form a single transistor, thereby increasing the net gate width (X direction in the figure) (Patent Document 1). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Patent No. 6973670 [Non-patent literature]

[0013] [Non-Patent Document 1] S. Kodama, T. Furuta, N. Watanabe, H. Ito, A. Kanda, M. Muraguchi and T. Ishibashi, “Variable Threshold AlGaAs / InGaAs Heterostructure Field-Effect Transistors with Paired Gates Fabricated Using theWafer-Bonding Technique”, Jpn. J. Appl. Phys., vol. 39, Part 1, No. 4B, (2000) pp. 2435-2438. Summary of the Invention [Problem to be solved by the invention]

[0014] However, simply increasing the gate width to improve current driving capability generates gate resistance from the gate electrode input end (feed section) to the gate electrode width direction. Particularly in the case of high-frequency signals, the gate resistance increases due to factors such as the skin effect, and the input current attenuates in the gate electrode width direction, so the current driving capability does not improve as much as expected.

[0015] Although a structure in which a single channel layer is sandwiched between two gates (front gate and back gate) is expected to improve gate controllability, the channel layer is only a single layer, so in principle it is difficult to achieve a current drive force higher than that of a typical single-gate transistor. Therefore, in order to increase the drive current, the gate electrode width must be increased, which, as mentioned above, poses the problem of increased gate resistance.

[0016] Furthermore, in a multi-finger structure, the more distant the finger portion from the feed portion, the more difficult it becomes for a high frequency signal to propagate due to gate resistance, and the current driving force does not improve as much as expected.

[0017] Furthermore, as the gate width increases, the footprint of the device increases, reducing the degree of integration. In other words, the number of amplifying devices that can be integrated within a specified area decreases, making it impossible to construct an amplifier with the desired output. Even if the circuit area is not specified, devices with large footprints require long wiring distances, which increases transmission loss and limits the ability to achieve high output.

[0018] Furthermore, the increase in gate resistance mentioned above deteriorates high-frequency characteristics. That is, when increasing the gate width to increase output power, there is a trade-off with a deterioration in high-frequency characteristics. [Means for solving the problem]

[0019] In order to solve the above-mentioned problems, a field effect transistor according to the present invention includes, on a surface, a source electrode, a first gate electrode, and a drain electrode, and, in a direction perpendicular to the surface, includes, in that order, a first barrier layer, a second gate electrode disposed in the first barrier layer, a first channel layer made of a semiconductor, a second barrier layer made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer, a second channel layer made of a semiconductor having a smaller energy gap than the second barrier layer, a third barrier layer, and the first gate electrode. The first barrier layer and the third barrier layer are made of an insulating film. do. Furthermore, a field-effect transistor according to the present invention comprises, on a surface, a source electrode, a first gate electrode, and a drain electrode, in that order, and, in a direction perpendicular to the surface, a first barrier layer, a second gate electrode disposed within the first barrier layer, a first channel layer made of a semiconductor, a second barrier layer made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer, a second channel layer made of a semiconductor having a smaller energy gap than the second barrier layer, a third barrier layer, and the first gate electrode, and further comprises a recess region around the second gate electrode to reduce parasitic capacitance caused by the second gate electrode. Furthermore, a field-effect transistor according to the present invention comprises, on a surface, a source electrode, a first gate electrode, and a drain electrode, in that order, and, in a direction perpendicular to the surface, a first barrier layer, a second gate electrode disposed in the first barrier layer, a first channel layer made of a semiconductor, a second barrier layer made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer, a second channel layer made of a semiconductor having a smaller energy gap than the second barrier layer, a third barrier layer, and the first gate electrode, wherein the energy gap of the first channel layer is smaller than that of the second channel layer. a step of forming a second gate electrode and a first barrier layer covering the second gate electrode on the semiconductor substrate, the step of bonding the first channel layer and the first barrier layer together so that the surface of the first channel layer faces the surface of the first barrier layer; a step of removing the semiconductor sacrificial substrate; and a step of forming a third barrier layer and a first gate electrode on the surface of the second channel layer, the first channel layer being made of a semiconductor; the second barrier layer being made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer; the second channel layer being made of a semiconductor having a smaller energy gap than the second barrier layer; the first barrier layer and the third barrier layer being made of an insulating film; and the semiconductor sacrificial substrate and the semiconductor substrate being made of the same semiconductor material. [Effects of the Invention]

[0020] According to the present invention, a field effect transistor capable of high output and high frequency operation can be provided. [Brief explanation of the drawings]

[0021] [Figure 1A] FIG. 1A is a schematic top view showing the configuration of a field-effect transistor according to a first embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view taken along line IB-IB' showing the configuration of the field effect transistor according to the first embodiment of the present invention. [Figure 1C] FIG. 1C is a cross-sectional view taken along the line IC-IC' showing the configuration of the field-effect transistor according to the first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view showing the configuration of a field effect transistor according to a second embodiment of the present invention. [Figure 3] FIG. 3 is a schematic cross-sectional view showing the configuration of a field effect transistor according to a third embodiment of the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the configuration of a field effect transistor according to a fourth embodiment of the present invention. [Figure 5] FIG. 5 is a schematic cross-sectional view showing the configuration of a field effect transistor according to a fifth embodiment of the present invention. [Figure 6A] FIG. 6A is a schematic top view showing the configuration of a conventional field effect transistor. [Figure 6B] FIG. 6B is a cross-sectional view taken along the line VIB-VIB' showing the configuration of a conventional field effect transistor. [Figure 7] FIG. 7 is a schematic cross-sectional view showing the configuration of a conventional field effect transistor. [Figure 8] FIG. 8 is a schematic top view showing the configuration of a conventional field effect transistor. DETAILED DESCRIPTION OF THE INVENTION

[0022] First Embodiment A field effect transistor according to a first embodiment of the present invention will be described with reference to FIGS. 1A to 1C.

[0023] <Configuration of field-effect transistor> In this embodiment, a field effect transistor using InP, which is one of the compound semiconductor materials effective for terahertz technology, as a substrate will be described as an example.

[0024] 1A and 1B, a field-effect transistor 10 according to this embodiment includes, in order, a semiconductor (InP) substrate 101, a buffer layer 102, a first barrier layer 104, a first channel layer (hereinafter also referred to as a "back-gate-side channel layer") 105, a second barrier layer 106, and a second channel layer (hereinafter also referred to as a "top-gate-side channel layer") 107. Here, a δ-doped layer 115 is provided within the second barrier layer 106.

[0025] Here, a second gate electrode (hereinafter also referred to as a “back gate electrode”) 103 is provided within the first barrier layer 104.

[0026] In addition, a first ohmic cap layer 109 and a source electrode 111 are provided in this order at a predetermined position (one position) on the surface of the second channel layer 107 (the surface opposite the second barrier layer 106), and a second ohmic cap layer 110 and a drain electrode 113 are provided in this order at another position.

[0027] Furthermore, a first gate electrode (hereinafter also referred to as a "top gate electrode") 112 is provided on the surface of the second channel layer 107, between the first ohmic capping layer 109 and the second ohmic capping layer 110, i.e., between the source electrode 111 and the drain electrode 113, via the third barrier layer 108. In this way, the field-effect transistor 10 has, on its surface, the source electrode 111, the first gate electrode 112, and the drain electrode 113, in this order.

[0028] The first barrier layer 104 is made of SiO2 and is formed to cover the back gate electrode 103. The back gate side insulating film 104 may be an oxide such as SiN, SiON, Al2O3, HfO2, or TiO2, a nitride, or a laminate film thereof. Hereinafter, the first barrier layer 104 will also be referred to as the "back gate side insulating film."

[0029] The back-gate-side insulating film 104 has a thickness of about 1 to 10 nm from the surface of the back-gate electrode 103 (the surface on the back-gate-side channel layer 105 side) to the back-gate-side channel layer 105. This thickness is not limited to this, and may be set so as to obtain a desired field effect from the back-gate electrode 103 to the back-gate-side channel layer 105. The total thickness of the back-gate-side insulating film 104 is obtained by adding the thickness of the second gate electrode (back-gate electrode) 103 (described later) to this thickness.

[0030] The second gate electrode (back gate electrode) 103 has a metal laminate structure made of Ti, Pt, and Au, and has a thickness of 100 to 500 nm. Other metals such as Mo may also be used.

[0031] Alternatively, the back gate electrode 103 may be made of n-type doped InP, InGaAs, InAlAs, or the like.

[0032] The width of the back gate electrode 103 is about 10 to 40 μm.

[0033] The length (gate length) of the back gate electrode 103 is about 10 to 200 nm, which corresponds to an operating frequency of about 100 G to 300 G. The gate length of the back gate electrode 103 is not limited to this and may be set according to the operating frequency.

[0034] Here, an example in which the back gate electrode 103 is disposed at the interface between the buffer layer 102 and the back gate side insulating film 104 has been shown, but the invention is not limited to this and may be arranged within the back gate side insulating film 104 .

[0035] The first channel layer (back gate side channel layer) 105 is made of InGaAs with a thickness of 5 to 20 nm. 0.53 Ga 0.47 As / InAs / In 0.53 Ga 0.47 It may also be a stacked structure of semiconductors such as InGaAs and InAs (H. Sugiyama et al., 2012 International Conference on Indium Phosphide and Related Materials, 2012, pp. 245-248.) Here, the first channel layer 105 may be any semiconductor having a smaller energy gap than the second barrier layer 106 and a lattice constant within a range in which the crystal quality is not deteriorated (for example, within a range in which lattice relaxation does not occur).

[0036] The second barrier layer 106 is made of InAlAs or InP (thickness: 5 to 20 nm). Here, the second barrier layer 106 may be made of any semiconductor having a larger energy gap than the first channel layer 105 and a lattice constant within a range in which the crystal quality is not deteriorated (for example, within a range in which lattice relaxation does not occur).

[0037] The δ-doped layer 115 in the second barrier layer 106 has a Si concentration of 1×10 12 ~1×10 13 cm -2 It is doped and formed into a sheet.

[0038] The δ-doped layer 115 is heavily doped to supply two-dimensional electrons to the channel layer and reduce the access resistance from the ohmic electrodes (the source electrode 111 and the drain electrode 113) to the back-gate side channel layer 105.

[0039] Specifically, the δ-doped layer 115 locally lowers the conduction band in the second barrier layer 106, increasing the probability of carrier tunneling. This reduces the access resistance to the backgate electrode side channel layer 105, which is located at a long distance (access distance) from the ohmic electrodes (source electrode 111, drain electrode 113), enabling efficient carrier injection.

[0040] The δ-doped layer 115 is formed in the middle portion of the second barrier layer 106. The position where the δ-doped layer 115 is formed is not limited thereto, and may be formed depending on the thickness of the second barrier layer 106. For example, the δ-doped layer 115 may be disposed close to the back-gate side channel layer 105 in order to efficiently increase the tunneling probability of carriers and reduce the access resistance.

[0041] The second channel layer (top gate side channel layer) 107 is made of InGaAs with a thickness of 5 to 20 nm. 0.53 Ga 0.47 As / InAs / In 0.53 Ga 0.47 The second channel layer 107 may have a stacked structure of semiconductors such as InGaAs and InAs. Here, the second channel layer 107 may be a semiconductor having a smaller energy gap than the second barrier layer 106 and a lattice constant within a range in which the crystal quality is not deteriorated (for example, within a range in which lattice relaxation does not occur).

[0042] The first ohmic cap layer 109 and the second ohmic cap layer 110 are each made of n-type InAlAs with a thickness of 5 to 20 nm, and are disposed on the second channel layer (top gate side channel layer) 107. Other than n-type InAlAs, n-type InGaAs or a stacked structure of InAlAs and InGaAs may also be used.

[0043] The source electrode 111 and the drain electrode 113 have a metal layered structure made of Ti, Pt, and Au, and form ohmic contact with the second channel layer 107 via the first ohmic cap layer 109 and the second ohmic cap layer 110, respectively. Other metals such as Mo, Ni, or Al may also be used for the source electrode 111 and the drain electrode 113. The thickness of the source electrode 111 and the drain electrode 113 is approximately 50 to 200 nm.

[0044] The third barrier layer 108 is disposed on the second channel layer (top gate side channel layer) 107 in a recess region (hereinafter also referred to as a “cap recess”) 114 between the first ohmic cap layer 109 and the second ohmic cap layer 110.

[0045] Here, the cap recess 114 is a hollow region where no ohmic cap layer is disposed.

[0046] The third barrier layer 108 is made of SiO2 with a thickness of 1 to 10 nm. The top-gate-side insulating film 108 may be an oxide such as SiN, SiON, Al2O3, HfO2, or TiO2, a nitride, or a laminate film thereof. Hereinafter, the third barrier layer 108 will also be referred to as the "top-gate-side insulating film."

[0047] The first gate electrode (top gate electrode) 112 is disposed on the third barrier layer 108 and directly above the back gate electrode 103.

[0048] Furthermore, the top gate electrode 112 does not have to be positioned directly above the back gate electrode 103, and may be positioned with a shift of about 100 to 150 nm therebetween, as long as it is positioned so that an electric field can be applied to the channel between the source electrode 111 and the drain electrode 113 between the top gate electrode 112 and the back gate electrode 103.

[0049] The top gate electrode 112 has a metal laminate structure made of Ti, Pt, and Au. Other metals such as Mo may also be used. The thickness of the top gate electrode 112 is about 100 to 500 nm.

[0050] The width of the top gate electrode 112 is about 10 to 40 μm.

[0051] The gate length of the top gate electrode 112 is the same as the length of the back gate electrode 103. Here, the gate length of the top gate electrode 112 may be different from that of the back gate electrode 103, and may be about 10 to 200 nm. In this case, it corresponds to an operating frequency of about 100 G to 300 G. The gate length of the top gate electrode 112 is not limited to this, and may be set according to the operating frequency.

[0052] As shown in FIGS. 1A and 1C, the back gate electrode 103 and the top gate electrode 112 are electrically connected by an inter-electrode connection portion 116.

[0053] Here, the top gate electrode 112 is arranged so that its end 118 is drawn out to the outside of the operating region of the field effect transistor 10, i.e., the region including the channel through which carriers travel (hereinafter referred to as the "mesa structure of the field effect transistor") 117.

[0054] The back gate electrode 103 has the same shape as the top gate electrode 112 and is disposed directly below the top gate electrode 112 .

[0055] The back gate electrode 103 and the top gate electrode 112 are electrically connected at their respective ends (feed portions) 118 by an inter-electrode connection portion 116. The inter-electrode connection portion 116 is formed by filling a conductive material inside a through-hole that penetrates vertically from the top gate-side insulating film 108 to the back gate-side insulating film 104 in the above-mentioned stacked structure. The conductive material may be Au, Pt, Ti, Mo, W, or the like.

[0056] Here, the inter-electrode connectors 116 may be disposed at both ends of the back gate electrode 103 and the top gate electrode 112, or may be disposed at either end.

[0057] The cross-sectional shape of the electrode connection portion 116 is rectangular. However, the cross-sectional shape of the electrode connection portion 116 may be elliptical, circular, polygonal, or the like in order to reduce the parasitic capacitance component.

[0058] The back gate electrode 103 may have a different shape from the top gate electrode 112 and may not be disposed directly below it.

[0059] Furthermore, the inter-electrode connection portion 116 is arranged so as not to protrude from both electrodes at the junction between the back gate electrode 103 and the top gate electrode 112. Here, the inter-electrode connection portion 116 may be arranged so as to protrude from both electrodes or from either one of the electrodes at the junction between the back gate electrode 103 and the top gate electrode 112, for the purpose of reducing gate resistance or the like.

[0060] This simplifies the circuit configuration and allows voltage to be applied to the back gate electrode 103 and the top gate electrode 112 simultaneously, making it easy to control.

[0061] Here, the back gate electrode 103 and the top gate electrode 112 may be configured not to be connected to each other, and each electrode may be controlled separately.

[0062] <Field-effect transistor manufacturing method> An example of a method for manufacturing the field effect transistor 10 according to this embodiment will be described below.

[0063] First, a semi-insulating InP substrate is used as a sacrificial substrate, and a buffer layer, a top-gate-side channel layer 107, a second barrier layer 106 including a δ-doped layer 115, and a back-gate-side channel layer 105 are grown on the sacrificial substrate in this order by metal organic chemical vapor deposition or molecular beam epitaxy.

[0064] In detail, following the growth of the buffer layer, a crystal of InGaAs or the like (film thickness: 5 to 20 nm) is grown as the top gate side channel layer 107.

[0065] Next, as the second barrier layer 106, a crystal of InAlAs or InP (film thickness: 5 to 20 nm) is grown.

[0066] Here, a δ-doped layer 115 is formed in the second barrier layer 106. The δ-doped layer 115 is formed by doping Si at a concentration of 1×10 12 ~1×10 13 cm -2 It is doped into a sheet shape.

[0067] Next, as the back-gate side channel layer 105, InGaAs (film thickness: 5 to 20 nm) is crystal-grown.

[0068] On the other hand, a buffer layer 102, a back gate electrode 103, and a back gate side insulating film 104 are laminated on a semi-insulating InP substrate 101 for a device.

[0069] Specifically, first, a buffer layer 102 such as undoped InAlAs is deposited by metal organic chemical vapor deposition or molecular beam epitaxy.

[0070] Next, when n-type InP, InGaAs, or InAlAs is used for the back gate electrode 103, the semiconductor is deposited by metal organic chemical vapor deposition or molecular beam epitaxy, and then processed by lithographic patterning and etching.

[0071] When the back gate electrode 103 has a laminated structure of metals such as Ti, Pt, Au, and Mo, it is formed by patterning using lithography and electroplating, electroless plating, vacuum deposition, sputtering, or the like.

[0072] Next, an oxide or nitride such as SiN, SiO2, or SiON is deposited by sputtering as the back-gate-side insulating film 104 so as to cover the back-gate electrode 103. Here, the back-gate-side insulating film 104 is deposited to a thickness of about 1 to 20 nm in addition to the usual thickness (1 to 10 nm), taking into consideration the film thickness to be removed by chemical mechanical polishing in the next step.

[0073] Next, the surface of the back-gate side insulating film 104 is planarized by chemical mechanical polishing or the like in order to bond it well to the sacrificial substrate.

[0074] Next, the surface of the back-gate side channel layer 105 of the laminated structure on the sacrificial substrate and the surface of the back-gate side insulating film 104 of the laminated structure on the semi-insulating InP substrate 101 for the device are bonded together so as to face each other.

[0075] Next, the sacrificial substrate and the buffer layer are removed by chemical mechanical polishing or etching, resulting in a laminated structure from the buffer layer 102 to the top gate side channel layer 107 being formed on the semi-insulating InP substrate 101.

[0076] Next, n-type InAlAs or the like is deposited (crystal grown) on the top gate side channel layer 107.

[0077] Next, a source electrode 111 and a drain electrode 113 are formed on the n-type InAlAs or the like by vapor deposition of a metal such as Ti, Pt, or Au and photolithography.

[0078] Next, a portion of the n-type InAlAs or the like between the source electrode 111 and the drain electrode 113 is removed by photolithography and etching to expose the surface of the top gate side channel layer 107 and form a cap recess 114. This forms a first ohmic cap layer 109 on which the source electrode 111 is disposed and a second ohmic cap layer 110 on which the drain electrode 113 is disposed.

[0079] Next, a top-gate-side insulating film 108 made of an oxide or nitride (film thickness: 1 to 10 nm) such as SiN, SiO2, or SiON is formed on a part of the top-gate-side channel layer 107 in the cap recess 114 by sputtering, photolithography, or the like.

[0080] Next, outside the mesa structure 117 of the field-effect transistor 10, a through-hole is formed that penetrates vertically from the top-gate-side insulating film 108 to the end (feed portion) of the back gate electrode 103 in the back-gate-side insulating film 104. Subsequently, a conductive material such as Au is filled into the through-hole to form the inter-electrode connection portion 116. As a result, one end of the inter-electrode connection portion 116 is electrically connected to the end of the back gate electrode 103.

[0081] Finally, the top gate electrode 112 is formed on the top gate side insulating film 108 in the cap recess 114, directly above the back gate electrode 103. Here, an end (feed portion) 118 of the top gate electrode 112 is disposed at the other end of the inter-electrode connection portion 116 and electrically connected.

[0082] <Effects> According to the field-effect transistor of this embodiment, by providing a channel layer on the back gate side and the top gate side, a high current driving force can be obtained and high frequency characteristics can be improved without increasing the gate width or gate resistance. In addition, circuits using the field-effect transistor can be highly integrated.

[0083] <Modification of the first embodiment> A field effect transistor according to a modification of the first embodiment of the present invention will be described below.

[0084] The field effect transistor according to this modification has the same configuration as that of the first embodiment, but is manufactured using a different method.

[0085] <Field-effect transistor manufacturing method> A method for manufacturing a field effect transistor according to this modification will be described below.

[0086] First, a buffer layer (eg, InAlAs) 102 is laminated on a semi-insulating InP substrate 101 for a device, and then a back gate electrode 103 and a back gate side insulating film 104 are formed.

[0087] Next, outside the mesa structure 117 of the field effect transistor, a part of the back-gate side insulating film 104 is etched to form an opening, and the buffer layer 102 is exposed.

[0088] Next, the same material as the buffer layer 102 (for example, InAlAs) is grown to fill the exposed buffer layer 102 in the opening.

[0089] Next, the back-gate side channel layer 105 is grown using the buried grown crystal (for example, InAlAs) as a nucleus.

[0090] Subsequently, the second barrier layer 106 including the δ-doped layer 115 and the top gate side channel layer 107 are grown in this order by metal organic chemical vapor deposition or molecular beam epitaxy.

[0091] Finally, similar to the first embodiment, a first ohmic cap layer 109, a second ohmic cap layer 110, a source electrode 111, a drain electrode 113, a cap recess 114, a top gate side insulating film 108, an inter-electrode connection portion 116, and a top gate electrode 112 are formed.

[0092] According to the field effect transistor of this modification, a lamination structure from the substrate to the ohmic cap layer can be fabricated through a series of lamination steps without requiring a bonding step, and therefore the field effect transistor can be easily manufactured.

[0093] <Second embodiment> A field effect transistor according to a second embodiment of the present invention will be described with reference to FIG.

[0094] <Configuration of field-effect transistor> 2, the field-effect transistor 20 according to this embodiment has a recess region (a region where the back-gate insulating film is not disposed, hereinafter referred to as a "back-gate recess") 219 in the first barrier layer 204 around the second gate electrode (back-gate electrode) 203. The other configurations are the same as those of the first embodiment.

[0095] <Field-effect transistor manufacturing method> An example of a method for manufacturing the field effect transistor 20 according to this embodiment will be described below.

[0096] First, a buffer layer 202 is laminated on a substrate (for example, semi-insulating InP) 201, and then a back gate electrode 203 is formed.

[0097] Next, a photoresist that dissolves in an organic solvent is applied on the buffer layer 202 so as to cover the back gate electrode 203, and then a photoresist pattern is formed as a sacrificial film in the region around the back gate electrode 203 (the region corresponding to the back gate recess 219) by a lithography process. Here, the thickness of the sacrificial film (photoresist pattern) is equal to or less than the thickness of the back gate electrode 203.

[0098] Next, a first barrier layer 204 made of an oxide such as SiN, SiO2, SiON, Al2O3, HfO2, or TiO2, a nitride, or a laminate film thereof is deposited.

[0099] Next, similarly to the first embodiment, a stacked structure is formed of a first channel layer (back-gate side channel layer) 205, a second barrier layer 206 including a δ-doped layer 215, and a second channel layer (top-gate side channel layer) 207. Here, similarly to the first modification of the first embodiment, a stacked structure may be formed.

[0100] Next, a through-hole reaching the sacrificial film is formed by lithography and etching in a position that will not affect the device characteristics, such as outside the mesa structure of the field-effect transistor. Subsequently, an organic solvent is injected into the sacrificial film through the through-hole, dissolving and removing the sacrificial film made of photoresist.

[0101] Here, the length of the back-gate-side recess 219 is set to 10 to 200 nm, similar to the length of the cap recess (recess on the top-gate side) 214. Here, the length of the back-gate-side recess 219 does not have to be the same as the length of the cap recess 214, and may be set in consideration of a trade-off between the mechanical strength of the stacked structure and the effect of reducing parasitic capacitance.

[0102] Furthermore, as shown in FIG. 2, the first barrier layer 204 may remain outside the back-gate recess 219.

[0103] Finally, similar to the first embodiment, a first ohmic cap layer 209, a second ohmic cap layer 210, a source electrode 211, a drain electrode 213, a cap recess 214, a third barrier layer 208, an inter-electrode connection 216, and a top gate electrode 212 are formed.

[0104] According to the field effect transistor of this embodiment, the parasitic capacitance component caused by the back gate electrode can be reduced, and high frequency characteristics can be improved.

[0105] <Third embodiment> A field effect transistor according to a third embodiment of the present invention will be described with reference to FIG.

[0106] <Configuration of field-effect transistor> 3, in the field-effect transistor 30 according to this embodiment, the second channel layer (top-gate side channel layer) 307 and the first channel layer (back-gate side channel layer) 305 are made of different materials. The other configurations are the same as those in the first embodiment.

[0107] The top gate side channel layer 307 is, for example, In 0。53 Ga 0。47 As.

[0108] The back gate side channel layer 305 is made of, for example, In 0.8 Ga 0.2 It is a pseudomorphic channel (a channel in which strain is applied due to lattice mismatch) made of As or InAs.

[0109] As a result, the barrier height decreases from the top gate side channel layer 307 to the second barrier layer 306 during carrier injection, thereby increasing the efficiency of carrier injection into the back gate side channel layer 305 and making the access resistance approximately the same as that of the top gate side channel layer 307.

[0110] According to the field-effect transistor of this embodiment, the current driving force of the top-gate side channel layer and the back-gate side channel layer can be made approximately the same, and the current driving force of the entire field-effect transistor can ideally be doubled without increasing the gate width.

[0111] Alternatively, the composition of each channel layer can be set to an optimum value so that the mobility of the back-gate side channel layer and the top-gate side channel layer is appropriately combined depending on the desired high-frequency characteristics, thereby further improving the high-frequency characteristics.

[0112] In detail, the top gate side channel layer 307, which is located at a short distance (access distance) from the ohmic electrodes (source electrode 311, drain electrode 313), is doped with InP lattice-matched to the InP substrate 301. 0.53 Ga 0.47 On the other hand, in the back gate side channel layer 305, which has a long access distance, In, which has a relatively high electron mobility, is used. 0.7 Ga 0.3 As, In 0.8 Ga 0.2 As or InAs is used.

[0113] This makes it possible to equalize the delay time of carriers traveling through the top gate side channel layer 307 and the back gate side channel layer 305, thereby reducing the carrier delay time difference during amplification operation and reducing output distortion.

[0114] Alternatively, the delay times in both channels may be made equal by independently optimizing the gate length of the top gate electrode 312 and the gate length of the back gate electrode 303 .

[0115] <Fourth embodiment> A field effect transistor according to a fourth embodiment of the present invention will be described with reference to FIG.

[0116] <Configuration of field-effect transistor> 4, the field-effect transistor 40 according to this embodiment includes, in this order, a semiconductor substrate 401, a buffer layer 402, a first barrier layer 404, a first channel layer (back-gate side channel layer) 405, a second barrier layer 406, a second channel layer (top-gate side channel layer) 407, and a third barrier layer 408. Here, a δ-doped layer 415 is provided in the second barrier layer 406. Also, a back-gate electrode 403 is provided in the first barrier layer 404.

[0117] Furthermore, a first ohmic cap layer 409 and a source electrode 411 are provided in this order at a predetermined position (one position) on the surface of the third barrier layer 408 (the surface opposite to the second channel layer 407), and a second ohmic cap layer 410 and a drain electrode 413 are provided in this order at another position.

[0118] Here, the source electrode 411 and the drain electrode 413 have a metal layer structure consisting of Ti, Pt, and Au, and form ohmic contact with the third barrier layer 408 via the first ohmic cap layer 409 and the second ohmic cap layer 410, respectively.

[0119] Furthermore, a first gate electrode (top gate electrode) 412 is provided on the surface of the third barrier layer 408 between the first ohmic cap layer 409 and the second ohmic cap layer 410, that is, between the source electrode 411 and the drain electrode 413.

[0120] Here, the first barrier layer 404 and the third barrier layer 408 are made of i-InAlAs. The first barrier layer 404 and the third barrier layer 408 may also be made of a semiconductor such as InP. Hereinafter, the first barrier layer 404 and the third barrier layer 408 will also be referred to as the "back-gate side barrier layer" and the "top-gate side barrier layer," respectively. The other configurations are the same as those in the first embodiment.

[0121] Here, the first barrier layer 404 may be a semiconductor having a lattice constant that is larger in energy gap than the first channel layer 405 and that does not deteriorate the crystal quality (for example, a range in which lattice relaxation does not occur). The third barrier layer 408 may be a semiconductor having a lattice constant that is larger in energy gap than the second channel layer 407 and that does not deteriorate the crystal quality (for example, a range in which lattice relaxation does not occur).

[0122] Furthermore, in order to increase the current driving force by increasing the carrier supply source, delta-doped layers 420 and 421 doped with a high concentration of Si may be formed in the back-gate side barrier layer 404 and the top-gate side barrier layer 408.

[0123] The δ-doped layer 415 in the second barrier layer 406 not only supplies carriers to the first channel layer 405 and the second channel layer 407, but also locally lowers the conduction band, thereby increasing the carrier tunneling probability and reducing the access resistance from the ohmic electrodes (source electrode 411, drain electrode 413) to the second channel layer 407.

[0124] Similarly, the δ-doped layer 420 in the back-gate-side barrier layer 404 and the δ-doped layer 421 in the top-gate-side barrier layer 408 supply carriers to the first channel layer 405 and the second channel layer 407. Here, the δ-doped layer may be formed in either the back-gate-side barrier layer 404 or the top-gate-side barrier layer 408, depending on the trade-off between carrier supply, reduced access resistance, and process conditions.

[0125] For example, the δ-doped layer 421 in the top-gate-side barrier layer 408 is expected to reduce the access resistance to the top-gate-side channel layer 407. On the other hand, even if the δ-doped layer 420 is formed in the back-gate-side barrier layer 404, the δ-doped layer 420 is located below the back-gate-side channel layer 405, so the introduction of the δ-doped layer 420 cannot be expected to reduce the access resistance.

[0126] Therefore, if carriers are sufficiently supplied from the δ-doped layer 415 in the second barrier layer 406 to the back-gate-side channel layer 405, it is not necessary to form the δ-doped layer 420 in the back-gate-side barrier layer 404. This makes it possible to omit the step of forming the δ-doped layer 420 in the back-gate-side barrier layer 404, thereby simplifying the manufacturing process.

[0127] The delta-doped layer 420 in the back-gate-side barrier layer 404 and the delta-doped layer 421 in the top-gate-side barrier layer 408 are formed in the center of both barrier layers 404, 408. Here, the delta-doped layers 420, 421 do not have to be formed in the center of the barrier layers, and their positions may be determined by a trade-off between the amount of carriers supplied to the channel layer and a reduction in access resistance.

[0128] For example, the closer the δ-doped layer 421 in the top-gate-side barrier layer 408 is to the top-gate-side channel layer 407, the more carriers it supplies to the top-gate-side channel layer 407. On the other hand, the closer the δ-doped layer 421 is to the ohmic electrodes (the source electrode 411 and the drain electrode 413), the greater the effect of reducing the access resistance.

[0129] Furthermore, by changing not only the position of the δ-doped layer but also the thickness of each barrier layer, it is possible to obtain a desired amount of carrier supply and a desired effect of reducing the access resistance.

[0130] Furthermore, the δ-doped layer 420 in the back-gate-side barrier layer 404 may be disposed at a position close to the back-gate-side channel layer 405 in order to increase the amount of carriers supplied to the back-gate-side channel layer 405 .

[0131] <Field-effect transistor manufacturing method> An example of a method for manufacturing the field effect transistor 40 according to this embodiment will be described below.

[0132] First, a buffer layer 402 is laminated on a substrate (for example, semi-insulating InP) 401, and then a back gate electrode 403 is formed.

[0133] Next, the growth of the back-gate-side barrier layer 404 made of InAlAs, InP, or the like is started using the buffer layers 402 on both sides of the back-gate electrode 403 as a base, and continues until it completely covers the back-gate electrode 403. Here, the δ-doped layer 420 in the back-gate-side barrier layer 404 is formed after the back-gate electrode 403 is completely covered with the back-gate-side barrier layer 404.

[0134] Next, the back-gate side channel layer 405, the second barrier layer 406 including the δ-doped layer 415, the top-gate side channel layer 407, and the top-gate side barrier layer 408 including the δ-doped layer 421 are crystal-grown in this order by metal organic chemical vapor deposition, molecular beam epitaxy, or the like.

[0135] Next, n-type InAlAs or the like is deposited (crystal grown) on the top gate side barrier layer 408.

[0136] Next, a source electrode 411 and a drain electrode 413 are formed on the n-type InAlAs or the like by vapor deposition of a metal such as Ti, Pt, or Au and photolithography.

[0137] Next, a portion of the n-type InAlAs or the like between the source electrode 411 and the drain electrode 413 is removed by photolithography and etching to expose the surface of the top gate-side barrier layer 408 and form a cap recess 414. This forms a first ohmic cap layer 409 on which the source electrode 411 is disposed and a second ohmic cap layer 410 on which the drain electrode 413 is disposed.

[0138] Next, outside the mesa structure of the field-effect transistor 40, a through-hole is formed that penetrates vertically from the top-gate-side barrier layer 408 to the end (feed portion) of the back-gate electrode 403 in the back-gate-side barrier layer 404. Subsequently, a conductive material such as Au is filled into the through-hole to form an inter-electrode connection portion 416. As a result, one end of the inter-electrode connection portion 416 is electrically connected to the end of the back-gate electrode 403.

[0139] Finally, a top gate electrode 412 is formed on the top gate side barrier layer 408 in the cap recess 414, directly above the back gate electrode 403. Here, an end (feed portion) of the top gate electrode 412 is disposed at the other end of the inter-electrode connection portion 416 and electrically connected.

[0140] According to the field-effect transistor of this embodiment, layers from the buffer layer to the top-gate-side barrier layer can be stacked on the semiconductor substrate through a series of crystal growth processes, so that the two channel layers (the top-gate-side channel layer and the back-gate-side channel layer) can be grown while retaining the lattice order of the semiconductor substrate, thereby achieving high quality, i.e., high mobility, in both channel layers. This allows for even higher current driving power and improved high-frequency characteristics.

[0141] Furthermore, since the wafer bonding method is not used, there is no need to prepare a sacrificial InP substrate, which reduces the manufacturing cost.

[0142] In the field-effect transistor according to this embodiment, either the first barrier layer 404 or the third barrier layer 408 may be a semiconductor layer, and the other may be an insulating film such as an oxide film. A field-effect transistor having this configuration may be fabricated using, for example, a wafer bonding technique.

[0143] For example, after forming a buffer layer 402 and a back gate electrode 403 on a semiconductor substrate 401, a first barrier layer 404 is deposited. Here, the first barrier layer 404 is made of an oxide such as SiN, SiO, SiON, AlO, HfO, or TiO, a nitride, or a laminated film thereof.

[0144] On the other hand, a buffer layer, a third barrier layer (top-gate side barrier layer) 408 consisting of a semiconductor layer including a δ-doped layer 421, a top-gate side channel layer 407, a second barrier layer 406 including a δ-doped layer 415, and a back-gate side channel layer 405 are stacked on a sacrificial InP substrate by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like.

[0145] Subsequently, as in the first embodiment, the sacrificial substrate is bonded to a semi-insulating InP substrate for a device, and then the sacrificial substrate and the buffer layer are removed to form a layered structure from the semiconductor substrate 401 to the top gate-side barrier layer 408. Thereafter, a first ohmic cap layer 409, a second ohmic cap layer 410, a source electrode 411, a drain electrode 413, a cap recess 414, an inter-electrode connection 416, and a top gate electrode 412 are formed.

[0146] This allows two channel layers (a top-gate channel layer and a back-gate channel layer) to be grown on the sacrificial substrate through a series of crystal growth processes while retaining the lattice order of the semiconductor substrate. As a result, high quality, i.e., high mobility, can be achieved in both channel layers in the stacked structure on the semi-insulating InP substrate for devices after the bonding process.

[0147] In this embodiment, a recess region may be formed around the back gate electrode, similarly to the second embodiment.

[0148] In this embodiment, similarly to the third embodiment, the second channel layer (top gate side channel layer) and the first channel layer (back gate side channel layer) may be made of different materials.

[0149] In this embodiment, similarly to the first embodiment, a first ohmic capping layer and a second ohmic capping layer may be disposed on the second channel layer, respectively. In this configuration, the source electrode and the drain electrode form ohmic contact with the second channel layer via the first ohmic capping layer and the second ohmic capping layer, respectively.

[0150] In this embodiment, the first barrier layer, the second barrier layer, and the third barrier layer may be made of different materials (semiconductors).

[0151] <Fifth embodiment> A field effect transistor according to a fifth embodiment of the present invention will be described with reference to FIG.

[0152] <Configuration of field-effect transistor> 5, a field-effect transistor 50 according to this embodiment includes, in this order, a semiconductor substrate 501, a first buffer layer 502, a first barrier layer (back-gate side barrier layer) 504, a first channel layer (back-gate side channel layer) 505, a second barrier layer 506, a second channel layer (top-gate side channel layer) 507, and a third barrier layer (top-gate side barrier layer) 508. A back-gate electrode 503 is also provided in the first barrier layer (back-gate side barrier layer) 504.

[0153] Here, the second barrier layer 506 is a semiconductor such as InAlAs, and is made of a material that is approximately lattice-matched to the semiconductor substrate, similar to the buffer layer. The other configurations are the same as those in the fourth embodiment.

[0154] Generally, a buffer layer is introduced for the purpose of forming a high-quality channel layer with extremely little lattice distortion. Therefore, in this embodiment, by introducing the same material as the buffer layer as the second barrier layer 506, it is possible to improve the quality, i.e., mobility, of both or either of the back-gate-side channel layer 505 and the top-gate-side channel layer 507.

[0155] Thus, a material that is "approximately lattice-matched" to a semiconductor substrate refers to a material that has a lattice constant in a range that does not cause degradation of crystal quality due to the occurrence of dislocations or defects when growing crystals on the semiconductor substrate.

[0156] For example, when a device is fabricated by a wafer bonding method using a sacrificial InP substrate, a top-gate-side barrier layer 508 and a top-gate-side channel layer 507 are formed on the sacrificial substrate in this order, followed by forming a second barrier layer 506 made of the same material as the buffer layer, and then growing a back-gate-side channel layer 505.

[0157] This allows the quality of the back-gate side channel layer 505 to be improved.

[0158] Alternatively, when each layer is grown sequentially on a substrate by a series of crystal growth processes, after forming the first buffer layer 502 to the back-gate side channel layer 505, a second barrier layer 506 made of the same material as the buffer layer is formed, and then a top-gate side channel layer 507 is grown.

[0159] This allows the quality of the top gate side channel layer 507 to be improved.

[0160] In the field-effect transistor 50 according to this embodiment, the stacked structure from the substrate 501 to the top-gate-side barrier layer 508 can also be fabricated by the following method.

[0161] First, an InP sacrificial substrate is prepared for growing the back-gate side channel layer 505, and a buffer layer (including the second barrier layer 506) and the back-gate side channel layer 505 are crystal-grown on the sacrificial substrate by metal organic chemical vapor deposition or molecular beam epitaxy.

[0162] On the other hand, a buffer layer 502, a back gate electrode 503, and a back gate side barrier layer 504 including a δ-doped layer 520 are formed on a semi-insulating InP substrate 501 for a device.

[0163] Next, the surface of the back-gate side channel layer 505 on the sacrificial substrate and the surface of the back-gate side barrier layer 504 on the semi-insulating InP substrate 501 for the device are bonded together so as to face each other.

[0164] Next, the InP sacrificial substrate and part of the buffer layer are removed by etching or chemical mechanical polishing to expose the second barrier layer 506 on the surface.

[0165] Next, using the exposed second barrier layer 506 as a base, a top gate side channel layer 507 and a top gate side barrier layer 508 are laminated.

[0166] This allows both the back-gate side channel layer 505 and the top-gate side channel layer 507 to be grown on the same material as the buffer layer (the second barrier layer 506), thereby improving the quality of both channel layers.

[0167] Furthermore, in this embodiment, a δ-doped layer 515 may be formed in the second barrier layer 506. This allows for the supply of carriers to the top-gate-side channel layer 507 and the back-gate-side channel layer 505 by the δ-doped layers 521 and 520 in the top-gate-side barrier layer 508 and the back-gate-side barrier layer 504, and further allows for the supply of carriers, thereby reducing the access resistance to the back-gate-side channel layer 505.

[0168] Furthermore, multiple δ-doped layers may be formed in the second barrier layer 506 to the extent that the quality of the top-gate-side channel layer 507 and the back-gate-side channel layer 505 can be maintained. This locally lowers the conduction band in the second barrier layer 506, allowing carriers to be efficiently injected into the back-gate-side channel layer 505 with low access resistance. In this way, the second barrier layer 506 (layer thickness: 100 to 300 nm) is thicker than the barrier layer, further reducing the access resistance to the back-gate-side channel layer 505.

[0169] According to the field-effect transistor of this embodiment, the crystal quality of at least one of the first channel layer (back-gate side channel layer) and the second channel layer (top-gate side channel layer) can be improved, and a higher current driving force can be obtained, thereby improving the high-frequency characteristics.

[0170] In the embodiment of the present invention, an example of an InP-based field effect transistor using an InP substrate is shown, but the present invention is not limited to this and can also be applied to a GaAs-based field effect transistor using a GaAs substrate, as well as to field effect transistors using other semiconductors such as GaN, InSb, and SiGe.

[0171] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc. of each component in the configuration and manufacturing method of the field effect transistor are shown, but the present invention is not limited to these examples. Anything that can exhibit the function and effect of a field effect transistor can be used. [Industrial Applicability]

[0172] The present invention relates to high-frequency electronic devices and can be applied to next-generation high-speed wireless communications, non-destructive testing using terahertz wave imaging, security applications using transmitted images, and material analysis using absorption spectra. [Explanation of symbols]

[0173] 10 Field-effect transistor 103 Second gate electrode 104 First Barrier Layer 105 First channel layer 106 Second Barrier Layer 107 Second Channel Layer 108 Third Barrier Layer 111 Source electrode 112 first gate electrode 113 Drain electrode

Claims

1. On the surface, in order, a source electrode; a first gate electrode; Drain electrode and Equipped with In a direction perpendicular to the surface, a first barrier layer; and a second gate electrode disposed within the first barrier layer; a first channel layer made of a semiconductor; a second barrier layer made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer; a second channel layer made of a semiconductor having a smaller energy gap than the second barrier layer; a third barrier layer; and the first gate electrode; Equipped with The first barrier layer and the third barrier layer are made of an insulating film. A field effect transistor characterized by:

2. A source electrode and a a first gate electrode; Drain electrode and Equipped with In a direction perpendicular to the surface, a first barrier layer; and a second gate electrode disposed within the first barrier layer; a first channel layer made of a semiconductor; a second barrier layer made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer; a second channel layer made of a semiconductor having an energy gap smaller than that of the second barrier layer; a third barrier layer; and the first gate electrode; Equipped with A recessed region is provided around the second gate electrode to reduce parasitic capacitance caused by the second gate electrode. A field effect transistor characterized by:

3. A source electrode and a a first gate electrode; Drain electrode and Equipped with In a direction perpendicular to the surface, a first barrier layer; and a second gate electrode disposed within the first barrier layer; a first channel layer made of a semiconductor; a second barrier layer made of a semiconductor having a larger energy gap than the first channel layer and including a δ-doped layer; a second channel layer made of a semiconductor having an energy gap smaller than that of the second barrier layer; a third barrier layer; and the first gate electrode; Equipped with The energy gap of the first channel layer is smaller than the energy gap of the second channel layer. A field effect transistor characterized by:

4. a first ohmic cap layer disposed between the second channel layer and the source electrode and made of a semiconductor to form an ohmic contact between the second channel layer and the source electrode; a second ohmic cap layer made of a semiconductor and disposed between the second channel layer and the drain electrode, the second ohmic cap layer forming an ohmic contact with the second channel layer; The field effect transistor according to claim 1 , comprising:

5. The first gate electrode and the second gate electrode are electrically connected.

4. The field effect transistor according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. At least one of the first barrier layer and the third barrier layer is made of a semiconductor having a larger energy gap than the first channel layer or the second channel layer.

4. The field effect transistor according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. the third barrier layer is made of a semiconductor having a larger energy gap than the second channel layer, a first ohmic cap layer disposed between the third barrier layer and the source electrode and forming an ohmic contact with the third barrier layer; a second ohmic cap layer disposed between the third barrier layer and the drain electrode and forming an ohmic contact with the third barrier layer; The field effect transistor according to claim 1 , comprising:

8. a buffer layer, and a second barrier layer, disposed on a surface of the first barrier layer opposite to the surface of the first channel layer. Semiconductor substrate and Equipped with The second barrier layer is substantially lattice-matched to the semiconductor substrate.

4. The field effect transistor according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. A step of growing crystals of a second channel layer, a second barrier layer, and a first channel layer in that order on a semiconductor sacrificial substrate; forming, in order, a second gate electrode and a first barrier layer covering the second gate electrode on the semiconductor substrate; a step of bonding a surface of the first channel layer and a surface of the first barrier layer so that they face each other; removing the semiconductor sacrificial substrate; forming a third barrier layer and a first gate electrode, in that order, on the surface of the second channel layer after removing the semiconductor sacrificial substrate; Equipped with the first channel layer is made of a semiconductor, the second barrier layer is made of a semiconductor having a larger energy gap than the first channel layer and includes a δ-doped layer; the second channel layer is made of a semiconductor having a smaller energy gap than the second barrier layer, the first barrier layer and the third barrier layer are made of an insulating film; The semiconductor sacrificial substrate and the semiconductor substrate are made of the same semiconductor material.

2. A method for manufacturing a field effect transistor comprising:

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