Semiconductor Devices

Abstract

The present invention suppresses a fracture mode that leads to breakage of a device in cases where a gallium nitride high-electron-mobility transistor is used as a power device. According to the present invention, a diode is connected in inverse parallel with an HEMT, and this inverse parallel connected diode is designed such that avalanche breakdown occurs therein before the drain-source voltage, which is the difference between the drain potential applied to a drain electrode 130 and the source potential applied to a source electrode 120, exceeds the breakdown voltage of the HEMT.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including, for example, a high electron mobility transistor and a diode. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2007-226475 (Patent Document 1) describes a semiconductor device that integrates a GaN-based field-effect transistor and a diode as its protection element. In particular, gallium nitride (GaN), silicon carbide (SiC), and silicon (Si) are exemplified as substrates on which the diodes are formed, and the Schottky diode is formed on the back surface of the substrate opposite to the element formation surface.

[0003] Japanese Patent Laid-Open Publication No. 2009-004398 (Patent Document 2) describes a semiconductor device that integrates a GaN-based lateral high electron mobility transistor and a diode, including a silicon-based lateral pn junction diode, a silicon-based vertical Schottky diode, and a silicon carbide-based vertical Schottky diode.

[0004] Japanese Patent Laid-Open Publication No. 2010-010262 (Patent Document 3) describes a semiconductor device that integrates a GaN-based lateral high electron mobility transistor and a pn junction diode formed on a silicon substrate. Here, the pn junction diode is a lateral pn junction diode formed by ion implantation into the silicon substrate.

[0005] Japanese Patent Laid-Open Publication No. 2010-267958 (Patent Document 4) describes a semiconductor device that integrates a GaN-based lateral high electron mobility transistor and a pn junction diode, where the pn junction diode is a GaN-based lateral pn junction diode and a silicon-based vertical pn junction diode.

[0006] Japanese Patent Laid-Open Publication No. 2019-004084 (Patent Document 5) describes a semiconductor device that integrates an element in which a GaN-based lateral high electron mobility transistor and a silicon carbide-based vertical junction field-effect transistor are connected in series on a silicon carbide substrate. Here, the drain electrode of the silicon carbide-based junction field-effect transistor is formed on the back surface of the silicon carbide substrate opposite the element formation surface, and therefore the current path is in the thickness direction of the silicon carbide substrate.

[0007] Non-Patent Document 1 describes a technique for epitaxially growing an AlGaN / GaN HEMT structure on a silicon carbide substrate with an off-angle of 0 to 2 degrees. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-226475 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-004398 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-010262 [Patent Document 4] Japanese Patent Application Laid-Open No. 2010-267958 [Patent Document 5] Japanese Patent Application Publication No. 2019-004084 [Non-patent literature]

[0009] [Non-Patent Document 1] M. Leszczynski et al., ECS Transactions, 50 (3), (2012), pp.163-171 [Non-patent document 2] EA Jones et al., IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 4, NO. 3, SEPTEMBER 2016, pp.707-719

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Non-Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0010] In recent years, achieving more efficient energy use has become an important and urgent issue toward a low-carbon society. To achieve this, the development of power devices for power converters, such as inverters, is crucial, as they can contribute to reducing power losses. In response to this trend, nitride semiconductors such as SiC (silicon carbide) and GaN (gallium nitride) are being considered as alternatives to silicon (Si) as power device materials. SiC and nitride semiconductors have larger breakdown field strengths and bandgaps than Si, enabling the provision of high-performance power devices that achieve both low on-resistance and high dielectric strength. Furthermore, nitride semiconductors can be used to fabricate high-electron mobility transistors (HEMs) using heterojunctions such as AlGaN / GaN. These heterojunctions offer superior high-frequency characteristics compared to SiC power MOSFETs, making them advantageous for compact, high-frequency applications in power converters.

[0011] However, in high electron mobility transistors that use nitride semiconductors as power device materials, when a drain-source voltage exceeding the breakdown voltage is applied, a breakdown mode occurs in which recovery does not occur, called avalanche breakdown, but rather leads to destruction.As a result, when using gallium nitride-based high electron mobility transistors as power devices, it is desirable to suppress the breakdown mode that leads to device destruction. [Means for solving the problem]

[0012] A semiconductor device in one embodiment includes a pn junction diode formed on a silicon carbide substrate, and a high electron mobility transistor formed on the pn junction diode.

[0013] Here, the pn junction diode includes a silicon carbide epitaxial layer of a first conductivity type formed on a silicon carbide substrate, and an electric field relaxation region of a second conductivity type that is opposite in conductivity to the first conductivity type and is formed in the silicon carbide epitaxial layer.

[0014] In contrast, a high electron mobility transistor includes a channel layer made of a first nitride semiconductor layer, a barrier layer made of a second nitride semiconductor layer in contact with the channel layer, a buffer layer provided between the channel layer and the silicon carbide epitaxial layer and made of a third nitride semiconductor layer having a larger band gap than the silicon carbide epitaxial layer, a source electrode in contact with a first region of the barrier layer, a drain electrode in contact with a second region of the barrier layer, and a gate electrode provided between the source electrode and the drain electrode.

[0015] In this case, the silicon carbide epitaxial layer is electrically connected to the source electrode, and the electric field relaxation region is electrically connected to the drain electrode, and in plan view, the electric field relaxation region includes a region extending beyond the drain electrode. [Effects of the Invention]

[0016] According to one embodiment, it is possible to prevent breakdown of the high electron mobility transistor. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 is a diagram illustrating a configuration example of a switching circuit. [Figure 2] FIG. 1 is a diagram showing a UIS test circuit. [Figure 3] 1 is a cross-sectional view showing the configuration of a semiconductor device based on a basic concept. [Figure 4] 1 is a plan view showing a configuration of a semiconductor device based on a basic concept; [Figure 5] FIG. 10 is a cross-sectional view showing a modified example of a semiconductor device based on the basic concept. [Figure 6] FIG. 10 is a plan view showing a modified example of the semiconductor device based on the basic concept. [Figure 7] FIG. 1 is a diagram showing a device structure for which a simulation was performed. [Figure 8] 10 is a graph showing a simulation result. [Figure 9] 10 is a graph showing evaluation results of a withstand voltage test in an off state. [Figure 10]10 is a graph showing the results of multiple sweeps in a pressure resistance test. [Figure 11] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment; [Figure 12] 1 is a flowchart showing a flow of a manufacturing process of a semiconductor device. [Figure 13] 10 is a graph showing experimental results of Id-Vds characteristics in the on-state. [Figure 14] 10 is a graph showing experimental results of transfer characteristics at Vds=5V. [Figure 15] 10 is a graph showing experimental results of Id-Vds characteristics with respect to negative Vds when Vgs=−4V. [Figure 16] FIG. 10 is a cross-sectional view showing a modified example. [Figure 17] FIG. 10 is a cross-sectional view showing a modified example. [Figure 18] FIG. 10 is a cross-sectional view showing a modified example. [Figure 19] FIG. 10 is a cross-sectional view showing a modified example. [Figure 20] FIG. 10 is a cross-sectional view showing a modified example. [Figure 21] FIG. 10 is a cross-sectional view showing a modified example. [Figure 22] 10 is a graph showing a simulation result. DETAILED DESCRIPTION OF THE INVENTION

[0018] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0019] <Example of switching circuit configuration> FIG. 1 is a diagram illustrating an example of the configuration of a switching circuit.

[0020] 1, a switching circuit 10 includes a power transistor Q1 and a diode FRD, which are connected in anti-parallel. That is, the power transistor Q1 has a gate electrode G, a source S, and a drain D, while the diode FRD has an anode A and a cathode C. The source S of the power transistor Q1 is electrically connected to the anode A of the diode FRD, while the drain D of the power transistor Q1 is electrically connected to the cathode C of the diode FRD. A gate control circuit (not shown) is connected to the gate electrode G of the power transistor Q1 configured in this manner, and this gate control circuit controls the switching operation (on / off operation) of the power transistor Q1.

[0021] <Types of switching elements> For example, the power transistor Q1 may be a power MOSFET, an IGBT (Insulated Gate Bipolar Transistor), a junction field effect transistor (JFET), or a high electron mobility transistor (HEMT).

[0022] <Diode> For example, when an IGBT is used as the power transistor Q1, it is necessary to provide a diode FRD connected in anti-parallel to the IGBT.

[0023] From the perspective of simply realizing a switching function using the power transistor Q1, an IGBT is required as the power transistor Q1, but it is not considered necessary to provide the diode FRD. In this regard, if the load connected to the switching circuit 10 includes an inductance, such as when the load is a motor, it is necessary to provide the diode FRD. The reason for this will be explained below.

[0024] The diode FRD is unnecessary if the load is a pure resistor that does not contain inductance, since there is no energy to return. However, if the load is connected to a circuit that contains inductance, such as a motor, there is a mode (freewheel mode) in which the load current flows in the opposite direction to the on switch. In other words, if the load contains inductance, energy may return from the load inductance to the switching circuit 10 (current may flow backward).

[0025] At this time, the IGBT alone does not have the function to allow this return current to flow, so it is necessary to connect a diode FRD in anti-parallel to the IGBT. That is, in the switching circuit 10, when the load includes an inductance, such as in motor control, the energy stored in the inductance (1 / 2LI) is released when the IGBT is turned off. 2 ) must be released. However, an IGBT alone cannot pass a reflux current to release the energy stored in the inductance. Therefore, a diode FRD is connected in anti-parallel to the IGBT to return the electrical energy stored in the inductance. In other words, the diode FRD has the function of passing a reflux current to release the electrical energy stored in the inductance. From the above, it can be seen that in a switching circuit 10 connected to a load including an inductance, if an IGBT is used as the power transistor Q1, it is necessary to provide a diode FRD in anti-parallel to the IGBT. This diode FRD is called a "freewheeling diode."

[0026] On the other hand, when a power MOSFET is used as the power transistor Q1, it is not necessary in principle to provide a freewheel diode connected in anti-parallel to the power MOSFET, because the device structure of a power MOSFET inevitably forms a body diode, which is a pn junction diode, parasitically, and this body diode functions as a freewheel diode.

[0027] Furthermore, unlike IGBTs, unipolar transistors (junction field-effect transistors, high electron mobility transistors, etc.) do not necessarily require a freewheel diode, regardless of whether they have a body diode or not. This is because the source and drain of a unipolar transistor have a symmetrical structure, allowing a freewheeling mode current to flow. Therefore, when focusing on high electron mobility transistors, it can be said that there is no need to provide a "freewheeling diode" for the original purpose of flowing a freewheeling current.

[0028] <Insights focusing on high electron mobility transistors> In the following, attention will be focused on a high electron mobility transistor (hereinafter sometimes referred to as a HEMT) using gallium nitride as the power transistor Q1.

[0029] In this case, as mentioned above, it can be said that it is not necessarily necessary to provide a "freewheel diode" in order to achieve the original purpose of flowing a return current.

[0030] Here, in a HEMT that uses gallium nitride crystals as the power device material, when a drain-source voltage exceeding the breakdown voltage is applied, a phenomenon unique to HEMTs occurs, which is a destruction mode that does not recover and leads to destruction, rather than a recoverable breakdown known as avalanche breakdown.As a result, when using gallium nitride HEMTs as power devices, it is important to suppress the destruction mode that leads to device destruction.

[0031] Gallium nitride crystals are also called Group III nitride semiconductors or nitride semiconductors, and are semiconductors represented by GaN, AlN, InN, and their mixed crystals (AlGaN, InGaN, etc.). The abbreviated names "gallium nitride system" and "GaN system" are also used.

[0032] Therefore, the present inventor is considering using the above-described "freewheel diode" from the perspective of suppressing the breakdown mode that leads to device breakdown in a gallium nitride-based HEMT. That is, the present inventor has focused on the "freewheel diode" which is not necessarily required for the original purpose of flowing a reflux current in a gallium nitride-based HEMT, and has come up with the idea of using this "freewheel diode" from the perspective of suppressing the breakdown mode that leads to the breakdown of the HEMT.

[0033] <Findings Focused on pn Junction Diodes> Hereinafter, as the diode FRD, attention is paid to a pn junction diode using silicon carbide. It has been found that a pn junction diode using silicon carbide can significantly reduce recovery loss compared to a silicon pn junction diode.

[0034] However, in diodes using silicon carbide, unipolar diodes called Schottky barrier diodes are the mainstream. There are very few practical examples of bipolar pn junction diodes. This is because when a current is passed in the forward direction through a pn junction diode using silicon carbide, device degradation called forward degradation occurs. Here, forward degradation is a phenomenon caused by an increase in originally existing crystal defects due to basal plane dislocations related to the SiC substrate.

[0035] Therefore, the present inventor is considering a lateral pn junction diode that conducts current in the lateral direction (horizontal direction on the substrate surface) from the perspective of suppressing forward degradation in a pn junction diode using silicon carbide. That is, the present inventor has come up with the idea of using a lateral pn junction diode that is not commonly used instead of the vertical (perpendicular to the substrate surface) pn junction diode commonly used in silicon carbide.

[0036] <Findings Focused on the Application of Power Transistors to Power Converters> Furthermore, in the following, we will proceed with our discussion on the assumption that non-destructive breakdown can be achieved by integrating a gallium nitride high electron mobility transistor with a pn junction diode. Specifically, we will focus on the situation in which a power transistor breaks down in its application to a power converter, and consider the device operation required in such a situation.

[0037] Switching tests using UIS (Unclamped Inductive Switching) circuits are commonly performed on power devices as a test to simulate situations that lead to breakdown. Figure 2 is a circuit diagram showing a UIS test circuit. In Figure 2, when a power transistor is turned on, energy is stored in an L load from a DC power supply. After a certain amount of energy has been stored, when the power transistor is turned off, the drain voltage jumps up, leading to breakdown. At this time, it is important that the power transistor undergoes a stable, non-destructive avalanche breakdown and is able to absorb the stored energy in the L load. Specifically, it is required that a breakdown current flows through breakdown current path A in Figure 2.

[0038] On the other hand, if current flows through breakdown current path B, the circuit malfunctions, the stable avalanche breakdown collapses, and the power transistor enters an oscillation mode where it repeatedly turns on and off. Specifically, when current flows through breakdown current path B, the gate voltage rises due to the finite gate resistance Rg, resulting in an oscillation mode where it repeatedly turns on and off erroneously. In particular, even in power transistors that are normally off, a negative voltage is applied to the gate electrode relative to the source electrode when the transistor is off to speed up turn-off. This causes the gate electrode to have the lowest potential, raising concerns about the inflow of holes generated by avalanche breakdown. Therefore, it is important to suppress the breakdown current flowing into the gate electrode of a power transistor.

[0039] The inventors therefore came up with a structure in which a buffer layer with a large band gap is placed between the gallium nitride HEMT and the above-mentioned "freewheel diode," thereby preventing the breakdown current generated in the "freewheel diode" from flowing into the HEMT.

[0040] <Basic Concept of the Embodiment> The following describes the technical concept based on the inventor's findings.

[0041] The basic idea of ​​this embodiment is to connect a diode in anti-parallel to a HEMT and design the diode so that it undergoes avalanche breakdown before the drain-source voltage, which is the difference between the drain potential applied to the drain electrode and the source potential applied to the source electrode, exceeds the breakdown voltage of the HEMT in its off state. The basic idea also includes the idea of ​​minimizing the flow of electrons and holes (especially holes) generated by the avalanche breakdown of the diode into the gate electrode of the HEMT.

[0042] According to this basic concept, the diode undergoes avalanche breakdown before the drain-source voltage exceeds the HEMT's breakdown voltage, thereby preventing the HEMT's breakdown mode, which occurs when the drain-source voltage exceeds the HEMT's breakdown voltage. In other words, the basic concept of this embodiment is that by designing the diode to undergo avalanche breakdown before the HEMT's breakdown voltage is exceeded, the drain-source voltage is clamped, preventing the HEMT from breaking down. Furthermore, the basic concept also includes the idea of ​​inserting a semiconductor layer between the diode and the HEMT that has a bandgap energy larger than the bandgap energy of the semiconductor that forms the diode, in order to prevent electrons and holes (especially holes) generated by avalanche breakdown from flowing into the gate electrode.

[0043] This basic concept focuses on the diode in a HEMT, which is not necessarily required for its original purpose of passing a return current, and actively utilizes this diode from the perspective of suppressing the breakdown modes that lead to the destruction of the HEMT. This effectively suppresses the occurrence of breakdown modes specific to HEMTs, and is an innovative and excellent technical concept in that it suppresses false turn-on when applied to actual power converters.

[0044] <Semiconductor device based on the basic concept> Next, a semiconductor device based on the above-mentioned basic concept will be described.

[0045] FIG. 3 is a cross-sectional view showing the configuration of a semiconductor device based on the basic concept.

[0046] As shown in FIG. 3, the semiconductor device based on the basic concept has a pn junction diode formed on a silicon carbide substrate 100, and a HEMT formed on the pn junction diode.

[0047] Specifically, the pn junction diode includes a p-type silicon carbide epitaxial layer 101 formed on a silicon carbide substrate 100, and an n-type electric field relaxation region (resurf region) 102 formed in the silicon carbide epitaxial layer 101. That is, a pn junction is formed in the boundary region between the p-type silicon carbide epitaxial layer 101 and the n-type electric field relaxation region 102, and as a result, the p-type silicon carbide epitaxial layer 101 and the n-type electric field relaxation region 102 form a pn junction diode. Here, the impurity concentration of the n-type impurity (donor) introduced into the electric field relaxation region 102 is higher than the impurity concentration of the p-type impurity (acceptor) introduced into the silicon carbide epitaxial layer 101.

[0048] On the other hand, the HEMT includes a buffer layer 110 having a band gap larger than that of the silicon carbide epitaxial layer 101, a channel layer 111 in contact with the buffer layer 110, a barrier layer 112 in contact with the channel layer 111, a source electrode 120 in contact with a first region of the barrier layer 112, a drain electrode 130 in contact with a second region of the barrier layer 112, and a gate electrode 140 provided between the source electrode 120 and the drain electrode 130. In the HEMT configured in this manner, two-dimensional electron gas is generated at the interface between the channel layer 111 and the barrier layer 112. The silicon carbide epitaxial layer 101 is electrically connected to the source electrode 120 via a plug PLG1, and the electric field reduction region 102 is electrically connected to the drain electrode 130 via a plug PLG2.

[0049] In FIG. 3, if the stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction (z direction in FIG. 3) and the direction from the drain electrode 130 toward the gate electrode 140 is defined as a second direction (-x direction in FIG. 3), then in a cross-sectional view, a first virtual line VL1 extending in the z direction from one end of the electric field relaxation region 102 intersects with a second virtual line VL2 extending in the -x direction between the drain electrode 130 and the gate electrode 140.

[0050] Note that, when the silicon carbide substrate is used as a reference, the first direction and the second direction can also be understood as a direction perpendicular to the main surface of the silicon carbide substrate, and a direction parallel to the main surface of the silicon carbide substrate (a direction perpendicular to the first direction).

[0051] FIG. 4 is a plan view showing the configuration of a semiconductor device based on the basic concept, and the cross-sectional view taken along line AA in FIG. 4 corresponds to FIG. 3. In FIG. 4, the source electrode 120 and the drain electrode 130 each extend in the x direction while facing each other, and have multiple finger portions protruding in the y direction. That is, the source electrode 120 and the drain electrode 130 of the semiconductor device have a "multi-finger structure." The electric field relaxation region 102 includes a region that protrudes from the drain electrode 130 toward the gate electrode 140.

[0052] Next, we will explain how the semiconductor device configured in this way realizes the basic concept. The basic concept is to design the pn junction diode connected in anti-parallel to the HEMT so that the pn junction diode undergoes avalanche breakdown before the drain-source voltage exceeds the HEMT's breakdown voltage. However, the key here is to avoid the pn junction diode from undergoing avalanche breakdown at a drain-source voltage significantly lower than the HEMT's breakdown voltage. In other words, it is important to ensure that the pn junction diode undergoes avalanche breakdown at a drain-source voltage that is lower than the HEMT's breakdown voltage but as close as possible to the HEMT's breakdown voltage. This is because, for example, if the HEMT itself has a breakdown voltage of 600 V or 1.2 kV, if the pn junction diode undergoes avalanche breakdown at around 100 V, the semiconductor device's breakdown voltage cannot be set to 600 V or 1.2 kV. In other words, the basic idea is to design the pn junction diode connected in anti-parallel to the HEMT so that it will undergo avalanche breakdown before the drain-source voltage exceeds the HEMT's withstand voltage, and to design the pn junction diode so that it will undergo avalanche breakdown at a drain-source voltage as close as possible to the HEMT's withstand voltage.

[0053] 3, this basic idea is realized by designing the electric field relaxation region 102 so that a first virtual line VL1 extending in the z direction from one end of the electric field relaxation region 102 intersects with a second virtual line VL2 extending in the −x direction between the drain electrode 130 and the gate electrode 140. In other words, the basic idea is realized by configuring the electric field relaxation region 102 to include a region that extends from the drain electrode 130 toward the gate electrode 140, as shown in FIGS.

[0054] For example, if the basic concept is not realized, that is, if the electric field relaxation region 102 does not extend from the drain electrode 130 toward the gate electrode 140, even if a positive potential of about 100 V is applied to the drain electrode 130, the depletion layer will not extend sufficiently due to the short length of the electric field relaxation region 102, resulting in avalanche breakdown of the pn junction diode. As a result, even if the breakdown voltage of the HEMT itself is about 600 V, the breakdown voltage of the semiconductor device as a whole will be about 100 V, as will be described later.

[0055] In contrast, when the electric field relaxation region 102 is configured to include a region that extends from the drain electrode 130 toward the gate electrode 140, the depletion layer extends sufficiently due to the long length of the electric field relaxation region 102, making it difficult for the pn junction diode to undergo avalanche breakdown at a low drain-source voltage. This makes it possible to avoid the breakdown voltage of the semiconductor device being approximately 100V, even if the breakdown voltage of the HEMT itself is approximately 600V.

[0056] That is, by designing the impurity concentration and length of the electric field relaxation region 102 to realize the basic concept (specifically, by designing the electric field relaxation region 102 to include a region that extends from the drain electrode 130 toward the gate electrode 140), the depletion layer can be sufficiently extended within the electric field relaxation region 102. As a result, while the design allows the anti-parallel connected pn junction diodes to undergo avalanche breakdown before the drain-source voltage exceeds the breakdown voltage of the HEMT, the pn junction diodes can be designed to undergo avalanche breakdown at a drain-source voltage that is lower than the breakdown voltage of the HEMT but as close as possible to the breakdown voltage of the HEMT. Furthermore, when the electric field relaxation region 102 is configured to include a region that extends from the drain electrode 130 toward the gate electrode 140, the electric field strength on the surface of the electric field relaxation region 102 is reduced, thereby reducing the effect of the electric field on the HEMT formed above the electric field relaxation region 102.

[0057] <Modification> FIG. 5 is a cross-sectional view showing a modified example of a semiconductor device based on the basic concept.

[0058] FIG. 6 is a plan view showing a modified example of a semiconductor device based on the basic concept, and the cross section taken along line AA in FIG. 6 corresponds to FIG.

[0059] 6, the plug PLG1 electrically connecting the source electrode 120 and the silicon carbide epitaxial layer and the plug PLG2 electrically connecting the drain electrode 130 and the electric field relaxation region 102 can also be disposed outside the "multi-finger structure." In this case, it becomes possible to reduce the cell pitch, thereby enabling the miniaturization of the semiconductor device.

[0060] <Verification results> Next, we will explain the verification results that demonstrate the usefulness of the basic concept.

[0061] Specifically, the results of a simulation of the breakdown voltage of a pn junction diode will be explained.

[0062] FIG. 7 is a diagram showing the device structure (simulation structure) used for the simulation. As shown in FIG. 7, the simulation - SiC region and p + SiC region, electric field relaxation region, and n + The simulation was carried out based on a structure in which a GaN-HEMT is formed on a pn junction diode having a SiC region, and an insulating film (SiO2 film) is formed on the GaN-HEMT. - The acceptor concentration Nax in the SiC region is set to 1×10 16 (cm -3 ), p + SiC region (anode side) and n + The distance LX between the SiC region (cathode side) was set to 11 μm, and the length LN of the electric field relaxation region and the donor doping concentration were changed to calculate the breakdown voltage of the pn junction diode. The calculation results are shown in Figure 8.

[0063] As shown in Figure 8, for example, to obtain a high breakdown voltage (breakdown voltage) of 600 V or more, the sheet concentration (DN) in the field relaxation region must be 3 × 10 12 (cm -2 ) or more is expected to be necessary. Also, by making the length (LN) of the electric field relaxation region 6 μm or more, it is expected that a breakdown voltage of 1.2 kV or more can be obtained. In this Figure 8, 13 (cm -2 ), the breakdown voltage increases monotonically up to 1.80×10 13 (cm -2 ) will decrease.

[0064] More detailed breakdown voltage simulation results are shown in Figure 22. ‐ Acceptor concentration in the SiC region Nax=7×10 15 (cm -3 ) and p + SiC region and n + The distance LX between the SiC region and the SiC region was set to 18 (μm). In FIG. 22, the sheet concentration (DN) is incremented finely. From FIG. 22, when the target withstand voltage is 600 V, the sheet concentration (DN) is 3.42 × 10 12 (cm -2 ) or more. When the breakdown voltage target is 1200V or more, the sheet concentration (DN) is 8.55×10 12 (cm -2 ) or more, and 1.27 × 10 13 (cm -2 ) It can be seen that the following can be done.

[0065] In addition, various simulation results revealed the following: Depending on the target breakdown voltage, p - Thickness of the SiC region, p - Acceptor concentration Nax in the SiC region, p + SiC region (anode side) and n + The distance (LX) between the SiC region (cathode side) and the length (LN) of the electric field relaxation region had to be adjusted as needed. -The acceptor concentration Nax in the SiC region is p - It was found that it depends on the thickness of the SiC region. On the other hand, it was found that the optimum sheet concentration (DN) of the electric field relaxation region does not depend on the target breakdown voltage. In other words, when the sheet concentration (DN) is 8.55 × 10 12 (cm -2 ) or more, and 1.27 × 10 13 (cm -2 ) or less, a shorter p + SiC region (anode side) and n + It was found that the target breakdown voltage could be obtained at the distance (LX) between the SiC region (cathode side).

[0066] Furthermore, FIG. 9 is a graph showing the evaluation results of a withstand voltage test in the off state.

[0067] 9 and 10 provide a preview of some of the evaluation results of the prototype device, which will be described later with reference to FIGS. 12 to 15. These are test results when the transistor is in the off state with −3 V applied between the gate and source.

[0068] As shown in Figure 9, even in actual breakdown voltage tests, not in simulations, the drain current (ID) gradually increased, and no breakdown occurred even when it reached 2 mA / mm. The prototype device used for the measurements had LX = 18 (μm), LN = 13 (μm), and Nax = 1 × 10 16 (cm -3 ), DN=1.0×10 13 (cm -2 ) In addition, an AlN buffer layer with a large band gap of 6.2 eV was placed between the HEMT and the diode. As a result, the gate current (IG) at breakdown was less than 1 / 200 of the drain current, and the source current (IS) was less than 1 / 50 of the drain current, indicating that the breakdown current flows through the pn junction diode. In other words, a non-destructive avalanche breakdown occurs in the pn junction diode, preventing destruction of the HEMT while suppressing the flow of breakdown current into the HEMT.

[0069] Therefore, it was possible to conduct multiple breakdown voltage tests on the same device, as shown in Figure 10. Figure 10 is a graph in which Figure 9 is plotted as a linear plot and multiple sweep results are superimposed. As shown in Figure 10, non-destructive avalanche breakdown occurs in the pn junction diode, and it can be seen that breakdown occurs stably no matter how many times it is conducted.

[0070] When the voltage at which the drain current reached 2 mA / mm was defined as the breakdown voltage, the breakdown voltage was 1.27 kV. As with the simulation results, by forming the electric field relaxation region to extend from the drain electrode, high breakdown voltage operation of 1.2 kV or more was experimentally confirmed.

[0071] From the above, it can be seen that the breakdown voltage of the pn junction diode can be adjusted to a high voltage by designing the electric field relaxation region to include a region that extends from the drain electrode toward the gate electrode. This means that, with a semiconductor device configuration based on the basic concept, it is possible to design the anti-parallel connected pn junction diodes to undergo avalanche breakdown before the drain-source voltage exceeds the HEMT's withstand voltage, while also designing the pn junction diodes to undergo avalanche breakdown at a drain-source voltage that is lower than the HEMT's withstand voltage but as close as possible to the HEMT's withstand voltage. Therefore, according to the above verification results, with a semiconductor device based on the basic concept, it is possible to prevent the HEMT from breaking down while This proves that it is possible to provide a semiconductor device that suppresses the flow of breakdown current into the HEMT and has a high breakdown voltage.

[0072] <Specific aspects> Next, a specific embodiment that embodies the basic concept of this embodiment will be described.

[0073] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to the present embodiment.

[0074] In FIG. 11, the semiconductor device has a pn junction diode formed on a silicon carbide substrate 100, and a HEMT formed on the pn junction diode.

[0075] Specifically, the pn junction diode includes a p-type silicon carbide epitaxial layer 101 formed on a silicon carbide substrate 100, and an n-type electric field relaxation region (resurf region) 102 formed in the silicon carbide epitaxial layer 101. The pn junction diode further includes a p-type semiconductor region 103 formed in the silicon carbide epitaxial layer 101 and having a higher acceptor concentration than the silicon carbide epitaxial layer 101, and a p-type semiconductor region 103 contained in the p-type semiconductor region 103. + The pn junction diode has an n-type semiconductor region 104. The n-type semiconductor region 104 is included in the electric field relaxation region 102. + The semiconductor region 105 is a semiconductor region having a thickness of 100 nm.

[0076] A HEMT is formed on the pn junction diode. Specifically, for example, a buffer layer 110 made of aluminum nitride (AlN) is formed on a pn junction diode whose main material is silicon carbide, and a channel layer 111 made of undoped gallium nitride (GaN) is formed on this buffer layer 110. In this case, the buffer layer is an undoped layer or a layer doped with impurities (carbon, iron, magnesium, etc.).

[0077] Here, the buffer layer 110 is formed for the purpose of alleviating the mismatch between the lattice spacing of silicon carbide that constitutes the pn junction diode and the lattice spacing of gallium nitride (GaN) that constitutes the channel layer 111. In other words, if the channel layer 111 made of gallium nitride (GaN) is formed directly on silicon carbide, many crystal defects will be formed in the channel layer 111, resulting in a decrease in the performance of the HEMT.

[0078] Furthermore, while the bandgap energy of silicon carbide is 3.2 eV, the bandgap energy of AlN is as large as 6.2 eV, which prevents electrons and holes generated by avalanche breakdown in a pn junction diode using silicon carbide from flowing into the GaN side.

[0079] For this reason, a buffer layer 110 with a large band gap is inserted between the silicon carbide that constitutes the pn junction diode and the channel layer 111 to prevent lattice relaxation and the inflow of electrons and holes generated by breakdown on the silicon carbide side into the GaN side. By forming this buffer layer 110, the quality of the channel layer 111 formed on the buffer layer 110 can be improved and the intrusion of electrons and holes into the GaN side during breakdown can be suppressed, thereby improving the performance of the HEMT.

[0080] Subsequently, a barrier layer 112 made of, for example, undoped aluminum gallium nitride (AlGaN) is formed on the channel layer 111. A source electrode 120 and a drain electrode 130 are formed on the barrier layer 112 at a distance from each other. That is, the source electrode 120 is formed so as to contact a first region of the barrier layer 112, and the drain electrode 130 is formed so as to contact a second region of the barrier layer 112.

[0081] The materials of the source electrode 120 and the drain electrode 130 are selected so that the source electrode 120 and the barrier layer 112, or the drain electrode 130 and the barrier layer 112, are in ohmic contact.

[0082] Next, a p-type cap layer 150 made of, for example, p-type gallium nitride (p-GaN) is formed on the barrier layer 112 sandwiched between the spaced apart source electrode 120 and drain electrode 130, and a gate electrode 140 is formed on this p-type cap layer 150.

[0083] In this embodiment, the buffer layer 110, the channel layer 111, and the barrier layer 112 that constitute the HEMT are formed as a mesa structure 115, and an insulating film 160 made of, for example, a silicon oxide film is formed on both side surfaces of this mesa structure 115.

[0084] The source electrode 120 of the HEMT is connected to the p-type pn junction diode via a plug PLG1. +The plug PLG1 is electrically connected to the p-type semiconductor region 104. + The pn-type semiconductor region 104 is in ohmic contact with the drain electrode 130 of the HEMT. + The plug PLG2 is electrically connected to the n-type semiconductor region 105. + The semiconductor region 105 is in ohmic contact with the semiconductor region 105 .

[0085] As a result, in the semiconductor device shown in FIG. 11, the HEMT and the pn junction diode are connected in antiparallel (see FIG. 1).

[0086] In a HEMT configured as described above, two-dimensional electron gas is generated near the interface between the channel layer 111 and the barrier layer 112. That is, the electron affinity of gallium nitride (GaN) constituting the channel layer 111 differs from the electron affinity of aluminum gallium nitride (AlGaN) constituting the barrier layer 112. Therefore, a conduction band offset due to the difference in electron affinity and the influence of piezoelectric polarization and spontaneous polarization present in the channel layer 111 and the barrier layer 112 generate a well-shaped potential lower than the Fermi level near the interface between the channel layer 111 and the barrier layer 112. As a result, electrons are accumulated in this well-shaped potential, thereby generating two-dimensional electron gas near the interface between the channel layer 111 and the barrier layer 112.

[0087] In the HEMT shown in Figure 11, the p-type cap layer 150 is formed under the gate electrode 140, allowing the threshold voltage to be designed to be positive or negative depending on the structure of the barrier layer 112. For example, the thicker the AlGaN constituting the barrier layer 112 and the higher its Al composition, the more negative the threshold voltage shifts. Specifically, the polarization charge density versus Al composition can be calculated using the calculation method disclosed in Non-Patent Document 7, and the threshold voltage can be designed from the thickness and dielectric constant of the AlGaN layer. More specifically, when the barrier layer 112 is 15 nm thick, setting the Al composition to 23% or less results in a positive threshold voltage, making the device normally-off. When applying HEMTs to power converters, normally-off devices are often required. However, this requires a lower Al composition, which reduces the two-dimensional electron gas concentration outside the gate electrode, tending to increase the on-resistance. Therefore, it is important to design the threshold voltage while considering the trade-off with on-resistance.

[0088] In the semiconductor device configured as above, in FIG. 11 , if the stacking direction of the pn junction diode and the HEMT is defined as a first direction (z direction in FIG. 11 ) and the direction from the drain electrode 130 toward the gate electrode 140 is defined as a second direction (−x direction in FIG. 11 ), in a cross-sectional view, a first virtual line VL1 extending from one end of the electric field relaxation region 102 in the z direction intersects with a second virtual line VL2 extending in the −x direction between the drain electrode 130 and the gate electrode 140. That is, the electric field relaxation region 102 includes a region extending from the drain electrode 130 toward the gate electrode 140. In addition, in a cross-sectional view, a third virtual line VL3 extending from one end of the p-type semiconductor region 103 in the z direction also intersects with the second virtual line VL2 extending in the −x direction between the drain electrode 130 and the gate electrode 140. That is, the p-type semiconductor region 103 includes a region extending from the gate electrode 140 toward the drain electrode 130.

[0089] As shown in Figure 11, in an actual device, electrodes are in contact with the semiconductor layer through contact holes in an insulating film formed on the semiconductor layer. More specifically, the source region, gate region, and drain region are regions where the electrodes contact the semiconductor layer. The overhang distance LC of the electric field reduction region 102 is defined as the overhang distance from the edge of the drain region toward the gate electrode. The drain region is the region where the drain electrode 130 contacts the barrier layer 112, and the edge of the drain region is the edge of the drain region closer to the gate electrode 140. The overhang distance LA of the p-type semiconductor region 103 is defined as the overhang distance from the edge of the gate region toward the drain electrode. The gate region is the region where the gate electrode 140 contacts the p-type cap layer 150, and the edge of the gate region is the edge of the gate region closer to the drain electrode 130. The gate-drain distance is the distance between the edge of the gate region and the edge of the drain region.

[0090] The semiconductor device of this embodiment is configured as described above.

[0091] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device according to this embodiment will be described.

[0092] FIG. 12 is a flowchart showing the flow of the manufacturing process of the semiconductor device shown in FIG. 11 that was actually fabricated as a prototype. As shown in FIG. 12, a silicon carbide substrate 100 having an off-angle of more than 2 degrees and not more than 4 degrees from the (0001) plane is prepared (S101). In the prototype, an n-type 4H—SiC substrate (4H-silicon carbide substrate) having an off-angle of 4 degrees in the <11-20> direction was used. Next, by using epitaxial growth by the CVD method, for example, a first p-type silicon carbide epitaxial layer (thickness 1 μm, acceptor concentration 1×10 18 (cm -3 )), and a second p-type silicon carbide epitaxial layer (thickness 16 μm, acceptor concentration 1 × 10 16 (cm -3)) is formed (S102). Aluminum (Al) is used as the acceptor dopant. Here, the first p-type silicon carbide epitaxial layer is not essential, as it is omitted in the cross-sectional view of FIG. 11. In other words, the silicon carbide epitaxial layer 101 shown in FIG. 11 indicates a second p-type silicon carbide epitaxial layer. Then, by using photolithography technology and ion implantation, an electric field relaxation region 102, a p-type semiconductor region 103, and a p + type semiconductor region 104 and n + After selectively forming the p-type semiconductor region 105 in the second p-type silicon carbide epitaxial layer, the impurities are activated by a high-temperature annealing treatment (S103).

[0093] In the prototype device, the electric field relaxation region 102, the p-type semiconductor region 103, and the p + type semiconductor region 104 and n + The sheet impurity concentration of the semiconductor region 105 is 1.0×10 13 (cm -2 ) (nitrogen (N) implantation), 1.2 × 10 14 (cm -2 ) (aluminum (Al) implanted), 5 × 10 15 (cm -2 )(Al injection), 7×10 14 (cm -2 ) (phosphorus (P) injection).

[0094] The dopant concentration of each region can be modified as follows. For example, the acceptor concentration of the second p-type silicon carbide epitaxial layer (silicon carbide epitaxial layer 101) is set to 2×10 15 (cm -3 )~1×10 17 (cm -3 However, as the concentration increases, the thickness of the silicon carbide epitaxial layer 101 must be reduced. 17 (cm -3 In the case of forming the silicon carbide epitaxial layer 101 as described above, it is desirable that the thickness of the silicon carbide epitaxial layer 101 is thinned to 1 μm or less, and that the silicon carbide substrate 100 is a high resistance substrate.

[0095] Electric field relaxation region 102, p-type semiconductor region 103, p + type semiconductor region 104 and n + The sheet impurity concentration (cm -2 ) are as follows. For example, the range of the sheet impurity concentration of the electric field relaxation region 102 is as described above with reference to FIG. 8 and FIG. 22. The p-type semiconductor region 103 is a region having the same conductivity as the silicon carbide epitaxial layer 101, and is not necessarily a region essential for device operation. However, by forming the p-type semiconductor region 103 with a higher concentration than the silicon carbide epitaxial layer 101, it is possible to prevent the intrusion of a depletion layer below the gate electrode 140, and providing the p-type semiconductor region 103 can improve long-term reliability in preventing breakdown. Therefore, the impurity concentration when providing the p-type semiconductor region 103 is desirably higher than the concentration of the two-dimensional electron gas, specifically, 1×10 13 (cm -2 ) or more of the sheet impurity concentration is preferable. + type semiconductor region 104 and n + The sheet impurity concentration of each of the semiconductor regions 105 is 5×10 14 (cm -2 ) or more is preferable.

[0096] As described above, the silicon carbide substrate 100 is typically a 4H-SiC off-substrate tilted at a predetermined angle from the (0001) plane (Si-plane) in the <11-20> direction. Here, the (000-1) plane (C-plane) may be used as the substrate primary surface instead of the Si-plane. When both the (0001) plane and the (000-1) plane are collectively referred to, they are referred to as the {0001} plane. The tilted crystal direction (off-direction) of the off-substrate may be <01-10> instead of <11-20>.

[0097] Thereafter, a buffer layer 110 made of AlN, a channel layer 111 (thickness 800 nm) made of GaN, a barrier layer 112 (Al composition 23%, thickness 20 nm) made of AlGaN, and a p-type cap layer 150 (thickness 60 nm) made of p-type GaN are formed by MOCVD, and an activation process of the impurity made of magnesium (Mg) is performed (S104).

[0098] Next, a mesa structure is formed using photolithography and dry etching (S105). Subsequently, a nickel film (Ni film) is deposited on the silicon carbide surface, and then sintering is performed to form plugs PLG1 and PLG2, which serve as ohmic electrodes. Furthermore, Al / Ti-based electrodes are formed on the barrier layer 112 as the source electrode 120 and the drain electrode 130, and a nickel (Ni) film is deposited as the gate electrode 140, followed by heat treatment to form an ohmic electrode (S106). Thereafter, for example, the surface is protected with an insulating film, and then a pad electrode is formed. In this manner, the semiconductor device according to this embodiment can be manufactured. In this prototype, the gate electrode 140 is an ohmic electrode using Ni, but it may also be a Schottky electrode made of, for example, a TiN-based alloy or an Al / Ti-based alloy.

[0099] <Element characteristics of the prototype device> Next, the evaluation results of the element characteristics of the device prototyped by the above-mentioned manufacturing method will be described.

[0100] The following evaluation results are obtained for the prototype device when the gate-drain distance is 26 μm, the protrusion distance of the electric field relaxation region 102 (LC in FIG. 11) is 15 μm, and the sheet impurity concentration of donors in the electric field relaxation region 102 is 1.0×10 13 (cm -2 ) The conditions were as follows: the protrusion distance (LA in FIG. 11) of the p-type semiconductor region 103 was 6 μm, and the sheet impurity concentration of the acceptor was 1.2×10 14 (cm -2 ) to form a good ohmic contact with SiC. +type semiconductor region 104 and n + The sheet impurity concentration of the semiconductor region 105 is 5×10 14 (cm -2 ) and above.

[0101] Figure 13 shows the I D -V DS The experimental results of the characteristics are shown below. As shown in Figure 13, this device exhibited a high current carrying capacity of 300 mA / mm, and a low on-resistance per gate width of 47 Ωmm was obtained. Unlike the "on-axis substrate" used in conventional HEMTs, this prototype used a silicon carbide substrate with a 4-degree off-axis angle, and roughness of about 30 nm was observed on the surface of the HEMT structure. However, the on-state characteristics were comparable to those of conventional HEMTs, demonstrating that high mobility of the two-dimensional electron gas was obtained.

[0102] The mobility of the two-dimensional electron gas was measured separately using Hall effect measurements. Specifically, a sample for measuring the Hall effect was prepared by forming a HEMT structure on a silicon carbide substrate with a 4-degree offset in the <11-20> direction. As a result, the mobility at room temperature (300 K) was 1550 (cm 2 / Vs), and a monotonically increasing trend was observed with decreasing temperature. At low temperatures (80 K), the mobility was 8720 (cm 2 / Vs). This result indicates that the mobility of two-dimensional electron gas is limited by phonon scattering, a physical property of the gas. In other words, it was confirmed that electrical characteristics equivalent to those on "on-axis substrates" used in general HEMTs can be obtained even on silicon carbide substrates with a 4° off-axis orientation, which has been avoided until now in GaN-based crystal growth.

[0103] Previously reported top data for 1.2kV breakdown voltage HEMTs using "on-axis substrates" was approximately 20Ωmm. The prototype device produced this time exhibited good characteristics in terms of on-resistance, on the same order as the top data, in the initial prototype, and achieved an on-resistance that was approximately 1 / 100th of the material limit of Si lateral transistors.

[0104] Figure 14 shows the experimental results of the transfer characteristics at Vds = 5 V. The gate threshold voltage was -0.25 V when determined at Id = 1 μA / mm, which is the general definition for HEMTs. Because the threshold voltage was negative, the device fabricated in this study was a normally-on type.

[0105] As shown in Figures 9 and 10, the breakdown voltage of this device was 1.2 kV or more, and it was non-destructive. Furthermore, the gate current at the time of breakdown was suppressed to 1 / 200 or less of the drain current.

[0106] Figure 15 shows the experimental results of the Id-Vds characteristics for negative Vds at Vgs = -4V. Here, negative Vds corresponds to a forward bias for the silicon carbide pn junction diode. Therefore, when the drain-source voltage reaches approximately -3V, which is the built-in voltage of the silicon carbide pn junction, current begins to flow through the integrated silicon carbide pn junction diode (IB in Figure 15). As the voltage decreases further, the HEMT gate channel opens, as with conventional HEMTs, and current also flows through the HEMT channel, and the current flowing through the silicon carbide pn junction diode is observed to be added (ID in Figure 15).

[0107] Additionally, a comparative device was fabricated in which the electric field relaxation region 102 in Figure 11 was not doped, i.e., the electric field relaxation region did not extend beyond the drain electrode. The evaluation result of the diode breakdown voltage of the comparative device was low, at around 100 V. It was found that having the electric field relaxation region 102 extend beyond the drain electrode is essential for obtaining a high breakdown voltage.

[0108] <Features of the embodiment> Next, the features of this embodiment will be described.

[0109] A first feature of this embodiment is that, for example, as shown in Fig. 11 , the electric field relaxation region 102 includes a region that extends from the drain electrode 130 toward the gate electrode 140. In other words, the first feature of this embodiment is that, in Fig. 11 , if the stacking direction of the pn junction diode and the HEMT is defined as a first direction (z direction in Fig. 11 ) and the direction from the drain electrode 130 toward the gate electrode 140 is defined as a second direction (-x direction in Fig. 11 ), a first virtual line VL1 extending in the z direction from one end of the electric field relaxation region 102 intersects with a second virtual line VL2 extending in the -x direction between the drain electrode 130 and the gate electrode 140 in a cross-sectional view. As a result, according to this embodiment, the length of the electric field relaxation region 102 is increased, and therefore, when a reverse bias is applied to the pn junction diode, a depletion layer can be sufficiently extended in the electric field relaxation region 102. As a result, while the anti-parallel connected pn junction diodes are designed to undergo avalanche breakdown before the drain-source voltage exceeds the breakdown voltage of the HEMT, the pn junction diodes can be designed to undergo avalanche breakdown at a drain-source voltage that is lower than the breakdown voltage of the HEMT but as close as possible to the breakdown voltage of the HEMT. In other words, the breakdown voltage of the pn junction diodes is lower than the drain-source breakdown voltage of the HEMT. Therefore, according to the first feature of this embodiment, it is possible to ensure the breakdown voltage of the semiconductor device while preventing breakdown of the HEMT.

[0110] A second feature of this embodiment is that a buffer layer with a large band gap relative to silicon carbide is provided between the HEMT and the pn junction diode. This prevents electrons and holes generated during avalanche breakdown of the pn junction diode from flowing into the gate electrode of the HEMT. This is because the band offset of the buffer layer relative to silicon carbide functions as a barrier against electrons and holes.

[0111] A third feature of this embodiment is that a HEMT is used as a power transistor. This ensures high conduction capability in the forward direction in a semiconductor device including a HEMT and a pn junction diode. In other words, this embodiment can reduce conduction loss in the forward direction. This is because a HEMT has high conduction capability.

[0112] The HEMT's high conduction capability is achieved by integrating it with a silicon carbide pn junction diode, which has a dielectric breakdown strength comparable to that of GaN. As a result, a non-destructive breakdown voltage of approximately 1.2 kV was achieved for the silicon carbide pn junction diode with a gate-drain distance of only 26 μm. If combined with a silicon pn junction diode, achieving a 1.2 kV breakdown voltage would require a horizontal cathode-anode distance of at least 120 μm, which would require a longer gate-drain distance for the HEMT. Naturally, this would result in a significant increase in on-resistance and chip area. For this reason, using a silicon pn junction diode would be impractical. In other words, integrating the HEMT with a silicon carbide pn junction diode allows for a shorter gate-drain distance for the HEMT, while still maintaining a non-destructive breakdown voltage of approximately 1.2 kV for the silicon carbide pn junction diode.

[0113] Another idea is to form a GaN-based pn junction diode between the channel layer and buffer layer. However, forming a p-type region in GaN-based materials by ion implantation is extremely difficult. Specifically, high-temperature annealing at 1300°C or higher is required to activate the Mg acceptor impurity after ion implantation. Meanwhile, GaN-based materials undergo thermal decomposition at temperatures above 1000°C under atmospheric pressure. To suppress thermal decomposition, annealing must be performed in a high-pressure nitrogen atmosphere above 10,000 atmospheres. Therefore, industrial fabrication of lateral pn junction diodes using GaN-based materials is extremely difficult. Another proposed method for selectively forming the p-type region of a GaN-based pn junction diode on a flat surface involves combining techniques such as etching, selective area crystal growth, and crystal surface planarization using CMP. However, this technology poses high industrial hurdles, such as mass production and yield, and there are concerns about rising costs.

[0114] A fourth feature of this embodiment is that a pn junction diode is connected in anti-parallel to the HEMT. This ensures high reverse conduction capability. That is, this embodiment can reduce reverse conduction loss.

[0115] For example, when a load such as a motor is connected to a circuit containing inductance, there is a mode (freewheel mode) in which load current flows in the opposite direction to the on-state of the switch. In this freewheel mode, the source potential becomes higher than the drain potential, and current flows in the reverse direction (from source electrode 120 to drain electrode 130), which is different from the normal forward direction.

[0116] In this embodiment, a pn junction diode is connected in anti-parallel to the HEMT. As a result, in the freewheeling mode, in addition to the reverse current through the HEMT, a forward current also flows through the pn junction diode connected in anti-parallel to the HEMT. Therefore, according to the fourth feature of this embodiment, it is possible to flow a reverse current that is larger than the forward current flowing through the pn junction diode connected in anti-parallel to the HEMT, compared to a semiconductor device configured using a normal HEMT alone. As a result, the semiconductor device of this embodiment has the remarkable effect of reducing conduction loss in the reverse direction.

[0117] Next, a fifth feature of this embodiment will be described.

[0118] For example, in this embodiment, a silicon carbide pn junction diode is formed on a high-resistivity silicon carbide substrate, and a GaN-based HEMT is formed on this pn junction diode. The reason for using a high-resistivity silicon carbide substrate is that it has the advantage of being able to reduce high-frequency loss and has the advantage of having high thermal conductivity, resulting in excellent heat dissipation characteristics. Therefore, in this embodiment, a silicon carbide pn junction diode is formed on a high-resistivity silicon carbide substrate, and a GaN-based HEMT is formed on this pn junction diode.

[0119] In this regard, when forming a silicon carbide-based pn junction diode on a silicon carbide substrate, for example, a vertical pn junction diode in which current flows in the thickness direction of the substrate can be considered. However, when forming a vertical pn junction diode on a silicon carbide substrate, it is known that a "forward degradation phenomenon" occurs, in which the forward current decreases when current flows in the vertical direction (thickness direction of the substrate) for a long period of time. This is thought to be due to basal plane dislocations formed at the interface between the silicon carbide substrate and the silicon carbide epitaxial layer.

[0120] Therefore, in this embodiment, instead of forming a vertical pn junction diode on a silicon carbide substrate, a horizontal pn junction diode that passes current in the horizontal direction of the substrate is formed. This is a fifth characteristic feature of this embodiment. That is, the fifth characteristic feature of this embodiment is that a horizontal pn junction diode is formed on a high-resistivity silicon carbide substrate.

[0121] In this case, in a lateral pn junction diode, current flows through the surface of the silicon carbide epitaxial layer, and therefore current does not flow through basal plane dislocations formed at the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. As a result, according to the fifth feature of the present embodiment, it is possible to suppress the "forward degradation phenomenon" in which the forward current decreases.

[0122] 11 , for example, a p-type semiconductor region 103 is provided, and in a cross-sectional view, a third virtual line VL3 extending in the z direction from one end of the p-type semiconductor region 103 intersects with a second virtual line VL2 extending in the −x direction between the drain electrode 130 and the gate electrode 140. That is, the sixth feature of the present embodiment is that the p-type semiconductor region 103 includes a region that extends from the gate electrode 140 toward the drain electrode 130.

[0123] As a result, according to this embodiment, the on-resistance of the pn junction diode can be reduced. Furthermore, the p-type semiconductor region 103 is electrically connected to the source electrode 120, and "0 V" is applied to the source electrode 120. As a result, "0 V" is also applied to the p-type semiconductor region 103. According to a sixth feature of this embodiment, the p-type semiconductor region 103 includes a region that extends from the gate electrode 140 toward the drain electrode 130. Therefore, this p-type semiconductor region 103 has the function of mitigating the influence of an electric field applied to the HEMT formed above the pn junction diode, similar to a "field plate." As a result, according to the sixth feature of this embodiment, the breakdown voltage of the HEMT can be improved.

[0124] Although an example in which the p-type semiconductor region 103 is provided has been described here, the p-type semiconductor region 103 is not an essential component, and the p-type semiconductor region 103 does not necessarily have to be provided.

[0125] 11, the seventh feature of the present embodiment is that the side surfaces of the mesa structure 115 are covered with the insulating film 160. As a result, according to the present embodiment, it is possible to reduce leakage current from the side surfaces of the mesa structure 115 in the HEMT.

[0126] Here, an example has been described in which insulating film 160 is formed to cover the side surfaces of mesa structure 115, but insulating film 160 covering the side surfaces of mesa structure 115 is not necessarily a necessary component, and insulating film 160 does not necessarily have to be provided.

[0127] Next, an eighth feature of this embodiment will be described.

[0128] In this embodiment, crystal growth of a silicon carbide epitaxial layer and a nitride semiconductor layer (AlN layer, GaN layer, AlGaN layer) is required on a 4H—SiC substrate (silicon carbide substrate).

[0129] Here, in the so-called homoepitaxial crystal growth in which a 4H—SiC layer is epitaxially grown on a 4H—SiC substrate, a 4H—SiC substrate is generally used that has a slight tilt (off-angle) of 4 degrees or more in the crystal orientation <11-20> relative to the (0001) plane, which is the growth surface, in order to prevent the incorporation of various polytypes other than 4H, such as 6H.

[0130] On the other hand, because GaN single crystal substrates are still under development and extremely expensive, heteroepitaxial crystal growth methods using alternative single crystal substrates that assume lattice mismatch have been put into practical use. 4H-SiC substrates have a lattice constant difference of approximately 3.3% with GaN single crystals, and a technique for growing nitride semiconductor layers on them with relatively good crystallinity is known. This technique has been put into practical use using metalorganic chemical vapor deposition (MOCVD), which is highly amenable to mass production. Silicon carbide substrates for this purpose serve as templates for directly growing nitride semiconductor layers without growing a SiC layer, and "on-axis" substrates are considered to be suitable. An "on-axis" substrate is a substrate that is not tilted (has no off-axis angle) from the (0001) growth plane. The standard off-axis error for "on-axis" substrates is within 0.25 degrees. Such "on-axis" substrates are considered unsuitable for homoepitaxial growth of conventional SiC layers due to the difficulty in suppressing polytype.

[0131] From the above, in this embodiment, crystal growth of a silicon carbide epitaxial layer and a nitride semiconductor layer is required on a silicon carbide substrate, but for crystal growth of the silicon carbide epitaxial layer, a silicon carbide substrate having an off-axis angle is generally used (Insight 1). In contrast, for crystal growth of a nitride semiconductor layer by MOCVD, an "on-axis substrate" is generally used (Insight 2). Therefore, in manufacturing the semiconductor device of this embodiment, it is difficult to achieve both Insight 1 and Insight 2, which are contradictory to each other, and there is technical difficulty in performing good crystal growth of the silicon carbide epitaxial layer and the nitride semiconductor layer on the silicon carbide substrate.

[0132] In this regard, the present inventors have intensively studied this technical difficulty and have newly discovered that, for example, by using a silicon carbide substrate having an off-angle of more than 2 degrees and not more than 4 degrees, it is possible to grow a good silicon carbide epitaxial layer and ensure the mobility of a HEMT using a nitride semiconductor layer grown by MOCVD. That is, an eighth feature of this embodiment is the use of a silicon carbide substrate having an off-angle of more than 2 degrees and not more than 4 degrees. According to this eighth feature of this embodiment, the performance of a semiconductor device including a HEMT and a pn junction diode can be ensured.

[0133] <Modification> <<Variations of the electric field relaxation region>> Below, we will explain a modification of the electric field relaxation region 102, which is a main component of the embodiment. The reason why the modification is necessary is as follows. In general, in order to improve the performance and reduce the cost of a transistor, it is required to shorten the distance between the gate electrode 140 and the drain electrode 130 while maintaining a desired breakdown voltage. That is, p + SiC region (anode side) and n + The distance (LX) between the SiC region (cathode side) is also required to be shorter while maintaining the desired breakdown voltage. - It is desirable to obtain a target breakdown voltage in the SiC region (silicon carbide epitaxial layer 101). To achieve this, a technique of spatially modulating the sheet concentration (DN) of the electric field relaxation region 102 is effective. However, even when the sheet concentration (DN) is spatially modulated, at least one location in the electric field relaxation region 102 must have a sheet concentration (DN) of 8.55×10 12 (cm -2 ) or more, and 1.27 × 10 13 (cm -2 ) or less. In the following, variations of the electric field relaxation region will be shown from the above viewpoint.

[0134] 16, by making the portion of electric field relaxation region 102 immediately below plug PLG2 shallower, it is possible to ensure the vertical breakdown voltage while reducing the thickness of silicon carbide epitaxial layer 101. In this case, since the thickness of silicon carbide epitaxial layer 101 can be reduced, it is possible to reduce the manufacturing cost of the semiconductor device.

[0135] As shown in Figure 17, by providing a slope to the electric field relaxation region 102, it is possible to improve the breakdown voltage for the same gate-drain electrode distance. As a result, it is possible to promote the miniaturization of semiconductor devices. Although not shown in the cross-sectional view of Figure 17, the island-shaped electric field relaxation region 102 is in contact with the drain electrode in the depth direction and other directions. This allows electrons to be quickly re-injected into the electric field relaxation region 102 when the device is turned on.

[0136] However, it is difficult to manufacture the inclined electric field relaxation region 102 shown in Fig. 17 in terms of the manufacturing process. Therefore, in consideration of ease of manufacture, for example, as shown in Fig. 18, in order to form the electric field relaxation region 102, ion implantation with different implantation energies is performed multiple times, thereby forming the inclined electric field relaxation region 102 shown in Fig. 17. relief It is possible to easily manufacture a structure equivalent to the region 102. Furthermore, by forming the electric field relaxation region 102 as shown in Fig. 19, the number of ion implantations can be reduced, thereby reducing the manufacturing cost of the semiconductor device.

[0137] As shown in Figure 20, by burying a portion of the electric field relaxation region 102 inside the silicon carbide epitaxial layer 101, it is possible to increase the impurity concentration of the electric field relaxation region 102 while ensuring the breakdown voltage of the pn junction diode. As a result, it is possible to reduce the conduction loss in the semiconductor device. Furthermore, as shown in Figure 21, by overlapping the p-type semiconductor region 103 and the electric field relaxation region 102 to form a so-called "super junction structure," it is possible to increase the impurity concentration of the electric field relaxation region 102 and to increase the length of the electric field relaxation region 102, thereby reducing the conduction loss while ensuring the breakdown voltage.

[0138] <<Variations of HEMT Structure>> In the embodiment, the buffer layer of the HEMT uses an AlN layer, but it can also be changed to AlGaN having a sufficiently large bandgap energy with respect to silicon carbide. Specifically, AlGaN having an Al composition of 30% or more and a bandgap energy of 4 eV or more can be used. That is, the buffer layer can be composed of Al x Ga 1-x N with an aluminum (Al) composition X greater than 30%.

[0139] Also, although AlGaN is used for the barrier layer of the HEMT, it can be changed to a III-V nitride semiconductor alloy having a larger bandgap energy than GaN serving as the channel layer, such as InAlN or InGaAlN. Further, the barrier layer can be made of a plurality of III-V nitride semiconductor alloys instead of a single layer, which can improve the performance of the HEMT. For example, the barrier layer can be AlGaN / AlN (AlN on the lower side). This can increase the mobility of the two-dimensional electron gas. Also, the barrier layer can be GaN / AlGaN (AlGaN on the lower side). This can reduce current collapse.

[0140] Furthermore, it is possible to additionally insert a III-V nitride semiconductor having a larger bandgap energy than GaN serving as the channel between the buffer layer and the channel layer. This can enhance the confinement of the two-dimensional electron gas and reduce the drain leakage current in the off state. layer

[0141] In the embodiment, as the gate structure of the HEMT, a structure is adopted in which an ohmic electrode using a Ni-based alloy is formed on p-type GaN (p-type cap layer 150). In this regard, it is also possible to form a similar ohmic electrode using a Pt-based alloy.

[0142] ​Moreover, instead of p-type GaN under the gate electrode, other p-type III-V nitride semiconductor alloys, such as p-type InGaN, AlInN, or AlGaN (Non-Patent Document 2, Fig. 8(b)), can be used.

[0143] Furthermore, it is possible to change the gate electrode to a Schottky electrode for p-type GaN. Typical Schottky electrodes include Ti-based alloys such as Al / Ti or TiN. This reduces the gate leakage current when a positive voltage is applied to the gate electrode, allowing a higher voltage (approximately 5V to 8V) to be applied to the gate electrode.

[0144] Alternatively, the p-type GaN layer under the gate electrode can be eliminated and an insulating layer can be provided (Non-Patent Document 2, Figs. 8(c), (e), and (f)). In this case, the AlGaN barrier layer under the gate electrode can be treated with a fluorine-based plasma (Non-Patent Document 2, Fig. 8(c)), or the barrier layer can be partially etched by dry etching (Non-Patent Document 2, Fig. 8(e)), or the barrier layer can be etched completely through (Non-Patent Document 2, Fig. 8(f)). This reduces the gate leakage current by using an insulated gate structure while controlling the threshold voltage, allowing the use of a higher gate voltage (approximately 15 V to 30 V).

[0145] Although not shown in the figure, the semiconductor device according to the embodiment can employ various field plate structures that have been reported so far. For example, the embodiment assumes that the semiconductor device is provided with three types of field plate structures connected to the gate electrode 140, the source electrode 120, and the drain electrode 130. This allows for the formation of a field plate in the GaN structure (HEMT) ) This prevents breakdown at high voltages and enables high voltage operation of 1.2 kV or more.

[0146] As a variation of the field plate structure, a field plate structure connected to the source electrode 120 can be adopted (Non-Patent Document 3, Fig. 1(a)). Also, a field plate structure connected to the drain electrode 130 can be adopted (Non-Patent Document 3, Fig. 1(b)). Furthermore, in addition to the field plate structure connected to the source electrode 120, a field plate structure connected to the gate electrode 140 can also be adopted (Non-Patent Document 4, Fig. 1(a)).

[0147] The number of stages in the field plates connected to the gate electrode 140, the source electrode 120, and the drain electrode 130 can also be increased. For example, it has been reported that a high breakdown voltage can be achieved by using two stages of field plates connected to the gate electrode 140 (Non-Patent Document 5, Fig. 1(a)). In this way, it is possible to adopt a structure with an increased number of field plate stages. However, increasing the number of stages increases the number of photolithography steps, which increases manufacturing costs. Taking this into consideration, it is also possible to adopt a structure in which the field plates are tilted (Non-Patent Document 6, Fig. 1).

[0148] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0149] 10 Switching Circuits 100 Silicon carbide substrate 101 Silicon carbide epitaxial layer 102 Electric field relaxation region 103 p-type semiconductor region 104 pages + Type semiconductor region 105n + Type semiconductor region 110 Buffer layer 111 Channel Layer 112 Barrier Layer 115 Mesa Structure 120 Source electrode 130 drain electrode 140 gate electrode 150 p-type cap layer 160 insulating film A Anode C cathode D Drain FRD Diode G gate electrode PLG1 plug PLG2 plug Q1 power transistor S sauce VL1 First virtual line VL2 Second virtual line VL3 Third virtual line

Claims

1. a pn junction diode formed on a silicon carbide substrate; a high electron mobility transistor formed on the pn junction diode; In a semiconductor device having The pn junction diode is a silicon carbide epitaxial layer of a first conductivity type formed on the silicon carbide substrate; an electric field relaxation region of a second conductivity type that is opposite to the first conductivity type and is formed in the silicon carbide epitaxial layer; Including, The high electron mobility transistor comprises: a channel layer made of a first nitride semiconductor layer; a barrier layer made of a second nitride semiconductor layer in contact with the channel layer; a buffer layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer being made of a third nitride semiconductor layer having a band gap larger than that of the silicon carbide epitaxial layer; a source electrode in contact with the first region of the barrier layer; a drain electrode in contact with the second region of the barrier layer; a gate electrode provided between the source electrode and the drain electrode; Including, the first region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the second region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the silicon carbide epitaxial layer is electrically connected to the source electrode; the electric field relaxation region is electrically connected to the drain electrode, In a plan view, the electric field relaxation region includes a region that protrudes from the drain electrode and is in contact with the second region, a stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction; When a direction perpendicular to the first direction is defined as a second direction, In a cross-sectional view, a first virtual line extending from one end of the electric field relaxation region in the first direction intersects with a second virtual line extending in the second direction between the drain electrode and the gate electrode; the source electrode and the drain electrode are not connected to the silicon carbide substrate.

2. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the breakdown voltage of the pn junction diode is lower than the breakdown voltage of the high electron mobility transistor in a drain-source voltage that is the difference between a drain potential applied to the drain electrode and a source potential applied to the source electrode.

3. 3. The semiconductor device according to claim 2, The pn junction diode has a function of preventing a breakdown mode of the high electron mobility transistor, which occurs when the drain-source voltage exceeds the breakdown voltage of the high electron mobility transistor, by avalanche breakdown.

4. 2. The semiconductor device according to claim 1, the pn junction diode is formed in the silicon carbide epitaxial layer, has an impurity concentration higher than that of the silicon carbide epitaxial layer, and has a semiconductor region of the first conductivity type electrically connected to the source electrode.

5. A pn ​​junction diode formed on a silicon carbide substrate; a high electron mobility transistor formed on the pn junction diode; In a semiconductor device having The pn junction diode is a silicon carbide epitaxial layer of a first conductivity type formed on the silicon carbide substrate; an electric field relaxation region of a second conductivity type that is opposite to the first conductivity type and is formed in the silicon carbide epitaxial layer; Including, The high electron mobility transistor comprises: a channel layer made of a first nitride semiconductor layer; a barrier layer made of a second nitride semiconductor layer in contact with the channel layer; a buffer layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer being made of a third nitride semiconductor layer having a band gap larger than that of the silicon carbide epitaxial layer; a source electrode in contact with the first region of the barrier layer; a drain electrode in contact with the second region of the barrier layer; a gate electrode provided between the source electrode and the drain electrode; Including, the first region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the second region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the silicon carbide epitaxial layer is electrically connected to the source electrode; the electric field relaxation region is electrically connected to the drain electrode, In a plan view, the electric field relaxation region includes a region that protrudes from the drain electrode and is in contact with the second region, a stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction; When a direction perpendicular to the first direction is defined as a second direction, In a cross-sectional view, a first virtual line extending from one end of the electric field relaxation region in the first direction intersects with a second virtual line extending in the second direction between the drain electrode and the gate electrode; the pn junction diode is formed in the silicon carbide epitaxial layer, has an impurity concentration higher than that of the silicon carbide epitaxial layer, and includes a semiconductor region of the first conductivity type electrically connected to the source electrode; In a cross-sectional view, a third imaginary line extending from one end of the semiconductor region in the first direction intersects with a second imaginary line extending in the second direction between the drain electrode and the gate electrode.

6. 6. The semiconductor device according to claim 5, The semiconductor device, wherein the semiconductor region has a function of mitigating the influence of an electric field applied to the high electron mobility transistor.

7. The semiconductor device according to any one of claims 1 to 6, the buffer layer is in contact with the electric field relaxation region, The buffer layer has an aluminum (Al) composition X of greater than 30%. ｘ Ga １－ｘ N, a semiconductor device.

8. The semiconductor device according to any one of claims 1 to 6, the buffer layer is in contact with the electric field relaxation region, The semiconductor device, wherein the buffer layer is made of AlN.

9. The semiconductor device according to any one of claims 1 to 6, the pn junction diode is a lateral diode having a main current path in a direction parallel to a main surface of the silicon carbide epitaxial layer.

10. A pn ​​junction diode formed on a silicon carbide substrate; a high electron mobility transistor formed on the pn junction diode; In a semiconductor device having The pn junction diode is a silicon carbide epitaxial layer of a first conductivity type formed on the silicon carbide substrate; an electric field relaxation region of a second conductivity type that is opposite to the first conductivity type and is formed in the silicon carbide epitaxial layer; Including, The high electron mobility transistor comprises: a channel layer made of a first nitride semiconductor layer; a barrier layer made of a second nitride semiconductor layer in contact with the channel layer; a buffer layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer being made of a third nitride semiconductor layer having a band gap larger than that of the silicon carbide epitaxial layer; a source electrode in contact with the first region of the barrier layer; a drain electrode in contact with the second region of the barrier layer; a gate electrode provided between the source electrode and the drain electrode; Including, the first region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the second region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the silicon carbide epitaxial layer is electrically connected to the source electrode; the electric field relaxation region is electrically connected to the drain electrode, In a plan view, the electric field relaxation region includes a region that protrudes from the drain electrode and is in contact with the second region, a stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction; When a direction perpendicular to the first direction is defined as a second direction, In a cross-sectional view, a first virtual line extending from one end of the electric field relaxation region in the first direction intersects with a second virtual line extending in the second direction between the drain electrode and the gate electrode; the silicon carbide substrate is a 4H-silicon carbide substrate having a main surface on which the silicon carbide epitaxial layer is formed, and the main surface has an off angle of more than 2 degrees and not more than 4 degrees from a {0001} plane in a predetermined crystal direction.

11. The semiconductor device according to any one of claims 1 to 6, the channel layer and the barrier layer are formed as a mesa structure; The semiconductor device, wherein the side surface of the mesa structure is covered with an insulating film.

12. A pn ​​junction diode formed on a silicon carbide substrate; a high electron mobility transistor formed on the pn junction diode; In a semiconductor device having The pn junction diode is a silicon carbide epitaxial layer of a first conductivity type formed on the silicon carbide substrate; an electric field relaxation region of a second conductivity type that is opposite to the first conductivity type and is formed in the silicon carbide epitaxial layer; Including, The high electron mobility transistor comprises: a channel layer made of a first nitride semiconductor layer; a barrier layer made of a second nitride semiconductor layer in contact with the channel layer; a buffer layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer being made of a third nitride semiconductor layer having a band gap larger than that of the silicon carbide epitaxial layer; a source electrode in contact with the first region of the barrier layer; a drain electrode in contact with the second region of the barrier layer; a gate electrode provided between the source electrode and the drain electrode; Including, the first region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the second region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the silicon carbide epitaxial layer is electrically connected to the source electrode; the electric field relaxation region is electrically connected to the drain electrode, In a plan view, the electric field relaxation region includes a region that protrudes from the drain electrode and is in contact with the second region, a stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction; When a direction perpendicular to the first direction is defined as a second direction, In a cross-sectional view, a first virtual line extending from one end of the electric field relaxation region in the first direction intersects with a second virtual line extending in the second direction between the drain electrode and the gate electrode; a breakdown voltage of 600 V or more between the source electrode and the drain electrode; The sheet impurity concentration of the donor added to the electric field relaxation region is 3.42×10 １２ (cm －２ ) or more.

13. A pn ​​junction diode formed on a silicon carbide substrate; a high electron mobility transistor formed on the pn junction diode; In a semiconductor device having The pn junction diode is a silicon carbide epitaxial layer of a first conductivity type formed on the silicon carbide substrate; an electric field relaxation region of a second conductivity type that is opposite to the first conductivity type and is formed in the silicon carbide epitaxial layer; Including, The high electron mobility transistor comprises: a channel layer made of a first nitride semiconductor layer; a barrier layer made of a second nitride semiconductor layer in contact with the channel layer; a buffer layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer being made of a third nitride semiconductor layer having a band gap larger than that of the silicon carbide epitaxial layer; a source electrode in contact with the first region of the barrier layer; a drain electrode in contact with the second region of the barrier layer; a gate electrode provided between the source electrode and the drain electrode; Including, the first region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the second region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the silicon carbide epitaxial layer is electrically connected to the source electrode; the electric field relaxation region is electrically connected to the drain electrode, In a plan view, the electric field relaxation region includes a region that protrudes from the drain electrode and is in contact with the second region, a stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction; When a direction perpendicular to the first direction is defined as a second direction, In a cross-sectional view, a first virtual line extending from one end of the electric field relaxation region in the first direction intersects with a second virtual line extending in the second direction between the drain electrode and the gate electrode; a breakdown voltage of 1200 V or more between the source electrode and the drain electrode; The sheet impurity concentration of the donor added to the electric field relaxation region is 8.55×10 １２ (cm －２ ) or more, 1.27 x 10 １３ (cm －２ ) or less.

14. A pn ​​junction diode formed on a silicon carbide substrate; a high electron mobility transistor formed on the pn junction diode; In a semiconductor device having The pn junction diode is a silicon carbide epitaxial layer of a first conductivity type formed on the silicon carbide substrate; an electric field relaxation region of a second conductivity type that is opposite to the first conductivity type and is formed in the silicon carbide epitaxial layer; Including, The high electron mobility transistor comprises: a channel layer made of a first nitride semiconductor layer; a barrier layer made of a second nitride semiconductor layer in contact with the channel layer; a buffer layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer being made of a third nitride semiconductor layer having a band gap larger than that of the silicon carbide epitaxial layer; a source electrode in contact with the first region of the barrier layer; a drain electrode in contact with the second region of the barrier layer; a gate electrode provided between the source electrode and the drain electrode; Including, the first region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the second region includes a portion of an upper surface facing an interface between the channel layer and the barrier layer, the silicon carbide epitaxial layer is electrically connected to the source electrode; the electric field relaxation region is electrically connected to the drain electrode, In a plan view, the electric field relaxation region includes a region that protrudes from the drain electrode and is in contact with the second region, a stacking direction of the pn junction diode and the high electron mobility transistor is defined as a first direction; When a direction perpendicular to the first direction is defined as a second direction, In a cross-sectional view, a first virtual line extending from one end of the electric field relaxation region in the first direction intersects with a second virtual line extending in the second direction between the drain electrode and the gate electrode; The semiconductor device, wherein the silicon carbide substrate is a high resistance substrate.

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