semiconductor devices

Abstract

To provide a semiconductor device having better controllability for changes in channel length by installing a channel drain region.SOLUTION: A semiconductor device includes a semiconductor layer and a trench gate structure including a gate dielectric layer 151 and a gate conductor 152. The semiconductor layer includes: a source region 130 extending in a direction from a first surface toward a second surface; a drift region 101 and a bulk region 110, at least a part of the drift region being located between the source region and the second surface of the semiconductor layer, a first portion of the bulk region being located between the source region and the drift region; and a channel drain region 120 located between the first portion 111 of the bulk region and the drift region, while the source region, the first portion of the bulk region and the channel drain region 120 are adjacent in order along a direction from the first surface to the second surface and each of them are adjacent to a first side wall 150a of the trench gate structure.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to the field of semiconductor device structures, and more particularly to semiconductor devices having trench gate structures. [Background technology]

[0002] Compared to planar transistor structures, vertical transistor structures offer the advantage of equalizing blocking voltage and conduction resistance within the same area. When using power device modules or multiple discrete devices in the same system, the characteristic variations between transistor devices are also an important consideration for the robustness of the integrated system. During the manufacturing process, transistors must undergo numerous process steps and different manufacturing equipment. Therefore, the device characteristics of transistors vary from device to device. As integration density increases, it is necessary to make the characteristics of each device more uniform, with channel length uniformity being one of the key parameters. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of the above problems, an object of the present disclosure is to provide a semiconductor device, which has better controllability of the change in channel length by providing a channel drain region. [Means for solving the problem]

[0004] 1. A semiconductor device according to an embodiment of the present disclosure, comprising: a semiconductor layer and a trench gate structure, the semiconductor layer having opposing first and second surfaces, at least a portion of the trench gate structure located in a trench in the first surface of the semiconductor layer, The semiconductor layer is a source region extending from the first surface toward the second surface; a drift region and a bulk region, wherein at least a portion of the drift region is located between the bulk region and a second surface of the semiconductor layer, and a first portion of the bulk region is located between the source region and the drift region; a channel drain region located between a first portion of the bulk region and the drift region, whereby the source region, the first portion of the bulk region, and the channel drain region are adjacent in order along a direction from the first surface to the second surface, and all adjacent to a first sidewall of the trench gate structure; The source region, the channel drain region, and the drift region are of a first conductivity type, and the bulk region is of a second conductivity type, and the first conductivity type and the second conductivity type are opposite to each other.

[0005] Optionally, the doping concentration of the channel drain region is greater than the doping concentration of the drift region.

[0006] Optionally, the first portion, the second portion, and the third portion of the bulk region are adjacent to each other in order along a width direction of the trench gate structure; a second portion of the bulk region adjacent to a second sidewall of the trench gate structure and the drift region, respectively; a third portion of the bulk region extending from a bottom surface of the trench gate structure toward the second surface and adjacent to the drift region; the channel drain region and the third portion of the bulk region are separated by the drift region; The first sidewall faces the second sidewall.

[0007] Optionally, the second portion of the bulk region includes a first sub-region and a second sub-region that are connected; the first sub-region is adjacent to a first portion of the bulk region, and the second sub-region is adjacent to a third portion of the bulk region; a distance from an edge of the channel drain region toward the second surface to the first surface is a first distance; a distance from an edge of the first subregion toward the second surface to the first surface is a second distance; a distance from an edge of the second subregion toward the second surface to the first surface is a third distance; The third distance is greater than the first distance, and the first distance is greater than the second distance, such that the channel drain region and the second sub-region are separated by the drift region along a width direction of the trench gate structure.

[0008] Optionally, edges of the second and third portions of the bulk region towards the second surface are connected.

[0009] Optionally, a distance from an edge of the channel drain region toward the second surface to the first surface is a first distance; a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance; The first distance is less than or equal to the fourth distance.

[0010] Optionally, a distance from an edge of the channel drain region toward the second surface to the first surface is a first distance; a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance; The first distance is greater than the fourth distance, and the channel drain region is adjacent to a portion of a bottom surface of the trench gate structure.

[0011] Optionally, the semiconductor layer further includes a body contact region, the body contact region extending from the first surface toward the second surface and adjacent to the bulk region; The body contact region is of a second conductivity type.

[0012] Optionally, along an extension direction of the trench gate structure, a portion of the body contact region is adjacent to the second sidewall and has a gap between another portion of the body contact region and the second sidewall, and the portion of the body contact region adjacent to the second sidewall and the portion having the gap are alternately arranged along the extension direction of the trench gate structure; Alternatively, the body contact region and the second sidewall are both separated by the bulk region.

[0013] Optionally, the body contact region and the source region are adjacent or separated by the bulk region.

[0014] Optionally, the trench gate structure includes a gate dielectric layer and a gate conductor; the gate dielectric layer covers an inner surface of the trench and covers the first surface adjacent to the trench, the trench extending from the first surface toward the second surface; a portion of the gate conductor is located in the trench and another portion extends outside the trench and covers the gate dielectric layer; The gate dielectric layer is located between the gate conductor and the semiconductor layer to separate the gate conductor and the semiconductor layer.

[0015] Optionally, the semiconductor layer comprises a SiC semiconductor layer.

[0016] Optionally, the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

[0017] Optionally, between two of the trench gate structures, the source region extends from a first sidewall of one of the trench gate structures toward a second sidewall of the other of the trench gate structures and is adjacent to a second portion of the bulk region. [Effects of the Invention]

[0018] One of the above technical solutions has the following beneficial effects.

[0019] The channel drain region, the first portion of the bulk region, and the source region are disposed in sequence vertically adjacent to the same sidewall of the trench gate structure, and the position of the channel drain region is used to control the channel length, thereby improving the uniformity of the channel length, the uniformity of the overlapping portion of the channel with the drain region, and the uniformity of the concentration in the drain region, thereby improving the overall performance of the device.

[0020] In some embodiments, the second portion of the bulk region is divided into a first sub-region and a second sub-region in the horizontal direction, and the first portion of the bulk region, the first sub-region, and the second sub-region are adjacent to each other in sequence. By adjusting the distance from the bottom edge of the first sub-region to the first surface of the semiconductor layer, the channel drain region and the second sub-region of the bulk region are separated by the drift region. Along the direction from the first surface to the second surface, the distance from the first sidewall of the trench gate structure to the bulk region gradually increases. In an on-state of the device, after a current flows through the source region, the channel, and the channel drain region, a wider current path flows to the second surface, thereby reducing the conduction resistance and further improving the performance of the device.

[0021] In some embodiments, the gate dielectric layer extends from the interior surface of the trench to the first surface of the semiconductor layer to protect adjacent portions of the trench gate structure and the first surface of the semiconductor layer.

[0022] It should be noted that the above general description and the following detailed description are merely illustrative and explanatory and do not limit the present disclosure. In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. Obviously, the drawings in the following description are not the limitation of the present disclosure, but are only related to some embodiments of the present disclosure. [Brief explanation of the drawings]

[0023] [Figure 1]1 shows a schematic perspective structural view of a semiconductor device according to a first embodiment of the present disclosure; [Figure 2] 1 shows a schematic planar structure diagram of a semiconductor device according to a first embodiment of the present disclosure. [Figure 3] 3 shows a schematic cross-sectional view taken along line AA in FIG. 2. [Figure 4] FIG. 2 shows a structural schematic diagram of a semiconductor device according to a second embodiment of the present disclosure. [Figure 5] FIG. 10 shows a schematic planar structure diagram of a semiconductor device according to a third embodiment of the present disclosure. [Figure 6] 6 shows a schematic cross-sectional view taken along line BB in FIG. 5. [Figure 7] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 8] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 9] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present disclosure will now be described in more detail with reference to the drawings. In each drawing, the same elements are represented by the same reference numerals. For clarity, parts of the drawings are not drawn to scale. Also, some known parts may not be shown. For simplicity, a semiconductor structure obtained through several steps may be depicted in one drawing.

[0025] In describing the structure of a device, when a layer or region is referred to as being "on" or "above" another layer or region, it should be understood that this may mean that the layer or region is directly on top of the other layer or region, or that other layers or regions may be included between the other layer or region. Also, if the device were inverted, the layer or region would be "below" or "below" the other layer or region.

[0026] To describe being directly on top of another layer or region, this specification employs phrases such as "directly on top of" or "on top of and adjacent to."

[0027] A power device generally includes an active device region, an edge termination region, and a crack-stop or blocking region. The active device region includes an active device array. The present disclosure relates to active device structures. The dimensions of the active devices may vary depending on product needs, and there may be bulk regions between the active devices within the active device region.

[0028] In the following, many specific details of the present disclosure, such as device structures, materials, dimensions, processing processes, techniques, etc., are set forth in order to provide a clearer understanding of the present disclosure, but as will be understood by those skilled in the art, the present disclosure may not be practiced according to these specific details.

[0029] Fig. 1 is a schematic perspective view of a semiconductor device according to a first embodiment of the present disclosure, Fig. 2 is a schematic plan view of the semiconductor device according to the first embodiment of the present disclosure, and Fig. 3 is a schematic cross-sectional view taken along line AA in Fig. 2. The structure above the semiconductor layer and part of the trench gate structure are omitted in Fig. 1, and the structure above the semiconductor layer is omitted in Fig. 2 in order to more clearly show the positional relationship between the structures and regions.

[0030] As shown in FIGS. 1 to 3 , a semiconductor device according to a first embodiment of the present disclosure includes a semiconductor layer 100, a plurality of trench gate structures 150, an interlayer dielectric layer 160, and a source metal layer 170. The semiconductor layer 100 has opposing first and second surfaces 10 and 20, and a plurality of trenches 102 extending from the first surface 10 to the second surface 20 into the semiconductor layer 100. The plurality of trench gate structures 150 are located in the corresponding trenches 102. The semiconductor layer 100 is, for example, a SiC substrate or a stacked structure including a SiC substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may use different materials and / or different numbers of layers for the semiconductor layer 100 as needed.

[0031] The semiconductor layer 100 includes a drift region 101, a bulk region 110, a channel drain region 120, a source region 130, a body contact region 140, and a drain contact region 180. The channel drain region 120, the source region 130, and the drift region 101 are of a first conductivity type, and the bulk region 110 and the body contact region 140 are of a second conductivity type, the first conductivity type and the second conductivity type being opposite. The first conductivity type is either P-type or N-type, and the second conductivity type is the other of P-type or N-type. The doping concentration of the channel drain region 120 is greater than the doping concentration of the drift region 101, and the doping concentration of the body contact region 140 is greater than the doping concentration of the bulk region 110.

[0032] The semiconductor device of this embodiment may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), and the conductivity type of the drain contact region 180 may be a first conductivity type or a second conductivity type. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may appropriately set the conductivity type of each region in the semiconductor layer 100 as needed to make the semiconductor device a MOSFET or an IGBT.

[0033] The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 coats the inner surface of the trench 102, and the gate conductor 152 is located in the trench 102. The gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152 and serves to separate the semiconductor layer 100 from the gate conductor 152. The trench gate structure 150 has a first sidewall 150a, a second sidewall 150b, and a bottom surface 150c, where the first sidewall 150a and the second sidewall 150b are opposite each other. The trench gate structures 150 extend along a Y-axis direction (the length direction of the trench gate structure 150) and are distributed at intervals along an X-axis direction (the width direction of the trench gate structure 150). Optionally, each pair of the X-axis direction, the Y-axis direction, and the Z-axis direction (the direction from the second surface 20 to the first surface 10) are perpendicular to each other. Optionally, the X-axis direction is the <11-20> direction or the <1-100> direction, and the plane of the first side wall 150a and the plane of the second side wall 150b are the (11-20) plane or the (1-100) plane.

[0034] The bulk region 110 includes a first portion 111, a second portion 112, and a third portion 113 that are connected in this order along the X-axis direction. Between two adjacent trench gate structures 150, the first portion 111 is adjacent to a first sidewall 150a of one of the trench gate structures 150, the second portion 112 and the third portion 113 are both adjacent to the other of the trench gate structures 150, the second portion 112 is adjacent to a second sidewall 150b of the trench gate structure 150, the third portion 113 is located between a bottom surface 150c of the trench gate structure 150 and the second surface 20, and the third portion 113 is adjacent to the bottom surface 150c of the trench gate structure 150, and edges of the second portion 112 and the third portion 113 that face the second surface 20 are substantially flush with each other so as to be connected. Optionally, the doping concentrations of the first portion 111, the second portion 112 and the third portion 113 are different.

[0035] The channel drain region 120 is adjacent to a bottom surface 150c of the trench gate structure 150, and the source region 130 extends from the first surface 10 to the second surface 20 of the semiconductor layer 100. The first portion 111 of the bulk region 110 is located between the channel drain region 120 and the source region 130 such that the channel drain region 120 and the source region 130 are separated by the first portion 111 along the Z-axis direction. The channel drain region 120, the first portion 111, and the source region 130 are adjacent to each other in order along the Z-axis direction and are all adjacent to a first sidewall 150a of the same trench gate structure 150. The channel drain region 120 is adjacent to the second portion 112 of the bulk region 110, and the channel drain region 120 and the third portion 113 of the bulk region 110 are separated by the drift region 101. The distance d1 from the edge of the channel drain region 120 toward the second surface 20 to the first surface 10 is equal to or less than the distance d4 from the bottom surface 150c of the trench gate structure 150 to the first surface 10.

[0036] In this embodiment, when the semiconductor device is in an on-state, the first portion 111 of the bulk region 110 and the portion adjacent to the first sidewall 150a of the trench gate structure 150 are inverted, thereby forming a channel. By locating the channel drain region 120 adjacent to the bottom surface 150c of the trench gate structure 150, the length of the channel can be precisely controlled, thereby improving the uniformity of the lengths of the channels in the semiconductor device. Additionally, by locating the channel drain region 120, the uniformity of the overlap of the channel with the drain region and the uniformity of the concentration of the drain region can be further improved, thereby improving the overall performance of the device.

[0037] In some specific embodiments, the channel drain region 120 and the source region 130 are formed in the same process step, thereby providing more precise control over the channel length and increasing channel length uniformity.

[0038] Optionally, between the two trench gate structures 150, the source region 130 extends from the first sidewall 150a of one trench gate structure 150 toward the second sidewall 150b of the other trench gate structure 150 so as to be adjacent to the second portion 112 of the bulk region 110. When the junction depth of the source region 130 is deep, the increased width of the source region 130 contributes to a reduction in the contact diffusion resistance of the source region 130.

[0039] The body contact region 140 extends from the first surface 10 toward the second surface 20 of the semiconductor layer 100 and is adjacent to the bulk region 110. Along the X-axis direction, between two adjacent trench gate structures 150, one end of the body contact region 140 is adjacent to the source region 130, and the other end is close to but not connected to the second sidewall 150b of the trench gate structure 150, and the body contact region 140 and the second sidewall 150b are separated by the bulk region 110.

[0040] The source metal layer 170 is located on the first surface 10 of the semiconductor layer 100 and is adjacent to the source region 130 and the body contact region 140, respectively. A portion of the bulk region 110 is exposed at the first surface 10, and the source metal layer 170 is adjacent to the partial bulk region 110 exposed at the first surface 10. The interlayer dielectric layer 160 is located between the semiconductor layer 100 and the source metal layer 170 and is disposed corresponding to the trench gate structure 150 to separate the source metal layer 170 from the trench gate structure 150. The source metal layer 170 and the interlayer dielectric layer 160 may have a multilayer structure made of different materials. As an example of the multilayer source metal layer 170, the source metal layer 170 includes a tungsten (W) layer directly covering the body contact region 140 and the source region 130, and an aluminum copper (AlCu) layer directly covering the tungsten layer. Optionally, the embodiment may further include portions not shown in the figures, such as connecting the gate conductor 152 to the gate metal layer by opening a gate contact region directly above the gate conductor 152, and locating the gate contact region directly on the gate conductor 152, separating the gate conductor 152 from the source metal layer 170 via an interlayer dielectric layer 160.

[0041] At least a portion of the drift region 101 is located between the source region 130 and the second surface 20, and is adjacent to the second portion 112, the third portion 113 of the bulk region 110, the channel drain region 120, the bottom surface 150c of the trench gate structure 150, and the drain contact region 180, respectively, and the drain contact region 180 extends from the second surface 20 of the semiconductor layer 100 toward the first surface 10.

[0042] Furthermore, the semiconductor device of this embodiment further includes a drain metal layer (not shown) located on the second surface 20 of the semiconductor layer 100 and connected to the drain contact region 180 .

[0043] FIG. 4 shows a structural schematic diagram of a semiconductor device according to a second embodiment of the present disclosure.

[0044] 4, the semiconductor device of the second embodiment of the present disclosure is similar to the first embodiment, and will not be further described here, but please refer to the description of Figures 1 to 3. The difference is that the body contact region 140 and the source region 130 in this embodiment are separated by the bulk region 110.

[0045] FIG. 5 is a schematic diagram of the planar structure of a semiconductor device according to a third embodiment of the present disclosure, and FIG. 6 is a schematic cross-sectional view taken along line BB in FIG. 5. In FIG. 6, the structure above the semiconductor layer is omitted in order to more clearly show the positional relationship between each structure and region. For the schematic cross-sectional view taken along line AA in FIG. 5, please refer to FIG. 3.

[0046] 5 and 6, the semiconductor device according to the third embodiment of the present disclosure is similar to the first embodiment, and therefore no further description will be given, and reference may be made to the description of FIGS. 1 to 3. The difference is that in this embodiment, a portion of the body contact region 140 is adjacent to the second sidewall 150b of the trench gate structure 150 along the Y-axis direction, another portion of the body contact region 140 and the second sidewall 150b are separated by the bulk region 110, leaving a gap, and the portion of the body contact region 140 adjacent to the second sidewall 150b and the portion leaving the gap are alternately arranged along the Y-axis direction.

[0047] The gate-to-source capacitance is composed of three components: the capacitance from the gate conductor 152 to the bulk region 110, the capacitance from the gate conductor 152 to the body contact region 140, and the capacitance from the gate conductor 152 to the source region 130. The source region 130 is electrically connected to the bulk region 110. Because the doping concentration of the body contact region 140 is higher than that of the bulk region 110 and its capacitance per unit area is higher, the total gate-to-source capacitance can be adjusted by adjusting the area of ​​the body contact region 140 that directly contacts the second sidewall 150b. Depending on the application and system requirements, the ratio of the gate charge or gate-to-drain capacitance to (gate-to-drain capacitance + gate-to-source capacitance) also varies. For example, during the turn-off of a hard-switched transistor, the drain voltage suddenly rises, causing gate self-turn-on behavior due to capacitive coupling. If there is a margin for gate self-turn-on, increasing the gate-to-source capacitance can improve the margin.

[0048] Optionally, the body contact region 140 and the source region 130 of the semiconductor device of the third embodiment of the present disclosure may be provided separated from each other as in the second embodiment of the present disclosure.

[0049] FIG. 7 shows a structural schematic diagram of a semiconductor device according to a fourth embodiment of the present disclosure.

[0050] 7, the semiconductor device of the fourth embodiment of the present disclosure is similar to the first embodiment, and therefore no further description will be given, and reference may be made to the descriptions of FIGS. 1 to 3. The difference is that in this embodiment, a distance d1 from the edge of the channel drain region 120 facing the second surface 20 to the first surface 10 is greater than a distance d4 from the bottom surface 150c of the trench gate structure 150 to the first surface 10, and the channel drain region 120 is adjacent to a portion of the bottom surface 150c of the trench gate structure 150, thereby matching the depth of the trench 102 and the implantation time and dose of the channel drain region 120, which are different.

[0051] Optionally, the body contact region 140 and the source region 130 of the semiconductor device of the fourth embodiment of the present disclosure may be provided separated from each other as in the second embodiment of the present disclosure.

[0052] Optionally, the body contact region 140 of the semiconductor device of the fourth embodiment of the present disclosure may be configured as in the third embodiment of the present disclosure, where a portion of the body contact region 140 is adjacent to the second sidewall 150b of the trench gate structure 150 along the Y-axis direction, and another portion of the body contact region 140 and the second sidewall 150b are separated by the bulk region 110 to form a gap, thereby adjusting capacitance modulation-related characteristics from the gate to the source.

[0053] FIG. 8 shows a structural schematic diagram of a semiconductor device according to a fifth embodiment of the present disclosure.

[0054] 8, the semiconductor device according to the fifth embodiment of the present disclosure is similar to the first embodiment, and therefore no further description will be given, and reference may be made to the descriptions of FIGS. 1 to 3. The difference is that in this embodiment, a portion of a trench gate structure 150 is located within the trench 102, and another portion is located above the first surface 10. Specifically, a gate dielectric layer 151 covers the inner surface of the trench 102 and also covers a portion of the first surface 10 adjacent to the trench 102, and a portion of a gate conductor 152 is located in the trench 102, and another portion extends outside the trench 102 and covers the gate dielectric layer 151 located on the first surface 10.

[0055] The trench gate structure 150 of this embodiment extends from inside the trench 102 to the first surface 10, protecting the portion of the first surface 10 adjacent to the trench 102 and reducing damage to the portion of the first surface 10 adjacent to the trench 102 during manufacturing.

[0056] Optionally, the body contact region 140 and the source region 130 of the semiconductor device of the fifth embodiment of the present disclosure may be provided separated from each other as in the second embodiment of the present disclosure.

[0057] Optionally, the body contact region 140 of the semiconductor device of the fifth embodiment of the present disclosure may be configured as in the third embodiment of the present disclosure, where a portion of the body contact region 140 is adjacent to the second sidewall 150b of the trench gate structure 150 along the Y-axis direction, and another portion of the body contact region 140 and the second sidewall 150b are separated by the bulk region 110 to form a gap, thereby adjusting capacitance modulation-related characteristics from the gate to the source.

[0058] Optionally, the channel drain region 120 of the semiconductor device of the fifth embodiment of the present disclosure may be configured as in the fourth embodiment of the present disclosure, in which the edge of the channel drain region 120 toward the second surface 20 exceeds the bottom surface 150c of the trench gate structure 150, and the channel drain region 120 is adjacent to a part of the bottom surface 150c of the trench gate structure 150, thereby matching the different depths of the trenches 102, the implantation time and the implantation amount of the channel drain region 120.

[0059] FIG. 9 shows a structural schematic diagram of a semiconductor device according to a sixth embodiment of the present disclosure.

[0060] 9, the semiconductor device according to the sixth embodiment of the present disclosure is similar to the first embodiment, and therefore no further explanation will be given, and reference may be made to the descriptions of FIGS. 1 to 3. The difference is that in this embodiment, the second portion 112 of the bulk region 110 includes a first sub-region 112a and a second sub-region 112b to which the second portion 112 is connected, and the first sub-region 112a is adjacent to the first portion 111 of the bulk region 110, and the second sub-region 112b is adjacent to the third portion 113 of the bulk region 110 along the X-axis direction.

[0061] The distance from the edge of the first portion 111 of the bulk region 110 facing the second surface 20 to the first surface 10 is d5, the distance from the edge of the channel drain region 120 facing the second surface 20 to the first surface 10 is d1, the distance from the edge of the first sub-region 112a facing the second surface 20 to the first surface 10 is d2, and the distance from the edge of the second sub-region 112b facing the second surface 20 to the first surface 10 is d3, where d3>d1>d2>d5. As a result, the channel drain region 120 and the second sub-region 112b are separated by the drift region 101 along the X-axis direction.

[0062] In this embodiment, by adjusting the distance d2 from the bottom edge of the first sub-region 112a to the first surface, the edge of the bulk region 110 adjacent to the first sidewall 150a becomes stepped, and the distance from the first sidewall 150a to the second portion 112 of the bulk region 110 gradually increases along the direction from the first surface 10 to the second surface 20. In this way, when the device is on, the current path through the source region 130, the channel and the channel drain region 120 to the second surface 20 becomes wider, thereby reducing the conduction resistance and further improving the performance of the device.

[0063] Optionally, the body contact region 140 and the source region 130 of the semiconductor device of the sixth embodiment of the present disclosure may be provided separated from each other as in the second embodiment of the present disclosure.

[0064] Optionally, the body contact region 140 of the semiconductor device of the sixth embodiment of the present disclosure may be configured as in the third embodiment of the present disclosure, where a portion of the body contact region 140 is adjacent to the second sidewall 150b of the trench gate structure 150 along the Y-axis direction, and another portion of the body contact region 140 and the second sidewall 150b are separated by the bulk region 110 to form a gap, thereby adjusting capacitance modulation-related characteristics from the gate to the source.

[0065] Optionally, the channel drain region 120 of the semiconductor device of the sixth embodiment of the present disclosure may be configured as in the fourth embodiment of the present disclosure, in which the edge of the channel drain region 120 toward the second surface 20 exceeds the bottom surface 150c of the trench gate structure 150, and the channel drain region 120 is adjacent to a part of the bottom surface 150c of the trench gate structure 150, thereby matching the different depths of the trenches 102, the implantation time and the implantation amount of the channel drain region 120.

[0066] Optionally, the trench gate structure of the semiconductor device of the sixth embodiment of the present disclosure may be configured as in the fifth embodiment of the present disclosure, with a portion of the trench gate structure 150 located within the trench 102 and another portion located above the first surface 10, thereby protecting the portion of the first surface 10 adjacent to the trench 102.

[0067] The above describes the embodiments of the present disclosure. However, these embodiments are merely for the purpose of illustration and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should be included within the scope of the present disclosure.

Claims

1. 1. A semiconductor device comprising: a semiconductor layer and a trench gate structure, the semiconductor layer having opposing first and second surfaces, at least a portion of the trench gate structure located in a trench in the first surface of the semiconductor layer, The semiconductor layer is a source region extending from the first surface toward the second surface; a drift region and a bulk region, wherein at least a portion of the drift region is located between the bulk region and the second surface of the semiconductor layer, and a first portion of the bulk region is located between the source region and the drift region; a channel drain region located between a first portion of the bulk region and the drift region, whereby the source region, the first portion of the bulk region, and the channel drain region are adjacent in order along a direction from the first surface to the second surface, and all adjacent to a first sidewall of the trench gate structure; the source region, the channel drain region, and the drift region are of a first conductivity type, the bulk region is of a second conductivity type, and the first conductivity type and the second conductivity type are opposite to each other; a distance from an edge of the channel drain region toward the second surface to the first surface is a first distance; a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance; the first distance is greater than the fourth distance, and the channel drain region is adjacent to a portion of a bottom surface of the trench gate structure.

2. The semiconductor device of claim 1 , wherein the channel drain region has a doping concentration greater than a doping concentration of the drift region.

3. the first portion, the second portion, and the third portion of the bulk region are adjacent to each other in order along a width direction of the trench gate structure, a second portion of the bulk region adjacent to a second sidewall of the trench gate structure and the drift region, respectively; a third portion of the bulk region extending from a bottom surface of the trench gate structure toward the second surface and adjacent to the drift region; the channel drain region and the third portion of the bulk region are separated by the drift region; The semiconductor device of claim 1 , wherein the first sidewall is opposite the second sidewall.

4. the second portion of the bulk region includes a first sub-region and a second sub-region that are connected; the first sub-region is adjacent to a first portion of the bulk region, and the second sub-region is adjacent to a third portion of the bulk region; a distance from an edge of the first subregion toward the second surface to the first surface is a second distance; a distance from an edge of the second subregion toward the second surface to the first surface is a third distance; 4. The semiconductor device of claim 3, wherein the third distance is greater than the first distance, and the first distance is greater than the second distance, such that the channel drain region and the second sub-region are separated by the drift region along a width direction of the trench gate structure.

5. The semiconductor device according to any one of claims 1 to 4, wherein edges of the second and third portions of the bulk region facing towards the second surface are connected.

6. the semiconductor layer further includes a body contact region, the body contact region extending from the first surface toward the second surface and adjacent to the bulk region; The semiconductor device of claim 3 or 4, wherein the body contact region is of a second conductivity type.

7. a portion of the body contact region is adjacent to the second sidewall along an extension direction of the trench gate structure, and a gap is formed between another portion of the body contact region and the second sidewall, and the portion of the body contact region adjacent to the second sidewall and the portion having the gap are alternately arranged along the extension direction of the trench gate structure; Alternatively, the body contact region and the second sidewall are both separated by the bulk region.

8. The semiconductor device of claim 6 , wherein the body contact region and the source region are adjacent or separated by the bulk region.

9. the trench gate structure includes a gate dielectric layer and a gate conductor; the gate dielectric layer covers an inner surface of the trench and covers the first surface adjacent to the trench, the trench extending from the first surface toward the second surface; a portion of the gate conductor is located in the trench and another portion extends outside the trench and covers the gate dielectric layer; The semiconductor device according to any one of claims 1 to 4, wherein the gate dielectric layer is located between the gate conductor and the semiconductor layer so as to separate the gate conductor and the semiconductor layer.

10. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor layer includes a SiC semiconductor layer.

11. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

12. 5. The semiconductor device of claim 3, wherein the source region extends between two of the trench gate structures from a first sidewall of one of the trench gate structures toward a second sidewall of the other of the trench gate structures and is adjacent to a second portion of the bulk region.

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