Storage unit, memory and manufacturing method thereof

JP7795659B2Active Publication Date: 2026-01-07SWAYSURE TECHNOLOGY CO LTD
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Patent Information

Application Number
JP2025014441
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2024-03-21
Filing Date
2025-01-31
Publication Date
2026-01-07
Estimated Expiration
2045-01-31
Patent Text Reader

Abstract

To reduce an occupied area of a storage unit.SOLUTION: A storage unit contains: a channel layer 400 that forms a reading pipe and a writing pipe of a vertical channel to be laminated; a gate dielectric layer 500; a gate electrode layer 600; and an insulation dielectric layer 800. The channel layer contains a first channel 411 and a second channel 421 that are laminated with an interval. The first channel is positioned to a housing hole 210, and the second channel is at least partially positioned to the housing hole. The gate electrode layer contains a first gate 611 and a second gate 621. The first gate is formed in the first inner hole 412 of the first channel, and is directly or indirectly is connected to the second channel. The second gate is at least partially formed into the second inner hole 422 of the second channel. The gate dielectric layer is formed to between the gate electrode layer and the channel layer, and the insulation dielectric layer is formed on at least between the first channel and the second channel.SELECTED DRAWING: Figure 1
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Citation Information

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