Solid-state imaging device and electronic device

Abstract

A solid-state imaging element (1) according to the present disclosure comprises a plurality of light-receiving pixels (11) arrayed in a matrix configuration inside a semiconductor layer (20). The light-receiving pixels (11) each have a pair of photoelectric conversion parts, a first separation region (24), and a second separation region (25). The photoelectric conversion parts are arranged adjacently to each other, and have a shared floating diffusion (FD). The first separation region (24) is disposed so as to surround the photoelectric conversion parts. The second separation region (25) is disposed between the photoelectric conversion parts. The first separation region (24) is rectangular-shaped in a plan view, and is provided so as to extend from a surface (20b) opposite to a light incident surface (20a) of the semiconductor layer (20) toward the light incident surface (20a). The second separation region (25) is disposed along a diagonal line of the first separation region (24) rectangular-shaped in the plan view, and is provided so as to extend from the surface (20b) opposite to the light incident surface (20a) of the semiconductor layer (20) toward the light incident surface (20a).

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device and an electronic device. [Background technology]

[0002] In recent years, there has been a technology for detecting a phase difference in a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor by irradiating light onto a pair of photodiodes from the same on-chip lens (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0219040 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-described conventional technology, there is room for further improvement in terms of increasing the amount of saturated signal charge of the photodiode in the light-receiving pixel that detects the phase difference (hereinafter also referred to as the phase difference detection pixel).

[0005] Therefore, the present disclosure proposes a solid-state imaging device and an electronic device that can increase the amount of saturated signal charge of a photodiode in a phase difference detection pixel. [Means for solving the problem]

[0006] According to the present disclosure, there is provided a solid-state imaging element. The solid-state imaging element includes a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer. Each of the light-receiving pixels includes a pair of photoelectric conversion units, a first isolation region, and a second isolation region. The pair of photoelectric conversion units are arranged adjacent to each other and have a shared floating diffusion. The first isolation region is arranged to surround the pair of photoelectric conversion units. The second isolation region is arranged between the pair of photoelectric conversion units. The first isolation region is rectangular in plan view and is provided to extend from the surface of the semiconductor layer opposite to the light incident surface toward the light incident surface. The second isolation region is arranged along a diagonal of the rectangular first isolation region in plan view and is provided to extend from the surface of the semiconductor layer opposite to the light incident surface toward the light incident surface. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a system configuration diagram illustrating a schematic configuration example of a solid-state imaging device according to each embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating an example of a pixel circuit according to the first embodiment of the present disclosure. [Figure 3] FIG. 2 is a plan view illustrating an example of the configuration of a light receiving pixel according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view taken along the line AA in FIG. 3. [Figure 5] FIG. 4 is a cross-sectional view taken along the line BB in FIG. 3. [Figure 6] 1 is a plan view showing an example of the configuration of a light receiving pixel group according to a first embodiment of the present disclosure. [Figure 7] FIG. 10 is a cross-sectional view showing an example of the configuration of a light-receiving pixel according to Modification 1 of the first embodiment of the present disclosure. [Figure 8] FIG. 10 is a cross-sectional view showing an example of the configuration of a light-receiving pixel according to Modification 2 of the first embodiment of the present disclosure. [Figure 9] FIG. 10 is a plan view showing an example of the configuration of a light receiving pixel group according to Modification 3 of the first embodiment of the present disclosure. [Figure 10] FIG. 10 is a plan view showing an example of the configuration of a light receiving pixel group according to Modification 4 of the first embodiment of the present disclosure. [Figure 11] FIG. 11 is a plan view showing an example of the configuration of a light receiving pixel group according to Modification 5 of the first embodiment of the present disclosure. [Figure 12] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 6 of the first embodiment of the present disclosure. [Figure 13] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 7 of the first embodiment of the present disclosure. [Figure 14] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 8 of the first embodiment of the present disclosure. [Figure 15] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel group according to Modification 8 of the first embodiment of the present disclosure. [Figure 16] FIG. 13 is a plan view showing another example of the configuration of a light receiving pixel group according to Modification 8 of the first embodiment of the present disclosure. [Figure 17] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 9 of the first embodiment of the present disclosure. [Figure 18] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel group according to Modification 9 of the first embodiment of the present disclosure. [Figure 19] FIG. 13 is a plan view showing another example of the configuration of a light receiving pixel group according to Modification 9 of the first embodiment of the present disclosure. [Figure 20] FIG. 22 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 10 of the first embodiment of the present disclosure. [Figure 21] FIG. 20 is a plan view showing another example of the configuration of a light receiving pixel according to Modification 10 of the first embodiment of the present disclosure. [Figure 22] FIG. 22 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 11 of the first embodiment of the present disclosure. [Figure 23] FIG. 23 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 12 of the first embodiment of the present disclosure. [Figure 24] FIG. 10 is a diagram illustrating an example of a pixel circuit according to a second embodiment of the present disclosure. [Figure 25] FIG. 10 is a plan view showing an example of the configuration of a light receiving pixel according to a second embodiment of the present disclosure. [Figure 26]FIG. 26 is a cross-sectional view taken along the line CC shown in FIG. 25. [Figure 27] FIG. 26 is a cross-sectional view taken along the line DD in FIG. 25. [Figure 28] FIG. 10 is a cross-sectional view showing an example of the configuration of a light-receiving pixel according to Modification 1 of the second embodiment of the present disclosure. [Figure 29] FIG. 10 is a cross-sectional view showing an example of the configuration of a light-receiving pixel according to Modification 2 of the second embodiment of the present disclosure. [Figure 30] FIG. 10 is a cross-sectional view showing an example of the configuration of a light-receiving pixel according to Modification 3 of the second embodiment of the present disclosure. [Figure 31] FIG. 10 is a cross-sectional view showing an example of the configuration of a light-receiving pixel according to Modification 4 of the second embodiment of the present disclosure. [Figure 32] FIG. 10 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 5 of the second embodiment of the present disclosure. [Figure 33] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 6 of the second embodiment of the present disclosure. [Figure 34] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 7 of the second embodiment of the present disclosure. [Figure 35] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 8 of the second embodiment of the present disclosure. [Figure 36] FIG. 13 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 9 of the second embodiment of the present disclosure. [Figure 37] FIG. 20 is a plan view showing an example of the configuration of a light receiving pixel according to a tenth modification of the second embodiment of the present disclosure. [Figure 38] FIG. 16 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 11 of the second embodiment of the present disclosure. [Figure 39] FIG. 20 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 12 of the second embodiment of the present disclosure. [Figure 40] FIG. 20 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 13 of the second embodiment of the present disclosure. [Figure 41] FIG. 21 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 14 of the second embodiment of the present disclosure. [Figure 42]FIG. 21 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 15 of the second embodiment of the present disclosure. [Figure 43] FIG. 21 is a plan view showing an example of the configuration of a light receiving pixel according to Modification 16 of the second embodiment of the present disclosure. [Figure 44] 1 is a block diagram illustrating an example of the configuration of an imaging device as an electronic device to which the technology according to the present disclosure is applied. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0009] In recent years, there has been a technology in back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensors that detects phase differences by irradiating light onto a pair of photodiodes from the same on-chip lens.

[0010] Furthermore, in such an image sensor, the dynamic range and the S / N ratio can be improved by increasing the saturation signal charge amount (Qs) of the photodiode.

[0011] However, in the above-mentioned conventional technology, it is necessary to form a separation region between a pair of photodiodes that detect the phase difference, and it is also necessary to form an overflow path within this separation region, so there are cases in which the volume of the photodiode itself is not sufficient.

[0012] That is, in the above-described conventional technology, there is room for further improvement in terms of increasing the amount of saturated signal charge of the photodiode in the light-receiving pixel that detects the phase difference (hereinafter also referred to as the phase difference detection pixel).

[0013] Therefore, it is expected that a technology capable of overcoming the above-mentioned problems and increasing the amount of saturated signal charge of the photodiode in the phase difference detection pixel will be realized.

[0014] [Structure of solid-state imaging device] 1 is a system configuration diagram showing a schematic configuration example of a solid-state imaging device 1 according to each embodiment of the present disclosure. As shown in FIG. 1, the solid-state imaging device 1, which is a CMOS image sensor, includes a pixel array unit 10, a system control unit 12, a vertical drive unit 13, a column readout circuit unit 14, a column signal processing unit 15, a horizontal drive unit 16, and a signal processing unit 17.

[0015] The pixel array section 10, system control section 12, vertical drive section 13, column readout circuit section 14, column signal processing section 15, horizontal drive section 16 and signal processing section 17 are provided on the same semiconductor substrate or on multiple electrically connected stacked semiconductor substrates.

[0016] The pixel array section 10 has light-receiving pixels 11 arranged two-dimensionally in a matrix, each having a photoelectric conversion element (photodiode PD (see Figure 3)) that can photoelectrically convert an amount of charge corresponding to the amount of incident light, store it internally, and output it as a signal.

[0017] In addition to the light-receiving pixels 11, the pixel array section 10 may include an area in which dummy pixels having a structure that does not have a photodiode PD, light-shielding pixels that block light incident from outside by shading the light-receiving surface, etc. are arranged in rows and / or columns.

[0018] The light-shielding pixels may have the same configuration as the light-receiving pixels 11, except that the light-receiving surfaces are structured so as to be light-shielded. In the following description, the photocharges corresponding to the amount of incident light may also be simply referred to as "charges," and the light-receiving pixels 11 may also be simply referred to as "pixels."

[0019] In the pixel array unit 10, pixel drive lines LD are formed for each row along the left-right direction in the drawing (the direction in which pixels in a pixel row are arranged) for the matrix-like pixel arrangement, and vertical pixel wiring LV is formed for each column along the up-down direction in the drawing (the direction in which pixels in a pixel column are arranged). One end of the pixel drive line LD is connected to an output terminal of the vertical drive unit 13 corresponding to each row.

[0020] The column readout circuit unit 14 includes at least a circuit that supplies a constant current to the light-sensitive pixels 11 in a selected row in the pixel array unit 10 for each column, a current mirror circuit, and a switch for selecting the light-sensitive pixel 11 to be read out.

[0021] The column readout circuit unit 14 forms an amplifier together with the transistor in the selected pixel in the pixel array unit 10, converts the photocharge signal into a voltage signal, and outputs it to the vertical pixel line LV.

[0022] The vertical drive unit 13 includes a shift register, an address decoder, etc., and drives each of the light-receiving pixels 11 in the pixel array unit 10, either all pixels at the same time or row by row, etc. Although the specific configuration of this vertical drive unit 13 is not shown in the figure, it is configured to have a readout scanning system and a sweep scanning system or a batch sweep and batch transfer system.

[0023] The readout scanning system sequentially selects and scans the light-receiving pixels 11 of the pixel array unit 10 row by row to read out pixel signals from the light-receiving pixels 11. In the case of row driving (rolling shutter operation), for the readout row on which the readout scanning system is to perform readout scanning, the readout scanning is performed in advance of the readout scanning by the shutter speed.

[0024] In the case of global exposure (global shutter operation), a collective discharge is performed prior to the collective transfer by the time of the shutter speed. This discharge discharges (resets) unnecessary charges from the photodiodes PD of the light-receiving pixels 11 in the readout row. The discharge (reset) of unnecessary charges then performs a so-called electronic shutter operation.

[0025] Here, the electronic shutter operation refers to an operation of discarding unnecessary photocharges that have been accumulated in the photodiode PD until just before, and starting new exposure (starting accumulation of photocharges).

[0026] The signal read by the readout operation by the readout scanning system corresponds to the amount of light that has entered since the previous readout operation or electronic shutter operation. In the case of row driving, the period from the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the accumulation time (exposure time) of the photocharges in the light-sensitive pixels 11. In the case of global exposure, the time from the collective sweep to the collective transfer is the accumulation time (exposure time).

[0027] The pixel signals output from each of the light-receiving pixels 11 in a pixel row selected and scanned by the vertical drive unit 13 are supplied through each of the vertical pixel wirings LV to a column signal processing unit 15. The column signal processing unit 15 performs predetermined signal processing on the pixel signals output from each of the light-receiving pixels 11 in the selected row through the vertical pixel wirings LV for each pixel column in the pixel array unit 10, and temporarily stores the pixel signals after signal processing.

[0028] Specifically, the column signal processing unit 15 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing, as signal processing. The CDS processing by the column signal processing unit 15 removes pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistor AMP.

[0029] In addition to the noise removal processing, the column signal processing unit 15 may be configured to have, for example, an AD conversion function so as to output pixel signals as digital signals.

[0030] The horizontal driving unit 16 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 15. By selective scanning by this horizontal driving unit 16, pixel signals that have been signal-processed by the column signal processing unit 15 are output sequentially to the signal processing unit 17.

[0031] The system control unit 12 includes a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 13, column signal processing unit 15, horizontal driving unit 16, etc. based on the various timing signals generated by the timing generator.

[0032] The solid-state imaging device 1 further includes a signal processing unit 17 and a data storage unit (not shown). The signal processing unit 17 has at least an addition processing function and performs various signal processing such as addition processing on the pixel signals output from the column signal processing unit 15.

[0033] The data storage unit temporarily stores data necessary for signal processing in the signal processing unit 17. The signal processing unit 17 and the data storage unit may be an external signal processing unit provided on a board separate from the solid-state imaging device 1, such as a DSP (Digital Signal Processor) or software processing, or may be mounted on the same board as the solid-state imaging device 1.

[0034] [Pixel circuit of the first embodiment] Next, an example of a pixel circuit according to the first embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of a pixel circuit according to the first embodiment of the present disclosure.

[0035] 2, in the first embodiment, a pair of light receiving pixels 11 share one readout circuit 18. Here, "shared" means that the pair of light receiving pixels 11 are electrically connected to a common readout circuit 18, that is, the outputs of the pair of light receiving pixels 11 are input to the common readout circuit 18.

[0036] The light-sensitive pixels 11 have common components. In Fig. 2, in order to distinguish the components of the light-sensitive pixels 11 from one another, identification numbers (1, 2) are added to the end of the reference numerals of the components of the light-sensitive pixels 11.

[0037] In the present disclosure, when it is necessary to distinguish the components of each photosensitive pixel 11 from one another, an identification number is added to the end of the reference numeral of the component of each photosensitive pixel 11. On the other hand, in the present disclosure, when it is not necessary to distinguish the components of each photosensitive pixel 11 from one another, the identification number at the end of the reference numeral of the component of each photosensitive pixel 11 is omitted.

[0038] Each of the light-receiving pixels 11 includes, for example, a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD. The photodiode PD is an example of a photoelectric conversion unit.

[0039] These light-receiving pixels 11 share a floating diffusion FD electrically connected to each transfer transistor TR. Here, "sharing" means that the individual photodiode PD of each light-receiving pixel 11 is electrically connected to the floating diffusion FD.

[0040] The photodiode PD performs photoelectric conversion to generate charges according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground potential).

[0041] The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR, that is, the transfer gate TG, is electrically connected to the pixel drive line LD (see FIG. 1). The transfer transistor TR is, for example, a CMOS transistor.

[0042] The floating diffusion FD is common to all the light-receiving pixels 11 that share one readout circuit 18, and is electrically connected to the input terminal of the readout circuit 18 that is common to these light-receiving pixels 11. This floating diffusion FD temporarily holds the charge output from the photodiode PD via the transfer transistor TR.

[0043] 2, the read circuit 18 includes, for example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and a switching transistor FDG. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0044] The source of the switching transistor FDG, which is the input of the readout circuit 18, is electrically connected to the floating diffusion FD, the drain of the switching transistor FDG is electrically connected to the source of the reset transistor RST, and the gate of the switching transistor FDG is electrically connected to the pixel drive line LD.

[0045] The drain of the reset transistor RST is electrically connected to a power supply voltage VDD, and the gate of the reset transistor RST is electrically connected to a pixel drive line LD.

[0046] The source of the amplifier transistor AMP is electrically connected to the drain of the select transistor SEL, the drain of the amplifier transistor AMP is electrically connected to the power supply voltage VDD, and the gate of the amplifier transistor AMP is electrically connected to the source of the switching transistor FDG and the floating diffusion FD.

[0047] The source of the selection transistor SEL, which is the output part of the readout circuit 18, is electrically connected to the vertical pixel line LV, and the gate of the selection transistor SEL is electrically connected to the pixel drive line LD.

[0048] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.

[0049] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion FD to the potential of the power supply voltage VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 18.

[0050] The amplifier transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplifier transistor AMP constitutes a source follower amplifier, and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD.

[0051] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing unit 15 (see FIG. 1) via the vertical pixel line LV.

[0052] The switching transistor FDG is used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark places. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (hereinafter also referred to as FD capacitance) is large, V when converted to voltage by the amplification transistor AMP will be small.

[0053] On the other hand, pixel signals become larger in bright places, so unless the FD capacitance is large, the floating diffusion FD cannot receive all the charge from the photodiode PD. Furthermore, the FD capacitance needs to be large so that V does not become too large (in other words, so that it becomes small) when converted to voltage by the amplification transistor AMP.

[0054] That is, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, and the overall FD capacitance increases. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance decreases. In this way, by switching the state of the switching transistor FDG, the FD capacitance can be made variable, and the conversion efficiency can be changed.

[0055] [Light-receiving pixel of the first embodiment] Next, a detailed configuration of the light receiving pixel 11 according to the first embodiment will be described with reference to Fig. 3 to Fig. 6. Fig. 3 is a plan view showing an example of the configuration of the light receiving pixel 11 according to the first embodiment of the present disclosure.

[0056] Moreover, Fig. 4 is a cross-sectional view taken along line AA in Fig. 3, and Fig. 5 is a cross-sectional view taken along line BB in Fig. 3. Note that pixel transistors, floating diffusions FD, and the like are omitted from the cross-sectional views shown in Fig. 4 and Fig. 5.

[0057] As shown in FIG. 4 and other figures, the pixel array section 10 includes a semiconductor layer 20, a planarization film 30, a color filter 40, and an on-chip lens 50.

[0058] The semiconductor layer 20 includes, for example, silicon. The semiconductor layer 20 has a plurality of photodiodes PD. The photodiodes PD are an example of photoelectric conversion units. Each light receiving pixel 11 is provided with a pair of photodiodes PD1 and PD2. By providing such a pair of photodiodes PD1 and PD2, the light receiving pixel 11 functions as a phase difference detection pixel.

[0059] The photodiode PD is composed of a first impurity region 21 containing impurities of a first conductivity type (for example, N-type) and a second impurity region 22 containing impurities of a second conductivity type (for example, P-type).

[0060] The first impurity region 21 is disposed in the center of the photodiode PD, and the second impurity region 22 is disposed along the side and bottom of the first impurity region 21 (the portion on the side opposite to the side where light L is incident).

[0061] Furthermore, the light-receiving pixel 11 has a first isolation region 24 and a second isolation region 25. The first isolation region 24 is disposed so as to surround the pair of photodiodes PD in one light-receiving pixel 11, as shown in FIG.

[0062] 4 and 5, the first isolation region 24 is provided so as to penetrate the semiconductor layer 20. The first isolation region 24 is made of a dielectric material with a low refractive index, such as silicon oxide (SiO2). This allows the first isolation region 24 to optically and electrically isolate the adjacent light-sensitive pixels 11 from each other.

[0063] 3, the second isolation region 25 is disposed between a pair of adjacent photodiodes PD in one light-receiving pixel 11. Moreover, the second isolation region 25 is provided so as to penetrate the semiconductor layer 20, as shown in FIG.

[0064] The second isolation region 25 is made of a dielectric material with a low refractive index, such as silicon oxide, and can thereby optically and electrically isolate a pair of adjacent photodiodes PD from each other.

[0065] In this way, in the first embodiment, the pair of photodiodes PD can be separated from each other using the second isolation region 25, and therefore the phase difference of the incident light L can be detected using the pair of photodiodes PD.

[0066] 3, in the first embodiment, second separation region 25 is arranged along one of two diagonals of first separation region 24, which is rectangular in plan view. For example, if the four corners of first separation region 24, which is rectangular in plan view, are corners C1, C2, C3, and C4, in clockwise order from the upper right, second separation region 25 is arranged along the diagonal line extending between corners C1 and C3.

[0067] This allows the volume of the photodiode PD to be increased compared to when the second isolation region 25 is arranged in a different direction in plan view (for example, a direction substantially parallel to one side of the first isolation region 24). Therefore, according to the first embodiment, the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel can be increased.

[0068] 3, in the first embodiment, it is preferable that the first isolation region 24 and the second isolation region 25 are not in contact with each other in a plan view. This makes it possible to arrange an overflow path connecting a pair of photodiodes PD in a gap formed between the first isolation region 24 and the second isolation region 25 (for example, near the corner C1 and near the corner C3).

[0069] Therefore, according to the first embodiment, by separately forming such an overflow path, it is possible to suppress a reduction in the volume of the photodiode PD, and therefore it is possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0070] In addition, in the first embodiment, since the first isolation region 24 and the second isolation region 25 are not in contact with each other in a planar view, pixel transistors, floating diffusions FDs, etc. can be arranged in the gap formed between the first isolation region 24 and the second isolation region 25.

[0071] For example, in the example of FIG. 3, in plan view, the floating diffusion FD is arranged at the corner C1, and the pixel transistor (for example, the amplification transistor AMP) and the active area AA of this pixel transistor are arranged at the corner C3.

[0072] That is, in the first embodiment, the first isolation region 24 and the second isolation region 25 are not in contact with each other in a plan view, which can improve the layout efficiency of the pixel array section 10. Note that the floating diffusion FD and the pixel transistor are provided, for example, on a surface 20b opposite to the light incident surface 20a of the semiconductor layer 20 in a cross-sectional view.

[0073] Furthermore, the pixel transistor arranged in the corner C3 is not limited to the amplification transistor AMP. Fig. 6 is a plan view showing an example of the configuration of the light receiving pixel group 100 according to the first embodiment of the present disclosure.

[0074] 6, one photosensitive pixel group 100 is made up of four photosensitive pixels 11 arranged in two rows and two columns in a plan view. The four photosensitive pixels 11 included in one photosensitive pixel group 100 share one readout circuit 18 (see FIG. 2).

[0075] In the first embodiment, in one photosensitive pixel group 100, an amplification transistor AMP is arranged in a corner C3 (see FIG. 3) of one (for example, the upper left) photosensitive pixel 11, and a selection transistor SEL is arranged in a corner C3 of one (for example, the upper right) photosensitive pixel 11.

[0076] In one photosensitive pixel group 100, a reset transistor RST is arranged at a corner C3 of one (for example, the bottom left) photosensitive pixel 11, and a switching transistor FDG is arranged at a corner C3 of one (for example, the bottom right) photosensitive pixel 11.

[0077] In this way, in the first embodiment, in the so-called 4×2 shared photosensitive pixel group 100, various types of pixel transistors may be arranged in the corners C3 of the plurality of photosensitive pixels 11. This makes it possible to further improve the layout efficiency of the pixel array unit 10.

[0078] In the first embodiment, the first isolation region 24 and the second isolation region 25 are preferably provided to penetrate the semiconductor layer 20. This allows the second impurity region 22 to be formed not only at the bottom of the first impurity region 21 but also on the side thereof, as shown in FIG.

[0079] This is because, in the process of forming the first isolation region 24 and the second isolation region 25, the second conductivity type impurities can also be diffused from the sidewalls of the trenches formed in the areas corresponding to the first isolation region 24 and the second isolation region 25.

[0080] Therefore, according to the first embodiment, the area of ​​the PN junction surface of the photodiode PD can be increased, and therefore the amount of saturated signal charge of the photodiode PD can be further increased.

[0081] In addition, in the first embodiment, by a process of diffusing impurities of the second conductivity type from the sidewalls of trenches formed in the regions corresponding to the above-mentioned first isolation region 24 and second isolation region 25, second impurity regions 22a can also be formed in corners C1 and C3, as shown in FIG. 5.

[0082] This makes it possible to form an overflow path connecting the pair of photodiodes PD together without separately forming a second impurity region by cutting out a part of the second isolation region 25. That is, in the first embodiment, the second impurity region 22a shown in FIG. 5 functions as an overflow path connecting the pair of photodiodes PD together.

[0083] In this way, in the first embodiment, the volume of the photodiode PD can be increased compared to when an overflow path is formed by cutting out a part of the second isolation region 25. Therefore, according to the first embodiment, the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel can be further increased.

[0084] Furthermore, in the first embodiment, it is possible to omit the step of separately forming the second impurity region by cutting out a part of the second isolation region 25. Therefore, according to the first embodiment, the manufacturing process of the pixel array unit 10 can be simplified, and the manufacturing cost of the solid-state imaging device 1 can be reduced.

[0085] Continuing with the description of other components of the pixel array section 10, the light-sensitive pixel 11 further includes a contact region 26 and transfer gates TG1 and TG2. The contact region 26 and the transfer gates TG1 and TG2 are provided on a surface 20b of the semiconductor layer 20 opposite to the light-incident surface 20a.

[0086] The contact regions 26 are electrically connected to the reference potential line, and are arranged at corners C2 and C4 of the light-sensitive pixel 11 in a plan view, as shown in Fig. 3. The contact region 26 arranged at corner C2 is electrically connected to photodiode PD2, and the contact region 26 arranged at corner C4 is electrically connected to photodiode PD1.

[0087] The transfer gate TG1 is disposed adjacent to the floating diffusion FD in a plan view and so as to shield the floating diffusion FD from the photodiode PD1.

[0088] The transfer gate TG2 is disposed adjacent to the floating diffusion FD in a plan view and so as to shield the floating diffusion FD from the photodiode PD2.

[0089] 4 and other figures, the planarization film 30 is disposed on the light incident surface 20a of the semiconductor layer 20, and planarizes the light incident surface 20a. The planarization film 30 is made of, for example, silicon oxide.

[0090] In the first embodiment, a fixed charge film (not shown) may be disposed between the photodiode PD and the first isolation region 24, the second isolation region 25, and the planarization film 30. Such a fixed charge film has the function of fixing charges (here, holes) at the interfaces between the photodiode PD and the first isolation region 24, the second isolation region 25, and the planarization film 30.

[0091] The fixed charge film is preferably made of a high-dielectric material with a large amount of fixed charge, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum oxide, zirconium oxide (ZrO2), titanium oxide, magnesium oxide (MgO2), or lanthanum oxide (La2O3).

[0092] The fixed charge film may also be made of praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), or the like.

[0093] The fixed charge film may also be made of gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), or the like.

[0094] The fixed charge film may also be made of ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), aluminum nitride (AlN), hafnium oxynitride (HfON), aluminum oxynitride film (AlON), or the like.

[0095] The color filter 40 is an optical filter that transmits light in a predetermined wavelength range out of the incident light L, and is provided between the on-chip lens 50 and the planarizing film 30.

[0096] The on-chip lens 50 is provided on the side of the semiconductor layer 20 where light L is incident, and has the function of condensing the light L toward the corresponding light-receiving pixel 11. The on-chip lens 50 is made of, for example, an organic material or silicon oxide.

[0097] 4 and 5, one on-chip lens 50 (i.e., one on-chip lens 50 for each pair of photodiodes PD) is provided for each light receiving pixel 11. This allows the light receiving pixel 11 to function as a phase difference detection pixel.

[0098] [Various Modifications of the First Embodiment] Next, various modifications of the first embodiment will be described with reference to FIGS.

[0099] <Variation 1> Fig. 7 is a cross-sectional view showing an example of the configuration of a light-receiving pixel 11 according to Modification 1 of the first embodiment of the present disclosure, and is a view corresponding to Fig. 4 of the first embodiment. As shown in Fig. 7, in Modification 1 of the first embodiment, the second isolation region 25 is provided from the surface 20b opposite to the light incident surface 20a of the semiconductor layer 20 to partway through the semiconductor layer 20 (i.e., without penetrating the semiconductor layer 20).

[0100] As a result, similarly to the first embodiment described above, the second impurity region 22 can be formed not only at the bottom but also at the side of the first impurity region 21. This is because, in the step of forming the first isolation region 24 and the second isolation region 25, the impurity of the second conductivity type can be diffused also from the sidewalls of the trenches formed in the portions corresponding to the first isolation region 24 and the second isolation region 25.

[0101] Therefore, according to the first modification of the first embodiment, the area of ​​the PN junction surface of the photodiode PD can be increased, and therefore the amount of saturated signal charge of the photodiode PD can be further increased.

[0102] Furthermore, in this modification 1, similarly to the above-described first embodiment, second impurity regions 22a (see FIG. 5) can also be formed in the corners C1 (see FIG. 3) and C3 (see FIG. 3).

[0103] This makes it possible to form an overflow path connecting the pair of photodiodes PD without separately forming a second impurity region by cutting out a part of the second isolation region 25. Therefore, according to the first modification of the first embodiment, it is possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0104] Furthermore, in this modification 1, it is possible to omit the step of separately forming the second impurity region by cutting out a part of the second isolation region 25. Therefore, according to modification 1 of the first embodiment, the manufacturing process of the pixel array section 10 can be simplified, and therefore the manufacturing cost of the solid-state imaging device 1 can be reduced.

[0105] In addition, in this variant example 1, as shown in FIG. 7, the second impurity region 22 is arranged on the light incident surface 20a side of the second isolation region 25, and therefore, the second impurity region 22 can also function as an overflow path connecting a pair of photodiodes PD.

[0106] Therefore, according to the first modification of the first embodiment, the light receiving pixels 11 can function more effectively as phase difference detection pixels.

[0107] <Variation 2> 8 is a cross-sectional view showing an example of the configuration of a light-receiving pixel 11 according to Modification 2 of the first embodiment of the present disclosure. As shown in Fig. 8, in Modification 2 of the first embodiment, the first isolation region 24 and the second isolation region 25 are provided from the surface 20b opposite to the light incident surface 20a of the semiconductor layer 20 to partway through the semiconductor layer 20 (i.e., without penetrating the semiconductor layer 20).

[0108] As a result, similarly to the first embodiment described above, the second impurity region 22 can be formed not only at the bottom but also at the side of the first impurity region 21. This is because, in the step of forming the first isolation region 24 and the second isolation region 25, the impurity of the second conductivity type can be diffused also from the sidewalls of the trenches formed in the portions corresponding to the first isolation region 24 and the second isolation region 25.

[0109] Therefore, according to the second modification of the first embodiment, the area of ​​the PN junction surface of the photodiode PD can be increased, and therefore the amount of saturated signal charge of the photodiode PD can be further increased.

[0110] Furthermore, in this modification 2, similarly to the above-described first embodiment, second impurity regions 22a (see FIG. 5) can also be formed in the corners C1 (see FIG. 3) and C3 (see FIG. 3).

[0111] This makes it possible to form an overflow path connecting the pair of photodiodes PD without separately forming a second impurity region by cutting out a part of the second isolation region 25. Therefore, according to the second modification of the first embodiment, it is possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0112] Furthermore, in this modification 2, it is possible to omit the step of separately forming the second impurity region by cutting out a part of the second isolation region 25. Therefore, according to modification 2 of the first embodiment, the manufacturing process of the pixel array unit 10 can be simplified, and therefore the manufacturing cost of the solid-state imaging device 1 can be reduced.

[0113] In addition, in this variant example 2, as shown in FIG. 8, the second impurity region 22 is arranged on the light incident surface 20a side of the second isolation region 25, and therefore, the second impurity region 22 can also function as an overflow path connecting a pair of photodiodes PD.

[0114] Therefore, according to the second modification of the first embodiment, the light receiving pixels 11 can function even better as phase difference detection pixels.

[0115] <Variations 3-5> 9 to 11 are plan views showing examples of the configuration of the light receiving pixel group 100 according to Modifications 3 to 5 of the first embodiment of the present disclosure. Note that, in order to facilitate understanding, elements other than the first isolation region 24 and the second isolation region 25 in the light receiving pixel 11 are not shown in these Figures.

[0116] In the above-described first embodiment, FIG. 6 shows an example in which all of the second isolation regions 25 in the plurality of light receiving pixels 11 included in the same light receiving pixel group 100 face the same direction, but the present disclosure is not limited to such an example.

[0117] For example, as shown in Figure 9, in four photosensitive pixels 11 arranged in two rows and two columns in a planar view, the second isolation regions 25 of the upper right and lower left photosensitive pixels 11 may face the same direction, and the second isolation regions 25 of the upper left and lower right photosensitive pixels 11 may face another same direction.

[0118] In this way, the plurality of light-sensitive pixels 11 included in the same light-sensitive pixel group 100 have second separation regions 25 facing in different directions, making it possible to detect phase differences in various directions.

[0119] Therefore, according to the third modification of the first embodiment, the light receiving pixels 11 can function even better as phase difference detection pixels.

[0120] Also, as shown in Figure 10, in four photosensitive pixels 11 arranged in two rows and two columns in a planar view, the second isolation regions 25 of the upper right and lower right photosensitive pixels 11 may face the same direction, and the second isolation regions 25 of the upper left and lower left photosensitive pixels 11 may face another same direction.

[0121] This also makes it possible to detect phase differences in various directions, allowing the light-receiving pixels 11 to function even better as phase difference detection pixels.

[0122] Also, as shown in Figure 11, in four photosensitive pixels 11 arranged in two rows and two columns in a planar view, the second isolation regions 25 of the upper right and upper left photosensitive pixels 11 may face the same direction, and the second isolation regions 25 of the lower right and lower left photosensitive pixels 11 may face another same direction.

[0123] This also makes it possible to detect phase differences in various directions, allowing the light-receiving pixels 11 to function even better as phase difference detection pixels.

[0124] <Variation 6> Fig. 12 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to Modification 6 of the first embodiment of the present disclosure, and corresponds to Fig. 3 of the first embodiment. As shown in Fig. 12, in Modification 6 of the first embodiment, the contact region 26 partially overlaps the second isolation region 25 in plan view.

[0125] This allows both photodiodes PD to be connected to the ground potential using one contact region 26, thereby improving the layout efficiency of the pixel array section 10.

[0126] <Variation 7> 13 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to Modification 7 of the first embodiment of the present disclosure. As shown in Fig. 13, in Modification 7 of the first embodiment, a pair of floating diffusions FD are provided for each of a pair of photodiodes PD.

[0127] Specifically, the floating diffusion FD1 corresponding to the photodiode PD1 is disposed at the corner C4 in plan view, and the floating diffusion FD2 corresponding to the photodiode PD2 is disposed at the corner C2 in plan view.

[0128] The floating diffusions FD1 and FD2 are electrically connected via a wiring layer (not shown), and therefore the photodiodes PD1 and PD2 share the floating diffusion FD.

[0129] A contact region 26 is disposed in the corner C1 of the light-receiving pixel 11 where the floating diffusion FD was disposed in the first embodiment.

[0130] In the seventh modification of the first embodiment, the planar configuration allows the floating diffusion FD, the contact region 26, and the pixel transistors to be efficiently arranged. Therefore, according to the seventh modification of the first embodiment, the layout efficiency of the pixel array section 10 can be improved.

[0131] <Variation 8> 14 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to Modification 8 of the first embodiment of the present disclosure. As shown in Fig. 14, in Modification 8 of the first embodiment, similar to Modification 7 described above, a pair of floating diffusions FD are provided for each of a pair of photodiodes PD.

[0132] In addition, in this modification 8, the contact region 26 is provided so as to overlap the second isolation region 25 in a plan view. Then, in the corner C1 of the light-sensitive pixel 11 where the contact region 26 was arranged in the above-described modification 7, another pixel transistor (for example, a selection transistor SEL) and the active region AA of this pixel transistor are arranged.

[0133] In the eighth modification of the first embodiment, such a planar configuration allows the floating diffusion FD, the contact region 26, and the two pixel transistors to be efficiently arranged. Therefore, according to the eighth modification of the first embodiment, the layout efficiency of the pixel array section 10 can be improved.

[0134] 15 is a plan view showing an example of the configuration of a light receiving pixel group 100 according to Modification 8 of the first embodiment of the present disclosure.

[0135] 15, in Modification 8, for example, two photosensitive pixels 11 arranged vertically in a plan view constitute one photosensitive pixel group 100. Furthermore, the two photosensitive pixels 11 included in one photosensitive pixel group 100 share one readout circuit 18 (see FIG. 2).

[0136] In the example of FIG. 15, in one photosensitive pixel group 100, a switching transistor FDG is arranged at a corner C1 (see FIG. 14) of one (for example, the upper) photosensitive pixel 11, and a reset transistor RST is arranged at a corner C3.

[0137] Furthermore, in one photosensitive pixel group 100, a selection transistor SEL is arranged at a corner C1 of another (for example, lower) photosensitive pixel 11, and an amplification transistor AMP is arranged at a corner C3.

[0138] In this way, in the eighth modification of the first embodiment, various types of pixel transistors may be arranged at the corners C1 and C3 of the plurality of light receiving pixels 11 in the so-called 2×2 shared light receiving pixel group 100. This makes it possible to further improve the layout efficiency of the pixel array unit 10.

[0139] 16 is a plan view showing another example of the configuration of the photosensitive pixel group 100 according to Modification 8 of the first embodiment of the present disclosure. As shown in Fig. 16, in Modification 8, one photosensitive pixel group 100 may be configured with, for example, two photosensitive pixels 11 aligned side by side in a plan view.

[0140] In this modification 8, in one photosensitive pixel group 100, the switching transistor FDG is arranged at the corner C1 (see FIG. 14) of one (for example, the right) photosensitive pixel 11, and the reset transistor RST is arranged at the corner C3.

[0141] Furthermore, in one photosensitive pixel group 100, a selection transistor SEL is arranged at a corner C1 of another (for example, left) photosensitive pixel 11, and an amplification transistor AMP is arranged at a corner C3.

[0142] In this way, in the eighth modification of the first embodiment, various types of pixel transistors may be arranged at the corners C1 and C3 of the plurality of light receiving pixels 11 in the so-called 4×1 shared light receiving pixel group 100. This makes it possible to further improve the layout efficiency of the pixel array unit 10.

[0143] <Variation 9> 17 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to Modification 9 of the first embodiment of the present disclosure. As shown in Fig. 17, in Modification 9 of the first embodiment, the arrangement of pixel transistors provided in the corner C3 differs from that of the first embodiment (Fig. 3) described above.

[0144] Specifically, an active area AA having a substantially L-shape in plan view is arranged along the corner C3, and different pixel transistors (for example, an amplifier transistor AMP and a selection transistor SEL) are arranged on each of the two sides of the active area AA.

[0145] In the ninth modification of the first embodiment, by having such a planar configuration, the floating diffusion FD, the contact region 26, and the pixel transistors can be arranged more efficiently. Therefore, according to the ninth modification of the first embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0146] Furthermore, in this modification 9, the area of ​​the active region AA can be made large by disposing the approximately L-shaped active region AA within the light-receiving pixel 11. Therefore, according to modification 9 of the first embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0147] 18 is a plan view showing an example of the configuration of a light receiving pixel group 100 according to a ninth modification of the first embodiment of the present disclosure.

[0148] 18, in this modification 9, for example, four light receiving pixels 11 arranged in two rows and two columns in a plan view constitute one light receiving pixel group 100. Furthermore, the four light receiving pixels 11 included in one light receiving pixel group 100 share one readout circuit 18 (see FIG. 2).

[0149] In this variant example 9, in one photosensitive pixel group 100, two amplification transistors AMP are arranged in a corner C3 (see Figure 17) of one (for example, the upper left) photosensitive pixel 11, and a selection transistor SEL is arranged in a corner C3 of one (for example, the upper right) photosensitive pixel 11.

[0150] In one photosensitive pixel group 100, a reset transistor RST is arranged at a corner C3 of one (for example, the bottom left) photosensitive pixel 11, and a switching transistor FDG is arranged at a corner C3 of one (for example, the bottom right) photosensitive pixel 11.

[0151] In this way, in the ninth modification of the first embodiment, various types of pixel transistors may be arranged in the corners C3 of the plurality of light receiving pixels 11 in the so-called 4×2 shared light receiving pixel group 100. This makes it possible to further improve the layout efficiency of the pixel array unit 10.

[0152] Furthermore, in the ninth modification of the first embodiment, a plurality of (two in FIG. 18 ) amplification transistors AMP connected in parallel can be provided in the readout circuit 18 shared by one light receiving pixel group 100. This can improve random noise in the readout circuit 18.

[0153] FIG. 19 is a plan view showing another example of the configuration of the light receiving pixel group 100 according to the ninth modification of the first embodiment of the present disclosure.

[0154] In the example of Figure 19, in one photosensitive pixel group 100, two amplification transistors AMP are arranged in the corner C3 (see Figure 17) of one (for example, the upper left) photosensitive pixel 11, and two amplification transistors AMP are arranged in the corner C3 of one (for example, the upper right) photosensitive pixel 11.

[0155] In one photosensitive pixel group 100, an amplification transistor AMP and a selection transistor SEL are arranged in a corner C3 of one (for example, the lower left) photosensitive pixel 11. In one photosensitive pixel group 100, a reset transistor RST and a switching transistor FDG are arranged in a corner C3 of one (for example, the lower right) photosensitive pixel 11.

[0156] In this way, in the ninth modification of the first embodiment, various pixel transistors may be arranged in the corners C3 of the plurality of light receiving pixels 11 in the so-called 4×2 shared light receiving pixel group 100. This also makes it possible to further improve the layout efficiency of the pixel array unit 10.

[0157] 19, five amplification transistors AMP connected in parallel can be provided in the readout circuit 18 (see FIG. 2) shared by one light receiving pixel group 100. This can improve random noise in the readout circuit 18.

[0158] <Modification 10> 20 is a plan view showing an example of the configuration of a light-receiving pixel 11 according to Modification 10 of the first embodiment of the present disclosure. As shown in Fig. 20, in Modification 10 of the first embodiment, similar to Modification 8 described above, a pair of floating diffusions FD are provided in each of a pair of photodiodes PD, and the contact region 26 is provided so as to overlap with the second isolation region 25 in plan view.

[0159] Further, a substantially L-shaped active area AA is arranged along the corner C1, and different pixel transistors (for example, a reset transistor RST and a switching transistor FDG) are arranged on the two sides of the active area AA.

[0160] Furthermore, a substantially L-shaped active area AA is arranged along the corner C3, and different pixel transistors (for example, an amplifier transistor AMP and a selection transistor SEL) are arranged on the two sides of the active area AA.

[0161] In the tenth modification of the first embodiment, the planar configuration allows the floating diffusion FD, the contact region 26, and the pixel transistors to be arranged more efficiently. Therefore, according to the tenth modification of the first embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0162] It should be noted that the arrangement of the pixel transistors in the light-receiving pixel 11 is not limited to the example in Fig. 20. Fig. 21 is a plan view showing another example of the configuration of the light-receiving pixel 11 according to the tenth modification of the first embodiment of the present disclosure.

[0163] In the example of FIG. 21, a substantially L-shaped active area AA is arranged along the corner C1, and different pixel transistors (for example, an amplifier transistor AMP and a selection transistor SEL) are arranged on each of the two sides of the active area AA.

[0164] Further, a substantially L-shaped active area AA is arranged along the corner C3, and different pixel transistors (for example, a reset transistor RST and a switching transistor FDG) are arranged on the two sides of the active area AA.

[0165] In the tenth modification of the first embodiment, even with such a planar configuration, the floating diffusion FD, the contact region 26, and the pixel transistors can be arranged more efficiently. Therefore, according to the tenth modification of the first embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0166] Furthermore, in this modification 10, the area of ​​the active region AA can be increased by disposing the approximately L-shaped active region AA within the light-receiving pixel 11. Therefore, according to modification 10 of the first embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0167] 20 and 21, a combination of an amplifier transistor AMP and a select transistor SEL, or a combination of a reset transistor RST and a switching transistor FDG may be arranged in one active region AA, thereby further improving the layout efficiency of the pixel array section 10.

[0168] <Variation 11> 22 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 11 of the first embodiment of the present disclosure. In Modification 11 of the first embodiment, the arrangement of the transfer gates TG1 and TG2 is different from that in the first embodiment (FIG. 3) described above.

[0169] 22, in plan view, the transfer gates TG1 and TG2 partially overlap the second isolation region 25. This also makes it possible to further improve the layout efficiency of the pixel array section 10.

[0170] <Variation 12> 23 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 12 of the first embodiment of the present disclosure. In Modification 12 of the first embodiment, the arrangement of pixel transistors is different from that of the above-described first embodiment (FIG. 3).

[0171] 23, in plan view, a part of the pixel transistor (here, the amplification transistor AMP) overlaps the second isolation region 25. This also makes it possible to further improve the layout efficiency of the pixel array section 10.

[0172] [Second embodiment] In recent years, a technology has emerged for back-illuminated CMOS image sensors that detects phase differences by illuminating four photodiodes through the same on-chip lens. Furthermore, in such image sensors, the dynamic range and SNR can be improved by increasing the saturation signal charge of the photodiodes.

[0173] However, in the above-mentioned conventional technology, it is necessary to form an isolation region between the four photodiodes that detect the phase difference, and it is also necessary to form an overflow path within this isolation region, so there are cases in which the volume of the photodiodes themselves is not sufficient.

[0174] That is, in the above-described conventional technology, there is room for further improvement in terms of increasing the amount of saturated signal charge of the photodiode in the phase difference detection pixel.

[0175] Therefore, it is hoped that a technology will be realized that can overcome the above-mentioned problems and increase the amount of saturated signal charge of the photodiodes in a phase difference detection pixel having four photodiodes.

[0176] [Pixel circuit of the second embodiment] First, an example of a pixel circuit according to the second embodiment will be described with reference to Fig. 24. Fig. 24 is a diagram showing an example of a pixel circuit according to the second embodiment of the present disclosure.

[0177] 24, in the second embodiment, four light receiving pixels 11 share one readout circuit 18. Here, "shared" means that the four light receiving pixels 11 are electrically connected to a common readout circuit 18, that is, the outputs of the four light receiving pixels 11 are input to the common readout circuit 18.

[0178] The photosensitive pixels 11 have common components. In Fig. 24, in order to distinguish the components of the photosensitive pixels 11 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the components of each photosensitive pixel 11.

[0179] In the present disclosure, when it is necessary to distinguish the components of each photosensitive pixel 11 from one another, an identification number is added to the end of the reference numeral of the component of each photosensitive pixel 11. On the other hand, in the present disclosure, when it is not necessary to distinguish the components of each photosensitive pixel 11 from one another, the identification number at the end of the reference numeral of the component of each photosensitive pixel 11 is omitted.

[0180] Each of the light-receiving pixels 11 includes, for example, a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD. The photodiode PD is an example of a photoelectric conversion unit.

[0181] These light-receiving pixels 11 share a floating diffusion FD electrically connected to each transfer transistor TR. Here, "sharing" means that the individual photodiode PD of each light-receiving pixel 11 is electrically connected to the floating diffusion FD.

[0182] The photodiode PD performs photoelectric conversion to generate charges according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground potential).

[0183] The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR, that is, the transfer gate TG, is electrically connected to the pixel drive line LD (see FIG. 1). The transfer transistor TR is, for example, a CMOS transistor.

[0184] The floating diffusion FD is common to all the light-receiving pixels 11 that share one readout circuit 18, and is electrically connected to the input terminal of the readout circuit 18 that is common to these light-receiving pixels 11. This floating diffusion FD temporarily holds the charge output from the photodiode PD via the transfer transistor TR.

[0185] 24, the read circuit 18 includes, for example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and a switching transistor FDG. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0186] The source of the switching transistor FDG, which is the input of the readout circuit 18, is electrically connected to the floating diffusion FD, the drain of the switching transistor FDG is electrically connected to the source of the reset transistor RST, and the gate of the switching transistor FDG is electrically connected to the pixel drive line LD.

[0187] The drain of the reset transistor RST is electrically connected to a power supply voltage VDD, and the gate of the reset transistor RST is electrically connected to a pixel drive line LD.

[0188] The source of the amplifier transistor AMP is electrically connected to the drain of the select transistor SEL, the drain of the amplifier transistor AMP is electrically connected to the power supply voltage VDD, and the gate of the amplifier transistor AMP is electrically connected to the source of the switching transistor FDG and the floating diffusion FD.

[0189] The source of the selection transistor SEL, which is the output part of the readout circuit 18, is electrically connected to the vertical pixel line LV, and the gate of the selection transistor SEL is electrically connected to the pixel drive line LD.

[0190] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.

[0191] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion FD to the potential of the power supply voltage VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 18.

[0192] The amplifier transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplifier transistor AMP constitutes a source follower amplifier, and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD.

[0193] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing unit 15 (see FIG. 1) via the vertical pixel line LV.

[0194] The switching transistor FDG is used to switch the conversion efficiency. The function of this switching transistor FDG is the same as that of the first embodiment described above, so a detailed description will be omitted.

[0195] [Light-receiving pixel of the second embodiment] Next, a detailed configuration of the light receiving pixel 11 according to the second embodiment will be described with reference to Fig. 25 to Fig. 27. Fig. 25 is a plan view showing an example of the configuration of the light receiving pixel 11 according to the second embodiment of the present disclosure.

[0196] 26 is a cross-sectional view taken along line CC in Fig. 25, and Fig. 27 is a cross-sectional view taken along line DD in Fig. 25. Note that pixel transistors, floating diffusions FD, and the like are omitted from the cross-sectional views shown in Fig. 26 and Fig. 27.

[0197] As shown in FIG. 26 and other figures, the pixel array section 10 includes a semiconductor layer 20, a planarization film 30, a color filter 40, and an on-chip lens 50.

[0198] The semiconductor layer 20 includes, for example, silicon. The semiconductor layer 20 has a plurality of photodiodes PD. The photodiodes PD are an example of photoelectric conversion units. As shown in FIG. 25, one light receiving pixel 11 is provided with four photodiodes PD1 to PD4. By providing these four photodiodes PD1 to PD4, the light receiving pixel 11 functions as a phase difference detection pixel.

[0199] The photodiode PD is composed of a first impurity region 21 containing impurities of a first conductivity type (for example, N-type) and a second impurity region 22 containing impurities of a second conductivity type (for example, P-type).

[0200] The first impurity region 21 is disposed in the center of the photodiode PD, and the second impurity region 22 is disposed along the side and bottom of the first impurity region 21 (the portion on the side opposite to the side where light L is incident).

[0201] Furthermore, the light receiving pixel 11 has a first isolation region 24 and a second isolation region 25. The first isolation region 24 is arranged so as to surround four photodiodes PD in one light receiving pixel 11, as shown in FIG.

[0202] 26 and 27, the first isolation region 24 is provided to penetrate the semiconductor layer 20. The first isolation region 24 is made of a dielectric material with a low refractive index, such as silicon oxide (SiO2). This allows the first isolation region 24 to optically and electrically isolate the adjacent light-sensitive pixels 11 from each other.

[0203] 25, the second isolation region 25 is disposed between four adjacent photodiodes PD in one light-receiving pixel 11. Moreover, the second isolation region 25 is provided so as to penetrate the semiconductor layer 20, as shown in FIG.

[0204] The second isolation region 25 is made of a dielectric material with a low refractive index, such as silicon oxide, and can thereby optically and electrically isolate the four photodiodes PD adjacent to each other.

[0205] In this way, in the second embodiment, the four photodiodes PD can be separated from one another using the second isolation region 25, and therefore the phase difference of the incident light L can be detected using the four photodiodes PD.

[0206] Furthermore, in the second embodiment, four photodiodes PD are provided in one light receiving pixel 11, so that a high dynamic range (HDR) image can be obtained without the need to capture images multiple times.

[0207] 25, in the second embodiment, the second separation region 25 is arranged along two diagonals of the first separation region 24, which is rectangular in plan view. For example, if the four corners of the first separation region 24, which is rectangular in plan view, are corners C1, C2, C3, and C4, in clockwise order from the upper right, the second separation region 25 is arranged along the diagonal line extending between corners C1 and C3 and the diagonal line extending between corners C2 and C4. That is, the second separation region 25 according to the second embodiment is substantially X-shaped in plan view.

[0208] This allows the volume of the photodiode PD to be increased compared to when the second isolation region 25 is arranged in a different direction in plan view (for example, in a direction approximately parallel to each of the two perpendicular sides of the first isolation region 24). Therefore, according to the second embodiment, the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel can be increased.

[0209] In the second embodiment, the first isolation region 24 and the second isolation region 25 may be provided so as to penetrate the semiconductor layer 20. This allows the second impurity region 22 to be formed not only at the bottom of the first impurity region 21 but also on the side thereof, as shown in FIG.

[0210] This is because, in the process of forming the first isolation region 24 and the second isolation region 25, the second conductivity type impurities can also be diffused from the sidewalls of the trenches formed in the areas corresponding to the first isolation region 24 and the second isolation region 25.

[0211] Therefore, according to the second embodiment, the area of ​​the PN junction surface of the photodiode PD can be increased, and therefore the amount of saturated signal charge of the photodiode PD can be further increased.

[0212] Continuing with the description of other components of the pixel array section 10, the light-receiving pixel 11 further includes a contact region 26, floating diffusions FD1-FD4, and transfer gates TG1-TG4. The contact region 26, floating diffusions FD1-FD4, and transfer gates TG1-TG4 are provided on a surface 20b of the semiconductor layer 20 opposite to the light incident surface 20a.

[0213] The contact regions 26 are electrically connected to the reference potential line, and as shown in FIG. 25, are arranged at the corners C1 to C4 of the light-sensitive pixel 11 in plan view.

[0214] The floating diffusion FD1 is part of the floating diffusion FD (see FIG. 24), and is adjacent to the intersection of the second isolation regions 25 in plan view, and is disposed between the intersection of the second isolation regions 25 and the photodiode PD1.

[0215] The floating diffusion FD2 is a part of the floating diffusion FD, and is adjacent to the intersection of the second isolation regions 25 in plan view, and is disposed between the intersection of the second isolation regions 25 and the photodiode PD2.

[0216] The floating diffusion FD3 is a part of the floating diffusion FD, and is adjacent to the intersection of the second isolation regions 25 in plan view, and is disposed between the intersection of the second isolation regions 25 and the photodiode PD3.

[0217] The floating diffusion FD4 is a part of the floating diffusion FD, and is adjacent to the intersection of the second isolation regions 25 in plan view, and is disposed between the intersection of the second isolation regions 25 and the photodiode PD4.

[0218] The floating diffusions FD1 to FD4 are electrically connected via a wiring layer (not shown), and therefore the photodiodes PD1 to PD4 share the floating diffusion FD.

[0219] The transfer gate TG1 is disposed adjacent to the floating diffusion FD1 in a plan view and so as to shield the floating diffusion FD1 from the photodiode PD1.

[0220] The transfer gate TG2 is disposed adjacent to the floating diffusion FD2 in a plan view and so as to shield the floating diffusion FD2 from the photodiode PD2.

[0221] The transfer gate TG3 is disposed adjacent to the floating diffusion FD3 in a plan view and so as to shield the floating diffusion FD3 from the photodiode PD3.

[0222] The transfer gate TG4 is disposed adjacent to the floating diffusion FD4 in a plan view and so as to shield the floating diffusion FD4 from the photodiode PD4.

[0223] In the second embodiment, the pixel transistors and the active regions AA of the pixel transistors are arranged so as to overlap with the four photodiodes PD, respectively, in plan view.

[0224] For example, in plan view, the switching transistor FDG is arranged so as to overlap the photodiode PD1, and the amplification transistor AMP is arranged so as to overlap the photodiode PD2.

[0225] In addition, in plan view, the selection transistor SEL is arranged so as to overlap the photodiode PD3, and the reset transistor RST is arranged so as to overlap the photodiode PD4.

[0226] In the second embodiment, such a planar configuration allows the floating diffusion FD, the contact region 26, and the pixel transistors to be arranged efficiently. Therefore, according to the second embodiment, the layout efficiency of the pixel array section 10 can be improved.

[0227] 26 and other figures, the planarization film 30 is disposed on the light incident surface 20a of the semiconductor layer 20, and planarizes the light incident surface 20a. The planarization film 30 is made of, for example, silicon oxide.

[0228] In the second embodiment, a fixed charge film (not shown) may be disposed between the photodiode PD and the first isolation region 24, the second isolation region 25, and the planarization film 30. Such a fixed charge film has the function of fixing charges (here, holes) at the interfaces between the photodiode PD and the first isolation region 24, the second isolation region 25, and the planarization film 30.

[0229] The fixed charge film is preferably made of a high-dielectric material having a large amount of fixed charge. For example, the fixed charge film may be made of the same material as the fixed charge film according to the first embodiment.

[0230] The color filter 40 is an optical filter that transmits light in a predetermined wavelength range out of the incident light L, and is provided between the on-chip lens 50 and the planarizing film 30.

[0231] The on-chip lens 50 is provided on the side of the semiconductor layer 20 where light L is incident, and has the function of condensing the light L toward the corresponding light-receiving pixel 11. The on-chip lens 50 is made of, for example, an organic material or silicon oxide.

[0232] 26 and 27, one on-chip lens 50 (i.e., one on-chip lens 50 for every four photodiodes PD) is provided for each light receiving pixel 11. This allows the light receiving pixel 11 to function as a phase difference detection pixel.

[0233] [Various Modifications of the Second Embodiment] Next, various modifications of the second embodiment will be described with reference to FIGS.

[0234] <Variation 1> Fig. 28 is a cross-sectional view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 1 of the second embodiment of the present disclosure, and is a view corresponding to Fig. 26 of the second embodiment. As shown in Fig. 28, in Modification 1 of the second embodiment, the second isolation region 25 is provided from the surface 20b opposite to the light incident surface 20a of the semiconductor layer 20 to partway through the semiconductor layer 20 (i.e., without penetrating the semiconductor layer 20).

[0235] This also makes it possible to form the second impurity region 22 not only at the bottom but also at the side of the first impurity region 21, as in the second embodiment described above. This is because, in the step of forming the first isolation region 24 and the second isolation region 25, the impurity of the second conductivity type can be diffused also from the sidewalls of the trenches formed in the portions corresponding to the first isolation region 24 and the second isolation region 25.

[0236] Therefore, according to the first modification of the second embodiment, the area of ​​the PN junction surface of the photodiode PD can be increased, and therefore the amount of saturated signal charge of the photodiode PD can be further increased.

[0237] In addition, in this variant example 1, as shown in Figure 28, the second impurity region 22 is arranged on the light incident surface 20a side of the second isolation region 25, so that the second impurity region 22 can also function as an overflow path connecting a pair of photodiodes PD.

[0238] Therefore, according to the first modification of the second embodiment, the light receiving pixels 11 can function even better as phase difference detection pixels.

[0239] <Variation 2> 29 is a cross-sectional view showing an example of the configuration of a light-receiving pixel 11 according to Modification 2 of the second embodiment of the present disclosure. As shown in Fig. 29, in Modification 2 of the second embodiment, the first isolation region 24 and the second isolation region 25 are provided from the surface 20b opposite to the light incident surface 20a of the semiconductor layer 20 to partway through the semiconductor layer 20 (i.e., without penetrating the semiconductor layer 20).

[0240] This also makes it possible to form second impurity region 22 not only at the bottom but also at the side of second impurity region 22, as in the second embodiment described above. This is because, in the step of forming first isolation region 24 and second isolation region 25, the impurity of the second conductivity type can be diffused also from the sidewalls of trenches formed in the portions corresponding to first isolation region 24 and second isolation region 25.

[0241] Therefore, according to the second modification of the second embodiment, the area of ​​the PN junction surface of the photodiode PD can be increased, and therefore the amount of saturated signal charge of the photodiode PD can be further increased.

[0242] In addition, in this variant example 2, as shown in Figure 29, the second impurity region 22 is arranged on the light incident surface 20a side of the second isolation region 25, so that the second impurity region 22 can also function as an overflow path connecting a pair of photodiodes PD.

[0243] Therefore, according to the second modification of the second embodiment, the light-receiving pixels 11 can function even better as phase difference detection pixels.

[0244] <Variation 3> 30 is a cross-sectional view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 3 of the second embodiment of the present disclosure. As shown in Fig. 30, in Modification 3 of the second embodiment, the second isolation region 25 is provided from the light incident surface 20a of the semiconductor layer 20 to partway through the semiconductor layer 20 (i.e., not penetrating the semiconductor layer 20).

[0245] This also makes it possible to separate the four photodiodes PD by the second separation region 25, as in the second embodiment described above. Therefore, according to the third modification of the second embodiment, the light receiving pixels 11 can function as phase difference detection pixels.

[0246] In addition, in this variant example 3, as shown in Figure 30, the second impurity region 22 is arranged on the opposite side of the light incident surface 20a of the second isolation region 25, so that the second impurity region 22 can also function as an overflow path connecting a pair of photodiodes PD.

[0247] Therefore, according to the third modification of the second embodiment, the light receiving pixels 11 can function even better as phase difference detection pixels.

[0248] <Variation 4> 31 is a cross-sectional view showing an example of the configuration of a light-receiving pixel 11 according to Modification 4 of the second embodiment of the present disclosure. As shown in Fig. 31, in Modification 4 of the second embodiment, the first isolation region 24 and the second isolation region 25 are provided from the light incident surface 20a of the semiconductor layer 20 to partway through the semiconductor layer 20 (i.e., not penetrating the semiconductor layer 20).

[0249] This also makes it possible to separate the four photodiodes PD by the second separation region 25, as in the above-described second embodiment. Therefore, according to the fourth modification of the second embodiment, the light receiving pixel 11 can function as a phase difference detection pixel.

[0250] In addition, in this variant example 4, as shown in Figure 31, the second impurity region 22 is arranged on the opposite side of the light incident surface 20a of the second isolation region 25, so that the second impurity region 22 can also function as an overflow path connecting a pair of photodiodes PD.

[0251] Therefore, according to the fourth modification of the second embodiment, the light-receiving pixels 11 can function even better as phase difference detection pixels.

[0252] <Variation 5> 32 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 5 of the second embodiment of the present disclosure. In Modification 5 of the second embodiment, the configuration of the second isolation region 25 differs from that of the above-described second embodiment (FIG. 25).

[0253] 32, the second separation region 25 has an end portion that does not contact the first separation region 24 in a plan view. For example, in this modification 5, the first separation region 24 and the second separation region 25 do not contact each other at corners C2 and C4.

[0254] This makes it possible to arrange, in the gap formed between the first isolation region 24 and the second isolation region 25, an overflow path that connects the pair of photodiodes PD adjacent to the gap.

[0255] For example, an overflow path connecting photodiode PD2 and photodiode PD3 can be disposed in the gap adjacent to corner C2, and an overflow path connecting photodiode PD1 and photodiode PD4 can be disposed in the gap adjacent to corner C4.

[0256] That is, in this modification 5, by separately forming such an overflow path, it is possible to suppress a decrease in the volume of the photodiode PD. Therefore, according to modification 5 of the second embodiment, it is possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0257] Furthermore, in this variant example 5, the second isolation region 25 has an end portion that is not in contact with the first isolation region 24 in a planar view, so that pixel transistors and the like can be placed in the gap formed between the first isolation region 24 and the second isolation region 25.

[0258] For example, in the example of FIG. 32, in plan view, a substantially L-shaped active area AA is arranged along the corner C2, and different pixel transistors (for example, an amplification transistor AMP and a selection transistor SEL) are arranged on each of the two sides of this active area AA.

[0259] In addition, in plan view, a substantially L-shaped active area AA is arranged along the corner C4, and different pixel transistors (for example, a reset transistor RST and a switching transistor FDG) are arranged on the two sides of this active area AA.

[0260] That is, in this fifth modification, the second isolation region 25 has an end portion that is not in contact with the first isolation region 24 in a plan view, and therefore the layout efficiency of the pixel array section 10 can be improved.

[0261] Furthermore, in this modification 5, the area of ​​the active region AA can be made large by disposing the approximately L-shaped active region AA within the light-receiving pixel 11. Therefore, according to modification 5 of the second embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0262] <Variation 6> 33 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 6 of the second embodiment of the present disclosure. In Modification 6 of the second embodiment, the configuration of the second isolation region 25 differs from that of Modification 5 (FIG. 32) described above.

[0263] 33, the first isolation region 24 and the second isolation region 25 are not in contact with each other. This allows an overflow path to be disposed in the gap formed between the first isolation region 24 and the second isolation region 25, connecting a pair of photodiodes PD adjacent to the gap.

[0264] That is, in this modification 6, it is possible to suppress a decrease in the volume of the photodiode PD by separately forming such an overflow path. Therefore, according to modification 6 of the second embodiment, it is possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0265] Furthermore, in this variant example 6, since the first isolation region 24 and the second isolation region 25 are not in contact with each other, pixel transistors and the like can be placed in the gap formed between the first isolation region 24 and the second isolation region 25.

[0266] 33, an active region AA having a generally C-shape in plan view is arranged, extending from near corner C3 to near corner C4, corner C1, corner C2, and corner C3. Different pixel transistors (e.g., an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG) are arranged on each of the four sides of this active region AA. One contact region 26 is arranged near corner C3.

[0267] That is, in this sixth modification, the first isolation region 24 and the second isolation region 25 are not in contact with each other, and therefore the layout efficiency of the pixel array section 10 can be further improved.

[0268] Furthermore, in this modification 6, the area of ​​the active region AA can be further increased by disposing the approximately C-shaped active region AA within the light-receiving pixel 11. Therefore, according to modification 6 of the second embodiment, the layout efficiency of the pixel array section 10 can be further improved.

[0269] <Variation 7> 34 is a plan view showing an example of the configuration of a light-sensitive pixel 11 according to Modification 7 of the second embodiment of the present disclosure. In Modification 7 of the second embodiment, the configuration of the second isolation region 25 differs from that of Modification 6 (FIG. 33) described above.

[0270] 33, second separation region 25 is not provided at the intersection in second separation region 25 which is substantially X-shaped in plan view. In other words, in this seventh modification, second separation region 25 has notch 25a at the intersection.

[0271] This allows an overflow path that connects a pair of photodiodes PD adjacent to the gap to be disposed in the gap formed in the cutout portion 25a.

[0272] That is, in this modification 7, by separately forming such an overflow path, it is possible to suppress a decrease in the volume of the photodiode PD. Therefore, according to modification 7 of the second embodiment, it is possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0273] Furthermore, in this modification 7, the second isolation region 25 has the cutout 25a, and thus the floating diffusion FD can be disposed in the cutout 25a. That is, in this modification 7, the second isolation region 25 has the cutout 25a, and thus the layout efficiency of the pixel array section 10 can be further improved.

[0274] Furthermore, in this modification 7, by arranging the cutout portion 25a of the second isolation region 25 in the center of the light-receiving pixel 11 in plan view, it is possible to arrange one floating diffusion FD shared by four photodiodes PD.

[0275] As a result, in the seventh modification of the second embodiment, the area of ​​the floating diffusion FD can be further increased, and the layout efficiency of the pixel array section 10 can be further improved.

[0276] <Variations 8-16> The planar configuration of the second isolation region 25 in the present disclosure is not limited to the examples of the second embodiment and modified examples 5 to 7 described so far. Figures 35 to 43 are plan views showing examples of the configuration of the light-sensitive pixel 11 according to modified examples 8 to 16 of the second embodiment of the present disclosure. Note that, to facilitate understanding, elements of the light-sensitive pixel 11 other than the first isolation region 24 and the second isolation region 25 are not shown in Figures 35 to 16.

[0277] For example, as shown in FIG. 35, the end of the second separation region 25, which is approximately X-shaped in a planar view, may contact the first separation region 24 at corners C2 and C4, but may not contact the first separation region 24 at corners C1 and C3.

[0278] Furthermore, as shown in FIG. 36, the end of the second separation region 25, which is approximately X-shaped in a planar view, may contact the first separation region 24 at all corners C1 to C4, and may have a notch 25a near the intersection in the portion extending from corners C1 and C3 toward the intersection.

[0279] Furthermore, as shown in FIG. 37, the end of the second separation region 25, which is approximately X-shaped in a planar view, may contact the first separation region 24 at all corners C1 to C4, and may have a notch 25a in the middle of the portion extending from corners C1 and C3 toward the intersection.

[0280] 38, the end of second separation region 25, which is generally X-shaped in plan view, contacts first separation region 24 at corners C2 and C4. On the other hand, in the example of Fig. 38, the end of second separation region 25 does not contact first separation region 24 at corners C1 and C3, and may have notches 25a near the intersections in the portions extending from corners C1 and C3 toward the intersections.

[0281] Furthermore, as shown in FIG. 39, the end of the second separation region 25, which is roughly X-shaped in a planar view, may contact the first separation region 24 at all corners C1 to C4, and may have a notch 25a near the intersection in the portion extending from corners C2 and C4 toward the intersection.

[0282] Also, as shown in Figure 40, the end of the second separation region 25, which is approximately X-shaped in a planar view, may be in contact with the first separation region 24 at all corners C1 to C4, and may have a notch 25a in the middle of the portion extending from corners C2 and C4 toward the intersection.

[0283] 41, the end of second separation region 25, which is generally X-shaped in plan view, contacts first separation region 24 at corners C1 and C3. On the other hand, in the example of Fig. 41, the end of second separation region 25 does not contact first separation region 24 at corners C2 and C4, and may have notches 25a near the intersections in the portions extending from corners C2 and C4 toward the intersections.

[0284] Furthermore, as shown in FIG. 42, the end of the second separation region 25, which is roughly X-shaped in a plan view, may contact the first separation region 24 at all corners C1 to C4, and may have a notch 25a at the intersection of the second separation region 25.

[0285] Furthermore, as shown in FIG. 43, the end of the second separation region 25, which is roughly X-shaped in a plan view, may contact the first separation region 24 at all corners C1 to C4, and may have a notch 25a in the middle of the portion extending from the corners C1 to C4 toward the intersection.

[0286] 35 to 43, the volume of the photodiode PD can be increased by arranging the second isolation region 25 along two diagonals of the first isolation region 24 that is rectangular in plan view. Therefore, according to the examples of Figures 35 to 43, the amount of saturated signal charge of the photodiode PD can be increased in the phase difference detection pixel.

[0287] Furthermore, in the examples of FIGS. 35 to 43, the second isolation region 25 has the cutout portion 25a, which makes it possible to improve the layout efficiency of the pixel array section 10.

[0288] [effect] The solid-state imaging device 1 according to the first embodiment includes a plurality of light-receiving pixels 11 arranged in a matrix within a semiconductor layer 20. Each light-receiving pixel 11 includes a pair of photoelectric conversion units (photodiodes PD), a first isolation region 24, and a second isolation region 25. The pair of photoelectric conversion units (photodiodes PD) are adjacent to each other and share a floating diffusion FD. The first isolation region 24 is disposed to surround the pair of photoelectric conversion units (photodiodes PD). The second isolation region 25 is disposed between the pair of photoelectric conversion units (photodiodes PD). The first isolation region 24 has a rectangular shape in a plan view and is provided to extend from a surface 20b of the semiconductor layer 20 opposite to the light incident surface 20a toward the light incident surface 20a. The second isolation region 25 is disposed along a diagonal of the first isolation region 24, which has a rectangular shape in a plan view, and is provided to extend from the surface 20b of the semiconductor layer 20 opposite to the light incident surface 20a toward the light incident surface 20a.

[0289] This makes it possible to increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0290] In the solid-state imaging device 1 according to the first embodiment, the first isolation region 24 and the second isolation region 25 do not contact each other in a plan view.

[0291] This makes it possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel, and also to improve the layout efficiency of the pixel array section 10.

[0292] The solid-state imaging device 1 according to the first embodiment further includes a pixel transistor provided on a surface 20b opposite to the light incident surface 20a of the semiconductor layer 20. The pixel transistor is disposed at one corner C3 of the four corners C1 to C4 of the first isolation region 24 that is rectangular in plan view and that is close to an end of the second isolation region 25. The floating diffusion FD is disposed at the other corner C1 of the four corners C1 to C4 of the first isolation region 24 that is rectangular in plan view and that is close to the end of the second isolation region 25.

[0293] This makes it possible to improve the layout efficiency of the pixel array section 10.

[0294] The solid-state imaging device 1 according to the first embodiment further includes a pixel transistor provided on a surface 20b opposite to the light incident surface 20a of the semiconductor layer 20. The pixel transistor is disposed at two corners C1 and C3 of the four corners C1 to C4 of the first isolation region 24 that are rectangular in plan view and that are close to the ends of the second isolation region 25, and the floating diffusion FD is disposed at two corners C2 and C4 of the four corners C1 to C4 of the first isolation region 24 that are not close to the ends of the second isolation region 25.

[0295] This makes it possible to improve the layout efficiency of the pixel array section 10.

[0296] In the solid-state imaging device 1 according to the first embodiment, the active region AA of the pixel transistor has a substantially L-shape in plan view.

[0297] This allows the layout efficiency of the pixel array section 10 to be further improved.

[0298] In the solid-state imaging device 1 according to the first embodiment, among the pixel transistors, a combination of an amplifier transistor AMP and a selection transistor SEL, or a combination of a reset transistor RST and a switching transistor FDG is arranged in one active region AA.

[0299] This allows the layout efficiency of the pixel array section 10 to be further improved.

[0300] In the solid-state imaging device 1 according to the first embodiment, the pixel transistors partially overlap the second isolation regions 25 in plan view.

[0301] This allows the layout efficiency of the pixel array section 10 to be further improved.

[0302] In the solid-state imaging device 1 according to the first embodiment, the light-receiving pixel 11 further includes a contact region 26 that is provided on the surface 20b of the semiconductor layer 20 opposite to the light incident surface 20a and is electrically connected to a reference potential line. The contact region 26 also partially overlaps the second isolation region 25 in plan view.

[0303] This makes it possible to improve the layout efficiency of the pixel array section 10.

[0304] The solid-state imaging device 1 according to the first embodiment also includes a photosensitive pixel group 100 having a plurality of photosensitive pixels 11. The plurality of photosensitive pixels 11 included in the same photosensitive pixel group 100 have second isolation regions 25 facing in different directions in a planar view.

[0305] This allows the light-receiving pixels 11 to function more effectively as phase difference detection pixels.

[0306] The solid-state imaging device 1 according to the first embodiment further includes a transfer transistor TRG that transfers charges accumulated in the photoelectric conversion unit (photodiode PD) to the floating diffusion FD. The gates (transfer gates TG1 and TG2) of the transfer transistor TRG partially overlap the second isolation region 25 in plan view.

[0307] This makes it possible to improve the layout efficiency of the pixel array section 10.

[0308] The solid-state imaging device 1 according to the second embodiment includes a plurality of light-receiving pixels 11 arranged in a matrix within the semiconductor layer 20. Each light-receiving pixel 11 includes four photoelectric conversion units (photodiodes PD), a first isolation region 24, and a second isolation region 25. The four photoelectric conversion units (photodiodes PD) are arranged adjacent to one another and have a shared floating diffusion FD. The first isolation region 24 is arranged to surround the four photoelectric conversion units (photodiodes PD) and is rectangular in plan view. The second isolation region 25 is arranged to separate the four photoelectric conversion units (photodiodes PD) and is arranged along two diagonals of the rectangular first isolation region 24 in plan view.

[0309] This makes it possible to increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel.

[0310] In the solid-state imaging device 1 according to the second embodiment, the second isolation region 25 has an end portion that is not in contact with the first isolation region 24 in a plan view.

[0311] This makes it possible to further increase the amount of saturated signal charge of the photodiode PD in the phase difference detection pixel, and also to improve the layout efficiency of the pixel array section 10.

[0312] The solid-state imaging device 1 according to the second embodiment further includes a pixel transistor provided on a surface 20b opposite to the light incident surface 20a of the semiconductor layer 20. The active region AA of the pixel transistor is disposed at one of four corners C1 to C4 of the first isolation region 24 that is rectangular in plan view and that is not in contact with the second isolation region 25.

[0313] This allows the layout efficiency of the pixel array section 10 to be further improved.

[0314] In the solid-state imaging device 1 according to the second embodiment, the second isolation region 25 has a notch 25a at the intersection.

[0315] This allows the layout efficiency of the pixel array section 10 to be further improved.

[0316] In addition, in the solid-state imaging device 1 according to the second embodiment, the floating diffusion FD is disposed so as to overlap the notch 25a in plan view.

[0317] This allows the layout efficiency of the pixel array section 10 to be further improved.

[0318] [Electronic equipment] Note that the present disclosure is not limited to application to solid-state imaging elements, and can be applied to all electronic devices that have solid-state imaging elements, such as camera modules, imaging devices, portable terminal devices with imaging functions, and copiers that use solid-state imaging elements in their image reading units.

[0319] Examples of such imaging devices include digital still cameras and video cameras, while examples of mobile terminal devices with imaging capabilities include smartphones and tablet terminals.

[0320] Fig. 44 is a block diagram showing a configuration example of an imaging device serving as electronic device 1000 to which the technology according to the present disclosure is applied. Electronic device 1000 in Fig. 44 is, for example, an imaging device such as a digital still camera or a video camera, or an electronic device such as a mobile terminal device such as a smartphone or a tablet terminal.

[0321] In FIG. 44, electronic device 1000 comprises a lens group 1001, a solid-state image sensor 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008.

[0322] In the electronic device 1000 , the DSP circuit 1003 , frame memory 1004 , display unit 1005 , recording unit 1006 , operation unit 1007 , and power supply unit 1008 are interconnected via a bus line 1009 .

[0323] The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging element 1002. The solid-state imaging element 1002 corresponds to the solid-state imaging element 1 according to the above-described embodiment, and converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0324] The DSP circuit 1003 is a camera signal processing circuit that processes signals supplied from the solid-state image sensor 1002. The frame memory 1004 temporarily stores image data processed by the DSP circuit 1003 on a frame-by-frame basis.

[0325] The display unit 1005 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the solid-state imaging element 1002. The recording unit 1006 records image data of the moving or still images captured by the solid-state imaging element 1002 on a recording medium such as a semiconductor memory or a hard disk.

[0326] In response to user operations, the operation unit 1007 issues operation commands for the various functions of the electronic device 1000. The power supply unit 1008 appropriately supplies various types of power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007 as operating power sources.

[0327] In the electronic device 1000 configured as above, by applying the solid-state imaging device 1 of each of the above-described embodiments as the solid-state imaging device 1002, it is possible to improve the signal quality.

[0328] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0329] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0330] The present technology can also be configured as follows. (1) a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is a pair of photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region arranged to surround the pair of photoelectric conversion units; a second isolation region disposed between the pair of photoelectric conversion units; and the first isolation region has a rectangular shape in a plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, The second isolation region is disposed along a diagonal line of the first isolation region, which is rectangular in plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface. Solid-state imaging element. (2) The first isolation region and the second isolation region are not in contact with each other in a plan view. The solid-state imaging device according to (1) above. (3) a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, the pixel transistor is disposed at one of four corners of the first isolation region that is rectangular in plan view and that is close to an end of the second isolation region; The floating diffusion is disposed at the other of the four corners of the first isolation region, which is rectangular in plan view, and which is adjacent to an end of the second isolation region. The solid-state imaging device according to (2) above. (4) a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, the pixel transistors are arranged at two corners of the first isolation region that are rectangular in plan view and are close to ends of the second isolation region, The floating diffusion is disposed at two corners of the first isolation region, which is rectangular in plan view, that are not adjacent to the ends of the second isolation region. The solid-state imaging device according to (2) above. (5) The active region of the pixel transistor has a substantially L-shape in plan view. The solid-state imaging device according to (3) or (4) above. (6) For one of the active regions, a combination of an amplification transistor and a selection transistor or a combination of a reset transistor and a switching transistor is arranged among the pixel transistors. The solid-state imaging device according to (5) above. (7) The pixel transistor partially overlaps the second isolation region in a plan view. The solid-state imaging device according to any one of (3) to (6) above. (8) the light-receiving pixel further includes a contact region provided on a surface of the semiconductor layer opposite to the light incident surface and electrically connected to a reference potential line; The contact region partially overlaps the second isolation region in a plan view. The solid-state imaging device according to any one of (1) to (7) above. (9) a light receiving pixel group having a plurality of the light receiving pixels, The plurality of light-receiving pixels included in the same light-receiving pixel group have the second isolation regions facing in different directions in a plan view. The solid-state imaging device according to any one of (1) to (8) above. (10) a transfer transistor that transfers the charge stored in the photoelectric conversion unit to the floating diffusion; The gate of the transfer transistor partially overlaps the second isolation region in plan view. The solid-state imaging device according to any one of (1) to (9) above. (11) a solid-state imaging element; an optical system that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging device; a signal processing circuit that processes an output signal from the solid-state imaging device, The solid-state imaging device is a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is a pair of photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region arranged to surround the pair of photoelectric conversion units; a second isolation region disposed between the pair of photoelectric conversion units; and the first isolation region has a rectangular shape in a plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, The second isolation region is disposed along a diagonal line of the first isolation region, which is rectangular in plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface. electronic equipment. (12) The first isolation region and the second isolation region are not in contact with each other in a plan view. The electronic device according to (11) above. (13) The solid-state imaging device is a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, the pixel transistor is disposed at one of four corners of the first isolation region that is rectangular in plan view and that is close to an end of the second isolation region; The floating diffusion is disposed at the other of the four corners of the first isolation region, which is rectangular in plan view, and which is adjacent to an end of the second isolation region. The electronic device according to (12) above. (14) The solid-state imaging device is a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, the pixel transistors are arranged at two corners of the first isolation region that are rectangular in plan view and are close to ends of the second isolation region, The floating diffusion is disposed at two corners of the first isolation region, which is rectangular in plan view, that are not adjacent to the ends of the second isolation region. The electronic device according to (12) above. (15) The active region of the pixel transistor has a substantially L-shape in plan view. The electronic device according to (13) or (14). (16) For one of the active regions, a combination of an amplification transistor and a selection transistor or a combination of a reset transistor and a switching transistor is arranged among the pixel transistors. The electronic device according to (15) above. (17) The pixel transistor partially overlaps the second isolation region in a plan view. The electronic device according to any one of (13) to (16) above. (18) the light-receiving pixel further includes a contact region provided on a surface of the semiconductor layer opposite to the light incident surface and electrically connected to a reference potential line; The contact region partially overlaps the second isolation region in a plan view. The electronic device according to any one of (11) to (17). (19) The solid-state imaging device is a light receiving pixel group including a plurality of the light receiving pixels; The plurality of light-receiving pixels included in the same light-receiving pixel group have the second isolation regions facing in different directions in a plan view. The electronic device according to any one of (11) to (18). (20) The solid-state imaging device is a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the floating diffusion; The gate of the transfer transistor partially overlaps the second isolation region in plan view. The electronic device according to any one of (11) to (19). (twenty one) a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is four photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region that is arranged so as to surround the four photoelectric conversion units and has a rectangular shape in a plan view; second isolation regions that are arranged to separate the four photoelectric conversion units and that are arranged along two diagonals of the first isolation region that is rectangular in plan view; have Solid-state imaging element. (twenty two) The second isolation region has an end portion that is not in contact with the first isolation region in a plan view. The solid-state imaging device according to (21) above. (twenty three) a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, The active region of the pixel transistor is disposed at one of four corners of the first isolation region that is rectangular in plan view and that is not in contact with the second isolation region. The solid-state imaging device according to (22) above. (twenty four) The second isolation region has a notch at the intersection. The solid-state imaging device according to any one of (21) to (23) above. (twenty five) The floating diffusion is disposed so as to overlap the notch in a plan view. The solid-state imaging device according to (24) above. (26) a solid-state imaging element; an optical system that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging device; a signal processing circuit that processes an output signal from the solid-state imaging device, The solid-state imaging device is a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is four photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region that is arranged so as to surround the four photoelectric conversion units and has a rectangular shape in a plan view; second isolation regions that are arranged to separate the four photoelectric conversion units and that are arranged along two diagonals of the first isolation region that is rectangular in plan view; have electronic equipment. (27) The second isolation region has an end portion that is not in contact with the first isolation region in a plan view. The electronic device according to (26) above. (28) The solid-state imaging device is a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, The active region of the pixel transistor is disposed at one of four corners of the first isolation region that is rectangular in plan view and that is not in contact with the second isolation region. The electronic device according to (27) above. (29) The second isolation region has a notch at the intersection. The electronic device according to any one of (26) to (28). (30) The floating diffusion is disposed so as to overlap the notch in a plan view. The electronic device according to (29) above. [Explanation of symbols]

[0331] 1. Solid-state imaging element 10 Pixel array section 11 photosensitive pixels 20 Semiconductor layer 20a Light incidence surface 20b side 24 1st separation area 25 Second separation area 25a Notch 100 photosensitive pixel group 1000 electronic equipment C1~C4 corner AMP Amplification transistor (an example of a pixel transistor) FD, FD1~FD4 Floating Diffusion FDG switching transistor (an example of a pixel transistor) PD, PD1 to PD4: Photodiodes (examples of photoelectric conversion units) RST Reset transistor (an example of a pixel transistor) SEL Select transistor (an example of a pixel transistor) TG1, TG2: Transfer gates (example of gates)

Claims

1. a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is a pair of photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region disposed so as to surround the pair of photoelectric conversion units; a second isolation region disposed between the pair of photoelectric conversion units; and the first isolation region has a rectangular shape in a plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, the second isolation region is disposed along a diagonal line of the first isolation region, which is rectangular in plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, The first isolation region and the second isolation region are not in contact with each other in a plan view. Solid-state imaging element.

2. a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, the pixel transistor is disposed at one of four corners of the first isolation region that is rectangular in plan view and that is close to an end of the second isolation region; The floating diffusion is disposed at the other of the four corners of the first isolation region, which is rectangular in plan view, and which is adjacent to an end of the second isolation region. The solid-state imaging device according to claim 1 .

3. a pixel transistor provided on a surface of the semiconductor layer opposite to the light incident surface, the pixel transistors are arranged at two corners of the first isolation region that are rectangular in plan view and that are close to ends of the second isolation region, The floating diffusion is disposed at two corners of the first isolation region, which is rectangular in plan view, that are not adjacent to the ends of the second isolation region. The solid-state imaging device according to claim 1 .

4. The active region of the pixel transistor has a substantially L-shape in plan view.

4. The solid-state imaging device according to claim 2.

5. For one of the active regions, a combination of an amplification transistor and a selection transistor or a combination of a reset transistor and a switching transistor is arranged among the pixel transistors.

5. The solid-state imaging device according to claim 4.

6. The pixel transistor partially overlaps the second isolation region in a plan view.

6. The solid-state imaging device according to claim 2.

7. A semiconductor device comprising a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer, The light receiving pixel is a pair of photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region disposed so as to surround the pair of photoelectric conversion units; a second isolation region disposed between the pair of photoelectric conversion units; and the first isolation region has a rectangular shape in a plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, the second isolation region is disposed along a diagonal line of the first isolation region, which is rectangular in plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, the light-receiving pixel further includes a contact region provided on a surface of the semiconductor layer opposite to the light incident surface and electrically connected to a reference potential line; The contact region partially overlaps the second isolation region in a plan view. Solid-state imaging element.

8. a light receiving pixel group having a plurality of the light receiving pixels, The plurality of light-receiving pixels included in the same light-receiving pixel group have the second isolation regions oriented in different directions in a plan view.

8. The solid-state imaging device according to claim 1.

9. a transfer transistor that transfers the charge stored in the photoelectric conversion unit to the floating diffusion; The gate of the transfer transistor partially overlaps the second isolation region in plan view.

9. The solid-state imaging device according to claim 1.

10. a solid-state imaging element; an optical system that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging device; a signal processing circuit that processes an output signal from the solid-state imaging device, The solid-state imaging device is a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is a pair of photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region disposed so as to surround the pair of photoelectric conversion units; a second isolation region disposed between the pair of photoelectric conversion units; and the first isolation region has a rectangular shape in a plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, the second isolation region is disposed along a diagonal line of the first isolation region, which is rectangular in plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, The first isolation region and the second isolation region are not in contact with each other in a plan view. electronic equipment.

11. A solid-state imaging element; an optical system that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging device; a signal processing circuit that processes an output signal from the solid-state imaging device, The solid-state imaging device is a plurality of light-receiving pixels arranged in a matrix within a semiconductor layer; The light receiving pixel is a pair of photoelectric conversion units arranged adjacent to each other and having a shared floating diffusion; a first isolation region disposed so as to surround the pair of photoelectric conversion units; a second isolation region disposed between the pair of photoelectric conversion units; and the first isolation region has a rectangular shape in a plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, the second isolation region is disposed along a diagonal line of the first isolation region, which is rectangular in plan view, and is provided so as to extend from a surface of the semiconductor layer opposite to the light incident surface toward the light incident surface, the light-receiving pixel further includes a contact region provided on a surface of the semiconductor layer opposite to the light incident surface and electrically connected to a reference potential line; The contact region partially overlaps the second isolation region in a plan view. electronic equipment.

Images