Semiconductor Devices

Abstract

To provide a semiconductor device with a new structure.SOLUTION: A semiconductor device comprises: a plurality of gate trenches which is dug from a front surface of a SiC semiconductor layer and has a side surface part and a bottom surface part; a gate electrode which is embedded in a gate trench; a source layer and a channel layer which are sequentially formed from the front surface of the SiC semiconductor layer in such a way as to be in contact with the side surface of the gate trench in an active region; an interlayer insulating film which is formed in such a way as to cover a portion of the front surface of the source layer and the gate electrode; a gate pad which is electrically connected to the gate electrode; a gate finger which is formed in a non-active region and is electrically connected to the gate electrode; and a pillar layer which is connected to the channel layer between the plurality of gate trenches in the active region and is formed to be deeper than the gate trenches.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a trench gate structure. [Background technology]

[0002] For example, Patent Document 1 discloses a trench-gate vertical MOSFET including an epitaxial layer in which an active cell array and a gate bus area are formed, a gate trench formed in the active cell array, a gate oxide film formed in the gate trench, a gate electrode made of polysilicon embedded in the gate trench, a trench formed in the gate bus area and connected to the gate trench, and a gate bus made of polysilicon embedded in the trench so as to cover the surface of the epitaxial layer in the gate bus area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2006-520091 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device with a novel configuration. [Means for solving the problem]

[0005] an interlayer insulating film formed to cover a portion of a surface of the SiC semiconductor layer and the gate electrode; a gate finger formed in the inactive region and electrically connected to the gate electrode; and a pillar layer formed in the active region between the plurality of gate trenches and deeper than the gate trenches, the SiC semiconductor layer having a rectangular shape in a plan view, and the gate pad being formed on a first side of the SiC semiconductor layer. Along The gate finger has a first portion connected to the gate pad and extending along the first side of the SiC semiconductor layer, and a second portion perpendicular to the first side of the first portion. Around a second portion extending from the end along the second side the gate electrode further has an overlap portion formed in the non-active region so as to cover a surface of the SiC semiconductor layer from an opening end of the gate trench, and the gate insulating film includes a planar insulating film formed on the surface of the SiC semiconductor layer in the non-active region, and the planar insulating film is interposed between at least the overlap portion and the surface of the SiC semiconductor layer. A semiconductor device is provided.

[0006] In one embodiment of the present invention, a portion of the gate trench extends from the active area below the gate finger.

[0008] In one embodiment of the present invention is the planar insulating film The thickness of the gate insulating film on the side surface of the gate trench is greater than the thickness of the gate insulating film on the side surface of the gate trench.

[0010] In one embodiment of the present invention, the gate electrode is made of polysilicon.

[0011] In one embodiment of the present invention, the gate fingers are made of aluminum.

[0015] In one embodiment of the present invention, in plan view, there is a portion in the outer periphery of the SiC semiconductor layer where the gate fingers are not formed.

[0016] In one embodiment of the present invention, the semiconductor device further includes a source pad electrically connected to the source layer and formed in a region that does not overlap the gate finger.

[0017] In one embodiment of the present invention, the semiconductor device further includes a drain layer that is in contact with the channel layer and that is formed to reach the back surface of the SiC semiconductor layer, and a drain electrode that is electrically connected to the drain layer on the back surface side of the SiC semiconductor layer.

[0018] In one embodiment of the present invention, the source layer and the drain layer are n-type, and the channel layer and the pillar layer are p-type.

[0019] In one embodiment of the present invention, a circular surface is formed on the upper edge of the gate trench.

[0020] In one embodiment of the present invention, the gate trench is recessed from the surface of the SiC semiconductor layer in the non-active region. Re The contact trench includes a contact hole.

[0021] In one embodiment of the present invention, in plan view And the above The contact trenches are formed in a stripe pattern.

[0022] In one embodiment of the present invention, the gate trench including the contact trench is formed so that, in a cross-sectional view, the side surface portion is continuous with the bottom surface portion via a circular surface.

[0023] In one embodiment of the present invention, the thickness of the gate insulating film on the bottom portion of the gate trench including the contact trench is greater than the thickness of the gate insulating film on the side portion of the gate trench including the contact trench.

[0025] In one embodiment of the present invention, the gate insulating film integrally includes a side insulating film on the side surface of the contact trench and a bottom insulating film on the bottom surface of the contact trench, and the side insulating film includes an overhang portion at an upper edge formed at an opening end of the contact trench that is selectively thicker than other portions of the side insulating film so as to protrude only toward the inside of the contact trench. [Brief explanation of the drawings]

[0029] [Figure 1] 1(a) and 1(b) are schematic plan views of a semiconductor device according to one embodiment of the present invention, with FIG. 1(a) showing an overall view and FIG. 1(b) showing an internal enlarged view. [Figure 2] 2(a), 2(b), and 2(c) are cross-sectional views of the semiconductor device, with FIG. 2(a) showing a cross section taken along line IIa-IIa in FIG. 1(b), FIG. 2(b) showing a cross section taken along line IIb-IIb in FIG. 1(b), and FIG. 2(c) showing a cross section taken along line IIc-IIc in FIG. 1(b). [Figure 3] FIG. 3 is a cross-sectional view showing a first embodiment of a gate finger portion of the semiconductor device. [Figure 4] FIG. 4 is a cross-sectional view showing a second embodiment of the gate finger portion of the semiconductor device. [Figure 5] FIG. 5 is a cross-sectional view showing a third embodiment of the gate finger portion of the semiconductor device. [Figure 6] FIG. 6 is a cross-sectional view showing a fourth embodiment of the gate finger portion of the semiconductor device. [Figure 7] FIG. 7 is a cross-sectional view showing a fifth embodiment of the gate finger portion of the semiconductor device. [Figure 8] FIG. 8 is a cross-sectional view showing a sixth embodiment of the gate finger portion of the semiconductor device. [Figure 9] FIG. 9 is a cross-sectional view showing a seventh embodiment of the gate finger portion of the semiconductor device. [Figure 10]FIG. 10 is a flow chart for explaining the method for manufacturing the semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a step of forming an inclined surface on the upper edge. [Figure 12] FIG. 12 is a diagram illustrating a process of forming a circular surface on the upper edge. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0031] 1(a) and 1(b) are schematic plan views of a semiconductor device according to one embodiment of the present invention, with FIG. 1(a) showing an overall view and FIG. 1(b) showing an internal enlarged view.

[0032] The semiconductor device 1 includes a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element (discrete element) using SiC (silicon carbide), and has a length of about 1 mm in the vertical direction on the paper surface of FIG.

[0033] As shown in FIG. 1( a), the semiconductor device 1 is disposed in the center of a SiC substrate 2, which is an example of a semiconductor layer. The semiconductor device 1 includes an active region 3 that functions as a field-effect transistor and a peripheral region 4 that surrounds the active region 3. A source pad 5, made of, for example, aluminum, is formed to cover almost the entire active region 3. In this embodiment, the source pad 5 has a square shape in a plan view. A removal region 6 is formed on the periphery of the source pad 5, along the peripheral region 4, and surrounds the central region of the source pad 5. A portion of the removal region 6 is selectively recessed toward the central region of the source pad 5. A gate pad 7 is disposed in this recess. A gate finger 8, made of, for example, aluminum, extends from the gate pad 7 along the peripheral region 4 and across the entire removal region 6. In this embodiment, a pair of gate fingers 8 are formed symmetrically with respect to the gate pad 7.

[0034] As shown in FIG. 1( b), a gate trench 9 is formed in the SiC substrate 2 directly below the source pad 5 and the like. The gate trench 9 is formed across the active region 3 and the peripheral region 4. The gate trench 9 includes active trenches 91 formed in a lattice shape in the active region 3 and used as gates of the MOSFET, and contact trenches 92 formed in stripes extending from each end of the active trench 91 to the peripheral region 4 and serving as contacts to gate electrodes 15 (described later) in the active trench 91. The contact trenches 92 are formed as extensions of the active trench 91. Note that the patterns of the active trenches 91 and the contact trenches 92 are not limited to these shapes. For example, the active trenches 91 may be striped or honeycomb-shaped. The contact trenches 92 may be lattice-shaped or honeycomb-shaped.

[0035] The active region 3 is further divided into a number of unit cells 10 by active trenches 91. In the active region 3, a number of unit cells 10 are regularly arranged in a matrix (rows and columns). + A p-type channel contact layer 11 is formed. + The n-type channel contact layer 11 is surrounded by + The n-type source layer 12 is formed. + The type source layer 12 forms the side surface of each unit cell 10 (the side surface of the active trench 91).

[0036] In the outer periphery region 4, the gate fingers 8 are laid along a direction crossing the stripe-shaped contact trenches 92. In this embodiment, the gate fingers 8 are laid in a region more inward than the longitudinal terminal ends of the contact trenches 92 (ends on the opposite side from the active trenches 91), and the terminal ends of the contact trenches 92 protrude outward beyond the gate fingers 8. In a region further outward than this terminal end, a low step portion 13 is formed in the SiC substrate 2 that is dug down all around the outer periphery region 4.

[0037] Next, the basic cross-sectional structure of the active region 3 and the peripheral region 4 of the semiconductor device 1 will be described.

[0038] 2(a), 2(b), and 2(c) are cross-sectional views of the semiconductor device, with FIG. 2(a) showing a cross section taken along line IIa-IIa in FIG. 1(b), FIG. 2(b) showing a cross section taken along line IIb-IIb in FIG. 1(b), and FIG. 2(c) showing a cross section taken along line IIc-IIc in FIG. 1(b).

[0039] As described above, the semiconductor device 1 includes the SiC substrate 2. In this embodiment, the SiC substrate 2 is of n-type, which is the first conductivity type, and functions as the drain region (drift layer) of the field effect transistor.

[0040] A p-type channel layer 14 is formed on the surface 21 side of the SiC substrate 2. In the p-type channel layer 14, n+ The n-type source layer 12 and + A p-type impurity region as an example of a second conductivity type is surrounded by the p-type source layer 12. + A type channel contact layer 11 is formed. + type source layer 12 and p + The channel contact layer 11 is exposed on the surface 21 of the SiC substrate 2 .

[0041] The surface 21 of the SiC substrate 2 is provided with n + A gate trench 9 is formed which penetrates the p-type source layer 12 and the p-type channel layer 14 and reaches the SiC substrate 2 serving as a drain region. The gate trench 9 divides the p-type channel layer 14 into a large number of unit cells 10 arranged, for example, in a lattice pattern.

[0042] A gate electrode 15 made of, for example, polysilicon is buried in the gate trench 9, and a gate insulating film 16 is interposed between the gate electrode 15 and the SiC substrate 2.

[0043] As shown by diagonal hatching in FIG. 1( b ), the gate electrode 15 is embedded in the gate trench 9 (active trench 91) in the active region 3 down to the surface 21 of the SiC substrate 2. This allows the gate electrode 15 to be formed in a lattice pattern, with the upper surface of each unit cell 10 exposed and not covered by the gate electrode 15. Meanwhile, the peripheral region 4 has an overlapping portion 17 formed from the opening end of the gate trench 9 (contact trench 92) to cover the surface 21 of the SiC substrate 2. In this embodiment, the overlapping portion 17 is formed so as to cross the stripe-shaped contact trench 92 along the gate finger 8. The gate insulating film 16 integrally includes a side insulating film 18 on the side surface of the gate trench 9, a bottom insulating film 19 on the bottom surface, and a planar insulating film 20 on the surface 21 of the SiC substrate 2. In this embodiment, the planar insulating film 20 is interposed at least between the overlapping portion 17 and the surface 21 of the SiC substrate 2.

[0044] In the active region 3, the gate electrode 15 is + The gate insulating film 10 extends between the p-type source layer 12 and the SiC substrate 2 as a drain region, and controls the formation of an inversion layer (channel) on the surface of the p-type channel layer 14 (on the side surface of the active trench 91). That is, the semiconductor device 1 has a MOSFET with a so-called trench gate structure.

[0045] In the active region 3, a p-type pillar layer 22 is formed in the SiC substrate 2 serving as a drain region. The p-type pillar layer 22 is formed in a region inside the p-type channel layer 14 of each unit cell 10. More specifically, in this embodiment, the p-type pillar layer 22 is formed in an approximately central region of the p-type channel layer 14, for example, in a shape similar to the p-type channel layer 14 (a square in a plan view in the layout of FIG. 1(b)). The p-type pillar layer 22 is formed so as to be continuous with the p-type channel layer 14, and extends toward the back surface of the SiC substrate 2 serving as a drain region to a position deeper than the p-type channel layer 14. That is, the p-type pillar layer 22 is formed in an approximately columnar shape (an approximately quadrangular pillar shape in the layout of FIG. 1(b)). As a result, the SiC substrate 2 has p-type pillar layers 22 arranged at an appropriate pitch and SiC substrates 2 serving as n-type drain regions sandwiched between adjacent p-type pillar layers 22 arranged alternately in a direction along the surface 21.

[0046] An interlayer film 23 made of, for example, silicon oxide is formed on the surface 21 of the SiC substrate 2. In the interlayer film 23, a contact hole 24 is selectively formed in the central region of the p-type channel layer 14 in the active region 3. The contact hole 24 is + The n-type channel contact layer 11 and its surroundings +1(b), a contact hole 25 is selectively formed in the interlayer film 23 directly below the gate finger 8 in the peripheral region 4. In this embodiment, the contact hole 25 is formed in a linear shape surrounding the active region 3 along the peripheral region 4 at the center of the gate finger 8 in the width direction.

[0047] The source pad 5 and the gate finger 8 (gate pad 7) are formed on the interlayer film 23. The source pad 5 is inserted into all the contact holes 24 at once, and n + type source layer 12 and p + The n-type channel contact layer 11 is connected to the n-type channel contact layer 11. + The p-type source layer 12 has the same potential as the source pad 5. The p-type channel layer 14 has a p + Since the gate electrode 15 is connected to the source pad 5 via the gate electrode channel contact layer 11, it has the same potential as the source pad 5. The gate finger 8 enters the contact hole 25 and is connected to the overlap portion 17 of the gate electrode 15. Therefore, the gate electrode 15 embedded in the active trench 91 is connected to the gate finger 8 via the overlap portion 17, and has the same potential as the gate finger 8 (gate pad 7).

[0048] In the semiconductor device 1 configured as described above, when an on-voltage is applied to the gate finger 8, the on-voltage is also applied to the overlap portion 17 of the gate electrode 15. Therefore, the electric field generated from the overlap portion 17 tends to concentrate at the upper edge of the contact trench 92. As a result, there is a risk of dielectric breakdown of the gate insulating film 16 at the upper edge of the contact trench 92. Therefore, the inventors of the present application have discovered the structures shown in FIGS. 3 to 9 as structures capable of preventing such dielectric breakdown of the gate insulating film 16.

[0049] 3 to 9 are cross-sectional views showing first to seventh embodiments of the gate finger portion of the semiconductor device. In Fig. 4 to Fig. 9, parts corresponding to those shown in the figures described above are denoted by the same reference numerals.

[0050] 3 , in the first embodiment, the side insulating film 18 includes an overhang portion 27 that is selectively thicker than other portions of the side insulating film 18 at an upper edge 26 of the contact trench 92 so as to protrude inward of the contact trench 92. Here, the upper edge 26 refers to a corner that includes an intersection line formed when the side surface of the contact trench 92 and the surface 21 of the SiC substrate 2 intersect.

[0051] The overhang portion 27 can improve the breakdown voltage of the gate insulating film 16 at the upper edge 26. Therefore, even if an electric field concentrates at the upper edge 26 when the gate is turned on, it is possible to prevent dielectric breakdown of the gate insulating film 16 at the upper edge 26. As a result, reliability against gate-on voltage can be improved.

[0052] Regarding the relationship of the thicknesses of the various parts of the gate insulating film 16, it is preferable that the thickness t2 of the bottom insulating film 19 is equal to or greater than the thickness t1 of the planar insulating film 20 (t2≧t1), and that both thicknesses t1 and t2 are greater than the thickness t3 of the side insulating film 18 (excluding the overhang portion 27). In other words, the relationship t2≧t1>t3 is satisfied.

[0053] This configuration can reduce the capacitance of a capacitor formed by the gate electrode 15 and the SiC substrate 2 serving as an n-type drain region, which face each other via the bottom insulating film 19. As a result, the capacitance of the entire gate (gate capacitance) can be reduced. Furthermore, the withstand voltage of the bottom insulating film 19 can be improved, which can prevent dielectric breakdown of the bottom insulating film 19 when the gate is turned off. Furthermore, since the planar insulating film 20 is also thick, the capacitance of a capacitor formed by the gate electrode 15 (overlap portion 17) and the SiC substrate 2 serving as an n-type drain region, which face each other via the planar insulating film 20, can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced.

[0054] Furthermore, the lower edge at the bottom of the contact trench 92 is a circular surface 28 that connects the side surface and bottom surface of the contact trench 92. In other words, the lower edge of the contact trench 92 is not sharp, but is rounded by the circular surface 28.

[0055] With this configuration, the electric field applied to the lower edge when the gate is turned off can be dispersed within the circular surface 28, thereby reducing the concentration of the electric field at the lower edge.

[0056] 4, in addition to the configuration of FIG. 3, upper edge 26 of contact trench 92 has inclined surface 29 that connects surface 21 of SiC substrate 2 to the side surface of contact trench 92. In other words, upper edge 26 of contact trench 92 has a chamfered shape.

[0057] With this configuration, the electric field applied to the upper edge 26 when the gate is turned on can be dispersed within the inclined surface 29, thereby mitigating the electric field concentration at the upper edge 26.

[0058] 5, in addition to the configuration of FIG. 3, the upper edge 26 of the contact trench 92 is formed into a circular surface 30 that connects the surface 21 of the SiC substrate 2 with the side surface of the contact trench 92. In other words, the upper edge 26 of the contact trench 92 is not sharp, but is rounded by the circular surface 30.

[0059] This configuration allows the electric field applied to the upper edge 26 when the gate is turned on to be dispersed within the circular surface 30, thereby reducing the electric field concentration at the upper edge 26.

[0060] In the fourth embodiment shown in FIG. 6, in addition to the configuration of FIG. 4, a p-type layer 31 is formed as a second conductivity type layer on the surface 21 side of the SiC substrate 2 at the same depth as the p-type channel layer 14 of the active region 3 (see FIG. 2(a)).

[0061] This configuration allows the p-type layer 31 in the peripheral region 4 to be formed in the same process as the p-type channel layer 14 in the active region 3, thereby simplifying the manufacturing process of the semiconductor device 1. Furthermore, the contact area between the gate insulating film 16 and the SiC substrate 2 serving as the n-type drain region can be reduced, thereby reducing the leakage current and gate capacitance.

[0062] In the fifth embodiment shown in FIG. 7, in addition to the configuration of FIG. 6, the n-type MOSFET of the active region 3 is provided in the p-type layer 31. + The n-type source layer 12 (see FIG. 2(a)) is formed at the same depth as the n-type source layer 12. + A mold layer 32 is formed.

[0063] With this configuration, n + The mold layer 32 is + Since it can be formed in the same process as the type source layer 12, the manufacturing process of the semiconductor device 1 can be simplified.

[0064] 8, in addition to the configuration of FIG. 6, a bottom p-type layer 33 is formed as a bottom second conductivity type layer at the same depth as the p-type pillar layer 22 in the active region 3 so as to be continuous with the p-type layer 31. The bottom p-type layer 33 is formed on the bottom and side surfaces of the contact trench 92 so as to hide the SiC substrate 2 serving as a drain region exposed in the contact trench 92 below the p-type layer 31. The bottom p-type layer 33 is continuous with the p-type layer 31 on the side surfaces of the contact trench 92.

[0065] This configuration allows a depletion layer, which is generated by the junction (pn junction) between the bottom p-type layer 33 and the SiC substrate 2 serving as the n-type drain region, to be generated near the contact trench 92. The presence of this depletion layer allows the equipotential surface to be spaced away from the gate insulating film 16. As a result, the electric field applied to the gate insulating film 16 at the bottom of the contact trench 92 can be alleviated. Furthermore, the bottom p-type layer 33 in the peripheral region 4 can be formed in the same process as the p-type pillar layer 22 in the active region 3, thereby simplifying the manufacturing process of the semiconductor device 1. This bottom p-type layer 33 may be combined with the configuration of FIG. 7, as in a seventh embodiment shown in FIG. 9.

[0066] Although not shown here, the overhang portion 27, the circular surface 28, the inclined surface 29, and the circular surface 30 shown in FIGS.

[0067] FIG. 10 is a flow chart for explaining the method for manufacturing the semiconductor device.

[0068] To manufacture the semiconductor device 1, for example, impurities are selectively implanted into the surface 21 of the SiC substrate 2, and an annealing process is performed (step S1). + Type source layer 12, p +Impurity regions such as the type channel contact layer 11 are formed. Next, the SiC substrate 2 is etched from the surface 21 in a predetermined pattern to form gate trenches 9 (active trenches 91 and contact trenches 92) in the SiC substrate 2 (step S2).

[0069] The next step is to form the gate insulating film 16 (step S3). The gate insulating film 16 is formed by depositing an insulating material in the gate trench 9 using a CVD method under predetermined conditions (gas flow rate, gas type, gas ratio, gas supply time, etc.) so that an overhang portion 27 that is selectively thicker at the upper edge 26 of the contact trench 92 than other portions is formed. In this way, the gate insulating film 16 having the overhang portion 27 is formed.

[0070] Here, when forming the inclined surface 29 on the upper edge 26 as shown in FIGS. 4 and 6 to 9, the SiC substrate 2 is thermally oxidized after the gate trench 9 is formed and before the gate insulating film 16 is formed. Specifically, as shown in FIG. 11, the SiC substrate 2 is thermally oxidized to form a sacrificial oxide film 34. When forming the sacrificial oxide film 34, oxidation begins uniformly from both the surface 21 of the SiC substrate 2 and the side surface of the contact trench 92 near the contact trench 92. Therefore, at the upper edge 26, the oxide film growing from the surface 21 of the SiC substrate 2 and the oxide film growing from the side surface of the contact trench 92 are integrated earlier than in other regions. As a result, the inclined surface 29 is formed below the integrated oxide films. Thereafter, the sacrificial oxide film 34 is removed, and the gate insulating film 16 is formed by a CVD method.

[0071] When the method of FIG. 11 is adopted, the p-type layer 31 and the n-type layer 32 are formed on the surface 21 side of the SiC substrate 2 as shown in FIGS. + If the mold layer 32 is formed, the thermal oxidation rate in that portion is faster than that of the SiC substrate 2 serving as the drain region, and therefore the inclined surface 29 can be formed more easily.

[0072] 5, when the circular surface 30 is formed on the upper edge 26, the SiC substrate 2 is subjected to H annealing after the gate trench 9 is formed and before the gate insulating film 16 is formed. Specifically, as shown in FIG. 12, the SiC substrate 2 is subjected to H annealing (H etching) at 1400° C. or higher, thereby forming the circular surface 30 on the upper edge 26.

[0073] 10 , after the gate insulating film 16 is formed, the gate trench 9 is backfilled and polysilicon is deposited until the entire gate trench 9 is covered (step S4). Then, by patterning the deposited polysilicon, the polysilicon outside the active trench 91 in the active region 3 is removed, and at the same time, the polysilicon is left as an overlap portion 17 in the peripheral region 4.

[0074] Next, the interlayer film 23 is formed on the SiC substrate 2 by a CVD method (step S5). Next, the interlayer film 23 is patterned to simultaneously form the contact holes 24 and 25 (step S6).

[0075] Next, a metal material such as aluminum is deposited on the interlayer film 23 by sputtering or vapor deposition (step S7), thereby forming the source pad 5, the gate pad 7, and the gate fingers 8. Through the above steps, the semiconductor device 1 shown in FIG.

[0076] Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0077] For example, it is possible to adopt a configuration in which the conductivity types of the semiconductor portions of the aforementioned semiconductor device 1 are reversed. For example, in the semiconductor device 1, the p-type portions may be n-type, and the n-type portions may be p-type.

[0078] Furthermore, the semiconductor used in the semiconductor device 1 is not limited to SiC, but may be, for example, Si, GaN, diamond, or the like.

[0079] Furthermore, the overlap portion 17 may be formed not only in the peripheral region 4 but also in the active region 3. For example, the overlap portion 17 may also be formed in the active region 3 by covering only the periphery of the opening end of the active trench 91 to the extent that the top surface of each unit cell 10 is not hidden. In this case, if the overhang portion 27 is also formed in the active trench 91, the same effect of improving breakdown voltage as described above can be obtained. In other words, the structure directly below the gate finger 8 is merely one example showing the effect of improving breakdown voltage by the overhang portion 27 of the present invention, and any structure that can achieve the same effect is not limited to the gate finger portion.

[0080] In addition, various design modifications can be made within the scope of the claims. Further features can be extracted from this specification as follows: "A1" a SiC semiconductor layer having an active area in which a transistor is formed and an inactive area surrounding the active area; a plurality of gate trenches dug from the surface of the SiC semiconductor layer and having side and bottom portions; a gate insulating film formed so as to cover at least the side surface and the bottom surface of the gate trench; a gate electrode embedded in the gate trench; a source layer and a channel layer formed in this order from a surface of the SiC semiconductor layer in the active region so as to contact a side surface of the gate trench; an interlayer insulating film formed to cover a portion of the surface of the source layer and the gate electrode; a gate pad electrically connected to the gate electrode; a gate finger formed in the non-active region and electrically connected to the gate electrode; a pillar layer formed between the plurality of gate trenches in the active region, the pillar layer being connected to the channel layer and being deeper than the gate trenches; The SiC semiconductor layer has a quadrangular shape in a plan view, the gate pad is disposed near a center of a first side of the SiC semiconductor layer, the gate finger includes a first portion connected to the gate pad and extending along the first side of the SiC semiconductor layer, a second portion extending from an end of the first portion on a second side perpendicular to the first side along the second side, and a third portion extending from an end of the first portion on a third side perpendicular to the first side along the third side. [A2] The semiconductor device according to [A1], wherein a portion of the gate trench extends from the active region below the gate finger. [A3] The semiconductor device according to [A1], wherein the width of the gate trench on the opening side increases toward the opening. "A4" The gate insulating film is also formed on the surface of the SiC semiconductor layer, The semiconductor device according to "A1", wherein the thickness of the gate insulating film on the surface of the SiC semiconductor layer is greater than the thickness of the gate insulating film on the side portion of the gate trench. [A5] The semiconductor device according to [A4], wherein the thickness of the gate insulating film at the bottom portion of the gate trench is equal to or greater than the thickness of the gate insulating film on the surface of the SiC semiconductor layer. [A6] The semiconductor device according to any one of [A1] to [A5], wherein the gate electrode is made of polysilicon. [A7] The semiconductor device according to any one of [A1] to [A6], wherein the gate finger is made of aluminum. "A8" The gate finger is a fourth portion protruding from a position of the second portion away from the first side toward the third side; The semiconductor device according to any one of "A1" to "A7", further including a fifth portion that protrudes from a position of the third portion away from the first side toward the second side. "A9" The semiconductor device described in "A8", wherein, in a planar view, the portion consisting of the second portion and the fourth portion and the portion consisting of the third portion and the fifth portion are symmetrical with respect to an imaginary line connecting the center point of the first side of the SiC semiconductor layer and the center point of the fourth side opposite to the first side. "A10" In a plan view, the second portion and the fourth portion are arranged along the outer peripheries of the second side and the fourth side of the SiC semiconductor layer, respectively; The semiconductor device according to "A9", wherein the third portion and the fifth portion are respectively arranged along the outer peripheries of the third side and the fourth side of the SiC semiconductor layer. "A11" The semiconductor device according to "A10", wherein, in plan view, there is a portion in the outer periphery of the SiC semiconductor layer where the gate fingers are not formed. [A12] The semiconductor device according to any one of [A1] to [A11], further including a source pad electrically connected to the source layer and formed in a region not overlapping the gate finger. "A13" a drain layer formed in contact with the channel layer and reaching the back surface of the SiC semiconductor layer; The semiconductor device according to "A1", further including a drain electrode electrically connected to the drain layer on the back surface side of the SiC semiconductor layer. [A14] The semiconductor device according to [A13], wherein the source layer and the drain layer are n-type, and the channel layer and the pillar layer are p-type. [A15] The semiconductor device according to [A13], wherein the source layer and the drain layer are p-type, and the channel layer and the pillar layer are n-type. "A16" A semiconductor device described in any one of "A1" to "A15", wherein the gate trench includes a contact trench that is dug down from the surface of the SiC semiconductor layer in the non-active region and in which the surface of the SiC semiconductor layer and the side portion are connected via a circular surface. [A17] The semiconductor device according to [A16], wherein, in a plan view, the gate trenches are formed in a lattice pattern in the active region, and the contact trenches are formed in a stripe pattern. "A18" A semiconductor device according to "A16" or "A17", wherein the gate trench including the contact trench has, in a cross-sectional view, a side portion formed so as to be continuous with the bottom portion via a circular surface. "A19" A semiconductor device according to any one of "A16" to "A18", wherein the thickness of the gate insulating film on the bottom portion of the gate trench including the contact trench is greater than the thickness of the gate insulating film on the side portion of the gate trench including the contact trench. "A20" The gate insulating film is also formed on the surface of the SiC semiconductor layer in the inactive region, The semiconductor device according to "A19", wherein the thickness of the gate insulating film on the surface of the SiC semiconductor layer is greater than the thickness of the gate insulating film on the side portion of the contact trench. "A21" The gate insulating film integrally includes a side insulating film on a side surface of the contact trench and a bottom insulating film on a bottom surface of the contact trench, A semiconductor device described in any one of claims "A18" to "A20", wherein the side insulating film includes an overhang portion at an upper edge formed at the opening end of the contact trench, which is selectively thicker than other portions of the side insulating film so as to protrude only inward into the contact trench. "A22" A SiC semiconductor layer having an active area in which a MOSFET is formed and a non-active area surrounding the active area; a plurality of gate trenches dug from the surface of the SiC semiconductor layer and having side and bottom portions; a gate insulating film formed so as to cover at least the side surface and the bottom surface of the gate trench; a gate electrode embedded in the gate trench; a source layer and a channel layer formed in this order from a surface of the SiC semiconductor layer in the active region so as to contact a side surface of the gate trench; an interlayer insulating film formed to cover a portion of the surface of the source layer and the gate electrode; a gate pad electrically connected to the gate electrode; a gate finger formed in the non-active region and electrically connected to the gate electrode; a pillar layer formed between the plurality of gate trenches in the active region, the pillar layer being connected to the channel layer and being deeper than the gate trenches; a contact trench recessed from the surface of the SiC semiconductor layer in the inactive region; a p-type layer formed so as to cover the side surface and bottom surface of the contact trench from the outside of the contact trench; The SiC semiconductor layer has a quadrangular shape in a plan view, the gate pad is disposed near a center of a first side of the SiC semiconductor layer, the gate finger includes a first portion connected to the gate pad and extending along the first side of the SiC semiconductor layer, a second portion extending from an end of the first portion on a second side perpendicular to the first side along the second side, and a third portion extending from an end of the first portion on a third side perpendicular to the first side along the third side. "A23" The semiconductor device according to claim 22, wherein the width of the gate trench on the opening side increases toward the opening. [A24] The semiconductor device according to [A22], wherein the contact trench has a surface of the SiC semiconductor layer and a side surface thereof connected to each other via a circular surface. [Explanation of symbols]

[0081] 1. Semiconductor device 2. SiC substrate 21 Surface 3 Active Area 4 Outer area 8 Gate Finger 9 Gate Trench 91 Active Trench 92 Contact Trench 12n + Type Source Layer 14 p-type channel layer 15 gate electrode 16 Gate insulating film 17 Overlap section 18 Side insulating film 19 Bottom insulating film 20 Planar insulating film 22 p-type pillar layer 23 Interlayer film 26 Upper Edge 27 Overhang 28 circular surfaces 29 Slope 30 circular surfaces 31 p-type layer 32n + mold layer 33 Bottom p-type layer 34 Sacrificial oxide film

Claims

1. a SiC semiconductor layer having an active region in which a transistor is formed and an inactive region surrounding the active region; a plurality of gate trenches dug from the surface of the SiC semiconductor layer and having side and bottom portions; a gate insulating film formed so as to cover at least the side surface and the bottom surface of the gate trench; a gate electrode embedded in the gate trench; a source layer and a channel layer formed in this order from a surface of the SiC semiconductor layer in the active region so as to contact a side surface of the gate trench; an interlayer insulating film formed to cover a portion of the surface of the source layer and the gate electrode; a gate pad electrically connected to the gate electrode; a gate finger formed in the non-active region and electrically connected to the gate electrode; a pillar layer formed between the plurality of gate trenches in the active region, the pillar layer being connected to the channel layer and being deeper than the gate trenches; The SiC semiconductor layer has a quadrangular shape in a plan view, the gate pad is disposed along a first edge of the SiC semiconductor layer; the gate finger includes a first portion connected to the gate pad and extending along the first side of the SiC semiconductor layer, and a second portion extending along the second side from an end of a second side of the first portion that is perpendicular to the first side; the gate electrode further has an overlap portion formed in the inactive region so as to cover a surface of the SiC semiconductor layer from an opening end of the gate trench, the gate insulating film includes a planar insulating film formed on a surface of the SiC semiconductor layer in the non-active region; the planar insulating film is interposed between at least the overlap portion and a surface of the SiC semiconductor layer, A semiconductor device, wherein a portion of the gate trench extends from the active area to below the gate finger.

2. The semiconductor device according to claim 1 , wherein the thickness of said planar insulating film is greater than the thickness of said gate insulating film on said side surface portion of said gate trench.

3. 3. The semiconductor device according to claim 1, wherein said gate electrode is made of polysilicon.

4. 4. The semiconductor device according to claim 1, wherein the gate finger is made of aluminum.

5. 5. The semiconductor device according to claim 1, wherein, in plan view, there is a portion in an outer periphery of the SiC semiconductor layer where the gate fingers are not formed.

6. 6. The semiconductor device according to claim 1, further comprising a source pad electrically connected to said source layer and formed in a region not overlapping said gate finger.

7. a drain layer formed in contact with the channel layer and reaching a back surface of the SiC semiconductor layer; The semiconductor device according to claim 1 , further comprising a drain electrode electrically connected to the drain layer on a back surface side of the SiC semiconductor layer.

8. 8. The semiconductor device according to claim 1, wherein the source layer and the drain layer are n-type, and the channel layer and the pillar layer are p-type.

9. 9. The semiconductor device according to claim 1, wherein a circular surface is formed on an upper edge of the gate trench.

10. 10. The semiconductor device according to claim 1, wherein the gate trench includes a contact trench that is dug down from the surface of the SiC semiconductor layer in the non-active region.

11. The semiconductor device according to claim 10 , wherein the contact trenches are formed in a stripe shape in a plan view.

12. 12. The semiconductor device according to claim 10, wherein the gate trench including the contact trench is formed so that the side surface portion is continuous with the bottom surface portion via a circular surface in a cross-sectional view.

13. The semiconductor device according to any one of claims 10 to 12, wherein a thickness of the gate insulating film on the bottom portion of the gate trench including the contact trench is greater than a thickness of the gate insulating film on the side portion of the gate trench including the contact trench.

14. the gate insulating film integrally includes a side insulating film on a side surface of the contact trench and a bottom insulating film on a bottom surface of the contact trench; The semiconductor device according to any one of claims 10 to 13, wherein the side insulating film includes an overhang portion at an upper edge formed at the opening end of the contact trench, the overhang portion being selectively thicker than other portions of the side insulating film so as to protrude only inward into the contact trench.

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