Semiconductor Devices

Abstract

To provide a technique for lowering on-resistance in horizontal semiconductor devices with trench gates.SOLUTION: A semiconductor device 1 has a semiconductor layer 10, a plurality of trench gates 30 extending from one major surface of the semiconductor layer 10 to a depth, and a trench drain 40 extending from one major surface of the semiconductor layer 10 to a depth. The semiconductor layer 10 is provided in contact with the bottom surface of each of the plurality of trench gates 30 and has an N-type high impurity concentration region 17, which has a higher concentration of N-type impurities than the drift layer 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a lateral semiconductor device having a trench gate. [Background technology]

[0002] Patent Document 1 discloses an example of a horizontal semiconductor device equipped with a trench gate. In this semiconductor device, electrons are injected vertically from a source electrode disposed on one main surface of a semiconductor layer through a channel formed on the side of the trench gate. The injected electrons can flow to a drain electrode disposed on one main surface of the semiconductor layer via a trench drain extending from one main surface of the semiconductor layer toward the depth thereof. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-174946 Summary of the Invention [Problem to be solved by the invention]

[0004] In this type of semiconductor device, a technique for reducing the on-resistance is required. This specification provides a technique for reducing the on-resistance in a lateral semiconductor device having a trench gate. [Means for solving the problem]

[0005] One embodiment of the semiconductor device disclosed in this specification may include a semiconductor layer, a drain electrode, a source electrode, a plurality of trench gates, and a trench drain. The drain electrode is disposed on at least a portion of one major surface of the semiconductor layer. The source electrode is disposed on at least a portion of the one major surface of the semiconductor layer. Each of the plurality of trench gates extends from the one major surface toward a depth of the semiconductor layer. Each of the plurality of trench gates has a gate electrode and a gate insulating film covering a bottom surface and a side surface of the gate electrode. The trench drain extends from the one major surface of the semiconductor layer toward a depth of the semiconductor layer. The trench drain has a drain connection region electrically connected to the drain electrode and a drain insulating film covering a side surface of the drain connection region. The semiconductor layer may include a drain layer of a first conductivity type, a drift layer of a first conductivity type provided on the drain layer and having a lower impurity concentration than the drain layer, a body layer of a second conductivity type provided on the drift layer and electrically connected to the source electrode, a source region of the first conductivity type provided on the body layer and electrically connected to the source electrode, and a high-concentration region of the first conductivity type provided in contact with a bottom surface of each of the plurality of trench gates and having a higher first-conductivity impurity concentration than the drift layer. Each of the plurality of trench gates is provided from one major surface of the semiconductor layer to reach the drift layer over the body layer and is spaced apart from the drain layer in the thickness direction of the semiconductor layer. The trench drain is provided from one major surface of the semiconductor layer to reach the drain layer over the drift layer. The drain connection region is electrically connected to the drain layer. In this semiconductor device, the high-concentration region is provided in contact with the bottom surface of the trench gate. Therefore, when the semiconductor device is turned on, carriers flowing vertically through the channel formed on the side of the trench gate can flow to the drain layer via the high-concentration region, thereby providing the semiconductor device with low on-resistance characteristics.

[0006] In the semiconductor device of the above embodiment, the width of the high concentration region may be greater than the width of the trench gate, thereby enabling the semiconductor device to have lower on-resistance characteristics.

[0007] In the semiconductor device of the above embodiment, the high concentration region may extend from the bottom surface of the trench gate to the drain layer, thereby enabling the semiconductor device to have lower on-resistance characteristics.

[0008] In the semiconductor device of the above embodiment, the high concentration region may extend between the adjacent trench gates, thereby enabling the semiconductor device to have lower on-resistance characteristics.

[0009] In the semiconductor device of the above embodiment, the concentration of the first conductivity type impurities in the high concentration region may be at least twice as high as the concentration of the first conductivity type impurities in the drift layer, and the semiconductor device can have low on-resistance characteristics.

[0010] In the semiconductor device of the above embodiment, the gate insulating film may include a lower gate insulating film covering the bottom surface and lower portions of the side surfaces of the gate electrode, and an upper gate insulating film covering upper portions of the side surfaces of the gate electrode and having a thickness thinner than that of the lower gate insulating film. The upper gate insulating film is in contact with the body layer. This semiconductor device can achieve both low channel resistance and high dielectric breakdown of the gate insulating film. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view of a main part of a semiconductor device. [Figure 2] 10 is a schematic cross-sectional view of a main part of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0012] As shown in FIG. 1, the semiconductor device 1 is a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10, a drain electrode 22 disposed on at least a portion of the surface of the semiconductor layer 10, a source electrode 24 disposed on at least a portion of the surface of the semiconductor layer 10, a plurality of trench gates 30, and a plurality of trench drains 40. For the purpose of clarity in the illustration, only one trench gate 30 out of the plurality of trench gates 30 is labeled with a reference numeral. The material of the semiconductor layer 10 is not particularly limited, but may be, for example, silicon. Alternatively, the material of the semiconductor layer 10 may be, for example, silicon carbide or a nitride semiconductor. The semiconductor layer 10 may be, for example, N + a drain layer 11, an N-type drift layer 12, a P-type body layer 13, and a P + a body contact region 14 of N type; + a P-type source region 15, a P-type hole ejection region 16, and an N + and a high concentration region 17 of the type.

[0013] The drain layer 11 is an N-type layer containing a high concentration of n-type impurities, and is provided in the lower layer of the semiconductor layer 10, and is disposed at a position exposed on the lower surface of the semiconductor layer 10. The drain layer 11 is a Si substrate.

[0014] The drift layer 12 is an N-type layer containing n-type impurities at a lower concentration than the drain layer 11, and is provided on the drain layer 11 and disposed between the drain layer 11 and the body layer 13. The drift layer 12 is an epitaxial layer formed by crystal growth from the upper surface of the drain layer 11, which is a Si substrate.

[0015] The body layer 13 is a P-type layer containing p-type impurities, and is provided in the upper portion of the semiconductor layer 10, and is arranged between the drift layer 12 and the source region 15. The body layer 13 is arranged in a region between adjacent trench gates 30, and contacts an upper portion of the side surface of each of the multiple trench gates 30. The body layer 13 is also arranged in a region between the trench gate 30 and the trench drain 40. The body layer 13 is a diffusion region formed by introducing p-type impurities into the upper portion of the drift layer 12 using, for example, ion implantation technology.

[0016] The body contact region 14 is a P-type region containing p-type impurities at a higher concentration than the body layer 13, and is provided on the body layer 13. The body contact region 14 is provided in the upper layer portion of the semiconductor layer 10, is located at a position exposed on the upper surface of the semiconductor layer 10, and is in ohmic contact with the source electrode 24. Therefore, the body layer 13 is electrically connected to the source electrode 24 via the body contact region 14. The body contact region 14 is located in a region between adjacent trench gates 30. The body contact region 14 is also located in a region between the trench gate 30 and the trench drain 40. The body contact region 14 is a diffusion region formed by introducing p-type impurities into the upper layer portion of the drift layer 12 using, for example, ion implantation technology.

[0017] The source region 15 is an N-type region containing a high concentration of N-type impurities, is provided in the upper portion of the semiconductor layer 10, is located at a position exposed on the upper surface of the semiconductor layer 10, and is in ohmic contact with the source electrode 24. The source region 15 is located in a region between adjacent trench gates 30 and contacts the upper portion of each of the side surfaces of the multiple trench gates 30. The source region 15 is not located in a region between the trench gate 30 and the trench drain 40. The source region 15 is a diffusion region formed by introducing N-type impurities into the upper portion of the drift layer 12 using, for example, ion implantation technology.

[0018] The hole ejection region 16 is a P-type region containing p-type impurities and is provided in a region between the trench gate 30 and the trench drain 40. In this example, the hole ejection region 16 is arranged to be in contact with a side surface of the trench drain 40. The hole ejection region 16 is also in contact with the body layer 13 and is configured to protrude from the body layer 13 into the drift layer 12 toward a depth of the semiconductor layer 10. The hole ejection region 16 is electrically connected to the source electrode 24 via the body layer 13 and the body contact region 14. The hole ejection region 16 is also arranged away from the drain layer 11. Alternatively, the hole ejection region 16 may be in contact with the drain layer 11. The hole ejection region 16 is a diffusion region formed by, after forming a trench to form the trench drain 40, introducing p-type impurities obliquely onto the side surface of the trench using, for example, ion implantation technology.

[0019] The high-concentration region 17 is an N-type region containing n-type impurities at a higher concentration than the drift layer 12, and is provided in contact with the bottom surface of each of the multiple trench gates 30. The high-concentration region 17 extends from the bottom surface of the trench gate 30 to the drain layer 11 and is in contact with the drain layer 11. The width of the high-concentration region 17 (the width of the high-concentration region 17 measured in the short-side direction of the trench gate 30, i.e., the width of the high-concentration region 17 measured in the left-right direction on the page) is greater than the width of the trench gate 30 in the short-side direction. Therefore, the high-concentration region 17 protrudes laterally from the side surface of the trench gate 30. Furthermore, the high-concentration region 17 is in contact with not only the bottom surface of the trench gate 30 but also a portion of the lower portion of the side surface of the trench gate 30. The high-concentration region 17 is a diffusion region formed by introducing n-type impurities into the bottom surface of the trench using, for example, ion implantation technology after forming the trench for forming the trench gate 30.

[0020] The trench gates 30 are arranged between a pair of trench drains 40 and are arranged, for example, in a stripe pattern when viewed in a plan view, although this is not particularly limited. Therefore, the trench gates 30 are arranged side by side at intervals along at least one direction when viewed in a plan view. In this example, three trench gates 30 are arranged between the pair of trench drains 40, but at least two or more trench gates 30 may be arranged. Each of the trench gates 30 extends from the surface of the semiconductor layer 10 toward a depth thereof, passing through the body layer 13 and reaching the drift layer 12. Each of the trench gates 30 is arranged away from the drain layer 11 in the thickness direction of the semiconductor layer 10.

[0021] Each of the trench gates 30 includes a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the drain electrode 22 and the source electrode 24 via an interlayer insulating film. The gate insulating film 34 covers the bottom and side surfaces of the gate electrode 32 and separates the gate electrode 32 from the semiconductor layer 10. In this example, the gate insulating film 34 includes a lower gate insulating film 34a and an upper gate insulating film 34b. The lower gate insulating film 34a covers the bottom and lower portions of the side surfaces of the gate electrode 32. The upper gate insulating film 34b covers the upper portions of the side surfaces of the gate electrode 32 and has a thickness thinner than that of the lower gate insulating film 34a. Although not particularly limited, the thickness of the lower gate insulating film 34a may be, for example, 150 nm to 250 nm, and the thickness of the upper gate insulating film 34b may be, for example, 50 nm to 100 nm. The entire portion of the body layer 13 separating the drift layer 12 and the source region 15 is in contact with the upper gate insulating film 34b. The channel resistance is kept low because the thin upper gate insulating film 34b contacts the portion of the body layer 13 where the channel (inversion layer) is formed. On the other hand, the thick lower gate insulating film 34a contacts the lower portions of the bottom and side surfaces of the trench gate 30, so dielectric breakdown in these portions is suppressed.

[0022] Each of the trench drains 40 extends from the surface of the semiconductor layer 10 toward a deeper portion thereof, passing through the body layer 13 and the drift layer 12 to reach the drain layer 11. Each of the trench drains 40 includes a drain connection region 42 and a drain insulating film 44. The drain connection region 42 is an N-type region containing a high concentration of N-type impurities. The upper end of the drain connection region 42 is exposed at the surface of the semiconductor layer 10, and the lower end of the drain connection region 42 is in ohmic contact with the drain electrode 22. Therefore, the drain layer 11 is electrically connected to the drain electrode 22 via the drain connection region 42. The drain connection region 42 may be made of any conductor, such as a metal. The drain insulating film 44 covers the side surface of the drain connection region 42 and separates the drain connection region 42 from the drift layer 12, the hole ejection region 16, the body layer 13, and the body contact region 14.

[0023] Next, the operation of the semiconductor device 1 will be described. When a voltage that makes the drain electrode 22 more positive than the source electrode 24 is applied between the drain electrode 22 and the source electrode 24 and a voltage higher than the threshold voltage is applied to the gate electrode 32, the semiconductor device 1 turns on. At this time, a channel (inversion layer) is formed in the body layer 13 that contacts the side surface of the trench gate 30. Electrons injected from the source region 15 connected to the source electrode 24 are injected into the drift layer 12 through the channel formed in the body layer 13. The electrons injected into the drift layer 12 further flow vertically within the drift layer 12 along the side surface of the trench gate 30 and then move to the drain layer 11 through the high-concentration region 17. The electrons that have moved to the drain layer 11 flow laterally through the drain layer 11 and flow to the drain electrode 22 disposed on the surface of the semiconductor layer 10 via the drain connection region 42. In this way, conduction is established between the drain electrode 22 and the source electrode 24, and the semiconductor device 1 turns on. When the voltage applied to the gate electrode 32 falls below the threshold voltage, the channel in the body layer 13 disappears, and the semiconductor device 1 turns off.

[0024] As described above, the semiconductor device 1 has a high-concentration region 17 provided in a portion of the current path. Without such a high-concentration region 17, the current would flow through the drift layer 12, which has a low n-type impurity concentration, resulting in a high on-resistance. On the other hand, the semiconductor device 1 can have low on-resistance characteristics by having a low-resistance high-concentration region 17 provided in a portion of the current path. The concentration of the n-type impurity in the high-concentration region 17 is at least twice the concentration of the n-type impurity in the drift layer 12. The high-concentration region 17 with such a concentration can have sufficiently low on-resistance characteristics compared to a case where the high-concentration region 17 is not provided.

[0025] In the semiconductor device 1, the width of the high-concentration region 17 is larger than the width of the trench gate 30. Therefore, the high-concentration region 17 can be located in the current path of electrons flowing vertically through the drift layer 12 along the side surface of the trench gate 30. The semiconductor device 1 can have lower on-resistance characteristics. In particular, in the semiconductor device 1, the high-concentration region 17 contacts not only the bottom surface of the trench gate 30 but also a portion of the lower portion of the side surface of the trench gate 30, i.e., a portion of the side surface of the lower gate insulating film 34a. This allows the high-concentration region 17 to be located in a long range of the electron current path. Furthermore, the side surface of the thick lower gate insulating film 34a is less affected by the gate voltage applied to the gate electrode 32, and drift resistance is likely to be large. Since the high-concentration region 17 is located in such a portion, the semiconductor device 1 can have lower on-resistance characteristics.

[0026] In the semiconductor device 1, the high-concentration region 17 extends between the bottom surface of the trench gate 30 and the drain layer 11. Therefore, most of the electrons that flow vertically in the drift layer 12 along the side surface of the trench gate 30 are prevented from flowing through the highly resistive drift layer 12, and can flow to the drain layer 11 via the high-concentration region 17. The semiconductor device 1 can have lower on-resistance characteristics.

[0027] The semiconductor device 1 is configured such that the drain layer 11 and the drift layer 12 are in contact between the trench gate 30 and the trench drain 40. That is, in the semiconductor device 1, the high-concentration region 17 between the trench gate 30 and the trench drain 40 does not extend significantly from the trench gate 30 toward the trench drain 40. The region between the trench gate 30 and the trench drain 40 is a region that is depleted when the semiconductor device 1 is turned off and maintains the drain-source voltage. Since the high-concentration region 17 with a high concentration of n-type impurities is not provided in this region, the breakdown voltage of the semiconductor device 1 is maintained. In this regard, as shown in FIG. 2, the high-concentration region 17 may extend between adjacent trench gates 30. The semiconductor device 1 shown in FIG. 2 can have lower on-resistance characteristics while maintaining the breakdown voltage.

[0028] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0029] 1: semiconductor device, 10: semiconductor layer, 11: drain layer, 12: drift layer, 13: body layer, 14: body contact region, 15: source region, 16: hole ejection region, 17: high concentration region, 22: drain electrode, 24: source electrode, 30: trench gate, 32: gate electrode, 34: gate insulating film, 40: trench drain, 42: drain connection region, 44: drain insulating film

Claims

1. a semiconductor layer; a drain electrode disposed on at least a portion of one major surface of the semiconductor layer; a source electrode disposed on at least a portion of the one principal surface of the semiconductor layer; a plurality of trench gates extending from the one main surface of the semiconductor layer toward a depth thereof, each of the plurality of trench gates having a gate electrode and a gate insulating film covering a bottom surface and a side surface of the gate electrode; a trench drain extending from the one main surface of the semiconductor layer toward a depth thereof, the trench drain having a drain connection region electrically connected to the drain electrode and a drain insulating film covering a side surface of the drain connection region; The semiconductor layer is a drain layer of a first conductivity type; a drift layer of a first conductivity type provided on the drain layer and having a lower concentration of first conductivity type impurities than the drain layer; a body layer of a second conductivity type provided on the drift layer and electrically connected to the source electrode; a first conductivity type source region provided on the body layer and electrically connected to the source electrode; a first conductivity type high concentration region provided in contact with each bottom surface of the plurality of trench gates and having a first conductivity type impurity concentration higher than that of the drift layer, each of the plurality of trench gates is formed from one main surface of the semiconductor layer beyond the body layer to a depth greater than the body layer and is provided to reach the drift layer, and is disposed apart from the drain layer in a thickness direction of the semiconductor layer; the trench drain is provided so as to extend from one main surface of the semiconductor layer, across the drift layer, and reach the drain layer; the drain connection region is electrically connected to the drain layer; the width of the high concentration region is greater than the width of the trench gate; The semiconductor device, wherein the high concentration region also contacts a part of a lower portion of a side surface of the trench gate.

2. The semiconductor device according to claim 1 , wherein said high concentration region extends from said bottom surface of said trench gate to said drain layer.

3. 3. The semiconductor device according to claim 1, wherein the high concentration region extends between adjacent ones of the trench gates.

4. 4. The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in said high concentration region is at least twice as high as the concentration of the first conductivity type impurity in said drift layer.

5. the gate insulating film includes a lower gate insulating film covering the bottom surface and lower portions of the side surfaces of the gate electrode, and an upper gate insulating film covering upper portions of the side surfaces of the gate electrode and having a thickness thinner than that of the lower gate insulating film, 5. The semiconductor device according to claim 1, wherein the upper gate insulating film is in contact with the body layer.

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