Semiconductor Devices

Abstract

To stabilize operation an a plurality of IGBTs in a semiconductor chip.SOLUTION: A semiconductor device comprises: a semiconductor substrate; each IGBT (Insulated Gate Bipolar Transistor) formed on the semiconductor substrate; a gate electrode; a plurality of gate wirings connected to each gate of each IGBT; and a gate resister connected to the gate electrode and the plurality of gate wirings. The gate resister comprises: a resistance element; a first contact connecting the gate electrode and a resistance element; and a plurality of second contacts that connects the resistance element and the plurality of gate wirings and is corresponded to each of the plurality of gata wirings. Each of the plurality of second contacts is formed in a distance different from the first contact.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor). [Background technology]

[0002] Some power modules that handle large amounts of power are configured by connecting multiple IGBT-equipped chips in parallel. In these power modules, multiple IGBTs operate simultaneously, so a gate resistor is built in to stabilize the switching operation.

[0003] Patent Document 1 discloses a technique for forming a gate resistor (polysilicon) having a stripe shape, which makes it possible to suppress an increase in chip area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-92214 Summary of the Invention [Problem to be solved by the invention]

[0005] The technology in Patent Document 1 makes it possible to reduce the area of ​​the gate resistance portion. Furthermore, by adjusting the stripe shape, it is possible to adjust the gate resistance value of an entire IGBT chip. However, Patent Document 1 does not mention adjusting the gate resistance value of each of the multiple IGBTs present in an IGBT chip.

[0006] Generally, an IGBT chip has an emitter pad formed on a region occupying most of its surface, and a gate pad formed on the periphery. It can be said that multiple IGBTs are formed within an IGBT chip. A gate potential is applied to each of the gates of the multiple IGBTs from the gate pad (gate electrode) via a gate resistor and gate wiring. For example, an IGBT located near the gate pad (or a polysilicon gate resistor formed as in Patent Document 1) has a different gate resistance value from an IGBT located far from the gate pad due to the gate wiring length. In other words, the gate resistance values ​​of the multiple IGBTs within an IGBT chip vary. Variations in the gate resistance values ​​of the multiple IGBTs within an IGBT chip result in variations in the switching (turn-on / turn-off) of each IGBT. Such variations in switching among the multiple IGBTs can reduce the breakdown resistance of the IGBT chip and increase switching losses.

[0007] It can be said that the variation in gate resistance value is proportional to the size of the IGBT chip. For IGBT chips for high power applications (high voltage and high current), the chip size becomes larger, so the above-mentioned issues become even more serious. A solution to this issue is required.

[0008] Other objects and novel features will become apparent from the description of this specification and the drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a semiconductor substrate, an IGBT (Insulated Gate Bipolar Transistor) formed on the semiconductor substrate, a gate electrode, a plurality of gate wirings connected to the gate of the IGBT, and a gate resistor connected to the gate electrode and the plurality of gate wirings, the gate resistor including a resistive element, a first contact connecting the gate electrode and the resistive element, and a plurality of second contacts corresponding to each of the plurality of gate wirings and connecting the resistive element to the plurality of gate wirings, each of the plurality of second contacts being formed at a different distance from the first contact. [Effects of the Invention]

[0010] In the semiconductor device according to one embodiment, it is possible to stabilize the operations of a plurality of IGBTs in the semiconductor device. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view of a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] A semiconductor device according to one embodiment will be described in detail below with reference to the drawings. In the specification and drawings, identical or corresponding components are designated by the same reference numerals, and duplicate explanations will be omitted. For the sake of convenience, some components may be omitted or simplified in the drawings. At least some of the embodiments may be combined with each other in any desired manner.

[0013] [Embodiment 1] (Configuration of semiconductor device) FIG. 1 is a plan view of a semiconductor (IGBT) chip 100, which is a semiconductor device according to the first embodiment. In FIG. 1, the insulating film is shown as transparent for ease of understanding. As shown in FIG. 1, most of the surface of the semiconductor chip 100 is covered with emitter pads 8 to 11 (portions of the emitter electrodes not covered with the protective film). A gate pad 1 and a gate electrode 2 are formed in the left corner of the semiconductor chip 100. A collector electrode 12 is formed on the back surface of the semiconductor chip 100. A gate potential is supplied to the gate pad 1, and an emitter potential is supplied to the emitter pads 8 to 11. Gate wirings 4 to 7 are connected to the gate electrode 2 (gate pad 1) via a gate resistor 3.

[0014] FIG. 2 is an enlarged view of the gate resistor 3. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 2. As shown in FIG. 3, the gate resistor 3 is composed of a resistive element 15 formed under the gate electrode 2 and gate wirings 4-7, and contacts 16-20. The gate electrode 2 and gate wirings 4-7 are made of, for example, aluminum (Al). The resistive element 15 is made of, for example, polysilicon (Poly-Si). Reference numeral 13 denotes a protective film, and 14 denotes an interlayer insulating film (SiO2).

[0015] The contact 16 (first contact) connects the gate electrode 2 to the resistive element 15. The contacts 17 to 20 (second contacts) connect the gate wirings 4 to 7 to the resistive element 15, respectively. Here, the resistance values ​​contributed to the gate wirings 4 to 7 by the resistive element 15 are R1 to R4, respectively. As is clear from FIG. 3, R1 <R2<R3<R4となる。

[0016] Next, the IGBT formed on the semiconductor chip 100 will be described with reference to Figures 4 and 5. Figure 4 is an enlarged view of region A in Figure 1. Figure 5 is a cross-sectional view taken along line CC' in Figure 4. Figures 4 and 5 show an example of an IGBT formed on the semiconductor chip 100. Here, a GE-S type (GE type shrink structure) IGBT, which is a type of IE type IGBT, is shown.

[0017] As shown in FIGS. 4 and 5 , the semiconductor chip 100 includes an emitter electrode 10, a collector electrode 12, a p+ type collector layer 46, an n+ type field stop layer 47, and an n− type drift layer 48 formed on a semiconductor substrate 60. The semiconductor chip 100 further includes a gate potential trench electrode (also referred to as a gate potential trench gate) 41 to which a gate potential is supplied, and an emitter potential trench electrode (also referred to as an emitter potential trench gate) 42 to which an emitter potential is supplied. A high-concentration n+ type hole barrier layer 45 is formed between the gate potential trench electrode 41 and the emitter potential trench electrode 42. The region formed by the gate potential trench electrode 41, the emitter potential trench electrode 42, and the hole barrier layer 45 is an active cell region. A p-type floating layer 44 (non-active cell region) and a p-type body layer 40 are formed between the two active cell regions.

[0018] The emitter electrode 10 is connected to the emitter potential trench electrode 42 via a contact 43. The emitter electrode 10 is connected to a p+ type body layer 51 via the contact 43 and a body contact. An n+ type emitter layer 52 and a p+ type base layer 53 are formed between the gate potential trench electrode 41 and the contact 43 of the emitter electrode 10. Note that reference numeral 49 in FIG. 5 denotes a gate insulating film, and reference numeral 50 denotes an interlayer insulating film.

[0019] The IGBT described above is formed under emitter electrodes 8, 9, 10, and 11.

[0020] Returning to Fig. 1 again, the semiconductor chip 100 of the first embodiment will be described. The gate wiring 4 is connected to a gate potential trench electrode 41 of the IGBT formed below the emitter electrode 8. The gate wiring 5 is connected to a gate potential trench electrode 41 of the IGBT formed below the emitter electrode 9. The gate wiring 6 is connected to a gate potential trench electrode 41 of the IGBT formed below the emitter electrode 10. The gate wiring 7 is connected to a gate potential trench electrode 41 of the IGBT formed below the emitter electrode 11.

[0021] As is clear from FIG. 1, in the order of the emitter electrodes 8, 9, 10, and 11, the distance from the gate pad 1 is far. And in the order of the gate wirings 4, 5, 6, and 7, the wiring length is long. In other words, the resistance value of each gate wiring is such that gate wiring 4 > gate wiring 5 > gate wiring 6 > gate wiring 7. Between each gate wiring and the gate pad 1 (gate electrode 2), the above-described gate resistor 3 is connected. That is, the gate resistors of the IGBTs formed under the emitter electrodes 8 to 11 are, respectively, the resistance value of gate wiring 4 + R1, the resistance value of gate wiring 5 + R2, the resistance value of gate wiring 6 + R3, and the resistance value of gate wiring 7 + R4. As described above, since R1 < R2 < R3 < R4, by adjusting the gate resistor 3 during manufacturing, it is possible to make the resistance value of gate wiring 4 + R1 ≒ the resistance value of gate wiring 5 + R2 ≒ the resistance value of gate wiring 6 + R3 ≒ the resistance value of gate wiring 7 + R4. (Effect)

[0022] As described above, in the IGBT chip 100 according to the first embodiment, a plurality of gate wirings connected to the gate of the IGBT and gate resistors having different resistance values are connected to each of the gate wirings. Thereby, it becomes possible to suppress the variation in the IGBT operation within the chip due to the variation in the gate wiring.

[0023] Note that the first embodiment has been described for a GE - S type IGBT, but it is not limited thereto. Other types (e.g., GG, EGE, GGEE, etc.) of IGBTs may also be used, or an IGBT having a planar gate structure without a trench gate may also be used.

[0024] [Second Embodiment] (Configuration of Semiconductor Device) FIG. 6 is a diagram showing the structure of an IGBT according to the second embodiment. Similar to the first embodiment, FIG. 6 is a cross-sectional view along the C - C' line in FIG. 4. The difference from the first embodiment is the gate potential trench electrode. The gate potential trench electrode 41 in the first embodiment is composed of two gate potential trench electrodes 41a and 41b in the second embodiment.

[0025] The meaning of the two gate potential trench electrodes 41a and 41b will be explained using Figure 7. Figure 7 is a diagram for explaining the resonance phenomenon that occurs when multiple IGBTs are connected in parallel. As shown in Figure 7, when multiple (two in Figure 7) IGBTs are connected in parallel, a loop circuit (dashed line) is formed by parasitic capacitances (C1 and C2). The loop circuit also includes parasitic inductances (L1 and L2). When a loop circuit is formed by the parasitic capacitance and parasitic inductance, a resonance phenomenon occurs. The lower diagram in Figure 7 is an equivalent circuit when a damping resistor R is inserted into the loop circuit to suppress the resonance phenomenon. The resonance frequency f and resonance condition Q in the equivalent circuit are as shown in Figure 7.

[0026] When a resonance phenomenon occurs, the operation of the semiconductor device (IGBT chip) 100 becomes unstable, so it is desirable to suppress the resonance phenomenon. Referring to the resonance condition Q, it can be seen that the resonance phenomenon can be suppressed by increasing the damping resistance R. In the case of an IGBT, the gate resistance functions as the damping resistance R, so the resonance phenomenon can be suppressed by increasing the gate resistance. However, simply increasing the gate resistance slows down the switching operation of the IGBT. In other words, it is necessary to determine the gate resistance taking into consideration both the suppression of the resonance phenomenon and the reduction of switching loss. Therefore, in the second embodiment, these two are achieved by dividing the gate potential trench electrode into two.

[0027] In the second embodiment, the IGBT has two gate potential trench electrodes 41a and 41b. The upper gate potential trench electrode 41a contributes more to the switching operation of the IGBT than the gate potential trench electrode 41b, so a small gate resistor is connected to the gate potential trench electrode 41a. The gate potential trench electrode 41b contributes more to damping resistance, so a large gate resistor is connected to the gate potential trench electrode 41b. This makes it possible to suppress the resonance phenomenon and reduce switching loss at the same time.

[0028] The gate resistors connected to the gate potential trench electrodes 41a, 41b can be realized by using a structure similar to that of the gate resistor 3 described in the first embodiment. FIGS. 8 and 9 show an example. In addition to the structure of FIG. 1, the gate resistor 3a is provided with a resistor R5 having an even greater resistance value than resistor R4. Resistor R5 is connected to gate pad 1 (gate electrode 2) and gate wiring 54. Gate wiring 54 is connected to gate potential trench electrode 41a of the IGBT formed under emitter pads 8 to 11. The gate resistor and gate wiring connected to gate potential trench electrode 41b are similar to those of gate potential trench electrode 41 in the first embodiment.

[0029] If variations in the gate resistance of the gate potential trench electrode 41a become a problem, as in embodiment 1, it is possible to suppress variations in the gate resistance by providing multiple resistors R5 and gate wiring 54 according to the distance from the gate pad 1.

[0030] In addition to being effective as a countermeasure against the resonance phenomenon, the second embodiment also has other effects. In trench-gate IGBTs, a problem has been observed in which hot holes are injected into the trench gate. When the IGBT is turned off, a dynamic avalanche occurs near the bottom of the trench gate, and Vce becomes a high voltage (resulting in the generation of hot holes). If the turn-off is completed in this state and the voltage of the trench gate becomes negative, the hot holes generated near the bottom of the trench gate are injected into the trench gate. In the second embodiment, the gate resistance of the gate potential trench electrode 41b (the bottom of the trench gate) is higher than that of the gate potential trench electrode 41a. This means that the operation timing of the gate potential trench electrode 41a can be shifted from the operation timing of the gate potential trench electrode 41b (the operation of the gate potential trench electrode 41b is slower). The timing at which the hot holes are generated can be shifted from the timing at which the voltage at the bottom of the trench gate becomes negative, thereby making it possible to suppress the problem described above.

[0031] (effect) As described above, the semiconductor chip 100a according to the second embodiment has a plurality of gate wirings connected to the gate of the IGBT, and gate resistors with different resistance values ​​connected to each of the gate wirings. The gate potential trench electrode of the IGBT is divided into two, and gate resistors with different resistance values ​​are connected to each of the two. This not only achieves the effects of the first embodiment, but also makes it possible to suppress the resonance phenomenon and reduce switching loss. Furthermore, it is possible to suppress problems caused by hot hole injection into the trench gate.

[0032] Although the second embodiment has been described using a GE-S type IGBT, the present invention is not limited to this and may be applied to other types of IGBTs having trench gates.

[0033] The present invention is not limited to the above-described embodiment, and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0034] 100, 100a Semiconductor chip (semiconductor device) 1 gate pad 2. Gate electrode 3, 3a gate resistor 4, 5, 6, 7, 54 gate wiring 8, 9, 10, 11 Emitter pads (emitter electrodes) 12 Collector electrode 13 Protective film 14 Interlayer insulating film 15 Resistive element 16, 17, 18, 19, 20 Contacts 40 p-type body layer 41, 41a, 41b Gate potential trench electrodes 42 Emitter potential trench electrode 43 Contacts 44 p-type floating layer 45 n+ type hole barrier layer 46 p+ type collector layer 47 n+ type field stop layer 48 n-type drift layer 49 Gate oxide 50 Interlayer insulating film 51 p+ type body layer 52 n+ type emitter layer 53 p+ type base layer

Claims

1. a semiconductor substrate; a plurality of IGBTs (Insulated Gate Bipolar Transistors) formed on the semiconductor substrate; A gate electrode; a plurality of gate wirings connected to gates of the plurality of IGBTs; a gate resistor connected to the gate electrode and the plurality of gate wirings; The gate resistor is A resistive element; a first contact connecting the gate electrode and the resistive element; a plurality of second contacts that connect the resistive element and the plurality of gate wirings and correspond to the plurality of gate wirings, each of the plurality of second contacts is formed at a different distance from the first contact; The plurality of gate wirings are a first gate wiring; a second gate wiring that is longer than the first gate wiring; The plurality of second contacts include: a third contact connected to the first gate wiring; a fourth contact connected to the second gate wiring; A semiconductor device, wherein a distance between the first contact and the third contact is longer than a distance between the first contact and the fourth contact.

2. the semiconductor substrate has a first region and a second region when viewed from the surface; the plurality of IGBTs are IGBTs formed in the first region and the second region, the first gate wiring is connected to a gate of an IGBT formed in the first region, 2. The semiconductor device according to claim 1, wherein said second gate wiring is connected to a gate of an IGBT formed in said second region.

3. 3. The semiconductor device according to claim 2, wherein a distance between said first region and said gate electrode is shorter than a distance between said second region and said gate electrode.

4. The semiconductor device according to claim 1 , wherein said resistive element includes polysilicon.

5. 2. The semiconductor device according to claim 1, wherein the gates of said plurality of IGBTs are trench gates.

6. A semiconductor substrate; a plurality of IGBTs (Insulated Gate Bipolar Transistors) formed on the semiconductor substrate; A gate electrode; a plurality of gate wirings connected to gates of the plurality of IGBTs; a gate resistor connected to the gate electrode and the plurality of gate wirings; The gate resistor is A resistive element; a first contact connecting the gate electrode and the resistive element; a plurality of second contacts that connect the resistive element and the plurality of gate wirings and correspond to the plurality of gate wirings, each of the plurality of second contacts is formed at a different distance from the first contact; the gates of the plurality of IGBTs are trench gates; the trench gate of each of the plurality of IGBTs is composed of a first trench gate and a second trench gate; the first trench gate is formed closer to the front surface of the semiconductor substrate than the second trench gate; the second trench gate is formed below the first trench gate; The plurality of gate wirings are a first gate wiring connected to the first trench gate; a second gate wiring connected to the second trench gate; The plurality of second contacts include: a third contact connected to the first gate wiring; a fourth contact connected to the second gate wiring; A semiconductor device, wherein a distance between the first contact and the third contact is shorter than a distance between the first contact and the fourth contact.

7. The first gate wiring is a third gate wiring connected to the first trench gate of a first IGBT among the plurality of IGBTs; a fourth gate wiring connected to the first trench gate of a second IGBT among the plurality of IGBTs and longer than the third gate wiring; The third contact comprises: a fifth contact connected to the third gate wiring; a sixth contact connected to the fourth gate wiring; 7. The semiconductor device according to claim 6, wherein a distance between said first contact and said fifth contact is longer than a distance between said first contact and said sixth contact.

8. the semiconductor substrate has a first region and a second region when viewed from the surface; 8. The semiconductor device according to claim 7, wherein said first IGBT is formed in said first region, and said second IGBT is formed in said second region.

9. 9. The semiconductor device according to claim 8, wherein a distance between said first region and said gate electrode is shorter than a distance between said second region and said gate electrode.

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