Semiconductor Devices

Abstract

Provided is a memory device having a large memory capacity. Provided is a highly reliable memory device. This semiconductor device has a first electrically conductive layer extending in a first direction, a structure extending in a second direction that intersects the first direction, and a first insulation layer and a second insulation layer. The structure has a functional layer, a semiconductor layer, a third insulation layer, and a second electrically conductive layer. At the intersection part of the first electrically conductive layer and the structure, the third insulation layer, the semiconductor layer, and the functional layer are arranged concentrically in this order in the center of the second electrically conductive layer. The first insulation layer and the second insulation layer are layered in the second direction. The functional layer and the first electrically conductive layer are arranged between the first insulation layer and the second insulation layer. The second electrically conductive layer, the third insulation layer, and the semiconductor layer have a portion positioned on the inside of a first opening provided on the first insulation layer, and a portion positioned on the inside of a second opening provided on the second insulation layer.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), storage devices, and sensors have been used in a variety of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components have been improving in various aspects, including miniaturization and reduced power consumption.

[0004] In particular, the amount of data handled by the electronic devices described above is increasing, and there is a demand for storage devices with large storage capacities. As a means for increasing storage capacity, for example, Patent Documents 1 and 2 disclose a NAND memory element with a three-dimensional structure that uses a metal oxide as a channel formation region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 3060 Brochure [Patent Document 2] Patent Publication No. 2018-207038 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a novel storage device.An object of one embodiment of the present invention is to provide a highly reliable storage device.An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0007] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device including a first conductive layer extending in a first direction, a structure extending in a second direction intersecting the first direction, and a first insulating layer and a second insulating layer. The structure includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. At the intersection of the first conductive layer and the structure, the third insulating layer, the semiconductor layer, and the functional layer are concentrically arranged in this order with the second conductive layer at the center. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are arranged between the first insulating layer and the second insulating layer. The second conductive layer, the third insulating layer, and the semiconductor layer each have a portion located inside a first opening provided in the first insulating layer and a portion located inside a second opening provided in the second insulating layer.

[0009] Another aspect of the present invention is a semiconductor device having a first conductive layer extending in a first direction, a structure extending in a second direction intersecting the first direction, and a first insulating layer and a second insulating layer. The structure has a functional layer, a third conductive layer, and a fourth insulating layer. At the intersection of the first conductive layer and the structure, the third conductive layer and the functional layer are concentrically arranged in this order with the fourth insulating layer at the center. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are arranged between the first insulating layer and the second insulating layer. The third conductive layer and the fourth insulating layer have a portion located inside a first opening provided in the first insulating layer and a portion located inside a second opening provided in the second insulating layer.

[0010] Another embodiment of the present invention is a semiconductor device including a first conductive layer and a fourth conductive layer extending in a first direction, a structure extending in a second direction intersecting the first direction, and a first insulating layer, a second insulating layer, and a fifth insulating layer. The structure includes a first portion and a second portion. The first portion includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. The second portion includes a sixth insulating layer, a semiconductor layer, a third insulating layer, and a second conductive layer. At an intersection between the first conductive layer, the fourth conductive layer, and the structure, the first portion includes the third insulating layer, the semiconductor layer, and the functional layer, arranged in this order, concentrically with the second conductive layer. Furthermore, at the intersection, the second portion includes the third insulating layer, the semiconductor layer, and the sixth insulating layer, arranged in this order, concentrically with the second conductive layer. The functional layer and the first conductive layer are disposed between the first insulating layer and the second insulating layer. The fourth conductive layer is disposed between the second insulating layer and the fifth insulating layer. The second conductive layer, the third insulating layer, and the semiconductor layer each have a portion located inside a first opening provided in the first insulating layer, a portion located inside a second opening provided in the second insulating layer, and a portion located inside a third opening provided in the fifth insulating layer.

[0011] In any of the above, it is preferable to have a seventh insulating layer. In this case, the seventh insulating layer is preferably disposed between the first insulating layer and the second insulating layer. Furthermore, it is preferable that the seventh insulating layer is provided in contact with the upper surface, the lower surface, and one side surface of the functional layer.

[0012] In any of the above, it is preferable to have an eighth insulating layer. In this case, it is preferable that the eighth insulating layer is disposed between the semiconductor layer and the functional layer. It is also preferable that the eighth insulating layer contains silicon and nitrogen. It is also preferable that the eighth insulating layer is disposed concentrically around the second conductive layer or the fourth insulating layer.

[0013] In any of the above, the first direction is preferably a direction perpendicular to the second direction.

[0014] In any of the above, the intersections preferably function as memory cells.

[0015] In any of the above, the semiconductor layer preferably contains at least one of indium and zinc.

[0016] In any of the above, the functional layer preferably exhibits ferroelectricity or antiferroelectricity.

[0017] In any of the above, the functional layer preferably contains either hafnium oxide or zirconium oxide, or both. [Effects of the Invention]

[0018] According to one aspect of the present invention, a novel storage device can be provided. According to one aspect of the present invention, a highly reliable storage device can be provided. According to one aspect of the present invention, a storage device with a large storage capacity can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be alleviated.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0020] 1A and 1B are cross-sectional and circuit diagrams of a memory string. 2A and 2B are cross-sectional views of a memory string. FIG. 3 is a graph showing an example of the hysteresis characteristic. 4A and 4B are cross-sectional views of a memory string. 5A to 5C are cross-sectional views of a memory string. 6A and 6B are cross-sectional and circuit diagrams of a memory string. 7A to 7C are cross-sectional views of a memory string. 8A and 8B are cross-sectional views illustrating a method for fabricating a memory string. 9A and 9B are cross-sectional views illustrating a method for fabricating a memory string. 10A and 10B are cross-sectional views illustrating a method for fabricating a memory string. 11A and 11B are cross-sectional views illustrating a method for fabricating a memory string. 12A and 12B are cross-sectional views illustrating a method for fabricating a memory string. FIG. 13 is a cross-sectional view illustrating a method for manufacturing a memory string. 14A and 14B are cross-sectional and circuit diagrams of a memory string. 15A and 15B are cross-sectional and circuit diagrams of a memory string. 16A and 16B are cross-sectional and circuit diagrams of a memory string. Figure 17A is a diagram explaining the classification of crystal structures, Figure 17B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 17C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. 18A and 18C are diagrams showing a film formation sequence for a metal oxide film, and Fig. 18B is a cross-sectional view of a metal oxide film manufacturing apparatus. FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device. FIG. 20 is a diagram illustrating a configuration example of a semiconductor device. FIG. 21 is a diagram illustrating an example of an information processing system constructed using a plurality of storage devices. 22A and 22B are perspective views of the semiconductor device. FIG. 23 is a block diagram illustrating the CPU. 24A and 24B are perspective views of a semiconductor device. 25A and 25B are perspective views of a semiconductor device. FIG. 26A is a perspective view showing an example of a semiconductor wafer, FIG. 26B is a perspective view showing an example of a chip, and FIGS. 26C and 26D are perspective views showing an example of an electronic component. 27A to 27J are perspective views or schematic diagrams illustrating examples of electronic devices. 28A to 28E are perspective views or schematic diagrams illustrating examples of electronic devices. 29A to 29C are diagrams illustrating an example of an electronic device. FIG. 30 is a diagram illustrating an example of the configuration of a computer system. FIG. 31 shows the hierarchical structure of IoT networks and trends in required specifications. Figure 32 is an image diagram of factory automation. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0022] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0023] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0024] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0025] A transistor is a type of semiconductor element that can amplify current or voltage, and perform switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) or a TFT (Thin Film Transistor).

[0026] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0027] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0028] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided in the drawing (such as the surface to be formed, the supporting surface, the adhesive surface, or the flat surface) is located above the laminate, the direction toward that surface may be expressed as "down" and the opposite direction as "up."

[0029] Furthermore, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0030] (Embodiment 1) In this embodiment, a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention includes a memory string extending in a normal direction relative to a surface on which the memory string is formed. The memory string has a configuration in which a plurality of memory elements (also referred to as memory cells or memory elements) are connected in the normal direction. In other words, the memory device according to the present invention can be said to have a configuration in which a plurality of memory elements are stacked in the normal direction. Therefore, the amount of data per unit area can be increased, and a large capacity can be achieved.

[0031] A memory string 100 according to one embodiment of the present invention will be described with reference to the drawings. The memory string 100 is a semiconductor device that functions as a 3D-NAND memory device. Note that in the drawings, arrows indicating the X, Y, and Z directions may be added. The X, Y, and Z directions are directions that intersect with each other. More specifically, the X, Y, and Z directions are directions that are perpendicular to each other. In this specification and the like, one of the X, Y, and Z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining may be referred to as the "third direction" or "third direction." In this embodiment, the direction perpendicular to the top surface of the conductive layer 101 is defined as the Z direction.

[0032] [Memory string configuration example 1] FIG. 1A is a cross-sectional view of the memory string 100 as viewed from the Y direction. Note that FIG. 1A depicts a central axis 131 of the memory string 100 extending in the Z direction. FIG. 1B is an equivalent circuit diagram of the memory string 100. The memory string 100 has a configuration in which multiple transistors Tr are connected in series. FIG. 2A is a cross-sectional view of a portion A1-A2 indicated by a dashed line in FIG. 1A as viewed from the Z direction. FIG. 2B is a cross-sectional view of a portion B1-B2 indicated by a dashed line in FIG. 1A as viewed from the Z direction.

[0033] The memory string 100 includes a conductive layer 101, m insulating layers 102 (where m is an integer of 2 or greater), and n conductive layers 103 (where n is an integer of 2 or greater), all disposed above a substrate (not shown). The insulating layers 102 and the conductive layers 103 are alternately stacked above the substrate. In FIG. 1A and other figures, the first insulating layer 102 is referred to as insulating layer 102_1, and the m-th insulating layer 102 is referred to as insulating layer 102_m. Similarly, the first conductive layer 103 is referred to as conductive layer 103_1, and the n-th conductive layer 103 is referred to as conductive layer 103_n. In this embodiment and other figures, any insulating layer 102 is simply referred to as "insulating layer 102." Similarly, any conductive layer 103 is simply referred to as "conductive layer 103."

[0034] The insulating layer 102 and the conductive layer 103 extend in the Y direction. The memory string 100 has a structure in which the insulating layers 102 and the conductive layers 103 are alternately stacked. For example, in FIG. 1A , an insulating layer 102_1 is provided on the conductive layer 101, a conductive layer 103_1 is provided on the insulating layer 102_1, an insulating layer 102_2 is provided on the conductive layer 103_1, a conductive layer 103_2 is provided on the insulating layer 102_2, an insulating layer 102_3 is provided on the conductive layer 103_2, a conductive layer 103_3 is provided on the insulating layer 102_3, and an insulating layer 102_4 is provided on the conductive layer 103_3. Furthermore, an insulating layer 102_m is provided on the conductive layer 103_n.

[0035] The memory string 100 also includes a conductive layer 104, an insulating layer 105, a structure 110, and an insulating layer 121. The structure 110 extends along the Z direction. The structure 110 is provided between the conductive layer 101 and the conductive layer 104 so as to penetrate the insulating layers 102_1 to 102_m and the conductive layers 103_1 to 103_n. That is, the structure 110 has a portion located inside an opening provided in each of the insulating layers 102_1 to 102_m.

[0036] The structure 110 has a columnar structure including a conductive layer 106, an insulating layer 111, a semiconductor layer 112, a functional layer 114, and an insulating layer 115. Specifically, the conductive layer 106 extends along a central axis 131, and the insulating layer 111 is provided adjacent to a side surface of the conductive layer 106. The semiconductor layer 112 is provided adjacent to a side surface of the insulating layer 111. The functional layer 114 is provided adjacent to the semiconductor layer 112. The insulating layer 115 is provided adjacent to the functional layer 114. As shown in FIGS. 2A and 2B , the insulating layer 111, the semiconductor layer 112, the functional layer 114, and the insulating layer 115 are each provided concentrically outside the conductive layer 106.

[0037] The insulating layer 115 is provided along the upper and lower surfaces of the functional layer 114 and the side surface facing the conductive layer 103. Here, the upper and lower surfaces of the functional layer 114 refer to a pair of surfaces perpendicular to the Z direction. The side surface of the functional layer 114 refers to one or more surfaces parallel to the Z direction.

[0038] 2A and 2B show the case where the cross-sectional shape of the structure 110 is circular, but the cross-sectional shape of the structure 110 is not limited to a circle. The cross-sectional shape of the structure 110 may be an ellipse, a triangle, a rectangle, or a polygon with pentagons or more sides. In addition, the outline of the cross-sectional shape of the structure 110 may be a curve, or a combination of straight lines and curves.

[0039] The insulating layer 121 is provided to cover the side surfaces of the insulating layers 102_1 to 102_m and the conductive layers 103_1 to 103_n. The conductive layer 104 is provided over the insulating layer 102_m. The conductive layers 101 and 104 are electrically connected to the semiconductor layer 112. The conductive layer 101 is electrically connected to the conductive layer 106. Thus, the conductive layer 106 is electrically connected to the semiconductor layer 112. The insulating layer 105 is provided over the insulating layer 102_m, the insulating layer 121, and the conductive layer 104.

[0040] In a direction perpendicular to the Z direction, a region (intersection) where the structure 110 and the conductive layer 103 overlap functions as a transistor Tr. Therefore, in a direction perpendicular to the Z direction, a region (intersection) where the structure 110 and the conductive layer 103 overlap functions as a memory cell (also referred to as a "storage element").

[0041] The conductive layer 103 functions as the gate of the transistor Tr. The memory string 100 shown in FIG. 1A has n regions (intersections) where the structures 110 and the conductive layer 103 overlap. Therefore, the memory string 100 shown in FIG. 1A has n transistors Tr. Therefore, the memory string 100 shown in FIG. 1A has n memory cells. The conductive layer 106 can also function as a back gate of the transistor Tr. Note that the conductive layer 106 does not have to be provided if it is not necessary. In that case, it is sufficient to form the central axis 131 so as to be located inside the insulating layer 111.

[0042] FIG. 2A corresponds to a cross-sectional view of a transistor Tr in the memory string 100 when viewed from the Z direction.

[0043] 1A, the first transistor Tr is denoted as transistor Tr_1, and the nth transistor Tr is denoted as transistor Tr_n. In the present embodiment and the like, any transistor Tr is simply referred to as "transistor Tr."

[0044] Generally, a memory cell that stores data by retaining charges in a charge storage layer has a stacked structure of a block layer, a charge storage layer, a tunnel layer, and a semiconductor layer. Such a memory cell may be called by various names depending on the stacked structure from the control gate to the semiconductor layer. For example, if the control gate, block layer, charge storage layer, tunnel layer, and semiconductor layer are made of metal, oxide, nitride, oxide, or semiconductor, it is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

[0045] The transistor Tr according to one embodiment of the present invention functions as a memory cell. The memory string 100 functions as a NAND memory device having n memory cells.

[0046] The memory cell shown in FIG. 1A is an example of a memory cell that does not have the tunnel layer. The conductive layer 103 functions as the memory cell control gate. The functional layer 114 functions as a charge storage layer, and the insulating layer 115 functions as a block layer. In other words, the memory cell has a configuration in which the block layer is provided on the control gate side.

[0047] As shown in FIG. 1B, the gate of the transistor Tr is electrically connected to a wiring CG. In FIG. 1B, the wiring CG electrically connected to the gate of the transistor Tr_1 is shown as wiring CG_1. Note that a part or all of the conductive layer 103 may function as the wiring CG. Note that the wiring CG is also called a "control gate" or a "control gate wiring."

[0048] In addition, among the transistors Tr_2 to Tr_n-1, the source of one of the adjacent transistors Tr is electrically connected to the drain of the other transistor Tr.

[0049] One of the source or drain of the transistor Tr_1 is electrically connected to a wiring SL, and the other is electrically connected to one of the source or drain of the transistor Tr_2. One of the source or drain of the transistor Tr_n is electrically connected to a wiring BL, and the other is electrically connected to one of the source or drain of the transistor Tr_n-1. The conductive layer 101 is electrically connected to the wiring SL, and the conductive layer 104 is electrically connected to the wiring BL. Note that the conductive layer 101 may function as the wiring SL, and the conductive layer 104 may function as the wiring BL.

[0050] The back gates of the transistors Tr (transistors Tr_1 to Tr_n) are electrically connected to the wiring SL through the wiring BGL. Note that the conductive layer 106 can function as the wiring BGL.

[0051] The functional layer 114 preferably exhibits ferroelectricity, antiferroelectricity, or ferrielectricity, and more preferably exhibits ferroelectricity or ferrielectricity that exhibits spontaneous polarization.

[0052] When an electric field is applied to a dielectric, positively charged and negatively charged areas are generated inside the dielectric. This phenomenon is called "polarization." A dielectric whose polarization disappears when the electric field is removed is called a "paraelectric," while a dielectric whose polarization remains even when the electric field is removed is called a "ferroelectric." The property of remaining polarization even when the electric field is removed is called "ferroelectricity." Polarization that remains even when the electric field is removed is called spontaneous polarization.

[0053] In this specification, a dielectric that generates spontaneous polarization is broadly referred to as a ferroelectric. Therefore, unless otherwise specified, in this specification, a dielectric that exhibits ferrielectricity (ferrielectric) is also included in the ferroelectric in a broad sense.

[0054] A material capable of exhibiting ferroelectricity is used as the functional layer 114. Examples of materials capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and hafnium oxide to which an element J1 (element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) has been added.

[0055] The functional layer 114 is made of PbTiO X (X is a real number greater than 0), piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate may also be used.

[0056] Alternatively, the functional layer 114 may be made of an organic ferroelectric material such as polyvinylidene fluoride (also called "PVDF") or a copolymer of vinylidene fluoride (also called "VDF") and trifluoroethylene (also called "TrFE").

[0057] The ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the functional layer 114 may have a layered structure made of multiple materials selected from the materials listed above.

[0058] Among these, hafnium oxide (HfO) is one of the materials that can exhibit ferroelectricity. X ", or "HO"), or materials with hafnium oxide and zirconium oxide ("HfZrO X HO or HZO is preferred because it can exhibit ferroelectricity even when processed into a thin film of a few nanometers. By using HO or HZO, the film thickness of the functional layer 114 can be set to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0059] In addition, HfZrO is a material that can exhibit ferroelectricity. XWhen using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can exhibit ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called hydrocarbon, HC) as a precursor. If the material that can exhibit ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can exhibit ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can exhibit ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, materials that can exhibit ferroelectricity include materials containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0060] When a film is formed using a material that can exhibit ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0061] The impurity concentration of the material capable of exhibiting ferroelectricity is preferably low. In particular, the concentration of hydrogen (H) and carbon (C) is preferably low. Specifically, the hydrogen concentration of the material capable of exhibiting ferroelectricity is preferably 5×10 20 atoms / cm 3 Less than 1×10 is preferred 20 atoms / cm 3 The carbon concentration of the material capable of exhibiting ferroelectricity is preferably 5×10 19 atoms / cm 3 Less than 1×10 is preferred 19 atoms / cm 3The following is more preferable. On the other hand, a dopant (typically silicon, carbon, etc.) for controlling the polarization state may be added to a material that can exhibit ferroelectricity. In this case, one method for adding carbon as a dopant may be to use a formation method using a material containing hydrocarbon as a precursor.

[0062] In addition, HfZrO is a material that can exhibit ferroelectricity. X When using hafnium oxide and zirconium oxide, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0063] Furthermore, the crystal structure of the material capable of exhibiting ferroelectricity is not particularly limited. For example, the crystal structure of the material capable of exhibiting ferroelectricity may be one or more selected from the group consisting of tetragonal, orthorhombic, and monoclinic. In particular, the material capable of exhibiting ferroelectricity preferably has an orthorhombic crystal structure, since ferroelectricity is expressed therein. Alternatively, the material capable of exhibiting ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0064] The crystal structure of a material that can exhibit ferroelectricity may be any crystal structure that does not have centrosymmetrical structure and can exhibit polarity, and therefore is not limited to an orthorhombic system and may be a crystal system other than a cubic system.

[0065] In the present embodiment and other cases, a layer formed of a material capable of exhibiting ferroelectricity is also referred to as a "ferroelectric layer." A ferroelectric layer has hysteresis characteristics. FIG. 3 is a graph showing an example of hysteresis characteristics. The hysteresis characteristics can be measured using a capacitance element using a ferroelectric layer as a dielectric. In FIG. 3, the horizontal axis represents the voltage (electric field) applied to the ferroelectric layer. This voltage is the potential difference between one electrode and the other electrode of a capacitance element using a ferroelectric layer as a dielectric. The electric field strength can be calculated by dividing this potential difference by the thickness of the ferroelectric layer.

[0066] In Figure 3, the vertical axis represents the polarization of the ferroelectric layer. When the polarization is positive, it indicates that the positive charges in the ferroelectric layer are biased toward one electrode of the capacitance element, and the negative charges are biased toward the other electrode of the capacitance element. On the other hand, when the polarization is negative, it indicates that the negative charges in the ferroelectric layer are biased toward one electrode of the capacitance element, and the positive charges are biased toward the other electrode of the capacitance element.

[0067] In addition, the polarization shown on the vertical axis of the graph in Figure 3 may be positive when negative charges are biased toward one electrode of the capacitance element and positive charges are biased toward the other electrode of the capacitance element, and negative when positive charges are biased toward one electrode of the capacitance element and negative charges are biased toward the other electrode of the capacitance element.

[0068] 3, the hysteresis characteristics of the ferroelectric layer can be represented by a curve 51 and a curve 52. The voltages at the two intersections of the curve 51 and the curve 52 are called the saturation polarization voltage VSP and the saturation polarization voltage −VSP, respectively.

[0069] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 51. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 52. Note that VSP is sometimes called the "positive saturation polarization voltage" or "first saturation polarization voltage," and -VSP is sometimes called the "negative saturation polarization voltage" or "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0070] Here, when the polarization of the ferroelectric layer changes according to curve 51, the voltage at which the polarization becomes zero is called the coercive voltage Vc. Also, when the polarization of the ferroelectric layer changes according to curve 52, the voltage at which the polarization becomes zero is called the coercive voltage -Vc. The values ​​of Vc and -Vc are between -VSP and VSP. Note that Vc may also be called the "positive coercive voltage" or "first coercive voltage," and -Vc may also be called the "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0071] Furthermore, when a voltage exceeding the coercive voltage is applied to the ferroelectric layer, the polarization of the ferroelectric layer is likely to be reversed. In a ferroelectric transistor (FeFET: Ferroelectric FET), if you do not want to reverse the polarization of the ferroelectric layer that functions as a gate insulating layer, you can simply set the voltage applied between the gate and source (also called "gate voltage" or "Vg") to be between -Vc and Vc. The larger the absolute value of the coercive voltage, the better.

[0072] Therefore, the difference between the threshold voltage VthD of a normally-on transistor made by utilizing polarization inversion and the threshold voltage VthE of a normally-off transistor is equal to or greater than −Vc and equal to or less than Vc.

[0073] Furthermore, when no voltage is applied to the ferroelectric layer (when the voltage is 0V), the maximum value of polarization is called the "remanent polarization Pr" and the minimum value is called the "remanent polarization -Pr." Furthermore, the absolute value of the difference between the remanent polarization Pr and the remanent polarization -Pr is called the "remanent polarization 2Pr." The larger the remanent polarization 2Pr, the greater the fluctuation range of the threshold voltage due to polarization reversal. Therefore, the larger the remanent polarization 2Pr, the more preferable it is.

[0074] The transistors Tr that make up the memory string 100 function as ferroelectric transistors. A ferroelectric transistor is a transistor that uses a ferroelectric material for the insulating layer that functions as the gate insulating layer. A ferroelectric transistor can change its threshold voltage by applying a voltage above a certain level to the gate.

[0075] A NAND-type ferroelectric memory can be realized by using ferroelectric transistors as the transistors Tr that make up the memory string 100. In addition, in the memory string 100, the conductive layer 106 may be omitted.

[0076] The semiconductor layer 112 of the transistor Tr can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0077] The semiconductor layer 112 may be a semiconductor with improved crystallinity using a catalytic element, which may be an element selected from metal elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge).

[0078] For example, amorphous silicon may be formed as the semiconductor layer 112, nickel may be added as a catalytic element, and heat treatment may be performed to enhance crystallinity. The catalytic element bonds with silicon to form silicide. The catalytic element also tends to bond with amorphous silicon and other regions with many defects. Therefore, the catalytic element contained in the silicide reacts with amorphous silicon to form new silicide. In this way, crystallization progresses as the silicide moves. Furthermore, by allowing the catalytic element to reach a semiconductor containing an impurity element such as a Group 15 element or a Group 13 element, re-diffusion of the catalytic element can be suppressed.

[0079] Furthermore, when nickel is added as a catalytic element to the semiconductor layer 112, a concentration gradient of the nickel element may occur in the semiconductor layer 112. For example, the nickel concentration may be lower in the region that functions as the channel of the transistor than in other regions (e.g., the source region and the drain region). In other words, the nickel concentration may be higher in the source region and the drain region than in the region that functions as the channel.

[0080] The semiconductor layer 112 functions as a semiconductor layer in which a channel of the transistor Tr is formed. The semiconductor layers used in the transistor Tr may be stacked. When stacking the semiconductor layers, semiconductor materials having different crystalline states may be used for each layer, or different semiconductor materials may be used for each layer.

[0081] The transistor Tr is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly small off-state current. Therefore, the power consumption of the memory string 100 can be reduced. Therefore, the power consumption of a semiconductor device including the memory string 100 can be reduced.

[0082] Furthermore, a memory cell including an OS transistor can be called an “OS memory.” Furthermore, a memory string 100 including the memory cell can also be called an “OS memory.”

[0083] Furthermore, an OS transistor can have a smaller on-resistance than a transistor that uses polycrystalline silicon for the semiconductor layer in which the channel is formed. That is, the conductivity of the body can be increased. By using an OS transistor for the transistor Tr, the operating speed of the memory string 100 can be increased. Note that the body here refers to the channel of the transistor that constitutes the memory string or the semiconductor layer (e.g., the semiconductor layer 112) that functions as the source / drain.

[0084] Furthermore, while polycrystalline silicon transistors exhibit variations in threshold voltage due to grain boundaries, OS transistors are less affected by grain boundaries and exhibit smaller variations in threshold voltage. Therefore, by using OS transistors for the transistors Tr, the memory string 100 can suppress malfunctions due to variations in threshold voltage.

[0085] Furthermore, OS transistors operate stably even in high-temperature environments, with little fluctuation in their characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in ambient temperatures above room temperature and below 200°C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Therefore, the memory string 100 including the OS memory operates stably even in high-temperature environments, and high reliability is achieved. Furthermore, OS transistors have a high dielectric strength voltage between the source and drain. By using OS transistors as the transistors constituting the memory string 100, a memory string 100 with stable operation and good reliability can be realized, even in high-temperature environments. Therefore, the reliability of a semiconductor device including the memory string 100 can be improved.

[0086] A NAND type storage device including an OS memory can also be called an "OS NAND type" or an "OS NAND type storage device." Furthermore, a 3D-NAND type storage device including an OS memory can also be called a "3D OS NAND type" or a "3D OS NAND type storage device." Therefore, the memory string 100 according to one embodiment of the present invention can be said to be a 3D OS NAND type storage device.

[0087] Furthermore, if it is desired to increase the storage capacity of a semiconductor device using memory strings 100, multiple memory strings 100 may be arranged in a lattice pattern (see FIG. 4A) or a houndstooth pattern (see FIG. 4B). Figures 4A and 4B are cross-sectional views corresponding to Figure 2A.

[0088] [Variation 1] Below, an example of the configuration of a memory string that is partially different from the configuration described above will be described.

[0089] [Variation 1-1] FIG. 5A shows a cross-sectional view of a portion of a memory string.

[0090] The configuration shown in FIG. 5A differs from the configuration illustrated in FIG. 1A mainly in that an insulating layer 116 is provided.

[0091] The insulating layer 116 is provided between the functional layer 114 and the semiconductor layer 112. The insulating layer 116 is also arranged concentrically with the conductive layer 106 at the center.

[0092] The insulating layer 116 is preferably made of, for example, a nitride. For example, a nitride such as silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, hafnium nitride, or hafnium nitride oxide is preferably used. In particular, it is preferable to use silicon nitride or silicon nitride oxide, which are nitrides of silicon.

[0093] Note that the insulating layer 116 is not limited to nitride, and an insulating material other than nitride can also be used. For example, oxides such as silicon oxide, silicon oxynitride, aluminum oxide, and aluminum oxynitride may be used.

[0094] By providing the insulating layer 116, leakage current flowing from the conductive layer 103 to the semiconductor layer 112 can be reduced, thereby reducing power consumption when the memory cell is driven.

[0095] [Variation 1-2] The configuration shown in FIG. 5B differs from the configuration illustrated in FIG. 1A mainly in that it does not have insulating layer 115.

[0096] 5B, the upper and lower surfaces of the functional layer 114 are provided in contact with the insulating layer 102. The side surfaces of the functional layer 114 are provided in contact with the conductive layer 103.

[0097] The absence of the insulating layer 115 makes it possible to increase the electric field strength applied to the functional layer 114 when a voltage is applied between the conductive layer 103 and the semiconductor layer 112. This is preferable because it allows the voltage for driving the memory cell to be lowered.

[0098] [Variation 1-3] The configuration shown in Fig. 5C is a configuration in which the insulating layer 116 illustrated in Fig. 5A is added to the configuration illustrated in Fig. 5B. With such a configuration, the leakage current of the memory cell can be reduced.

[0099] [Memory string configuration example 2] Fig. 6A shows a cross-sectional view of the memory string 100A, and Fig. 6B is an equivalent circuit diagram of the memory string 100A.

[0100] The memory string 100A has a structure 110A instead of the structure 110. The structure 110A has a conductive layer 141 and an insulating layer 142 instead of the conductive layer 106, the insulating layer 111, and the semiconductor layer 112 that the structure 110 has. In addition, the central axis 131 passes through the insulating layer 142.

[0101] The conductive layer 141 is provided adjacent to the side surface of the insulating layer 142. The conductive layer 141 is provided concentrically around the outer surface of the insulating layer 142.

[0102] In the direction perpendicular to the Z direction, the region (intersection) where the structural body 110A and the conductive layer 103 overlap functions as a memory element FTJ. In the example shown in Figures 6A and 6B, the memory string 100A has n memory elements FTJ stacked.

[0103] Functional layer 114 is sandwiched between conductive layer 141 and conductive layer 103. Insulating layer 115 is provided between functional layer 114 and conductive layer 103. Therefore, it can be said that memory element FTJ has a MFIM (Metal Ferroelectrics Insulator Metal) structure.

[0104] Various conductive materials can be used for the conductive layer 141. For example, a conductive film such as a metal film, an alloy film, a conductive oxide film, or a conductive nitride film can be used as a single layer or a stacked layer.

[0105] As the conductive oxide film, metal oxides such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide can also be used.

[0106] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0107] The FTJ memory element functions as a ferroelectric tunnel junction (FTJ) memory. FTJ memory is a nonvolatile memory element (ferroelectric memory) that utilizes a tunnel junction and is fabricated using a capacitive element (ferroelectric capacitor) with at least a ferroelectric layer. FTJ memory has features such as a small footprint, high-speed operation, and nondestructive readout. Furthermore, FTJ memory utilizes a tunnel junction, and has an element configuration that functions as both a capacitor and a diode, allowing for high density. This allows for the realization of a memory device with a large memory capacity. FTJ memory can also be said to have a tunnel junction element with a ferroelectric layer.

[0108] FTJ memory is a memory element that utilizes the difference in the current flowing between a pair of electrodes depending on the direction of spontaneous polarization of a ferroelectric material. Therefore, FTJ memory can also be called a resistance change memory.

[0109] [Variation 2] Below, a configuration example that is partially different from the configuration of the memory string 100A will be described.

[0110] [Variation 2-1] FIG. 7A shows a cross-sectional view of a portion of a memory string.

[0111] The configuration shown in Fig. 7A is an example in which an insulating layer 116 is applied to the configuration illustrated in Fig. 6A. For the insulating layer 116, the above-mentioned modified example 1-1 can be applied.

[0112] The insulating layer 116 can reduce leakage current flowing from the conductive layer 103 to the conductive layer 141, thereby reducing power consumption when the memory cell is driven.

[0113] [Variation 2-2] The configuration shown in FIG. 7B differs from the configuration illustrated in FIG. 6A mainly in that it does not have insulating layer 115.

[0114] By not providing the insulating layer 115, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the manufacturing yield can be improved.

[0115] In the case of the configuration shown in FIG. 7B, it is preferable to select and use conductive materials having different ladder functions for conductive layer 103 and conductive layer 141.

[0116] [Variation 2-3] The configuration shown in Fig. 7C is a configuration in which the insulating layer 116 illustrated in Fig. 7A is added to the configuration illustrated in Fig. 7B. With such a configuration, the leakage current of the memory cell can be reduced.

[0117] [Memory string manufacturing method example] An example of a method for manufacturing a memory string according to one embodiment of the present invention will be described below, taking the memory string 100 illustrated in FIG. 1A as an example.

[0118] 8A, a laminate is produced by laminating insulating layers 102 and conductive layers 103. An i-th (i is an integer of 1 or more) insulating layer 102_i is disposed above a substrate (not shown), and a conductive layer 103_i is laminated above it.

[0119] The insulating layer 102 is preferably made of a material with a reduced concentration of impurities such as water or hydrogen. For example, the amount of hydrogen molecules desorbed per unit area of ​​the insulating layer 102 is 2×10 in the temperature range of 50° C. to 500° C., as measured by thermal desorption spectroscopy (TDS). 15 molecules / cm 2 Less than 1 × 10 15 molecules / cm 2 Less than or equal to 5 × 10 14 molecules / cm 2 The insulating layer 102 may be an insulating layer from which oxygen is released by heating. However, materials that can be used for the insulating layer 102 are not limited to those described above.

[0120] Note that the insulating layer 102 may have a stacked structure of multiple insulating layers. For example, the insulating layer 102 may be a stacked structure of hafnium oxide and silicon oxynitride. Alternatively, the insulating layer 102 may be a stacked structure of silicon oxide and silicon nitride. Of the multiple insulating layers constituting the insulating layer 102, an insulating layer that is in contact with the conductive layer 103 is preferably an insulating layer that has a function of suppressing oxygen permeation.

[0121] Next, a resist mask is formed over the stack, and openings 145 are formed in the insulating layer 102 and the conductive layer 103 by etching using the resist mask (see FIG. 8B).

[0122] The resist mask can be formed by, for example, lithography, printing, inkjet printing, or the like, as appropriate. When the resist mask is formed by the inkjet printing, a photomask is not used, which may reduce the manufacturing cost. Furthermore, the etching process may be a dry etching process, a wet etching process, or both. Processing by the dry etching process is suitable for fine processing.

[0123] In forming a resist mask by lithography, a resist is first formed, and then the resist is exposed to light through a photomask. The exposed region is then removed or left using a developer to form a resist mask.

[0124] Conductive layers, semiconductor layers, insulating layers, etc. can be processed into desired shapes by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Immersion technology can also be used, in which exposure is performed by filling a liquid (e.g., water) between the substrate and the projection lens. Instead of the light described above, a beam such as an electron beam or an ion beam can also be used. Note that when a beam such as an electron beam or an ion beam is used, a photomask is not required. Note that the resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0125] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched, whereby a hard mask having a desired shape can be formed.

[0126] As a dry etching apparatus for performing an etching process using the dry etching method, for example, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0127] Next, a portion of conductive layer 103 exposed on the side surface of opening 145 is etched to recess conductive layer 103 from the side surface of opening 145 (see FIG. 9A). Etching of conductive layer 103 may be performed under conditions that provide a selectivity with respect to insulating layer 102.

[0128] The conductive layer 103 can be etched by an isotropic etching method. For example, wet etching or isotropic plasma etching can be used. In particular, wet etching is preferably used.

[0129] Next, an insulating layer 115 is formed along the side surface of the opening 145 (see FIG. 9B). The surfaces of the insulating layer 102 and the conductive layer 103 exposed in the opening 145 are covered with the insulating layer 115. The insulating layer 115 can be made of any of the insulating materials described above, such as silicon nitride or silicon oxide. In particular, it is preferable to use silicon nitride. The insulating layer 115 may have a stacked structure of multiple insulating layers.

[0130] Next, the functional layer 114 is formed along the surface of the insulating layer 115 (see FIG. 10A). The functional layer 114 is formed so as to fill in the recesses in the upper surface of the insulating layer 115.

[0131] The insulating layer 115 and the functional layer 114 are preferably formed using a film formation method with high coverage. For example, it is preferable to form them using the ALD method. In particular, by forming them using the thermal ALD method, not only can the insulating layer 115 and the functional layer 114 be formed with high coverage, but also impurities contained in the insulating layer 115 and the functional layer 114 can be effectively reduced.

[0132] Next, the insulating layer 115 and the functional layer 114 are partially etched within the opening 145. The insulating layer 115 and the functional layer 114 are etched except for the portions that overlap with the insulating layer 102 when viewed from the Z direction (see FIG. 10B).

[0133] 10B, the inner wall of the opening 145 is formed by the side surfaces of the insulating layer 102, the insulating layer 115, and the functional layer 114. At this time, it is preferable to perform etching so as not to create steps between the surfaces of the insulating layer 102, the insulating layer 115, and the functional layer 114. This makes it possible to flatten the surface on which the semiconductor layer 112 or the like to be formed later will be formed, thereby suppressing the generation of defects in the film of the semiconductor layer 112 or the like.

[0134] Next, the semiconductor layer 112 is formed along the inner wall of the opening 145 (see FIG. 11A). Here, the semiconductor layer 112 is made of an oxide semiconductor.

[0135] The semiconductor material used for the semiconductor layer 112 may be, for example, a metal oxide having a composition of In:Ga:Zn=4:2:3, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these. Alternatively, the semiconductor material used for the semiconductor layer 112 may be a metal oxide having a composition of In:Zn=5:1 or In:Zn=10:1, or a composition close to these. Alternatively, indium oxide may be used for the semiconductor layer 112.

[0136] Alternatively, the semiconductor layer 112 may have a multi-layer structure. For example, the semiconductor layer 112 may be a stack of a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition close to these, and a metal oxide having a composition of In:Ga:Zn=4:2:3, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these.

[0137] Alternatively, the semiconductor layer 112 may have a three-layer structure in which a metal oxide having a composition of In:Ga:Zn=4:2:3, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these, is sandwiched between two layers of metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition close to these.

[0138] In addition, in the manufacturing process of the memory cell, it is preferable to perform heat treatment while the surface of the semiconductor layer 112 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the semiconductor layer 112, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0139] By performing a treatment for supplying oxygen to the semiconductor layer 112 (also referred to as an “oxygen addition treatment”), oxygen vacancies in the semiconductor layer 112 are repaired by the supplied oxygen. In other words, “V O +O→null reaction can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the semiconductor layer 112, and the hydrogen can be removed as HO (dehydration). As a result, the hydrogen remaining in the semiconductor layer 112 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0140] Alternatively, the oxygen-adding treatment can be performed by microwave treatment in an oxygen-containing atmosphere. In this case, the semiconductor layer 112 is irradiated with microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, or the like. For the microwave treatment, a microwave treatment device having a power source for generating high-density plasma using microwaves is preferably used. The microwave treatment device may also have a power source for applying RF to the substrate side. Using high-density plasma can generate high-density oxygen radicals. Applying RF to the substrate (not shown) can efficiently guide oxygen ions generated by the high-density plasma into the opening 145. The microwave treatment is preferably performed under reduced pressure, with a pressure of 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and even more preferably 400 Pa or higher. The oxygen flow ratio O2 / (O2+Ar) is preferably 50% or lower, and more preferably 10% to 30%. The treatment temperature is preferably 750°C or lower, preferably 500°C or lower, for example, approximately 400°C. Furthermore, after the oxygen plasma treatment, a heat treatment may be carried out successively without exposure to the outside air.

[0141] The V contained in the semiconductor layer 112 is oxidized by the action of plasma, microwaves, etc. O H can be split off, and hydrogen H can be removed from the semiconductor layer 112. That is, in the semiconductor layer 112, O H → H + V O )" and "V O +O→null” reaction occurs, and the hydrogen concentration in the semiconductor layer 112 can be reduced. O H can be reduced to lower the carrier concentration.

[0142] Subsequently, an insulating layer 111 is formed along the side surface of the semiconductor layer 112 (see FIG. 11B). For example, silicon oxide, silicon oxynitride, or the like may be used as the insulating layer 111. By providing an insulating layer containing oxygen in contact with the semiconductor layer 112, oxygen vacancies in the semiconductor layer 112 can be reduced, and the reliability of the transistor can be improved. Furthermore, oxygen addition treatment may be performed after the insulating layer 111 is formed.

[0143] Subsequently, the conductive layer 106 is formed along the side surface of the insulating layer 111 (see FIG. 12A). The conductive layer 106 is preferably formed so as to fill the opening 145.

[0144] In this manner, the semiconductor layer 112, the insulating layer 111, and the conductive layer 106 of the structure body 110 can be embedded inside the opening 145.

[0145] Next, a portion of the laminate is removed in a region that does not overlap with the structure 110 when viewed from the Z direction to form a region 132 (see FIG. 12B). The region 132 can be formed in a manner similar to that for the opening 145. In the region 132, the side surfaces of the insulating layer 102 and the conductive layer 103 are exposed. When viewed from the Z direction, the region 132 is preferably in the shape of a strip extending in the X or Y direction. Alternatively, the region 132 may be in the shape of a grid extending in the X and Y directions.

[0146] Subsequently, an insulating layer 121 is formed to fill the region 132 (see FIG. 13). For example, an insulating material that has a function of suppressing permeation of impurities such as water and hydrogen is preferably used for the insulating layer 121. For example, aluminum oxide or the like may be used for the insulating layer 121.

[0147] Note that the insulating layer 121 may have a stacked structure of multiple insulating layers. For example, the insulating layer 121 may be a stacked structure of hafnium oxide and silicon oxynitride. Of the multiple insulating layers constituting the insulating layer 121, an insulating layer in contact with the conductive layer 103 preferably has a function of suppressing oxygen permeation.

[0148] In this manner, the memory string 100 can be fabricated.

[0149] [Memory string configuration example 3] An example of a memory string having a configuration that is partially different from that described above will be described below.

[0150] [Configuration Example 3-1] Fig. 14A shows a cross-sectional view of a portion of the configuration of a memory string 100B, which will be described below as an example, and Fig. 14B shows an equivalent circuit diagram corresponding to Fig. 14A.

[0151] The memory string 100B has a plurality of memory cells 150 stacked in the Z direction with an insulating layer 102 interposed therebetween. The memory cell 150 has a transistor 151 and a capacitor 152.

[0152] The memory cell 150 has a configuration (also written as 1Tr1C) that includes one transistor 151 and one capacitor 152. The capacitor 152 is a ferroelectric capacitor using a ferroelectric substance. One memory cell 150 can also be called an FeRAM (Ferroelectric Random Access Memory).

[0153] The memory string 100B includes a conductive layer 106, an insulating layer 111, a semiconductor layer 112, a conductive layer 103a, a conductive layer 103b, a functional layer 114, an insulating layer 116, an insulating layer 117, and the like.

[0154] The transistor 151 includes a conductive layer 103 a, an insulating layer 117 , a semiconductor layer 112 , an insulating layer 111 , and a conductive layer 106 .

[0155] The transistor 151 has a pair of gates sandwiching a semiconductor layer 112. The conductive layer 103a functions as one of the gates, and the conductive layer 106 functions as the other gate. The insulating layer 117 functions as one of the gate insulating layers, and the insulating layer 111 functions as the other gate insulating layer.

[0156] The capacitor 152 includes a conductive layer 103 b , a functional layer 114 , and a semiconductor layer 112 .

[0157] The capacitor 152 has a configuration in which the functional layer 114 is sandwiched between the conductive layer 103b and the semiconductor layer 112. The conductive layer 103b functions as one electrode, and the semiconductor layer 112 functions as the other electrode.

[0158] A region of the semiconductor layer 112 in contact with the insulating layer 117 functions as a channel formation region (denoted as I) of the transistor 151. A portion of the semiconductor layer 112 other than the channel formation region is a low-resistance region (N + It is preferable that the

[0159] For example, by using an oxide insulating film (preferably a silicon oxide film) that releases oxygen when heated as the insulating layer 117 in contact with the semiconductor layer 112, oxygen is supplied from the insulating layer 117 to the semiconductor layer 112 by heat during the manufacturing process, and oxygen vacancies in the semiconductor layer 112 are filled, so that a high-resistance channel formation region can be selectively formed in the semiconductor layer 112.

[0160] The conductive layer 103a and the insulating layer 117 are sandwiched between a pair of insulating layers 116. The conductive layer 103b and the functional layer 114 are sandwiched between a pair of insulating layers 116. An insulating layer 102 is provided between two adjacent insulating layers 116.

[0161] An opening is provided in each insulating layer 102 and each insulating layer 116. Inside these openings, a semiconductor layer 112, an insulating layer 111, and a conductive layer 106 are provided.

[0162] It is preferable to use insulating films containing different materials for the insulating layer 116 and the insulating layer 102. In this case, it is preferable to use an insulating nitride film for the insulating layer 116 and an insulating oxide film for the insulating layer 102.

[0163] FIG. 14A shows an example in which the conductive layer 103a and the conductive layer 103b each extend in the Y direction. Preferably, different conductive films are used for the conductive layer 103a and the conductive layer 103b. This allows the transistor 151 and the capacitor 152 to be separately formed. For example, first, etching is performed to recess the side surface of the conductive layer 103a, forming the insulating layer 117. Next, etching is performed to recess the side surface of the conductive layer 103b, forming the functional layer 114. Thereafter, the semiconductor layer 112, the insulating layer 111, and the conductive layer 106 are formed, allowing the transistor 151 and the capacitor 152 to be separately formed. Note that etching to recess the side surface of the conductive layer 103b may be performed first.

[0164] [Configuration Example 3-2] Fig. 15A shows a cross-sectional view of a portion of the configuration of a memory string 100C, which will be described below as an example, and Fig. 15B shows an equivalent circuit diagram corresponding to Fig. 15A.

[0165] The memory string 100C has a plurality of transistors 160 stacked in the Z direction with an insulating layer 116 and an insulating layer 118 interposed therebetween.

[0166] The transistor 160 has a ferroelectric applied to the gate insulating layer, and can also be called a ferroelectric transistor (FeFET).

[0167] The memory string 100C includes a conductive layer 106, an insulating layer 111, a semiconductor layer 112, a functional layer 114, a conductive layer 103, an insulating layer 116, an insulating layer 118, and the like.

[0168] The transistor 160 includes a conductive layer 103, a functional layer 114, a semiconductor layer 112, an insulating layer 111, and a conductive layer 106. The conductive layer 103 functions as one gate, and the conductive layer 106 functions as the other gate. The functional layer 114 has ferroelectricity and functions as one gate insulating layer. The insulating layer 111 functions as the other gate insulating layer.

[0169] The conductive layer 103 and the functional layer 114 are sandwiched between a pair of insulating layers 116. Between a pair of conductive layers 103 adjacent to each other in the Z direction and between a pair of functional layers 114, there are regions where the insulating layers 116 and the insulating layers 118 are alternately stacked.

[0170] A portion of the semiconductor layer 112 is provided in contact with the side surfaces of the insulating layers 116 and 118 in a region where the insulating layers 116 and 118 are alternately stacked. Here, it is preferable to use materials with different linear thermal expansion coefficients for the insulating layers 116 and 118. In this way, by providing the semiconductor layer 112 in contact with two types of insulating layers exhibiting different linear thermal expansion coefficients, different stresses are applied to the semiconductor layer 112 in the portion in contact with the insulating layer 116 and the portion in contact with the insulating layer 118 due to heat (typically heat of 200°C or higher and 500°C or lower) applied during the manufacturing process. As a result, strain energy is applied to the semiconductor layer 112 due to the different stresses, strain occurs in the semiconductor layer 112, and carrier conductivity increases. That is, a low-resistance region 161 (N + ) can be formed.

[0171] For example, it is preferable to use a nitride insulating film for the insulating layer 116 and an oxide insulating film for the insulating layer 118. For example, silicon nitride can be used for the insulating layer 116 and silicon oxide can be used for the insulating layer 118. Note that the stacking order of the insulating layer 116 and the insulating layer 118 is not limited to this and may be reversed. Furthermore, three or more insulating layers with different linear thermal expansion coefficients may be stacked.

[0172] On the other hand, a portion (denoted as I) that functions as a channel formation region of the transistor 160 is sandwiched between the functional layer 114 and the insulating layer 111. Here, by using an oxide insulating film (preferably a silicon oxide film) that releases oxygen when heated as the insulating layer 111, oxygen is supplied from the insulating layer 111 to the semiconductor layer 112 by heat during the manufacturing process, and oxygen vacancies in the semiconductor layer 112 are filled, so that a high-resistance channel formation region can be selectively formed in the semiconductor layer 112.

[0173] An opening is provided in each of the insulating layers 116 and 118. Inside the openings, the semiconductor layer 112, the insulating layer 111, and the conductive layer 106 are provided.

[0174] [Configuration Example 3-3] Fig. 16A shows a cross-sectional view of a portion of the configuration of a memory string 100D, which will be described below as an example, and Fig. 16B shows an equivalent circuit diagram corresponding to Fig. 15A.

[0175] The memory string 100D has a plurality of memory elements 170 stacked in the Z direction with insulating layers 102 interposed therebetween.

[0176] The memory element 170 has a configuration in which a ferroelectric and an insulating layer 116 are sandwiched between a pair of electrodes. The memory element 170 can also be called a ferroelectric tunnel junction (FTJ) memory.

[0177] The memory string 100D includes a conductive layer 103, a functional layer 114, an insulating layer 116, a conductive layer 141, and an insulating layer 142. The insulating layer 142 may not be provided if it is not necessary. In that case, the memory string 100D may be formed so that the central axis 131 is located inside the conductive layer 141.

[0178] The memory element 170 includes a conductive layer 103, a functional layer 114, an insulating layer 116, and a conductive layer 141. The conductive layer 103 functions as one electrode, and the conductive layer 141 functions as the other electrode. The conductive layer 103 corresponds to a part of the wiring ME1 in FIG. 16B, and the conductive layer 141 corresponds to a part of the wiring ME2.

[0179] In the memory element 170, the conductive layer 103 and the conductive layer 141 can be formed using the same conductive material. Note that different conductive materials may also be used for these layers.

[0180] The description of the above modification 1-1 can be applied to the insulating layer 116. For example, it is preferable to use silicon nitride or silicon nitride oxide as the insulating layer 116.

[0181] The conductive layer 103 and the functional layer 114 are sandwiched between a pair of insulating layers 102. One or more insulating layers 102 are provided between adjacent pairs of conductive layers 103 and between adjacent functional layers 114. The insulating layer 102 may be a single layer or a laminated film.

[0182] An opening is provided in each insulating layer 102. Inside the openings, an insulating layer 116, a conductive layer 141, and an insulating layer 142 are provided.

[0183] This concludes the description of memory string configuration example 3.

[0184] [Memory cell constituent materials] Next, constituent materials that can be used for the memory string 100 and the like will be described.

[0185] 〔substrate〕 The memory string 100 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride (GaN). Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductor substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0186] [Insulating layer] The insulating layer may be made of an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like.

[0187] For example, as transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using high-k materials for the insulating layer that functions as the gate insulating layer makes it possible to lower the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulating layer.

[0188] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0189] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0190] Furthermore, the electrical characteristics of an OS transistor can be stabilized by surrounding it with an insulating layer that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. The insulating layer that has a function of suppressing the permeation of impurities such as hydrogen and oxygen can be, for example, a single-layer or stacked insulating film containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities such as hydrogen and oxygen can be a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0191] In this specification, for example, silicon oxynitride refers to a silicon compound containing more oxygen than nitrogen, silicon nitride oxide refers to a silicon compound containing more nitrogen than oxygen, aluminum oxynitride refers to an aluminum compound containing more oxygen than nitrogen, and aluminum nitride oxide refers to an aluminum compound containing more nitrogen than oxygen.

[0192] When an oxide semiconductor is used for the semiconductor layer 112, an insulating layer adjacent to the semiconductor layer 112 is preferably an insulating layer having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor layer 112, oxygen vacancies in the semiconductor layer 112 can be compensated for.

[0193] Further, the insulating layer may be a single layer of an insulating film made of the above-mentioned material, or a plurality of insulating layers made of the above-mentioned material may be stacked.

[0194] For example, when an insulating layer is provided in contact with a conductive layer, an insulating layer having a function of suppressing oxygen permeation may be used as the insulating layer to prevent oxidation of the conductive layer, and examples of the insulating layer include hafnium oxide, aluminum oxide, and silicon nitride.

[0195] In addition, when an insulating layer is stacked adjacent to a conductive layer, it is preferable to use an insulating layer having a function of suppressing oxygen permeation as the insulating layer in contact with the conductive layer. For example, an insulating layer in contact with the conductive layer may be formed using hafnium oxide, and an insulating layer in contact with the insulating layer may be formed using silicon oxynitride.

[0196] [Conductive Layer] The conductive layer is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0197] Furthermore, a single conductive layer formed from the above-mentioned material may be used as the conductive layer, or multiple conductive layers formed from the above-mentioned material may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0198] [Oxide Semiconductor] An oxide semiconductor, which is a type of metal oxide, is preferably used for the semiconductor layer 112. An oxide semiconductor that can be used for an OS transistor will be described below.

[0199] The oxide semiconductor preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0200] Here, we consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, element M, and zinc. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, element M may be a combination of multiple of the aforementioned elements. Representative examples of In-M-Zn oxides include In-Ga-Zn oxide (also known as IGZO), In-Sn-Zn oxide, and In-Al-Zn oxide (also known as IAZO).

[0201] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 17A. Fig. 17A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0202] As shown in FIG. 17A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0203] The structure within the bold frame shown in Figure 17A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0204] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 17B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 17B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 17B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 17B is 500 nm.

[0205] As shown in Figure 17B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film (Intensity). Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 17B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0206] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 17C. Figure 17C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 17C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0207] As shown in FIG. 17C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0208] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 17A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) and nanocrystalline oxide semiconductor (nc-OS). Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0209] Next, we will explain the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS.

[0210] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0211] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0212] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0213] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0214] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0215] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0216] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current and field-effect mobility of transistors. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0217] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, because the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0218] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also known as selected-area electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0219] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0220] [Configuration of oxide semiconductor] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0221] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0222] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0223] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0224] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0225] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0226] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0227] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0228] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0229] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0230] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0231] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 100 . Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may be referred to as an i-type or substantially i-type.

[0232] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0233] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0234] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0235] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0236] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0237] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0238] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0239] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0240] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0241] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor layer 112 is not limited to the above-described oxide semiconductor. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer 112. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may be used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0242] In this specification, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0243] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0244] The semiconductor material used in the semiconductor device according to one embodiment of the present invention may be, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0245] [Film formation method] The conductive layer, insulating layer, and semiconductor layer can be formed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0246] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0247] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0248] The ALD method is also a film formation method that can reduce plasma damage to the workpiece, and because no plasma damage occurs during film formation, the ALD method also produces films with fewer defects.

[0249] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0250] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transport and pressure adjustment compared to when forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0251] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases may be sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). To prevent mixing of the multiple source gases, an inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first source gas, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0252] Thermal CVD methods such as MOCVD and ALD can form a variety of films, including metal films, semiconductor films, and inorganic insulating films. For example, to form an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. Furthermore, the combinations are not limited to these; trimethylgallium can be replaced with triethylgallium (Ga(C2H5)3), and dimethylzinc can be replaced with diethylzinc (Zn(C2H5)2).

[0253] For example, when forming a hafnium oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamido)hafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizer. Other materials include tetrakis(ethylmethylamido)hafnium.

[0254] For example, when forming an aluminum oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0255] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be filmed, and radicals of oxidizing gas (O2, dinitrogen monoxide) are supplied to react with the adsorbed material.

[0256] For example, when forming a tungsten film using an ALD deposition system, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0257] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film formation system using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, or Ga-Zn-O layers may also be formed using these gases. While HO gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Furthermore, In(CH3)3 gas may be replaced with In(C2H5)3 gas. Furthermore, Ga(CH3)3 gas may be replaced with Ga(C2H5)3 gas. Moreover, Zn(C2H5)2 gas may be used instead of Zn(CH3)2 gas.

[0258] A more specific film formation method and film formation apparatus using the ALD method will be described below.

[0259] The ALD method utilizes the self-regulating properties of atoms to deposit atoms one layer at a time, which allows for the formation of extremely thin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films at low temperatures.

[0260] In the ALD method, a first source gas (also called a precursor) and a second source gas (also called an oxidizing gas) are alternately introduced into the chamber for reaction, and film formation is achieved by repeating this process. When introducing the precursor or oxidizing gas, N2, Ar, or other carrier / purge gases can be introduced into the reaction chamber along with the precursor or oxidizing gas. The use of a carrier / purge gas prevents the precursor or oxidizing gas from adsorbing to the inside of the piping and valves, allowing the precursor or oxidizing gas to be introduced into the reaction chamber (also called a carrier gas). Furthermore, the carrier / purge gas allows the precursor or oxidizing gas remaining in the reaction chamber to be quickly exhausted (also called a purge gas). Because of its dual role of introduction (carrier) and exhaust (purge), it is sometimes called a carrier / purge gas. Furthermore, the use of a carrier / purge gas improves the uniformity of the resulting film, making it preferable.

[0261] 18A shows a sequence for forming a film of a material that can exhibit ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method. In the following, the formation of a ferroelectric layer containing hafnium oxide and zirconium oxide is shown as an example.

[0262] The precursor 501 may be a precursor containing hafnium and one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen. The precursor 502 may be a precursor containing zirconium and one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen. In this section, HfCl4 is used as the precursor 501 containing hafnium, and ZrCl4 is used as the precursor 502 containing zirconium.

[0263] Precursors 501 and 502 are formed by heating and gasifying liquid or solid raw materials. Precursor 501 is formed from a solid HfCl4 raw material, and precursor 502 is formed from a solid ZrCl4 raw material. Precursors 501 and 502 preferably have reduced impurities, and these solid raw materials also preferably have reduced impurities. Examples of such impurities include Ba, Cd, Co, Cr, Cu, Fe, Ga, Li, Mg, Mn, Na, Ni, Sr, V, and Zn. In the solid HfCl4 raw material and the solid ZrCl4 raw material, the above impurities are preferably less than 1000 wppb. Here, wppb is a unit that represents the concentration of an impurity converted into mass in parts per billion.

[0264] The oxidizing gas 503 may be any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2. In this example, a gas containing H2O is used as the oxidizing gas 503. The carrier / purge gas 504 may be any one or more selected from N2, He, Ar, Kr, and Xe. In this example, N2 is used as the carrier / purge gas 504.

[0265] First, an oxidizing gas 503 is introduced into the reaction chamber (step S01). Next, the introduction of the oxidizing gas 503 is stopped, leaving only the carrier purge gas 504, and the oxidizing gas 503 remaining in the reaction chamber is purged (step S02). Next, a precursor 501 and a carrier purge gas 504 are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (step S03). In this way, the precursor 501 is adsorbed onto the surface to be formed. Next, the introduction of the precursor 501 is stopped, leaving only the carrier purge gas 504, and the precursor 501 remaining in the reaction chamber is purged (step S04). Next, the oxidizing gas 503 is introduced into the reaction chamber. By introducing the oxidizing gas 503, the precursor 501 is oxidized to form hafnium oxide (step S05). Next, the introduction of the oxidizing gas 503 is stopped, and only the carrier purge gas 504 is used to purge the oxidizing gas 503 remaining in the reaction chamber (step S06).

[0266] Next, precursor 502 and carrier purge gas 504 are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (step S07). In this way, precursor 502 is adsorbed onto the oxygen layer of the hafnium oxide. Next, the introduction of precursor 502 is stopped, and only carrier purge gas 504 is used to purge the precursor 502 remaining in the reaction chamber (step S08). Next, returning to step S01, oxidizing gas 503 is introduced into the reaction chamber. By introducing oxidizing gas 503, precursor 502 is oxidized, and zirconium oxide is formed on the hafnium oxide.

[0267] The above-described steps S01 to S08 constitute one cycle, which is repeated until the desired film thickness is achieved. Note that steps S01 to S08 may be performed at a temperature in the range of 250° C. to 450° C., preferably 350° C. to 400° C.

[0268] As described above, by forming a film using the ALD method, a layered crystalline structure can be formed in which a hafnium layer, an oxygen layer, a zirconium layer, and an oxygen layer are repeated. Furthermore, as described above, by forming a film using a precursor with reduced impurities, it is possible to prevent impurities from being mixed in during film formation and interfering with the formation of the layered crystalline structure. In this way, by forming a layered crystalline structure with high crystallinity, it is possible to impart high ferroelectricity.

[0269] Next, a manufacturing apparatus used for film formation by the ALD method will be described with reference to Fig. 18B, which is a schematic diagram of a manufacturing apparatus 900 for the ALD method.

[0270] 18B, the manufacturing apparatus 900 includes a reaction chamber 901, a gas inlet 903, a reaction chamber inlet 904, an exhaust port 905, a wafer stage 907, and a shaft 908. In FIG. 18B, a wafer 950 is placed on the wafer stage 907.

[0271] The reaction chamber 901 may be provided with a heater system for heating the interior of the reaction chamber 901, the precursor 501, the precursor 502, the oxidizing gas 503, and the carrier / purge gas 504. The wafer stage 907 may be provided with a heater system for heating the wafer 950. The wafer stage 907 may also be provided with a rotation mechanism for horizontally rotating the stage about an axis 908. Although not shown, a gas supply system is installed before the gas inlet 903 to introduce the precursor 501, the precursor 502, the oxidizing gas 503, and the carrier / purge gas 504 into the gas inlet 903 at appropriate timing and at appropriate flow rates for appropriate periods of time. Although not shown, an exhaust system including a vacuum pump is installed beyond the exhaust port 905.

[0272] The manufacturing apparatus 900 shown in Figure 18B is an ALD apparatus known as a cross-flow type. The flows of precursor 501, precursor 502, oxidizing gas 503, and carrier / purge gas 504 in the cross-flow type are described below. Precursor 501, precursor 502, oxidizing gas 503, and carrier / purge gas 504 flow from gas inlet 903 to reaction chamber 901 via reaction chamber inlet 904, reach wafer 950, and are exhausted through exhaust port 905. The arrows in Figure 8 schematically show the direction of gas flow.

[0273] As described above, in step S05 of introducing oxidizing gas 503 into reaction chamber 901 shown in FIG. 18A, precursor 501 adsorbed on wafer 950 is oxidized by oxidizing gas 503 to form hafnium oxide. Due to the cross-flow structure of manufacturing apparatus 900, oxidizing gas 503 comes into contact with heated reaction chamber components for a long time before reaching wafer 950. For this reason, when O3 is used as oxidizing gas 503, for example, the oxidizing gas 503 reacts with a high-temperature solid surface before reaching wafer 950, decomposing the oxidizing gas 503 and reducing its oxidizing power. Therefore, the deposition rate of hafnium oxide depends on the distance the oxidizing gas reaches from reaction chamber inlet 904 to wafer 950. When wafer stage 907 rotates horizontally around axis 908, the periphery of wafer 950 reaches oxidizing gas 503 first, resulting in a hafnium oxide film with a thicker film thickness at the periphery and a thinner film thickness at the center.

[0274] Therefore, it is necessary to set the heating temperature of the reaction chamber to an appropriate temperature to prevent the oxidizing power from decreasing due to the decomposition of the oxidizing gas 503. Note that although the oxidation of the precursor 501 has been described above as an example, the same applies to the oxidation of the precursor 502.

[0275] As a result, hafnium oxide having excellent in-plane film thickness uniformity can be formed. The in-plane film thickness uniformity is preferably ±1.5% or less, and more preferably ±1.0% or less. Here, "in-plane" refers to a square substrate whose size is 5 inches on a side. If the RANGE is defined as the maximum in-plane film thickness minus the minimum in-plane film thickness, and the in-plane film thickness uniformity is defined as ±PNU (Percent Non-Uniformity) (%), then ±PNU (%) can be calculated as follows: ±PNU (%) = (RANGE × 100) / (2 × average in-plane film thickness).

[0276] Furthermore, the oxidizing gas 503 forms a highly uniform oxygen layer, which allows the formation of a layered crystal structure with higher regularity, thereby providing high ferroelectricity.

[0277] As another example of a method for forming an oxide film using the ALD method, a method for forming an In-M-Zn oxide film will be described below with reference to FIG. 18C.

[0278] 18C shows an example of a film formation sequence in which a film is formed using precursors 511 to 513 and an oxidizing gas 514. The film formation sequence includes steps S11 to S13.

[0279] The precursor 511 can be a precursor containing indium. The precursor 512 can be a precursor containing an element M. The precursor 513 can be a precursor containing zinc. Note that each of the precursors 511 to 513 may be a precursor formed of an inorganic substance (sometimes referred to as an inorganic precursor) or a precursor formed of an organic substance (sometimes referred to as an organic precursor). The oxidizing gas 514 can be a gas applicable to the oxidizing gas 503 described in the above embodiment.

[0280] First, step S11 is performed. In step S11, the following steps are performed in order: introducing precursor 511 and allowing the precursor containing indium to be adsorbed onto the surface to be formed; stopping the introduction of precursor 511 and purging excess precursor 511 from within the chamber; introducing oxidizing gas 514 and oxidizing precursor 511 to form an In layer; and stopping the introduction of oxidizing gas 514 and purging excess oxidizing gas 514 from within the chamber.

[0281] Next, step S12 is performed. In step S12, the following steps are performed in order: introducing precursor 512 and causing the precursor having element M to be adsorbed onto the surface of the In layer; stopping the introduction of precursor 512 and purging excess precursor 512 from within the chamber; introducing oxidizing gas 514 and oxidizing precursor 512 to form an M layer; and stopping the introduction of oxidizing gas 514 and purging excess oxidizing gas from within the chamber.

[0282] Next, step S13 is performed. In step S13, the following steps are performed in order: introducing precursor 513 and allowing the zinc-containing precursor to be adsorbed onto the surface of the M layer; stopping the introduction of precursor 513 and purging excess precursor 513 from within the chamber; introducing oxidizing gas 514 and oxidizing precursor 513 to form a Zn layer; and stopping the introduction of oxidizing gas 514 and purging excess oxidizing gas 514 from within the chamber.

[0283] Steps S11 to S13 constitute one cycle, and by repeating this cycle, an In-M-Zn oxide having a desired film thickness can be formed. Note that the element M or Zn may be mixed into the In layer during or after film formation due to heat treatment. Also, In or Zn may be mixed into the M layer. Also, In or M may be mixed into the Zn layer.

[0284] The number of times steps S11 to S13 are performed in one cycle is not limited to one. The number of times steps S11 to S13 are performed in one cycle may be set so that an In-M-Zn oxide with a desired composition is obtained. For example, to form an In-M-Zn oxide film with an atomic ratio of In:M:Zn=1:1:2, steps S11, S13, S12, and S13 may be repeated as one cycle. Alternatively, an In-Zn oxide film can be formed by repeating a cycle consisting of steps S11 and S12. Alternatively, a precursor 513 may be introduced in the step of introducing precursor 512 in step S12, thereby forming an (M, Zn) layer in step S12. Alternatively, an In layer containing element M or Zn may be formed in step S11 by introducing precursor 512 or precursor 513 in the step of introducing precursor 511 in step S11. By appropriately combining these, a desired oxide film can be formed.

[0285] Two or more of the manufacturing devices used for ALD film formation may be incorporated into a multi-chamber film formation device. In this case, by setting the In-M-Zn oxide and the ferroelectric layer to be formed in different manufacturing devices, the In-M-Zn oxide and the ferroelectric layer can be formed successively without switching the precursor and oxidizing gas.

[0286] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0287] (Embodiment 2) In this embodiment, a semiconductor device 400 including a memory device or a semiconductor device according to one embodiment of the present invention will be described.

[0288] Fig. 19 is a block diagram showing an example configuration of a semiconductor device 400. The semiconductor device 400 shown in Fig. 19 has a drive circuit 410 and a memory array 420. The memory array 420 has one or more memory strings 100. Fig. 19 shows an example in which the memory array 420 has a plurality of memory strings 100 arranged in a matrix.

[0289] The drive circuit 410 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412, and a voltage generation circuit 428.

[0290] In the semiconductor device 400, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0291] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 412.

[0292] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal for the peripheral circuit 411 so that this operation mode is executed.

[0293] The voltage generating circuit 428 has a function of generating a negative voltage. WAKE has a function of controlling the input of CLK to the voltage generating circuit 428. For example, when an H-level signal is given to WAKE, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 428 generates a negative voltage.

[0294] The peripheral circuit 411 is a circuit for writing and reading data to and from the memory string 100. The peripheral circuit 411 has a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, an output circuit 426, and a sense amplifier 427.

[0295] The row decoder 441 and the column decoder 442 have the function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying a row to access, and the column decoder 442 is a circuit for specifying a column to access. The row driver 423 has the function of selecting the wiring CG specified by the row decoder 441. The column driver 424 has the function of writing data to the memory string 100, reading data from the memory string 100, and holding the read data.

[0296] The input circuit 425 has a function of holding a signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is data (Din) to be written to the memory string 100. The data (Dout) read from the memory string 100 by the column driver 424 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is a signal RDA.

[0297] PSW241 is the V to the peripheral circuit 415DD The PSW 242 has the function of controlling the supply of V to the row driver 423. HM Here, the high power supply voltage of the semiconductor device 400 is V DD and the low power supply voltage is GND (ground potential). HM is the high supply voltage used to drive the word line high, and V DD 19, in the peripheral circuit 415, V DD Although the number of power domains to which power is supplied is set to one, it is also possible to set multiple power domains. In this case, a power switch should be provided for each power domain.

[0298] The drive circuit 410 and memory array 420 of the semiconductor device 400 may be provided on the same plane. Alternatively, as shown in FIG. 20, the drive circuit 410 and memory array 420 may be provided overlapping each other. By providing the drive circuit 410 and memory array 420 overlapping each other, the signal propagation distance can be shortened. FIG. 20 also includes an enlarged perspective view of a portion of the semiconductor device 400.

[0299] Furthermore, the semiconductor device 400 may use an arithmetic processing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) as the control circuit 412 of the drive circuit 410. By using a CPU and / or a GPU, the semiconductor device 400 can be realized with an arithmetic processing function.

[0300] By using the memory string 100 according to one embodiment of the present invention, a part of the memory array 420 can function as a main memory, a cache memory, or the like. The memory string 100 can also function like a flash memory. Therefore, a part of the memory array 420 can function like a flash memory. The semiconductor device 400 according to one embodiment of the present invention can function as a universal memory.

[0301] Furthermore, according to one aspect of the present invention, the functions of a CPU, a cache memory, and a storage can be realized on the same chip.

[0302] 20 includes a driver circuit 410 including a CPU and a 3D OS NAND memory device according to one embodiment of the present invention in a memory array 420. The 3D OS NAND memory device according to one embodiment of the present invention functions as a cache memory and a storage.

[0303] 21 shows how a host 450 manages a plurality of semiconductor devices 400. Each semiconductor device 400 has an arithmetic processing function and can perform parallel writing and reading to a cache memory and storage. By having the host 450 manage a plurality of semiconductor devices 400, an information processing system that realizes non-von Neumann computing can be constructed.

[0304] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0305] (Embodiment 3) In this embodiment mode, an example of a processing unit that can include a semiconductor device such as the memory device described in the above embodiment mode will be described.

[0306] 23 is a block diagram of the arithmetic processing device 1100. In FIG. 23, an example of the configuration of a CPU is shown as an example of the configuration that can be used for the arithmetic processing device 1100.

[0307] The arithmetic processing device 1100 shown in FIG. 23 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may also be provided on separate chips.

[0308] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding that data.

[0309] The arithmetic processing device 1100 shown in Figure 23 is merely one example of a simplified configuration, and actual arithmetic processing devices 1100 have a wide variety of configurations depending on their applications. For example, the arithmetic processing device 1100 shown in Figure 23 or a configuration including an arithmetic circuit may be used as one core, and a configuration may be used in which multiple such cores operate in parallel, i.e., a GPU-like configuration. Furthermore, the number of bits that the arithmetic processing device 1100 can handle in its internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0310] An instruction input to the processor 1100 via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0311] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Furthermore, the interrupt controller 1194 processes interrupt requests from external input / output devices or peripheral circuits while the arithmetic processing unit 1100 is executing a program, by determining their priority or mask status. The register controller 1197 generates an address for the register 1196 and reads or writes data from or to the register 1196 depending on the state of the arithmetic processing unit 1100.

[0312] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0313] 23, a memory device is provided in the register 1196 and the cache 1199. As the memory device, for example, the memory device described in the above embodiment can be used.

[0314] In the arithmetic processing device 1100 shown in FIG. 23, the register controller 1197 selects the holding operation of the register 1196 in accordance with an instruction from the ALU 1191. That is, it selects whether to hold data in a flip-flop or a capacitive element in the memory cell of the register 1196. If holding data in a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. If holding data in a capacitive element is selected, the data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 1196 can be stopped.

[0315] The arithmetic processing device 1100 is not limited to a CPU, but may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), or the like.

[0316] The semiconductor device 400 and the arithmetic processing unit 1100 described in the above embodiment can be provided overlapping each other. FIGS. 22A and 22B are perspective views of a semiconductor device 1150A. The semiconductor device 1150A includes a semiconductor device 400 functioning as a memory device on the arithmetic processing unit 1100. The arithmetic processing unit 1100 and the semiconductor device 400 have overlapping regions. To make the configuration of the semiconductor device 1150A easier to understand, the arithmetic processing unit 1100 and the semiconductor device 400 are shown separately in FIG. 23B.

[0317] By stacking the semiconductor device 400 and the arithmetic processing device 1100, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0318] Furthermore, multiple semiconductor devices 400 may be provided on top of the arithmetic processing device 1100. Perspective views of a semiconductor device 1150B are shown in FIGS. 24A and 24B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the arithmetic processing device 1100. The arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. To make the configuration of the semiconductor device 1150B easier to understand, the arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 24B.

[0319] The semiconductor device 400a and the semiconductor device 400b function as memory devices. For example, one of the semiconductor device 400a and the semiconductor device 400b may be a NOR memory device, and the other may be a NAND memory device. Both the semiconductor device 400a and the semiconductor device 400b may be NAND memory devices. Examples of NOR memory devices include DRAM and SRAM. Since NOR memory devices can operate faster than NAND memory devices, for example, part of the semiconductor device 400a can be used as the main memory and / or cache 1199. Note that the stacking order of the semiconductor device 400a and the semiconductor device 400b may be reversed.

[0320] 25A and 25B show perspective views of semiconductor device 1150C. Semiconductor device 1150C has a configuration in which arithmetic processing device 1100 is sandwiched between semiconductor device 400a and semiconductor device 400b. The arithmetic processing device 1100, semiconductor device 400a, and semiconductor device 400b have overlapping regions. To make the configuration of semiconductor device 1150C easier to understand, FIG. 25B shows arithmetic processing device 1100, semiconductor device 400a, and semiconductor device 400b separately.

[0321] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 400a and the arithmetic processing unit 1100 and the communication speed between the semiconductor device 400b and the arithmetic processing unit 1100. In addition, the power consumption can be reduced compared to the semiconductor device 1150B.

[0322] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0323] (Fourth embodiment) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an electronic component in which the semiconductor device is incorporated will be described.

[0324] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 26A.

[0325] 26A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of wafer 4801. Note that on the upper surface of wafer 4801, a portion where circuit portions 4802 are not present is spacing 4803, which is an area for dicing.

[0326] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0327] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0328] By performing a dicing process, chips 4800a as shown in FIG. 26B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0329] 26A 。 Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Figure 26A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0330] <Electronic components> 26C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 26C includes a chip 4800a in a mold 4711. A memory device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0331] 26C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0332] 26D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0333] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0334] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0335] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0336] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0337] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0338] Furthermore, in SiP or MCM using silicon interposers, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on the interposer.

[0339] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0340] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 26D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0341] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0342] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0343] (Embodiment 5) In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0344] A storage device according to one embodiment of the present invention can be applied to, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and also includes a large-scale computer such as a server system.

[0345] 27A to 27J and 28A to 28E illustrate examples of electronic devices including a memory device according to one embodiment of the present invention, each of which includes an electronic component 4700 or an electronic component 4730 including the memory device.

[0346] [mobile phone] 27A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0347] By applying a storage device according to one embodiment of the present invention, the information terminal 5500 can store temporary files (such as caches when using a web browser) generated when an application is executed.

[0348] [Wearable devices] 27B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0349] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0350] [Information terminal] 27C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0351] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0352] 27A to 27C are taken as examples of electronic devices, and are illustrated in Fig. 27A to 27C, respectively, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0353] [electric appliances] 27D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0354] A storage device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the storage device.

[0355] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0356] [Game consoles] 27E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0357] FIG. 27F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 27F, the controller 7522 can include a display unit that displays game images, a touch panel that serves as an input interface other than buttons, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 27F, and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0358] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer displays, game displays, and head-mounted displays.

[0359] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0360] Furthermore, by applying the storage device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files necessary for calculations that occur during game execution can be stored.

[0361] As an example of a game machine, a portable game machine is shown in FIG. 27E. Also, a home-use stationary game machine is shown in FIG. 27F. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0362] [Moving object] The storage device described in the above embodiment can be applied to a vehicle, which is a moving object, and to the vicinity of the driver's seat of the vehicle.

[0363] FIG. 27G illustrates an automobile 5700 as an example of a moving object.

[0364] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0365] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0366] The storage device described in the above embodiment can temporarily store information, and therefore, for example, the computer can be used to store necessary temporary information in an automatic driving system for the automobile 5700 or a system that performs road guidance, hazard prediction, etc. The display device may be configured to display temporary information such as road guidance and hazard prediction. The display device may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0367] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0368] [camera] The storage device described in the above embodiment can be applied to a camera.

[0369] 27H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0370] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0371] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0372] 27I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0373] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the storage device described above, the video camera 6300 can store temporary files generated during encoding.

[0374] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0375] 27J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0376] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0377] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (such as in the case of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0378] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0379] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0380] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0381] [PC expansion device] The storage devices described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0382] Figure 28A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Figure 28A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0383] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the storage devices and the like described in the above embodiments. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0384] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals or digital cameras.

[0385] FIG. 28B is a schematic diagram of the external appearance of an SD card, and FIG. 28C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0386] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0387] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0388] FIG. 28D is a schematic diagram of the external appearance of an SSD, and FIG. 28E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 is equipped with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0389] [Calculator] 29A is an example of a large-scale computer. The computer 5600 has a rack 5610 in which a plurality of rack-mounted computers 5620 are stored.

[0390] Computer 5620 can have the configuration shown in the perspective view in Fig. 29B, for example. In Fig. 29B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0391] PC card 5621 shown in FIG. 29C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 29C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0392] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0393] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0394] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0395] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0396] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0397] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0398] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0399] Next, a configuration example of a computer system applicable to the calculator 5600 will be described. Fig. 30 is a diagram illustrating a configuration example of a computer system 700. The computer system 700 is configured to include software and hardware. Note that the hardware included in a computer system may be referred to as an information processing device.

[0400] The software that makes up the computer system 700 includes an operating system including device drivers, middleware, various development environments, AI-related application programs (AI applications), and application programs unrelated to AI.

[0401] The device driver includes an application program for controlling an auxiliary storage device, a display device, a printer, and other externally connected devices.

[0402] The hardware that constitutes the computer system 700 includes a first processor, a second processor, a first storage device, etc. The second processor also includes a second storage device.

[0403] The first processing unit may be, for example, a central processing unit such as a Noff OS CPU. The Noff OS CPU has a storage means (e.g., nonvolatile memory) using OS transistors, and has a function of storing necessary information in the storage means and stopping the power supply to the central processing unit when operation is not required. Using a Noff OS CPU as the first processing unit can reduce the power consumption of the computer system 700.

[0404] The second arithmetic processing device may be, for example, a GPU or an FPGA. Preferably, the second arithmetic processing device is an AI OS Accelerator. The AI ​​OS Accelerator is configured using OS transistors and has arithmetic means such as a product-sum operation circuit. The AI ​​OS Accelerator consumes less power than a general GPU. Using the AI ​​OS Accelerator as the second arithmetic processing device can reduce the power consumption of the computer system 700.

[0405] It is preferable to use a storage device according to an embodiment of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. Furthermore, using a 3D OS NAND type storage device makes it easier to realize a non-von Neumann type computer system.

[0406] A 3D OS NAND type storage device consumes less power than a 3D NAND type storage device that uses Si transistors. Using a 3D OS NAND type storage device as a storage device can reduce the power consumption of the computer system 700. In addition, because a 3D OS NAND type storage device can function as a universal memory, the number of parts required to configure the computer system 700 can be reduced.

[0407] By configuring the semiconductor device constituting the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, the processing unit, and the storage device. Monolithic integration of the hardware not only makes it possible to reduce the size, weight, and thickness of the hardware, but also facilitates further reduction in power consumption.

[0408] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0409] (Sixth embodiment) A normally-off CPU (also referred to as an "Noff-CPU") can be realized by using the OS memory described in this specification etc. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an "off state") even when the gate voltage is 0 V.

[0410] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from the standby state. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0411] The Noff-CPU can be suitably used in small-scale systems such as IoT terminal devices (also called "endpoint microcomputers") 803 in the field of IoT (Internet of Things).

[0412] Figure 31 shows the hierarchical structure of an IoT network and trends in required specifications. In Figure 31, power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of an IoT network is broadly divided into an upper-level cloud field 801 and a lower-level embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, and home appliances.

[0413] The higher the layer, the more processing performance is required rather than low power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs (System on a Chip), etc. are used. Furthermore, the lower the layer, the more power consumption is required rather than processing performance, and the number of devices increases explosively. A semiconductor device according to one embodiment of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.

[0414] The term "endpoint" refers to the terminal area of ​​the embedded field 802. Devices used as endpoints include, for example, microcomputers used in factories, home appliances, infrastructure, agriculture, and the like.

[0415] FIG. 32 illustrates an image of factory automation as an application example of an endpoint microcontroller. A factory 884 is connected to a cloud 883 via an Internet line. The cloud 883 is connected to a home 881 and an office 882 via the Internet line. The Internet line may be a wired communication system or a wireless communication system. For example, in the case of a wireless communication system, a semiconductor device according to one embodiment of the present invention may be used in a communication device to perform wireless communication in accordance with a communication standard such as a fourth-generation mobile communication system (4G) or a fifth-generation mobile communication system (5G). The factory 884 may be connected to factories 885 and 886 via the Internet line.

[0416] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to a cloud 883 and transmitting and receiving information. The master device 831 is also connected to a plurality of industrial robots 842 included in an IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet ("Ethernet" is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0417] A factory manager can connect to a factory 884 via a cloud 883 from a home 881 or office 882 to know the operating status, etc. He can also check for incorrect or missing items, give instructions on where to put them, measure takt time, etc.

[0418] In recent years, the introduction of IoT into factories has been progressing worldwide under the name of "smart factories." In smart factory cases, there have been reported cases where endpoint microcomputers are used not only for simple inspection and auditing but also for fault detection and anomaly prediction.

[0419] In small-scale systems such as endpoint microcontrollers, the overall system power consumption during operation is often low, so the CPU tends to account for a large proportion of power consumption. For this reason, the power reduction effect of Noff-CPUs during standby operation is significant in small-scale systems such as endpoint microcontrollers. On the other hand, in the embedded field of IoT, quick response is sometimes required, and the use of Noff-CPUs makes it possible to achieve fast recovery from standby operation.

[0420] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0421] 100: memory string, 100A to 100D: memory string, 101: conductive layer, 102: insulating layer, 103: conductive layer, 103a, 103b: conductive layer, 104: conductive layer, 105: insulating layer, 106: conductive layer, 110: structure, 110A: structure, 111: insulating layer, 112: semiconductor layer, 114: functional layer, 115: insulating layer, 116: insulating layer, 117: insulating layer, 118: insulating layer, 121: insulating layer, 131: central axis, 132: region, 141: conductive layer, 142: insulating layer, 145: opening, 150: memory cell, 151: transistor, 152: capacitance, 160: transistor, 170: memory element

Claims

1. a first conductive layer extending in a first direction; a structure extending in a second direction intersecting the first direction; a first insulating layer and a second insulating layer; The structure is a functional layer, a semiconductor layer, a third insulating layer, a second conductive layer, and a fourth insulating film; At an intersection between the first conductive layer and the structure, the third insulating layer, the semiconductor layer, and the functional layer are concentrically arranged in this order around the second conductive layer; the first insulating layer and the second insulating layer are stacked in the second direction; the functional layer, the first conductive layer, and the fourth insulating film are disposed between the first insulating layer and the second insulating layer; the fourth insulating film is provided in contact with an upper surface, a lower surface, and one side surface of the functional layer, the second conductive layer, the third insulating layer, and the semiconductor layer each have a portion located inside a first opening provided in the first insulating layer and a portion located inside a second opening provided in the second insulating layer; a flat surface is formed between the first insulating layer, the fourth insulating film, and the functional layer; the semiconductor layer has a region in contact with the flat surface; Semiconductor device.

2. In claim 1, The first direction is a direction perpendicular to the second direction. Semiconductor device.

3. In claim 1, The functional layer exhibits ferroelectricity or antiferroelectricity. Semiconductor device.

4. In claim 1, The functional layer contains either hafnium oxide or zirconium oxide, or both. Semiconductor device.

5. In claim 1, The intersection functions as a memory cell. Semiconductor device.

6. In claim 1, The semiconductor layer contains at least one of indium and zinc. Semiconductor device.

7. In claim 1, the third insulating layer contains at least one of silicon oxide and silicon oxynitride; Semiconductor device.

8. In claim 1, the first conductive layer is a gate electrode; Semiconductor device.

9. In claim 1, the second conductive layer is a gate electrode having a function different from that of the first conductive layer; Semiconductor device.

10. In claim 1, the fourth insulating film contains at least one of silicon nitride and silicon oxide; Semiconductor device.

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