semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device in which a cell that is at the end of a column of cells and does not have a logic function comprises: a transistor (ND1) that is opposite a transistor of a cell that is adjacent in the Y direction; a buried power rail (12) that is on the same side of the transistor (ND1) as the transistor of the adjacent cell and supplies a power supply voltage (VSS); and a buried power rail (11A) that is on the opposite side of the transistor (ND1) from the transistor of the adjacent cell and supplies a power supply voltage (VDD). Buried power rail (11A) is larger than buried power rail (12) in the Y direction.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells. [Background technology]

[0002] The standard cell method is known as a method for forming semiconductor integrated circuits on a semiconductor substrate. In this method, basic units with specific logic functions (such as inverters, latches, flip-flops, and full adders) are prepared in advance as standard cells, and multiple standard cells are placed on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, in order to increase the integration density of semiconductor integrated circuit devices, it has been proposed to use buried power rails (BPRs), which are power supply wiring provided in a buried interconnect layer, for standard cells, rather than power supply wiring provided in a metal wiring layer formed above transistors as in the past.

[0004] Patent Document 1 discloses a configuration in which, in a block made up of standard cells, power supply wiring is configured as buried power supply wiring, the source of a transistor is connected to this buried power supply wiring, and it is further connected to power supply wiring provided in an upper wiring layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0080969 (FIG. 1E) Summary of the Invention [Problem to be solved by the invention]

[0006] Since buried power supply wiring is formed by being buried in the substrate, it cannot be formed in the region where the source, drain, and channel of a transistor exist. Therefore, if the buried power supply wiring is made thicker in order to strengthen the power supply wiring for the purpose of suppressing a drop in power supply voltage, this will lead to an increase in the area of ​​the standard cell, and therefore will hinder the high integration of semiconductor integrated circuits.

[0007] An object of the present disclosure is to enable a semiconductor integrated circuit device that uses embedded power wiring to have its power wiring strengthened without hindering high integration. [Means for solving the problem]

[0008] In a first aspect of the present disclosure, a semiconductor integrated circuit device includes a plurality of cell rows each including standard cells aligned in a first direction and aligned in a second direction perpendicular to the first direction, the plurality of cell rows including: a first standard cell arranged in a first cell row second from one end in the second direction and having a logic function; and a second standard cell arranged in a second cell row at the one end in the second direction and adjacent to the first cell row, the second standard cell adjacent to the first standard cell in the second direction and having no logic function, the first standard cell including a first region in which a transistor of a first conductivity type is formed, a second region in which a transistor of a second conductivity type is formed, a first transistor which is the transistor of the first conductivity type formed in the first region, a second transistor which is the transistor of the second conductivity type formed in the second region, and a buried wiring layer. the second standard cell comprises a third region in which a transistor of the second conductivity type is formed, a third transistor of the second conductivity type formed in the third region and facing the second transistor in the second direction, a third buried power supply wiring formed in the buried wiring layer and arranged on the side of the third transistor facing the second transistor, and supplying the second power supply voltage, and a fourth buried power supply wiring formed in the buried wiring layer and arranged on the opposite side of the third transistor from the second transistor, and supplying the first power supply voltage, and the size of the fourth buried power supply wiring in the second direction is larger than the size of the third buried power supply wiring in the second direction.

[0009] According to this embodiment, a second standard cell having no logic function is arranged in a second cell row at one end of the plurality of cell rows. The second standard cell is adjacent to the first standard cell having the logic function in the second direction. The second standard cell includes a third transistor facing the second transistor of the first standard cell, a third buried power wiring for supplying a second power supply voltage, and a fourth buried power wiring for supplying a first power supply voltage. The third buried power wiring is arranged on the side of the third transistor facing the second transistor of the first standard cell, and the fourth buried power wiring is arranged on the side of the third transistor facing the second transistor of the first standard cell. The size of the fourth buried power wiring in the second direction is larger than the size of the third buried power wiring in the second direction. This allows the fourth buried power wiring to be thickened without increasing the area of ​​the second standard cells in the second cell row. Therefore, in a semiconductor integrated circuit device using buried power wiring, it is possible to strengthen the power wiring without hindering high integration.

[0010] In a second aspect of the present disclosure, a semiconductor integrated circuit device includes a plurality of cell rows each including standard cells aligned in a first direction and aligned in a second direction perpendicular to the first direction, the plurality of cell rows including a first standard cell arranged in a first cell row and having a logic function, and a second standard cell arranged in a second cell row adjacent to the first cell row and adjacent to the first standard cell in the second direction and being a multi-height cell having no logic function, the first standard cell including a first region in which a transistor of a first conductivity type is formed, a second region in which a transistor of a second conductivity type is formed, a first transistor which is the transistor of the first conductivity type formed in the first region, a second transistor which is the transistor of the second conductivity type formed in the second region, and a first power supply formed in a buried wiring layer. the second standard cell comprises a first buried power supply wiring that supplies a voltage, and a second buried power supply wiring formed in a buried wiring layer and that supplies a second power supply voltage, the second standard cell comprising: a third region in which a transistor of the second conductivity type is formed; a third transistor that is the transistor of the second conductivity type formed in the third region and that faces the second transistor in the second direction; a third buried power supply wiring that is formed in the buried wiring layer and that is arranged on the side of the third transistor that faces the second transistor and that supplies the second power supply voltage; and a fourth buried power supply wiring that is formed in the buried wiring layer and that is arranged on the opposite side of the third transistor from the second transistor and that supplies the first power supply voltage,

[0011] According to this embodiment, a second standard cell, which is a multi-height cell without a logic function, is arranged in a second cell row among the multiple cell rows. The second standard cell is adjacent to the first standard cell having a logic function in the second direction. The second standard cell includes a third transistor facing the second transistor of the first standard cell, a third buried power wiring for supplying a second power supply voltage, and a fourth buried power wiring for supplying a first power supply voltage. The third buried power wiring is arranged on the side of the third transistor facing the second transistor of the first standard cell, and the fourth buried power wiring is arranged on the side of the third transistor opposite the second transistor of the first standard cell. The size of the fourth buried power wiring in the second direction is larger than the size of the third buried power wiring in the second direction. This allows the fourth buried power wiring to be thickened without increasing the area of ​​the second standard cell in the second cell row. Therefore, in a semiconductor integrated circuit device using buried power wiring, it is possible to strengthen the power wiring without hindering high integration. [Effects of the Invention]

[0012] According to the present disclosure, in a semiconductor integrated circuit device using embedded power wiring, it is possible to strengthen the power wiring without hindering high integration. [Brief explanation of the drawings]

[0013] [Figure 1] Layout example of circuit blocks included in the semiconductor integrated circuit device according to the first embodiment [Figure 2] An example of the layout structure of a power tap cell. (a) is a plan view, (b) and (c) are cross-sectional views. [Figure 3] An example of the layout structure of an inverter cell. (a) is a plan view, and (b) and (c) are cross-sectional views. [Figure 4] An example of the layout structure of a power tap cell in an edge row, where (a) is a plan view, and (b) and (c) are cross-sectional views. [Figure 5]An example of the layout structure of a termination cell. (a) is a plan view, and (b) and (c) are cross-sectional views. [Figure 6] (a) Modified power tap cell, (b) Modified power tap cell in the edge row, (c) Modified terminal cell [Figure 7] (a) shows a modified example of a power tap cell in an end row, and (b) shows a modified example of a terminal cell. [Figure 8] Terminal cell variants [Figure 9] Layout example of a circuit block included in a semiconductor integrated circuit device according to a second embodiment [Figure 10] (a) is an example of the layout structure of a power tap cell 1M, and (b) is an example of the layout structure of a cell CM. [Figure 11] (a) is a modified example of power tap cell 1M, and (b) is a modified example of cell CM. [Figure 12] 10A and 10B are examples of triple-height cells in the second embodiment, where (a) is a power tap cell and (b) is a cell. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter, simply referred to as cells as appropriate), and at least some of the plurality of standard cells include, for example, nanosheet FETs (Field Effect Transistors). A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In addition, in the present disclosure, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals that serve as the source or drain of the nanosheet FET are referred to as "pads."

[0015] In this disclosure, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction.

[0016] (First embodiment) FIG. 1 shows an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment. In the layout of FIG. 1, multiple cell rows CR, each including standard cells C aligned in the X direction, are arranged in the Y direction. The standard cells C include, for example, nanosheet FETs. The multiple cell rows CR are arranged upside down (flipped in the Y direction) every other row. Power supply wiring 3 that supplies a power supply voltage VDD and power supply wiring 4 that supplies a power supply voltage VSS are arranged alternately between the cell rows CR. The power supply wiring 3 and 4 are so-called buried power rails (BPR) formed in a buried wiring layer. The cells C included in each cell row CR are supplied with power supply voltages VDD and VSS from the power supply wiring 3 and 4 arranged above and below the cell row CR in the drawing.

[0017] In the cell rows at both ends of the circuit block in the Y direction, i.e., the topmost cell row CRA and the bottommost cell row CRB, termination cells CE are arranged in the X direction. A "termination cell" is a cell that does not have a logical function and is used to terminate the circuit block without contributing to the logical function of the circuit block. By placing termination cells, it is possible to suppress variations in the finished shape of the layout pattern of cells inside the termination cells, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0018] In the multiple cell rows CR, CRA, CRB, power tap cell groups 2a, 2b, 2c, each including multiple power tap cells 1, are arranged at equal intervals in the X direction. Each of the power tap cell groups 2a, 2b, 2c includes multiple power tap cells 1 at the same position in the X direction. M2 wiring extending in the Y direction is laid within the power tap cell 1, and by arranging the power tap cells 1 adjacent to each other in the Y direction, M2 power supply wirings 5, 6 extending in the Y direction within the circuit block are formed. The M2 power supply wiring 5 is connected via a via to the power supply wiring 3 that supplies VDD within the power tap cell 1. The M2 power supply wiring 6 is connected via a via to the power supply wiring 4 that supplies VSS within the power tap cell 1. This forms a mesh-like power supply wiring network, strengthening the power supply.

[0019] Note that configurations other than the embedded power supply wiring and the M2 power supply wiring are omitted in Fig. 1. The configurations of the power tap cell 1, cell C, and terminal cell CE will be described below.

[0020] FIG. 2 shows an example of the layout structure of a power tap cell 1 in a cell row CR, where (a) is a plan view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B-B' in (a). In FIG. 2, the cell frame CL of the power tap cell 1 is indicated by a bold line. This is also true for the subsequent plan views. FIG. 3 shows an example of the layout structure of an inverter cell as an example of cell C, where (a) is a plan view, (b) is a cross-sectional view along line A-A', and (c) is a cross-sectional view along line B-B'.

[0021] First, the layout structure of the inverter cell will be described with reference to FIG.

[0022] As shown in FIG. 3(a), power supply wiring 11 and 12 extending in the X direction are provided at both ends of the inverter cell in the Y direction. Both power supply wiring 11 and 12 are buried power supply wiring (BPR) formed in a buried wiring layer. Power supply wiring 11 supplies a power supply voltage VDD, and power supply wiring 12 supplies a power supply voltage VSS. Power supply wiring 11 is shared with other cells C arranged in the same cell column CR as the inverter cell, forming power supply wiring 3 in FIG. 1. Power supply wiring 12 is shared with other cells C arranged in the same cell column CR as the inverter cell, forming power supply wiring 4 in FIG. 1.

[0023] A P-type transistor P1 is formed in a P-type transistor region AP on the N-well, and an N-type transistor N1 is formed in an N-type transistor region AN on the P-type substrate.

[0024] The transistor P1 has a nanosheet 21 consisting of two sheets as a channel portion. In other words, the transistor P1 is a nanosheet FET. Pads 22a and 22b consisting of semiconductor layers with an integral structure connected to the two sheets are formed on both ends of the nanosheet 21 in the X direction. The pads 22a and 22b become the source and drain regions of the transistor P1.

[0025] The transistor N1 has a nanosheet 26 consisting of two sheets as a channel portion. In other words, the transistor N1 is a nanosheet FET. Pads 27a and 27b consisting of semiconductor layers with an integral structure connected to the two sheets are formed on both ends of the nanosheet 26 in the X direction. The pads 27a and 27b become the source and drain regions of the transistor N1.

[0026] The gate wiring 31 extends in the Y direction and surrounds the nanosheet 21 of the transistor P1 with a gate insulating film (not shown) in between, and also surrounds the nanosheet 26 of the transistor N1 with a gate insulating film (not shown) in between. The gate wiring 31 serves as the gates of the transistors P1 and N1.

[0027] Local wirings (denoted as LI in the figure) 41, 42, and 43 are formed extending in the Y direction. The local wiring 41 is connected to the pad 22a and is also connected to the power supply wiring 11 through a via. The local wiring 42 is connected to the pad 27a and is also connected to the power supply wiring 12 through a via. The local wiring 43 is connected to the pads 22b and 27b.

[0028] M1 wirings 51 and 52 extending in the X direction are formed in the first metal wiring layer. The M1 wiring 51 is connected to the gate wiring 31 through a via. An input terminal of an inverter cell is provided above the M1 wiring 51. The M1 wiring 52 is connected to the local wiring 43 through a via. An output terminal of an inverter cell is provided above the M1 wiring 52.

[0029] That is, the local interconnects 41, 42, and 43 are formed in a local interconnect layer above the buried power interconnect and below the M1 interconnect, and are connected to the sources or drains of the transistors P1 and N1. The cell terminals are provided in the M1 interconnect layer, and the inter-cell interconnects are provided in interconnect layers above the M1 interconnect layer.

[0030] Next, the layout structure of the power tap cell 1 will be described with reference to FIG.

[0031] 2(a), similar to the inverter cell, power supply lines 11 and 12, which are embedded power supply lines extending in the X direction, are provided at both ends in the Y direction of the power tap cell 1. The power supply line 11 supplies a power supply voltage VDD, and the power supply line 12 supplies a power supply voltage VSS.

[0032] In the power tap cell 1, no nanosheets are formed and no transistors are formed.

[0033] The gate wiring 35 extends in the Y direction. Local wirings 46 and 47 extending in the Y direction are formed on both sides of the gate wiring 35 in the X direction. The local wirings 46 and 47 are formed in the same local wiring layer as the local wirings 41, 42, and 43 of the inverter cells. The local wiring 46 is connected to the power supply wiring 11 through a via. The local wiring 47 is connected to the power supply wiring 12 through a via.

[0034] M2 wirings 61 and 62 extending in the Y direction are formed in the second metal wiring layer. The M2 wiring 61 overlaps the local wiring 46 in a plan view and is connected to the local wiring 46 through a via and an M1 wiring. The M2 wiring 62 overlaps the local wiring 47 in a plan view and is connected to the local wiring 47 through a via and an M1 wiring. The M2 wirings 61 and 62 extend in the Y direction to the cell frame CL.

[0035] FIG. 4 shows an example of the layout structure of a power tap cell 1 in the cell row CRA, which is the top row of the circuit block, where (a) is a plan view, (b) is a cross-sectional view taken along line A-A' in (a), and (c) is a cross-sectional view taken along line B-B' in (a). FIG. 5 shows an example of the layout structure of a termination cell CA in the cell row CRA, where (a) is a plan view, (b) is a cross-sectional view taken along line A-A', and (c) is a cross-sectional view taken along line B-B'. Note that the cell row CRB, which is the bottom row of the circuit block, has a power tap cell 1 and a termination cell CA arranged in a configuration that is the inverted configuration of FIGS. 4 and 5.

[0036] The configuration of the power tap cell shown in Fig. 4 is almost the same as the configuration of the power tap cell shown in Fig. 2. However, the power supply wiring 11A that supplies the power supply voltage VDD has a wiring width greater than that of the power supply wirings 11 and 12.

[0037] The layout structure of the termination cell CA will be described with reference to FIG.

[0038] An N-type dummy transistor ND1 is formed in an N-type transistor region AN on a P-type substrate. The dummy transistor ND1 has a nanosheet 28 consisting of two sheets as a channel portion. Pads 29a and 29b consisting of semiconductor layers with an integral structure connected to the two sheets are formed on both ends of the nanosheet 28 in the X direction. On the other hand, no dummy transistor is formed in a P-type transistor region AP on the N well.

[0039] The gate wiring 32 extends in the Y direction and surrounds the nanosheet 28 of the dummy transistor ND1 with a gate insulating film (not shown) sandwiched therebetween. Local wirings 44, 45, 46, and 47 extending in the Y direction are formed. The local wirings 44 and 45 are connected to the power supply wiring 11A through vias. The local wiring 46 is connected to the pad 29a and is also connected to the power supply wiring 12 through a via. The local wiring 47 is connected to the pad 29b and is also connected to the power supply wiring 12 through a via.

[0040] 2 and 4 are arranged in a row in the Y direction as shown in Fig. 1. As a result, M2 wirings 61 and 62 are each continuous across the multiple power tap cells 1 lined up in the Y direction, thereby forming the M2 power wirings 5 ​​and 6 in Fig. 1. In each power tap cell 1, M2 wiring 61 is connected to power wiring 11 through a via and an M1 wiring, and M2 wiring 62 is connected to power wiring 12 through a via and an M1 wiring, so that M2 power wiring 5 is connected to power wiring 3, and M2 power wiring 6 is connected to power wiring 4.

[0041] As shown in FIG. 5, in the terminal cell CE, nanosheets, pads, gates, and local wiring are formed in the transistor region on the side of the adjacent cell C in the Y direction (the N-type transistor region AN at the bottom of the drawing in FIG. 5). This makes it possible to suppress variations in the finished shape of the layout pattern for the cells C in the cell row CR. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices, improve yields, and improve reliability.

[0042] Furthermore, in the termination cell CE, no dummy transistors, including nanosheets and pads, are formed in the P-type transistor region AP. This allows the wiring width of the embedded power wiring 11A to be expanded toward the interior of the termination cell CE. In other words, by not forming dummy transistors in the P-type transistor region AP, thick embedded power wiring 11A can be arranged without increasing the cell area. This allows the power wiring to be strengthened without hindering the high integration of the semiconductor integrated circuit. Furthermore, since the P-type transistor region AP is not adjacent to other cells C, not forming dummy transistors there does not impair the aforementioned effects of suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield, and improving reliability.

[0043] According to this embodiment, a termination cell CE having no logic function is arranged in the cell rows CRA and CRB at the ends of the circuit block. The termination cell CE is adjacent to a cell C having a normal logic function in the Y direction. The termination cell CE includes a dummy transistor ND1 facing the transistor of the adjacent cell C, a buried power supply wiring 12 supplying VSS, and a buried power supply wiring 11A supplying VDD. The buried power supply wiring 12 is arranged on the side of the dummy transistor ND1 facing the transistor of the cell C, and the buried power supply wiring 11A is arranged on the opposite side of the dummy transistor ND1 from the transistor of the cell C. The size of the buried power supply wiring 11A in the Y direction is larger than the size of the buried power supply wiring 12 in the Y direction. This allows the buried power supply wiring 11A to be thicker without increasing the area of ​​the termination cell CE in the cell rows CRA and CRB. Therefore, in a semiconductor integrated circuit device using buried power supply wiring, the power supply wiring can be strengthened without hindering high integration.

[0044] (Variation 1) FIG. 6(a) is a modified example of the power tap cell 1 shown in FIG. 2. In the layout structure of FIG. 6(a), the local wirings 46, 47 extend to the cell frame CL. Similarly, for the power tap cell 1 shown in FIG. 4, the local wirings 46, 47 may also be extended to the cell frame CL. With this modified example, in the power tap cell columns 2a, 2b, and 2c of FIG. 1, the local wirings 46 of the power tap cells 1 are connected to each other, and the local wirings 47 of the power tap cells 1 are connected to each other to form local power wiring extending in the Y direction. As a result, the M2 power wiring and the local power wiring together form a power wiring network, and the power supply in the Y direction can be strengthened.

[0045] (Variation 2) FIG. 6(b) is a modified example of the power tap cell 1 shown in FIG. 4, and FIG. 6(c) is a modified example of the termination cell CE shown in FIG. 5. In the layout structure of FIG. 6(b), M1 wirings 51 and 52 extend to the cell frame CL in the X direction. The M1 wiring 51 is connected to the power supply wiring 11A through a via and a local wiring 46. The M1 wiring 52 is connected to the power supply wiring 12 through a via and a local wiring 47. In the layout structure of FIG. 6(c), M1 wirings 53 and 54 extend to the cell frame CL in the X direction. The M1 wiring 53 is connected to the power supply wiring 11A through a via and a local wiring 44 and 45. The M1 wiring 54 is connected to the power supply wiring 12 through a via and a local wiring 46 and 47.

[0046] 6(b) and 6(c), in the cell rows CRA and CRB of FIG. 1, the M1 wiring 51 of the power tap cell 1 and the M1 wiring 53 of the terminal cell CE are connected to each other, and the M1 wiring 52 of the power tap cell 1 and the M1 wiring 54 of the terminal cell CE are connected to each other to form an M1 power wiring extending in the X direction. As a result, the M1 power wiring and the embedded power wiring together form a power wiring network, and the power supply in the X direction can be strengthened.

[0047] In addition, in FIGS. 6(b) and 6(c), the M1 wirings 51 to 54 may be replaced with wirings in multiple layers.

[0048] (Variation 3) FIG. 7(a) shows a further modified example of the power tap cell 1 shown in FIG. 6(b), and FIG. 7(b) shows a further modified example of the termination cell CE shown in FIG. 6(c). In the layout structure of FIG. 7(a), M1 wirings 55 and 56 are added, extending to the cell frame CL in the X direction. The M1 wiring 55 is connected to the power supply wiring 11A through a via and a local wiring 46. The M1 wiring 56 is connected to the power supply wiring 12 through a via and a local wiring 47. In the layout structure of FIG. 7(b), M1 wirings 57 and 58 are added, extending to the cell frame CL in the X direction. The M1 wiring 57 is connected to the power supply wiring 11A through a via and a local wiring 44 and 45. The M1 wiring 58 is connected to the power supply wiring 12 through a via and a local wiring 46 and 47.

[0049] 7(a) and 7(b), in the cell rows CRA and CRB of FIG. 1, the M1 wiring 55 of the power tap cell 1 and the M1 wiring 57 of the terminal cell CE are connected to each other, and the M1 wiring 56 of the power tap cell 1 and the M1 wiring 58 of the terminal cell CE are connected to each other to form an M1 power wiring extending in the X direction. This makes it possible to further strengthen the power supply in the X direction.

[0050] In addition, in FIGS. 7(a) and 7(b), the M1 wirings 51 to 58 may be replaced with wirings in multiple layers.

[0051] (Variation 4) FIG. 8 shows another modification of the termination cell CE shown in FIG. 7(b). In the layout structure of FIG. 8, the M1 wiring 53 supplies the power supply voltage VSS instead of the power supply voltage VDD. The local wiring 48 extends in the Y direction so as to overlap with the power supply wirings 11A and 12 in a plan view, but is not connected to the power supply wiring 11A but is connected to the power supply wiring 12. The M1 wiring 53 is connected to the local wiring 48 through a via, but is not connected to the local wiring 44 connected to the power supply wiring 11A. The M1 wiring 57 is connected to the local wiring 44 through a via. The M1 wirings 54 and 58 are connected to the local wirings 46 and 48 through vias.

[0052] 8, the M1 wiring 57 that supplies the power supply voltage VDD and the M1 wirings 53 and 58 that supply the power supply voltage VSS are arranged alternately, so that an inter-wiring capacitance can be formed between the M1 wirings. This inter-wiring capacitance can suppress fluctuations in the power supply voltage.

[0053] (Other variations) 4, the local wiring 46 and the power wiring 11A are connected through one via, but they may be connected through multiple vias, or through a via that is long in the Y direction.

[0054] Furthermore, in the power tap cell 1 and the termination cell CE, the dummy gate wiring is formed from the P-type transistor region AP to the N-type transistor region AN, but the dummy gate wiring may be divided into the P-type transistor region AP and the N-type transistor region AN.

[0055] (Second embodiment) 9 is an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the second embodiment. In the layout of FIG. 9, a cell row CRM having double-height cells aligned in the X direction is arranged in the center in the Y direction. A thick embedded power wiring 3M extending in the X direction is arranged in the center in the Y direction of the cell row CRM. The power wiring 3M supplies a power supply voltage VDD. The rest of the configuration is the same as in the layout of FIG. 1, and common components are assigned the same reference numerals, and detailed description thereof may be omitted here.

[0056] The cell row CRM is arranged with a cell CM and a power tap cell 1M. The cell width (size in the X direction) of the cell CM is uniform and is the same as the cell width of the terminal cell CE. The power tap cell 1M is arranged in the same position in the X direction as the power tap cell 1 in the other cell row. The M2 power wiring 5 is connected to the power wiring 3M through a via within the power tap cell 1M. This further strengthens the power supply compared to the layout in Figure 1.

[0057] FIG. 10(a) is a plan view showing an example of the layout structure of the power tap cells 1M in the cell row CRM, and FIG. 10(b) is a plan view showing an example of the layout structure of the cells CM in the cell row CRM.

[0058] As shown in FIGS. 10(a) and 10(b), a power supply wiring 111 extending in the X direction is provided at the center of the power tap cell 1M and the cell CM in the Y direction. Furthermore, power supply wirings 112 and 113 extending in the X direction are provided at both ends of the power tap cell 1M and the cell CM in the Y direction. The power supply wirings 111, 112, and 113 are all buried power wirings (BPR) formed in a buried wiring layer. The power supply wiring 111 has a wiring width (size in the Y direction) larger than that of the power supply wirings 112 and 113. The power supply wiring 111 supplies a power supply voltage VDD, and the power supply wirings 112 and 113 supply a power supply voltage VSS. The power supply wiring 111 is shared with other power tap cells 1M and cells CM arranged in the cell row CRM to form the power supply wiring 3M in FIG. 9. The power supply wirings 112 and 113 are shared with other power tap cells 1M and cells CM arranged in the cell row CRM to form the power supply wiring 4 in FIG. 9.

[0059] As shown in Figure 10(a), in the power tap cell 1M, no nanosheet is formed, and no transistor is formed. Local wirings 141 and 142 extending in the Y direction are formed on both sides in the X direction of gate wirings 131 and 132 extending in the Y direction. The local wiring 141 is connected to the power wiring 111 through a via. The local wiring 142 is connected to the power wirings 112 and 113 through a via.

[0060] M2 wirings 161 and 162 extending in the Y direction are formed in the second metal wiring layer. The M2 wiring 161 overlaps the local wiring 141 in a planar view and is connected to the local wiring 141 through a via and an M1 wiring. The M2 wiring 162 overlaps the local wiring 142 in a planar view and is connected to the local wiring 142 through a via and an M1 wiring. The M2 wirings 161 and 162 extend to the cell frame CL in the Y direction.

[0061] As shown in FIG. 10(b), in cell CM, N-type dummy transistors ND11 and ND12 are formed in an N-type transistor region AN on a P-type substrate. Dummy transistor ND11 has a nanosheet 121 made of two sheets as a channel portion. Pads 122a and 122b made of a semiconductor layer with an integrated structure connected to the two sheets are formed at both ends of nanosheet 121 in the X direction. Dummy transistor ND12 has a nanosheet 123 made of two sheets as a channel portion. Pads 124a and 124b made of a semiconductor layer with an integrated structure connected to the two sheets are formed at both ends of nanosheet 123 in the X direction. On the other hand, no dummy transistors are formed in a P-type transistor region AP on the N well.

[0062] The gate wiring 133 extends in the Y direction and surrounds the nanosheet 121 of the dummy transistor ND11 with a gate insulating film (not shown) in between. The gate wiring 134 extends in the Y direction and surrounds the nanosheet 123 of the dummy transistor ND12 with a gate insulating film (not shown) in between.

[0063] Local wiring 143a, 143b, 144a, and 144b are formed extending in the Y direction. The local wiring 143a is connected to the pad 122a and is also connected to the power supply wiring 112 through a via. The local wiring 143b is connected to the pad 122b and is also connected to the power supply wiring 112 through a via. The local wiring 144a is connected to the pad 124a and is also connected to the power supply wiring 113 through a via. The local wiring 144b is connected to the pad 124b and is also connected to the power supply wiring 113 through a via.

[0064] Local wirings 145a, 145b, 146a, and 146b are formed to extend in the Y direction. The local wirings 145a, 145b, 146a, and 146b are connected to the power supply wiring 111 through vias.

[0065] As shown in Figure 10(b), in cell CM, nanosheets, pads, gates, and local wiring are formed in the transistor region on the side of adjacent cell C in the Y direction (N-type transistor regions AN on the upper and lower sides of the drawing in Figure 10(b)). This makes it possible to suppress variations in the finished shape of the layout pattern for cells C in other cell rows CR. Therefore, it is possible to suppress manufacturing variations in semiconductor integrated circuit devices, improve yields, and improve reliability.

[0066] Furthermore, in cell CM, no dummy transistors, including nanosheets and pads, are formed in the P-type transistor region AP. This allows for the formation of wide embedded power wiring 111. In other words, by not forming dummy transistors in the P-type transistor region AP, wide embedded power wiring 111 can be arranged without increasing the cell area. This allows for the strengthening of power wiring without hindering the high integration of semiconductor integrated circuits. Furthermore, since the P-type transistor region AP is not adjacent to other cells C, not forming dummy transistors there does not impair the effects of suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield, and improving reliability, as described above.

[0067] As described above, in this embodiment, a double-height cell CM without a logic function is arranged in a cell row CRM of a circuit block. The double-height cell CM is adjacent to a cell C with a normal logic function in the Y direction. The double-height cell CM includes dummy transistors ND11 and ND12 that face the transistor of the adjacent cell C, buried power supply wiring 112 and 113 that supply VSS, and buried power supply wiring 111 that supplies VDD. The buried power supply wiring 112 and 113 are arranged on the side of the dummy transistors ND11 and ND12 that faces the transistor of the cell C, and the buried power supply wiring 111 is arranged on the side of the dummy transistors ND11 and ND12 that faces the transistor of the cell C. The size of the buried power supply wiring 111 in the Y direction is larger than the size of the buried power supply wiring 112 and 113 in the Y direction. This allows the buried power supply wiring 111 to be thicker without increasing the area of ​​the double-height cell CM in the cell row CRM. Therefore, in a semiconductor integrated circuit device using buried power supply wiring, it is possible to strengthen the power supply wiring without hindering high integration.

[0068] The position at which the cell string CRM is arranged is not limited to that shown in FIG. 9. That is, it may be arranged at a position other than the center of the circuit block in the Y direction. Also, multiple rows of cell strings CRM may be arranged in the circuit block. Furthermore, the power supply wiring 3M passing through the cell string CRM may be a wiring that supplies the power supply voltage VSS. Furthermore, both the cell string CRM through which the power supply wiring 3M that supplies the power supply voltage VDD passes and the cell string CRM through which the power supply wiring 3M that supplies the power supply voltage VSS passes may be arranged in the circuit block.

[0069] (Variation 1) FIG. 11(a) is a modified example of the power tap cell 1M shown in FIG. 10(a). In the layout structure of FIG. 11(a), local wirings 141, 142 extend to the cell frame CL. By combining this modified example 1 with modified example 1 of the first embodiment, local power wirings extending in the Y direction are formed in the power tap cell columns 2a, 2b, and 2c of FIG. 9. As a result, the M2 power wiring and the local power wirings together form a power wiring network, and the power supply in the Y direction can be strengthened.

[0070] 11(a), M1 wirings 151, 152, 153, and 154 extend to the cell frame CL in the X direction. The M1 wirings 151 and 154 are connected to the power supply wirings 112 and 113 through vias and the local wiring 142. The M1 wirings 152 and 153 are connected to the power supply wiring 111 through a via and the local wiring 141. In the layout structure of FIG. 11(b), M1 wirings 155, 156, 157, and 158 extend to the cell frame CL in the X direction. The M1 wiring 155 is connected to the power supply wiring 112 through vias and the local wirings 143a and 143b. The M1 wiring 156 is connected to the power supply wiring 111 through vias and the local wirings 145a and 145b. The M1 wiring 157 is connected to the power supply wiring 111 through vias and the local wirings 146a and 146b. The M1 wiring 158 is connected to the power supply wiring 113 through vias and local wirings 144a and 144b.

[0071] 11(a) and (b), in the cell row CRM of FIG. 9, the M1 wiring 151 of the power tap cell 1M and the M1 wiring 155 of the cell CM are connected to each other, and the M1 wiring 154 of the power tap cell 1M and the M1 wiring 158 of the cell CM are connected to each other to form an M1 power supply wiring extending in the X direction that supplies the power supply voltage VSS. Furthermore, the M1 wiring 152 of the power tap cell 1M and the M1 wiring 156 of the cell CM are connected to each other, and the M1 wiring 153 of the power tap cell 1M and the M1 wiring 157 of the cell CM are connected to each other to form an M1 power supply wiring extending in the X direction that supplies the power supply voltage VDD. As a result, the M1 power supply wiring and the buried power supply wiring together form a power supply wiring network, and the power supply in the X direction can be strengthened.

[0072] In addition, in FIGS. 11(a) and 11(b), the M1 wirings 151 to 158 may be replaced with wirings in multiple layers.

[0073] (Variation 2) In the above-described embodiment, a cell row CRM consisting of double-height cells is arranged to strengthen the power supply, but it is also possible to arrange a cell row consisting of cells with a cell height higher than double-height cells, for example, triple-height cells.

[0074] 12 shows an example of a layout structure of a triple-height cell according to a modified example, where (a) is a power tap cell and (b) is another cell. A power supply wiring 211 that supplies a power supply voltage VSS and a power supply wiring 212 that supplies a power supply voltage VDD are arranged in the center in the Y direction. A power supply wiring 213 that supplies a power supply voltage VDD and a power supply wiring 214 that supplies a power supply voltage VSS are arranged at both ends in the Y direction. The power supply wirings 211 to 214 are formed in a buried wiring layer. The power supply wirings 211 and 212 have a larger wiring width (size in the Y direction) than the power supply wirings 213 and 214.

[0075] 12(a), in the power tap cell, a local wiring 241 is connected to power wirings 212 and 213 through vias, and an M2 wiring 261 is connected to the local wiring 241 through vias and an M1 wiring. A local wiring 242 is connected to power wirings 211 and 214 through vias, and the M2 wiring 262 is connected to the local wiring 242 through vias and an M1 wiring.

[0076] 12(b), in the other cells, a P-type dummy transistor PD2 is formed in a P-type transistor region AP on the N-well at the upper side of the drawing. Also, an N-type dummy transistor ND2 is formed in an N-type transistor region AN on the P-type substrate at the lower side of the drawing. On the other hand, no dummy transistor is formed in the transistor region at the center in the Y direction.

[0077] 12, by arranging a cell row made up of triple-height cells in a circuit block, the wiring width of the embedded power supply wiring that supplies the power supply voltage VDD and the embedded power supply wiring that supplies the power supply voltage VSS can be increased. This allows for a stronger power supply, and the efficiency of cell placement for strengthening the power supply is higher than when arranging a cell row made up of double-height cells.

[0078] (Other embodiments) In the above embodiment, the embedded power supply wirings 3A and 3B at the top and bottom ends of the circuit block supply the power supply voltage VDD, but instead, they may supply the power supply voltage VSS.

[0079] In this case, in the layout structure of the termination cell CE shown in Figure 5, the power supply wiring 12 that supplies the power supply voltage VSS becomes thicker, and the power supply wiring 11A that supplies the power supply voltage VDD becomes thinner. There are no dummy transistors in the N-type transistor region on the P-type substrate, and P-type dummy transistors are formed in the P-type transistor region on the N-well. Also, in the layout structure of the power tap cell 1 shown in Figure 4, the power supply wiring 12 that supplies the power supply voltage VSS becomes thicker, and the power supply wiring 11A that supplies the power supply voltage VDD becomes thinner. These termination cells CE and power tap cells 1 can be arranged upside down in the cell row CRA, which is the top row of the circuit block, and arranged without being upside down in the cell row CRB, which is the bottom row of the circuit block.

[0080] Alternatively, the power supply wiring at the top end of the circuit block and the power supply wiring at the bottom end of the circuit block may supply different power supply voltages. In this case, the cell row CRA, which is the top row of the circuit block, and the cell row CRB, which is the bottom row of the circuit block, have termination cells CE and power tap cells 1 with different layout structures arranged therein.

[0081] Furthermore, the power supply wiring extending in the Y direction of the power tap cell 1 is M2 wiring, but this is not limited to this and may be metal wiring other than the M2 wiring layer, or may be metal wiring formed in multiple wiring layers.

[0082] In each of the above-described embodiments, the power tap cell groups do not have to be arranged at equal intervals in the X direction. For example, the power tap cell groups may be arranged at closer intervals in an area where a stronger power supply is desired than in other areas. In other words, the power tap cell groups may be arranged at a predetermined interval in the X direction.

[0083] In the above-described embodiments, the transistor formed in each cell is a nanosheet FET, but is not limited to this and may be, for example, a fin transistor. Also, although the nanosheet FET of each cell has two nanosheets, the number of nanosheets is not limited to two.

[0084] Furthermore, the width (size in the X direction) of the power tap cell is not limited to that shown in each of the above-described embodiments. For example, the width of the power tap cell may be further increased, and two M2 wires for supplying VDD and two M2 wires for supplying VSS may be arranged. Also, the M2 power supply wire may be reduced to one, and the width of the power tap cell may be reduced, or three or more M2 power supply wires may be arranged in parallel, and the width of the power tap cell may be increased. [Industrial Applicability]

[0085] The present disclosure is useful for improving the performance of semiconductor chips, for example, because it enables strengthening of power supply wiring without hindering high integration in semiconductor integrated circuit devices that use embedded power supply wiring. [Explanation of symbols]

[0086] 1.1M Power Tap Cells 2a, 2b, 2c Power tap cell group 3, 3A, 3B, 3M, 4 Embedded power wiring 5,6 Metal power wiring 11, 11A, 12 Embedded power wiring 46 Local Wiring 51, 52, 53, 54, 55, 56, 57, 58 M1 wiring 61 M2 wiring 111,112,113 Embedded power wiring 141,142 Local wiring 151, 152, 153, 154, 155, 156, 157, 158 M1 wiring 161,162 M2 wiring 211,212,213,214 Embedded power wiring 241,242 Local Wiring 261,262 M2 wiring C Cell CE Termination Cell CM Double Height Cell CR, CRA, CRB, CRM cell row P1,N1 transistors ND1, ND11, ND12, ND2 dummy transistors PD2 dummy transistor

Claims

1. a plurality of cell rows each including standard cells aligned in a first direction and arranged side by side in a second direction perpendicular to the first direction; The plurality of cell rows are a first standard cell having a logic function, the first standard cell being arranged in a first cell row that is second from one end in the second direction; a second standard cell that is disposed in a second cell row at the one end in the second direction and adjacent to the first cell row, the second standard cell being adjacent to the first standard cell in the second direction, and having no logic function; The first standard cell is a first region in which a transistor of a first conductivity type is formed; a second region in which a transistor of a second conductivity type is formed; a first transistor, which is a transistor of the first conductivity type formed in the first region; a second transistor, which is a transistor of the second conductivity type formed in the second region; a first buried power supply wiring formed in the buried wiring layer and supplying a first power supply voltage; a second buried power supply wiring formed in the buried wiring layer and supplying a second power supply voltage; The second standard cell is a third region in which the second conductivity type transistor is formed; a third transistor of the second conductivity type formed in the third region and facing the second transistor in the second direction; a third buried power supply wiring formed in a buried wiring layer and arranged on the second transistor side of the third transistor, the third buried power supply wiring supplying the second power supply voltage; a fourth buried power supply wiring formed in a buried wiring layer and disposed on the opposite side of the third transistor from the second transistor, the fourth buried power supply wiring supplying the first power supply voltage; The size of the fourth embedded power supply wiring in the second direction is larger than the size of the third embedded power supply wiring in the second direction. A semiconductor integrated circuit device characterized by:

2. 2. The semiconductor integrated circuit device according to claim 1, The second standard cell is a first metal wiring formed in a metal wiring layer, extending in the first direction, overlapping the fourth buried power supply wiring in a plan view, and electrically connected to the fourth buried power supply wiring; A semiconductor integrated circuit device characterized by:

3. 3. The semiconductor integrated circuit device according to claim 2, The second standard cell is a second metal wiring formed in a metal wiring layer, extending in the first direction, overlapping the fourth buried power supply wiring in a plan view, and supplying the second power supply voltage; A semiconductor integrated circuit device characterized by:

4. 2. The semiconductor integrated circuit device according to claim 1, a power tap cell group provided in each of the plurality of cell rows and including a plurality of power tap cells aligned in the second direction; The power tap cell group includes: a first metal power supply wiring formed in a metal wiring layer, extending in the second direction, and supplying the first power supply voltage; a second metal power supply wiring formed in a metal wiring layer, extending in the second direction, and supplying the second power supply voltage; A semiconductor integrated circuit device characterized by:

5. 5. The semiconductor integrated circuit device according to claim 4, The power tap cell group includes: a first local power supply wiring formed in a local wiring layer in which local wiring contacting a source and a drain of a transistor included in the standard cell is formed, extending in the second direction, overlapping the first metal power supply wiring in a plan view, and supplying the first power supply voltage; a second local power supply wiring formed in a local wiring layer, extending in the second direction, overlapping the second metal power supply wiring in a plan view, and supplying the second power supply voltage; A semiconductor integrated circuit device characterized by:

6. a plurality of cell rows each including standard cells aligned in a first direction and arranged side by side in a second direction perpendicular to the first direction; The plurality of cell rows are a first standard cell arranged in a first cell row and having a logic function; a second standard cell that is a multi-height cell having no logic function and that is arranged in a second cell row adjacent to the first cell row and adjacent to the first standard cell in the second direction; The first standard cell is a first region in which a transistor of a first conductivity type is formed; a second region in which a transistor of a second conductivity type is formed; a first transistor, which is a transistor of the first conductivity type formed in the first region; a second transistor, which is a transistor of the second conductivity type formed in the second region; a first buried power supply wiring formed in the buried wiring layer and supplying a first power supply voltage; a second buried power supply wiring formed in the buried wiring layer and supplying a second power supply voltage; The second standard cell is a third region in which the second conductivity type transistor is formed; a third transistor of the second conductivity type formed in the third region and facing the second transistor in the second direction; a third buried power supply wiring formed in a buried wiring layer and arranged on the second transistor side of the third transistor, the third buried power supply wiring supplying the second power supply voltage; a fourth buried power supply wiring formed in a buried wiring layer and disposed on the opposite side of the third transistor from the second transistor, the fourth buried power supply wiring supplying the first power supply voltage; The size of the fourth embedded power supply wiring in the second direction is larger than the size of the third embedded power supply wiring in the second direction. A semiconductor integrated circuit device characterized by:

7. 7. The semiconductor integrated circuit device according to claim 6, The second standard cell is a fifth buried power supply wiring formed in a buried wiring layer, arranged on an opposite side of the fourth buried power supply wiring from the second transistor, and supplying the second power supply voltage; The size of the fifth embedded power supply wiring in the second direction is larger than the size of the third embedded power supply wiring in the second direction. A semiconductor integrated circuit device characterized by:

8. 7. The semiconductor integrated circuit device according to claim 6, The second standard cell is a first metal wiring formed in a metal wiring layer, extending in the first direction, overlapping the fourth buried power supply wiring in a plan view, and electrically connected to the fourth buried power supply wiring; A semiconductor integrated circuit device characterized by:

9. 7. The semiconductor integrated circuit device according to claim 6, a power tap cell group provided in each of the plurality of cell rows and including a plurality of power tap cells aligned in the second direction; The power tap cell group includes: a first metal power supply wiring formed in a metal wiring layer, extending in the second direction, and supplying the first power supply voltage; a second metal power supply wiring formed in a metal wiring layer, extending in the second direction, and supplying the second power supply voltage; A semiconductor integrated circuit device characterized by:

10. 10. The semiconductor integrated circuit device according to claim 9, The power tap cell group includes: a first local power supply wiring formed in a local wiring layer in which local wiring contacting a source and a drain of a transistor included in the standard cell is formed, extending in the second direction, overlapping the first metal power supply wiring in a plan view, and supplying the first power supply voltage; a second local power supply wiring formed in a local wiring layer, extending in the second direction, overlapping the second metal power supply wiring in a plan view, and supplying the second power supply voltage; A semiconductor integrated circuit device characterized by:

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